Chameleon

View nvidia.patch

1*** /chameleon/trunk/i386/libsaio/nvidia.c␉2011-12-11 03:18:19.000000000 +0000␊
2--- /patched/nvidia.c␉2011-12-14 19:20:18.000000000 +0000␊
3***************␊
4*** 99,107 ****␊
5 ␊
6 static struct nv_chipsets_t NVKnownChipsets[] = {␊
7 ␉{ 0x00000000, "Unknown" },␊
8- // temporary placement␊
9- ␉{ 0x10DE0DF4, "GeForce GT 450M" }, //Azi + issue #99␊
10- ␉{ 0x10DE1251, "GeForce GTX 560M" }, // Asus G74SX␊
11 //========================================␊
12 ␉// 0040 - 004F␉␊
13 ␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊
14--- 99,104 ----␊
15***************␊
16*** 400,405 ****␊
17--- 397,403 ----␊
18 ␉{ 0x10DE05E2, "GeForce GTX 260" },␊
19 ␉{ 0x10DE05E3, "GeForce GTX 285" },␊
20 ␉{ 0x10DE05E6, "GeForce GTX 275" },␊
21+ ␉{ 0x10DE05E7, "Tesla C1060" }, ␊
22 ␉{ 0x10DE05EA, "GeForce GTX 260" },␊
23 ␉{ 0x10DE05EB, "GeForce GTX 295" },␊
24 ␉{ 0x10DE05ED, "Quadroplex 2200 D2" },␊
25***************␊
26*** 439,446 ****␊
27--- 437,446 ----␊
28 ␉{ 0x10DE061B, "Quadro VX 200" },␊
29 ␉{ 0x10DE061C, "Quadro FX 3600M" },␊
30 ␉{ 0x10DE061D, "Quadro FX 2800M" },␊
31+ ␉{ 0x10DE061E, "Quadro FX 3700M" }, ␊
32 ␉{ 0x10DE061F, "Quadro FX 3800M" },␊
33 ␉// 0620 - 062F␉␊
34+ ␉{ 0x10DE0621, "GeForce GT 230" }, ␊
35 ␉{ 0x10DE0622, "GeForce 9600 GT" },␊
36 ␉{ 0x10DE0623, "GeForce 9600 GS" },␊
37 ␉{ 0x10DE0625, "GeForce 9600 GSO 512"},␊
38***************␊
39*** 448,453 ****␊
40--- 448,454 ----␊
41 ␉{ 0x10DE0627, "GeForce GT 140" },␊
42 ␉{ 0x10DE0628, "GeForce 9800M GTS" },␊
43 ␉{ 0x10DE062A, "GeForce 9700M GTS" },␊
44+ ␉{ 0x10DE062B, "GeForce 9800M GS" }, ␊
45 ␉{ 0x10DE062C, "GeForce 9800M GTS" },␊
46 ␉{ 0x10DE062D, "GeForce 9600 GT" },␊
47 ␉{ 0x10DE062E, "GeForce 9600 GT" },␊
48***************␊
49*** 477,482 ****␊
50--- 478,484 ----␊
51 ␉{ 0x10DE0652, "GeForce GT 130M" },␊
52 ␉{ 0x10DE0653, "GeForce GT 120M" },␊
53 ␉{ 0x10DE0654, "GeForce GT 220M" },␊
54+ ␉{ 0x10DE0655, "GeForce GT 120" }, ␊
55 ␉{ 0x10DE0656, "GeForce 9650 S" },␊
56 ␉{ 0x10DE0658, "Quadro FX 380" },␊
57 ␉{ 0x10DE0659, "Quadro FX 580" },␊
58***************␊
59*** 507,512 ****␊
60--- 509,515 ----␊
61 ␉{ 0x10DE06DD, "Quadro 4000" },␊
62 ␉{ 0x10DE06DE, "Tesla M2050" },␉// TODO: sub-device id: 0x0846␊
63 ␉{ 0x10DE06DE, "Tesla M2070" },␉// TODO: sub-device id: ?␉␊
64+ ␉{ 0x10DE06DF, "Tesla M2070-Q" }, ␊
65 ␉// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070␊
66 ␉// 06E0 - 06EF␉␊
67 ␉{ 0x10DE06E0, "GeForce 9300 GE" },␊
68***************␊
69*** 524,534 ****␊
70--- 527,539 ----␊
71 ␉{ 0x10DE06EC, "GeForce G 105M" },␊
72 ␉{ 0x10DE06EF, "GeForce G 103M" },␊
73 ␉// 06F0 - 06FF␉␊
74+ ␉{ 0x10DE06F1, "GeForce G105M" }, ␊
75 ␉{ 0x10DE06F8, "Quadro NVS 420" },␊
76 ␉{ 0x10DE06F9, "Quadro FX 370 LP" },␊
77 ␉{ 0x10DE06FA, "Quadro NVS 450" },␊
78 ␉{ 0x10DE06FB, "Quadro FX 370M" },␊
79 ␉{ 0x10DE06FD, "Quadro NVS 295" },␊
80+ ␉{ 0x10DE06FF, "HICx16 + Graphics" }, ␊
81 ␉// 0700 - 070F␊
82 ␉// 0710 - 071F␊
83 ␉// 0720 - 072F␊
84***************␊
85*** 555,560 ****␊
86--- 560,566 ----␊
87 ␉// 0820 - 082F␊
88 ␉// 0830 - 083F␊
89 ␉// 0840 - 084F␊
90+ ␉{ 0x10DE0840, "GeForce 8200M" }, ␊
91 ␉{ 0x10DE0844, "GeForce 9100M G" },␊
92 ␉{ 0x10DE0845, "GeForce 8200M G" },␊
93 ␉{ 0x10DE0846, "GeForce 9200" },␊
94***************␊
95*** 577,582 ****␊
96--- 583,589 ----␊
97 ␉{ 0x10DE0866, "GeForce 9400M G" },␊
98 ␉{ 0x10DE0867, "GeForce 9400" },␊
99 ␉{ 0x10DE0868, "nForce 760i SLI" },␊
100+ ␉{ 0x10DE0869, "GeForce 9400" }, ␊
101 ␉{ 0x10DE086A, "GeForce 9400" },␊
102 ␉{ 0x10DE086C, "GeForce 9300 / nForce 730i" },␊
103 ␉{ 0x10DE086D, "GeForce 9200" },␊
104***************␊
105*** 596,601 ****␊
106--- 603,610 ----␊
107 ␉// 0880 - 088F␊
108 ␉// 0890 - 089F␊
109 ␉// 08A0 - 08AF␊
110+ ␉{ 0x10DE08A0, "GeForce 320M" }, ␊
111+ ␉{ 0x10DE08A4, "GeForce 320M" }, ␊
112 ␉// 08B0 - 08BF␊
113 ␉// 08C0 - 08CF␊
114 ␉// 08D0 - 08DF␉␊
115***************␊
116*** 623,628 ****␊
117--- 632,639 ----␊
118 ␉{ 0x10DE0A20, "GeForce GT220" },␊
119 ␉{ 0x10DE0A22, "GeForce 315" },␊
120 ␉{ 0x10DE0A23, "GeForce 210" },␊
121+ ␉{ 0x10DE0A26, "GeForce 405" }, ␊
122+ ␉{ 0x10DE0A27, "GeForce 405" }, ␊
123 ␉{ 0x10DE0A28, "GeForce GT 230M" },␊
124 ␉{ 0x10DE0A29, "GeForce GT 330M" },␊
125 ␉{ 0x10DE0A2A, "GeForce GT 230M" },␊
126***************␊
127*** 632,637 ****␊
128--- 643,649 ----␊
129 ␉// 0A30 - 0A3F␉␊
130 ␉{ 0x10DE0A34, "GeForce GT 240M" },␊
131 ␉{ 0x10DE0A35, "GeForce GT 325M" },␊
132+ ␉{ 0x10DE0A38, "Quadro 400" }, ␊
133 ␉{ 0x10DE0A3C, "Quadro FX 880M" },␊
134 ␉// 0A40 - 0A4F␊
135 ␉// 0A50 - 0A5F␊
136***************␊
137*** 656,662 ****␊
138--- 668,676 ----␊
139 ␉{ 0x10DE0A73, "GeForce 305M" },␊
140 ␉{ 0x10DE0A74, "GeForce G210M" },␊
141 ␉{ 0x10DE0A75, "GeForce G310M" },␊
142+ ␉{ 0x10DE0A76, "ION" }, ␊
143 ␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊
144+ ␉{ 0x10DE0A7A, "GeForce 315M" }, ␊
145 ␉{ 0x10DE0A7C, "Quadro FX 380M" },␊
146 ␉// 0A80 - 0A8F␊
147 ␉// 0A90 - 0A9F␊
148***************␊
149*** 697,706 ****␊
150 ␉{ 0x10DE0CA2, "GeForce GT 320" },␊
151 ␉{ 0x10DE0CA3, "GeForce GT 240" },␊
152 ␉{ 0x10DE0CA4, "GeForce GT 340" },␊
153 ␉{ 0x10DE0CA7, "GeForce GT 330" },␊
154 ␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊
155 ␉{ 0x10DE0CA9, "GeForce GTS 250M" },␊
156! ␉{ 0x10DE0CAC, "GeForce 315" },␊
157 ␉{ 0x10DE0CAF, "GeForce GT 335M" },␊
158 ␉// 0CB0 - 0CBF␉␊
159 ␉{ 0x10DE0CB0, "GeForce GTS 350M" },␊
160--- 711,721 ----␊
161 ␉{ 0x10DE0CA2, "GeForce GT 320" },␊
162 ␉{ 0x10DE0CA3, "GeForce GT 240" },␊
163 ␉{ 0x10DE0CA4, "GeForce GT 340" },␊
164+ ␉{ 0x10DE0CA5, "GeForce GT 220" }, ␊
165 ␉{ 0x10DE0CA7, "GeForce GT 330" },␊
166 ␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊
167 ␉{ 0x10DE0CA9, "GeForce GTS 250M" },␊
168! ␉{ 0x10DE0CAC, "GeForce GT 220" }, ␊
169 ␉{ 0x10DE0CAF, "GeForce GT 335M" },␊
170 ␉// 0CB0 - 0CBF␉␊
171 ␉{ 0x10DE0CB0, "GeForce GTS 350M" },␊
172***************␊
173*** 730,740 ****␊
174--- 745,759 ----␊
175 ␉{ 0x10DE0DC5, "GeForce GTS 450" },␊
176 ␉{ 0x10DE0DC6, "GeForce GTS 450" },␊
177 ␉{ 0x10DE0DCA, "GF10x" },␊
178+ ␉{ 0x10DE0DCD, "GeForce GT 555M" }, ␊
179+ ␉{ 0x10DE0DCE, "GeForce GT 555M" }, ␊
180 ␉// 0DD0 - 0DDF␉␊
181 ␉{ 0x10DE0DD1, "GeForce GTX 460M" },␊
182 ␉{ 0x10DE0DD2, "GeForce GT 445M" },␊
183 ␉{ 0x10DE0DD3, "GeForce GT 435M" },␊
184+ ␉{ 0x10DE0DD6, "GeForce GT 550M" }, ␊
185 ␉{ 0x10DE0DD8, "Quadro 2000" },␊
186+ ␉{ 0x10DE0DDA, "Quadro 2000M" }, ␊
187 ␉{ 0x10DE0DDE, "GF106-ES" },␊
188 ␉{ 0x10DE0DDF, "GF106-INT" },␊
189 ␉// 0DE0 - 0DEF␉␊
190***************␊
191*** 743,755 ****␊
192--- 762,781 ----␊
193 ␉{ 0x10DE0DE2, "GeForce GT 420" },␊
194 ␉{ 0x10DE0DE5, "GeForce GT 530" },␊
195 ␉{ 0x10DE0DEB, "GeForce GT 555M" },␊
196+ ␉{ 0x10DE0DEC, "GeForce GT 525M" }, ␊
197+ ␉{ 0x10DE0DED, "GeForce GT 520M" }, ␊
198 ␉{ 0x10DE0DEE, "GeForce GT 415M" },␊
199 ␉// 0DF0 - 0DFF␉␊
200 ␉{ 0x10DE0DF0, "GeForce GT 425M" },␊
201 ␉{ 0x10DE0DF1, "GeForce GT 420M" },␊
202 ␉{ 0x10DE0DF2, "GeForce GT 435M" },␊
203 ␉{ 0x10DE0DF3, "GeForce GT 420M" },␊
204+ ␉{ 0x10DE0DF4, "GeForce GT 540M" }, ␊
205+ ␉{ 0x10DE0DF5, "GeForce GT 525M" }, ␊
206+ ␉{ 0x10DE0DF6, "GeForce GT 550M" }, ␊
207+ ␉{ 0x10DE0DF7, "GeForce GT 520M" }, ␊
208 ␉{ 0x10DE0DF8, "Quadro 600" },␊
209+ ␉{ 0x10DE0DFA, "Quadro 1000M" }, ␊
210 ␉{ 0x10DE0DFE, "GF108 ES" },␊
211 ␉{ 0x10DE0DFF, "GF108 INT" },␊
212 ␉// 0E00 - 0E0F␊
213***************␊
214*** 762,768 ****␊
215--- 788,797 ----␊
216 ␉{ 0x10DE0E25, "D12U-50" },␊
217 ␉// 0E30 - 0E3F␉␊
218 ␉{ 0x10DE0E30, "GeForce GTX 470M" },␊
219+ ␉{ 0x10DE0E31, "GeForce GTX 485M" }, ␊
220 ␉{ 0x10DE0E38, "GF104GL" },␊
221+ ␉{ 0x10DE0E3A, "Quadro 3000M" }, ␊
222+ ␉{ 0x10DE0E3B, "Quadro 4000M" }, ␊
223 ␉{ 0x10DE0E3E, "GF104-ES" },␊
224 ␉{ 0x10DE0E3F, "GF104-INT" },␊
225 ␉// 0E40 - 0E4F␉␊
226***************␊
227*** 798,825 ****␊
228 ␉// 1020 - 102F␊
229 ␉// 1030 - 103F␊
230 ␉// 1040 - 104F␊
231! ␉{ 0x10DE1040, "GeForce GT 520" },␉␊
232 ␉// 1050 - 105F␊
233 ␉{ 0x10DE1050, "GeForce GT 520M" },␊
234 ␉// 1060 - 106F␊
235 ␉// 1070 - 107F␊
236 ␉// 1080 - 108F␊
237 ␉{ 0x10DE1080, "GeForce GTX 580" },␊
238 ␉{ 0x10DE1081, "GeForce GTX 570" },␊
239 ␉{ 0x10DE1082, "GeForce GTX 560 Ti" },␊
240 ␉{ 0x10DE1083, "D13U" },␊
241 ␉{ 0x10DE1088, "GeForce GTX 590" },␊
242 ␉// 1090 - 109F␉␊
243 ␉{ 0x10DE1098, "D13U" },␊
244! ␉{ 0x10DE109A, "N12E-Q5" },␊
245 ␉// 10A0 - 10AF␊
246 ␉// 10B0 - 10BF␊
247 ␉// 10C0 - 10CF␊
248 ␉{ 0x10DE10C3, "GeForce 8400 GS" },␊
249 ␉// 1200 - ␊
250 ␉{ 0x10DE1200, "GeForce GTX 560 Ti" },␊
251 ␉{ 0x10DE1244, "GeForce GTX 550 Ti" },␊
252! ␉{ 0x10DE1245, "GeForce GTS 450" },␉␊
253 };␊
254 ␊
255 static uint16_t swap16(uint16_t x)␊
256--- 827,873 ----␊
257 ␉// 1020 - 102F␊
258 ␉// 1030 - 103F␊
259 ␉// 1040 - 104F␊
260! ␉{ 0x10DE1040, "GeForce GT 520" },␊
261 ␉// 1050 - 105F␊
262 ␉{ 0x10DE1050, "GeForce GT 520M" },␊
263+ ␉{ 0x10DE1054, "GeForce GT 410M" }, ␊
264+ ␉{ 0x10DE1056, "NVS 4200M" }, ␊
265+ ␉{ 0x10DE1057, "NVS 4200M" }, ␊
266 ␉// 1060 - 106F␊
267 ␉// 1070 - 107F␊
268+ ␉{ 0x10DE107F, "NVIDIA GF119-ES" }, ␊
269 ␉// 1080 - 108F␊
270 ␉{ 0x10DE1080, "GeForce GTX 580" },␊
271 ␉{ 0x10DE1081, "GeForce GTX 570" },␊
272 ␉{ 0x10DE1082, "GeForce GTX 560 Ti" },␊
273 ␉{ 0x10DE1083, "D13U" },␊
274+ ␉{ 0x10DE1084, "GeForce GTX 560" }, ␊
275+ ␉{ 0x10DE1086, "GeForce GTX 570" }, ␊
276+ ␉{ 0x10DE1087, "GeForce GTX 560 Ti-448" }, ␊
277 ␉{ 0x10DE1088, "GeForce GTX 590" },␊
278+ ␉{ 0x10DE1089, "GeForce GTX 580" }, ␊
279+ ␉{ 0x10DE108B, "GeForce GTX 590" }, ␊
280 ␉// 1090 - 109F␉␊
281+ ␉{ 0x10DE1091, "Tesla M2090" }, ␊
282 ␉{ 0x10DE1098, "D13U" },␊
283! ␉{ 0x10DE109A, "Quadro 5010M" }, ␊
284! ␉{ 0x10DE109B, "Quadro 7000" }, ␊
285 ␉// 10A0 - 10AF␊
286 ␉// 10B0 - 10BF␊
287 ␉// 10C0 - 10CF␊
288+ ␉{ 0x10DE10C0, "GeForce 9300 GS" }, ␊
289 ␉{ 0x10DE10C3, "GeForce 8400 GS" },␊
290+ ␉{ 0x10DE10C5, "GeForce 405" }, ␊
291+ ␉// 10D0 - 10DF␊
292+ ␉{ 0x10DE10D8, "NVS 300" }, ␊
293 ␉// 1200 - ␊
294 ␉{ 0x10DE1200, "GeForce GTX 560 Ti" },␊
295+ ␉{ 0x10DE1201, "GeForce GTX 560" }, ␊
296+ ␉{ 0x10DE1241, "GeForce GT 545" }, ␊
297+ ␉{ 0x10DE1243, "GeForce GT 545" }, ␊
298 ␉{ 0x10DE1244, "GeForce GTX 550 Ti" },␊
299! ␉{ 0x10DE1245, "GeForce GTS 450" },␊
300! ␉{ 0x10DE1251, "GeForce GTX 560M" }, ␊
301 };␊
302 ␊
303 static uint16_t swap16(uint16_t x)␊
304***************␊
305*** 830,839 ****␊
306 static uint16_t read16(uint8_t *ptr, uint16_t offset)␊
307 {␊
308 ␉uint8_t ret[2];␊
309! ␉␊
310 ␉ret[0] = ptr[offset+1];␊
311 ␉ret[1] = ptr[offset];␊
312! ␉␊
313 ␉return *((uint16_t*)&ret);␊
314 }␊
315 ␊
316--- 878,887 ----␊
317 static uint16_t read16(uint8_t *ptr, uint16_t offset)␊
318 {␊
319 ␉uint8_t ret[2];␊
320! ␊
321 ␉ret[0] = ptr[offset+1];␊
322 ␉ret[1] = ptr[offset];␊
323! ␊
324 ␉return *((uint16_t*)&ret);␊
325 }␊
326 ␊
327***************␊
328*** 851,862 ****␊
329 static uint32_t read32(uint8_t *ptr, uint16_t offset)␊
330 {␊
331 ␉uint8_t ret[4];␊
332! ␉␊
333 ␉ret[0] = ptr[offset+3];␊
334 ␉ret[1] = ptr[offset+2];␊
335 ␉ret[2] = ptr[offset+1];␊
336 ␉ret[3] = ptr[offset];␊
337! ␉␊
338 ␉return *((uint32_t*)&ret);␊
339 }␊
340 #endif␊
341--- 899,910 ----␊
342 static uint32_t read32(uint8_t *ptr, uint16_t offset)␊
343 {␊
344 ␉uint8_t ret[4];␊
345! ␊
346 ␉ret[0] = ptr[offset+3];␊
347 ␉ret[1] = ptr[offset+2];␊
348 ␉ret[2] = ptr[offset+1];␊
349 ␉ret[3] = ptr[offset];␊
350! ␊
351 ␉return *((uint32_t*)&ret);␊
352 }␊
353 #endif␊
354***************␊
355*** 869,875 ****␊
356 ␉}␊
357 ␉␊
358 ␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊
359! ␉␊
360 ␉if (!dcbptr) {␊
361 ␉␉printf("no dcb table found\n");␊
362 ␉␉return PATCH_ROM_FAILED;␊
363--- 917,923 ----␊
364 ␉}␊
365 ␉␊
366 ␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊
367! ␊
368 ␉if (!dcbptr) {␊
369 ␉␉printf("no dcb table found\n");␊
370 ␉␉return PATCH_ROM_FAILED;␊
371***************␊
372*** 892,898 ****␊
373 ␉␉␉headerlength = dcbtable[1];␊
374 ␉␉␉numentries␉ = dcbtable[2];␊
375 ␉␉␉recordlength = dcbtable[3];␊
376! ␉␉␉␊
377 ␉␉␉sig = *(uint32_t *)&dcbtable[6];␊
378 ␉␉}␊
379 ␉␉else␊
380--- 940,946 ----␊
381 ␉␉␉headerlength = dcbtable[1];␊
382 ␉␉␉numentries␉ = dcbtable[2];␊
383 ␉␉␉recordlength = dcbtable[3];␊
384! ␊
385 ␉␉␉sig = *(uint32_t *)&dcbtable[6];␊
386 ␉␉}␊
387 ␉␉else␊
388***************␊
389*** 942,948 ****␊
390 ␉{␊
391 ␉␉uint32_t connection;␊
392 ␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊
393! ␉␉␊
394 ␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
395 ␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
396 ␉␉␉continue;␊
397--- 990,996 ----␊
398 ␉{␊
399 ␉␉uint32_t connection;␊
400 ␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊
401! ␊
402 ␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
403 ␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
404 ␉␉␉continue;␊
405***************␊
406*** 1201,1212 ****␊
407 ␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊
408 ␉}␊
409 ␉␊
410! ␉// Workaround for GT 420/430 & 9600M GT␊
411 ␉switch (nvda_dev->device_id)␊
412 ␉{␊
413 ␉␉case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430␊
414 ␉␉case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420␊
415! ␉␉case 0x0649: vram_size = 512*1024*1024; break;␉// 9600M GT␊
416 ␉␉default: break;␊
417 ␉}␊
418 ␉␊
419--- 1249,1262 ----␊
420 ␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊
421 ␉}␊
422 ␉␊
423! ␉// Workaround for 9600M GT, GT 420/430/440 & GT 525M␊
424 ␉switch (nvda_dev->device_id)␊
425 ␉{␊
426+ ␉␉case 0x0649: vram_size = 512*1024*1024; break;␉// 9600M GT␊
427+ ␉␉case 0x0DE0: vram_size = 1024*1024*1024; break; // GT 440␊
428 ␉␉case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430␊
429 ␉␉case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420␊
430! ␉␉case 0x0DEC: vram_size = 1024*1024*1024; break; // GT 525M␊
431 ␉␉default: break;␊
432 ␉}␊
433 ␉␊
434

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Attachment to issue 202

Created: 12 years 4 months ago by ErmaC