1 | /*␊ |
2 | * Intel ACPI Component Architecture␊ |
3 | * AML Disassembler version 20091214␊ |
4 | *␊ |
5 | * Disassembly of ./SSDT.aml, Sun Jul 29 19:04:39 2012␊ |
6 | *␊ |
7 | *␊ |
8 | * Original Table Header:␊ |
9 | * Signature "SSDT"␊ |
10 | * Length 0x00000144 (324)␊ |
11 | * Revision 0x01␊ |
12 | * Checksum 0x6B␊ |
13 | * OEM ID "PmRefA"␊ |
14 | * OEM Table ID "CpuCst"␊ |
15 | * OEM Revision 0x00001000 (4096)␊ |
16 | * Compiler ID "INTL"␊ |
17 | * Compiler Version 0x20100331 (537920305)␊ |
18 | */␊ |
19 | DefinitionBlock ("./SSDT.aml", "SSDT", 1, "PmRefA", "CpuCst", 0x00001000)␊ |
20 | {␊ |
21 | External (\_PR_.CPU7, DeviceObj)␊ |
22 | External (\_PR_.CPU6, DeviceObj)␊ |
23 | External (\_PR_.CPU5, DeviceObj)␊ |
24 | External (\_PR_.CPU4, DeviceObj)␊ |
25 | External (\_PR_.CPU3, DeviceObj)␊ |
26 | External (\_PR_.CPU2, DeviceObj)␊ |
27 | External (\_PR_.CPU1, DeviceObj)␊ |
28 | External (\_PR_.CPU0, DeviceObj)␊ |
29 | ␊ |
30 | Scope (\_PR)␊ |
31 | {␊ |
32 | Name (CST, Package (0x04)␊ |
33 | {␊ |
34 | 0x03, ␊ |
35 | Package (0x04)␊ |
36 | {␊ |
37 | ResourceTemplate ()␊ |
38 | {␊ |
39 | Register (FFixedHW, ␊ |
40 | 0x01, // Bit Width␊ |
41 | 0x02, // Bit Offset␊ |
42 | 0x0100000000000000, // Address␊ |
43 | ,)␊ |
44 | }, ␊ |
45 | ␊ |
46 | One, ␊ |
47 | 0x0001, ␊ |
48 | 0x000003E8␊ |
49 | }, ␊ |
50 | ␊ |
51 | Package (0x04)␊ |
52 | {␊ |
53 | ResourceTemplate ()␊ |
54 | {␊ |
55 | Register (FFixedHW, ␊ |
56 | 0x01, // Bit Width␊ |
57 | 0x02, // Bit Offset␊ |
58 | 0x0300000000000010, // Address␊ |
59 | ,)␊ |
60 | }, ␊ |
61 | ␊ |
62 | 0x02, ␊ |
63 | 0x0040, ␊ |
64 | 0x000001F4␊ |
65 | }, ␊ |
66 | ␊ |
67 | Package (0x04)␊ |
68 | {␊ |
69 | ResourceTemplate ()␊ |
70 | {␊ |
71 | Register (FFixedHW, ␊ |
72 | 0x01, // Bit Width␊ |
73 | 0x02, // Bit Offset␊ |
74 | 0x0300000000000030, // Address␊ |
75 | ,)␊ |
76 | }, ␊ |
77 | ␊ |
78 | 0x04, ␊ |
79 | 0x0080, ␊ |
80 | 0x000000C8␊ |
81 | }␊ |
82 | })␊ |
83 | }␊ |
84 | ␊ |
85 | Scope (\_PR.CPU0)␊ |
86 | {␊ |
87 | Alias (CST, _CST)␊ |
88 | }␊ |
89 | ␊ |
90 | Scope (\_PR.CPU1)␊ |
91 | {␊ |
92 | Alias (CST, _CST)␊ |
93 | }␊ |
94 | ␊ |
95 | Scope (\_PR.CPU2)␊ |
96 | {␊ |
97 | Alias (CST, _CST)␊ |
98 | }␊ |
99 | ␊ |
100 | Scope (\_PR.CPU3)␊ |
101 | {␊ |
102 | Alias (CST, _CST)␊ |
103 | }␊ |
104 | ␊ |
105 | Scope (\_PR.CPU4)␊ |
106 | {␊ |
107 | Alias (CST, _CST)␊ |
108 | }␊ |
109 | ␊ |
110 | Scope (\_PR.CPU5)␊ |
111 | {␊ |
112 | Alias (CST, _CST)␊ |
113 | }␊ |
114 | ␊ |
115 | Scope (\_PR.CPU6)␊ |
116 | {␊ |
117 | Alias (CST, _CST)␊ |
118 | }␊ |
119 | ␊ |
120 | Scope (\_PR.CPU7)␊ |
121 | {␊ |
122 | Alias (CST, _CST)␊ |
123 | }␊ |
124 | }␊ |
125 | ␊ |
126 |