1 | /*␊ |
2 | * Intel ACPI Component Architecture␊ |
3 | * AML Disassembler version 20091214␊ |
4 | *␊ |
5 | * Disassembly of ./SSDT-3.aml, Sun Jul 29 19:39:53 2012␊ |
6 | *␊ |
7 | *␊ |
8 | * Original Table Header:␊ |
9 | * Signature "SSDT"␊ |
10 | * Length 0x000003B1 (945)␊ |
11 | * Revision 0x01␊ |
12 | * Checksum 0x54␊ |
13 | * OEM ID "APPLE "␊ |
14 | * OEM Table ID "CpuPm"␊ |
15 | * OEM Revision 0x00001000 (4096)␊ |
16 | * Compiler ID "INTL"␊ |
17 | * Compiler Version 0x20110623 (537986595)␊ |
18 | */␊ |
19 | DefinitionBlock ("./SSDT-3.aml", "SSDT", 1, "APPLE ", "CpuPm", 0x00001000)␊ |
20 | {␊ |
21 | External (\_PR_.CPU7, DeviceObj)␊ |
22 | External (\_PR_.CPU6, DeviceObj)␊ |
23 | External (\_PR_.CPU5, DeviceObj)␊ |
24 | External (\_PR_.CPU4, DeviceObj)␊ |
25 | External (\_PR_.CPU3, DeviceObj)␊ |
26 | External (\_PR_.CPU2, DeviceObj)␊ |
27 | External (\_PR_.CPU1, DeviceObj)␊ |
28 | External (\_PR_.CPU0, DeviceObj)␊ |
29 | ␊ |
30 | Scope (\_PR.CPU0)␊ |
31 | {␊ |
32 | Name (VERS, "Core i7 3.9 GHz Maximum Clock SSDT based on Greggen\'s at tonymacx86.com 2012-05-16")␊ |
33 | Name (APSN, 0x04)␊ |
34 | Name (APSS, Package (0x18)␊ |
35 | {␊ |
36 | Package (0x06)␊ |
37 | {␊ |
38 | 0x0F3C, ␊ |
39 | Zero, ␊ |
40 | 0x0A, ␊ |
41 | 0x0A, ␊ |
42 | 0x2700, ␊ |
43 | 0x2700␊ |
44 | }, ␊ |
45 | ␊ |
46 | Package (0x06)␊ |
47 | {␊ |
48 | 0x0ED8, ␊ |
49 | Zero, ␊ |
50 | 0x0A, ␊ |
51 | 0x0A, ␊ |
52 | 0x2600, ␊ |
53 | 0x2600␊ |
54 | }, ␊ |
55 | ␊ |
56 | Package (0x06)␊ |
57 | {␊ |
58 | 0x0E74, ␊ |
59 | Zero, ␊ |
60 | 0x0A, ␊ |
61 | 0x0A, ␊ |
62 | 0x2500, ␊ |
63 | 0x2500␊ |
64 | }, ␊ |
65 | ␊ |
66 | Package (0x06)␊ |
67 | {␊ |
68 | 0x0E10, ␊ |
69 | Zero, ␊ |
70 | 0x0A, ␊ |
71 | 0x0A, ␊ |
72 | 0x2400, ␊ |
73 | 0x2400␊ |
74 | }, ␊ |
75 | ␊ |
76 | Package (0x06)␊ |
77 | {␊ |
78 | 0x0DAC, ␊ |
79 | Zero, ␊ |
80 | 0x0A, ␊ |
81 | 0x0A, ␊ |
82 | 0x2300, ␊ |
83 | 0x2300␊ |
84 | }, ␊ |
85 | ␊ |
86 | Package (0x06)␊ |
87 | {␊ |
88 | 0x0D48, ␊ |
89 | Zero, ␊ |
90 | 0x0A, ␊ |
91 | 0x0A, ␊ |
92 | 0x2200, ␊ |
93 | 0x2200␊ |
94 | }, ␊ |
95 | ␊ |
96 | Package (0x06)␊ |
97 | {␊ |
98 | 0x0CE4, ␊ |
99 | Zero, ␊ |
100 | 0x0A, ␊ |
101 | 0x0A, ␊ |
102 | 0x2100, ␊ |
103 | 0x2100␊ |
104 | }, ␊ |
105 | ␊ |
106 | Package (0x06)␊ |
107 | {␊ |
108 | 0x0C80, ␊ |
109 | Zero, ␊ |
110 | 0x0A, ␊ |
111 | 0x0A, ␊ |
112 | 0x2000, ␊ |
113 | 0x2000␊ |
114 | }, ␊ |
115 | ␊ |
116 | Package (0x06)␊ |
117 | {␊ |
118 | 0x0C1C, ␊ |
119 | Zero, ␊ |
120 | 0x0A, ␊ |
121 | 0x0A, ␊ |
122 | 0x1F00, ␊ |
123 | 0x1F00␊ |
124 | }, ␊ |
125 | ␊ |
126 | Package (0x06)␊ |
127 | {␊ |
128 | 0x0BB8, ␊ |
129 | Zero, ␊ |
130 | 0x0A, ␊ |
131 | 0x0A, ␊ |
132 | 0x1E00, ␊ |
133 | 0x1E00␊ |
134 | }, ␊ |
135 | ␊ |
136 | Package (0x06)␊ |
137 | {␊ |
138 | 0x0B54, ␊ |
139 | Zero, ␊ |
140 | 0x0A, ␊ |
141 | 0x0A, ␊ |
142 | 0x1D00, ␊ |
143 | 0x1D00␊ |
144 | }, ␊ |
145 | ␊ |
146 | Package (0x06)␊ |
147 | {␊ |
148 | 0x0AF0, ␊ |
149 | Zero, ␊ |
150 | 0x0A, ␊ |
151 | 0x0A, ␊ |
152 | 0x1C00, ␊ |
153 | 0x1C00␊ |
154 | }, ␊ |
155 | ␊ |
156 | Package (0x06)␊ |
157 | {␊ |
158 | 0x0A8C, ␊ |
159 | Zero, ␊ |
160 | 0x0A, ␊ |
161 | 0x0A, ␊ |
162 | 0x1B00, ␊ |
163 | 0x1B00␊ |
164 | }, ␊ |
165 | ␊ |
166 | Package (0x06)␊ |
167 | {␊ |
168 | 0x0A28, ␊ |
169 | Zero, ␊ |
170 | 0x0A, ␊ |
171 | 0x0A, ␊ |
172 | 0x1A00, ␊ |
173 | 0x1A00␊ |
174 | }, ␊ |
175 | ␊ |
176 | Package (0x06)␊ |
177 | {␊ |
178 | 0x09C4, ␊ |
179 | Zero, ␊ |
180 | 0x0A, ␊ |
181 | 0x0A, ␊ |
182 | 0x1900, ␊ |
183 | 0x1900␊ |
184 | }, ␊ |
185 | ␊ |
186 | Package (0x06)␊ |
187 | {␊ |
188 | 0x0960, ␊ |
189 | Zero, ␊ |
190 | 0x0A, ␊ |
191 | 0x0A, ␊ |
192 | 0x1800, ␊ |
193 | 0x1800␊ |
194 | }, ␊ |
195 | ␊ |
196 | Package (0x06)␊ |
197 | {␊ |
198 | 0x08FC, ␊ |
199 | Zero, ␊ |
200 | 0x0A, ␊ |
201 | 0x0A, ␊ |
202 | 0x1700, ␊ |
203 | 0x1700␊ |
204 | }, ␊ |
205 | ␊ |
206 | Package (0x06)␊ |
207 | {␊ |
208 | 0x0898, ␊ |
209 | Zero, ␊ |
210 | 0x0A, ␊ |
211 | 0x0A, ␊ |
212 | 0x1600, ␊ |
213 | 0x1600␊ |
214 | }, ␊ |
215 | ␊ |
216 | Package (0x06)␊ |
217 | {␊ |
218 | 0x0834, ␊ |
219 | Zero, ␊ |
220 | 0x0A, ␊ |
221 | 0x0A, ␊ |
222 | 0x1500, ␊ |
223 | 0x1500␊ |
224 | }, ␊ |
225 | ␊ |
226 | Package (0x06)␊ |
227 | {␊ |
228 | 0x07D0, ␊ |
229 | Zero, ␊ |
230 | 0x0A, ␊ |
231 | 0x0A, ␊ |
232 | 0x1400, ␊ |
233 | 0x1400␊ |
234 | }, ␊ |
235 | ␊ |
236 | Package (0x06)␊ |
237 | {␊ |
238 | 0x076C, ␊ |
239 | Zero, ␊ |
240 | 0x0A, ␊ |
241 | 0x0A, ␊ |
242 | 0x1300, ␊ |
243 | 0x1300␊ |
244 | }, ␊ |
245 | ␊ |
246 | Package (0x06)␊ |
247 | {␊ |
248 | 0x0708, ␊ |
249 | Zero, ␊ |
250 | 0x0A, ␊ |
251 | 0x0A, ␊ |
252 | 0x1200, ␊ |
253 | 0x1200␊ |
254 | }, ␊ |
255 | ␊ |
256 | Package (0x06)␊ |
257 | {␊ |
258 | 0x06A4, ␊ |
259 | Zero, ␊ |
260 | 0x0A, ␊ |
261 | 0x0A, ␊ |
262 | 0x1100, ␊ |
263 | 0x1100␊ |
264 | }, ␊ |
265 | ␊ |
266 | Package (0x06)␊ |
267 | {␊ |
268 | 0x0640, ␊ |
269 | Zero, ␊ |
270 | 0x0A, ␊ |
271 | 0x0A, ␊ |
272 | 0x1000, ␊ |
273 | 0x1000␊ |
274 | }␊ |
275 | })␊ |
276 | Method (ACST, 0, NotSerialized)␊ |
277 | {␊ |
278 | Return (Package (0x06)␊ |
279 | {␊ |
280 | One, ␊ |
281 | 0x04, ␊ |
282 | Package (0x04)␊ |
283 | {␊ |
284 | ResourceTemplate ()␊ |
285 | {␊ |
286 | Register (FFixedHW, ␊ |
287 | 0x01, // Bit Width␊ |
288 | 0x02, // Bit Offset␊ |
289 | 0x0000000000000000, // Address␊ |
290 | 0x01, // Access Size␊ |
291 | )␊ |
292 | }, ␊ |
293 | ␊ |
294 | One, ␊ |
295 | 0x03, ␊ |
296 | 0x03E8␊ |
297 | }, ␊ |
298 | ␊ |
299 | Package (0x04)␊ |
300 | {␊ |
301 | ResourceTemplate ()␊ |
302 | {␊ |
303 | Register (FFixedHW, ␊ |
304 | 0x01, // Bit Width␊ |
305 | 0x02, // Bit Offset␊ |
306 | 0x0000000000000010, // Address␊ |
307 | 0x03, // Access Size␊ |
308 | )␊ |
309 | }, ␊ |
310 | ␊ |
311 | 0x03, ␊ |
312 | 0xCD, ␊ |
313 | 0x01F4␊ |
314 | }, ␊ |
315 | ␊ |
316 | Package (0x04)␊ |
317 | {␊ |
318 | ResourceTemplate ()␊ |
319 | {␊ |
320 | Register (FFixedHW, ␊ |
321 | 0x01, // Bit Width␊ |
322 | 0x02, // Bit Offset␊ |
323 | 0x0000000000000020, // Address␊ |
324 | 0x03, // Access Size␊ |
325 | )␊ |
326 | }, ␊ |
327 | ␊ |
328 | 0x06, ␊ |
329 | 0xF5, ␊ |
330 | 0x015E␊ |
331 | }, ␊ |
332 | ␊ |
333 | Package (0x04)␊ |
334 | {␊ |
335 | ResourceTemplate ()␊ |
336 | {␊ |
337 | Register (FFixedHW, ␊ |
338 | 0x01, // Bit Width␊ |
339 | 0x02, // Bit Offset␊ |
340 | 0x0000000000000030, // Address␊ |
341 | 0x03, // Access Size␊ |
342 | )␊ |
343 | }, ␊ |
344 | ␊ |
345 | 0x07, ␊ |
346 | 0xF5, ␊ |
347 | 0xC8␊ |
348 | }␊ |
349 | })␊ |
350 | }␊ |
351 | }␊ |
352 | ␊ |
353 | Scope (\_PR.CPU1)␊ |
354 | {␊ |
355 | Method (APSS, 0, NotSerialized)␊ |
356 | {␊ |
357 | Return (\_PR.CPU0.APSS)␊ |
358 | }␊ |
359 | }␊ |
360 | ␊ |
361 | Scope (\_PR.CPU2)␊ |
362 | {␊ |
363 | Method (APSS, 0, NotSerialized)␊ |
364 | {␊ |
365 | Return (\_PR.CPU0.APSS)␊ |
366 | }␊ |
367 | }␊ |
368 | ␊ |
369 | Scope (\_PR.CPU3)␊ |
370 | {␊ |
371 | Method (APSS, 0, NotSerialized)␊ |
372 | {␊ |
373 | Return (\_PR.CPU0.APSS)␊ |
374 | }␊ |
375 | }␊ |
376 | ␊ |
377 | Scope (\_PR.CPU4)␊ |
378 | {␊ |
379 | Method (APSS, 0, NotSerialized)␊ |
380 | {␊ |
381 | Return (\_PR.CPU0.APSS)␊ |
382 | }␊ |
383 | }␊ |
384 | ␊ |
385 | Scope (\_PR.CPU5)␊ |
386 | {␊ |
387 | Method (APSS, 0, NotSerialized)␊ |
388 | {␊ |
389 | Return (\_PR.CPU0.APSS)␊ |
390 | }␊ |
391 | }␊ |
392 | ␊ |
393 | Scope (\_PR.CPU6)␊ |
394 | {␊ |
395 | Method (APSS, 0, NotSerialized)␊ |
396 | {␊ |
397 | Return (\_PR.CPU0.APSS)␊ |
398 | }␊ |
399 | }␊ |
400 | ␊ |
401 | Scope (\_PR.CPU7)␊ |
402 | {␊ |
403 | Method (APSS, 0, NotSerialized)␊ |
404 | {␊ |
405 | Return (\_PR.CPU0.APSS)␊ |
406 | }␊ |
407 | }␊ |
408 | }␊ |
409 | ␊ |
410 |