Chameleon

View cpu.c

1/*
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>
3 * AsereBLN: 2009: cleanup and bugfix
4 */
5
6#include "libsaio.h"
7#include "platform.h"
8#include "cpu.h"
9#include "bootstruct.h"
10#include "boot.h"
11
12#ifndef DEBUG_CPU
13#define DEBUG_CPU 0
14#endif
15
16#if DEBUG_CPU
17#define DBG(x...)printf(x)
18#else
19#define DBG(x...)msglog(x)
20#endif
21
22/*
23 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer
24 */
25static uint64_t measure_tsc_frequency(void)
26{
27 uint64_t tscStart;
28 uint64_t tscEnd;
29 uint64_t tscDelta = 0xffffffffffffffffULL;
30 unsigned long pollCount;
31 uint64_t retval = 0;
32 int i;
33
34 /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT
35 * counter 2. We run this loop 3 times to make sure the cache
36 * is hot and we take the minimum delta from all of the runs.
37 * That is to say that we're biased towards measuring the minimum
38 * number of TSC ticks that occur while waiting for the timer to
39 * expire. That theoretically helps avoid inconsistencies when
40 * running under a VM if the TSC is not virtualized and the host
41 * steals time. The TSC is normally virtualized for VMware.
42 */
43 for(i = 0; i < 10; ++i)
44 {
45 enable_PIT2();
46 set_PIT2_mode0(CALIBRATE_LATCH);
47 tscStart = rdtsc64();
48 pollCount = poll_PIT2_gate();
49 tscEnd = rdtsc64();
50 /* The poll loop must have run at least a few times for accuracy */
51 if(pollCount <= 1)
52 continue;
53 /* The TSC must increment at LEAST once every millisecond. We
54 * should have waited exactly 30 msec so the TSC delta should
55 * be >= 30. Anything less and the processor is way too slow.
56 */
57 if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)
58 continue;
59 // tscDelta = MIN(tscDelta, (tscEnd - tscStart))
60 if( (tscEnd - tscStart) < tscDelta )
61 tscDelta = tscEnd - tscStart;
62 }
63 /* tscDelta is now the least number of TSC ticks the processor made in
64 * a timespan of 0.03 s (e.g. 30 milliseconds)
65 * Linux thus divides by 30 which gives the answer in kiloHertz because
66 * 1 / ms = kHz. But we're xnu and most of the rest of the code uses
67 * Hz so we need to convert our milliseconds to seconds. Since we're
68 * dividing by the milliseconds, we simply multiply by 1000.
69 */
70
71 /* Unlike linux, we're not limited to 32-bit, but we do need to take care
72 * that we're going to multiply by 1000 first so we do need at least some
73 * arithmetic headroom. For now, 32-bit should be enough.
74 * Also unlike Linux, our compiler can do 64-bit integer arithmetic.
75 */
76 if(tscDelta > (1ULL<<32))
77 retval = 0;
78 else
79 {
80 retval = tscDelta * 1000 / 30;
81 }
82 disable_PIT2();
83 return retval;
84}
85
86/*
87 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU
88 * - multi. is read from a specific MSR. In the case of Intel, there is:
89 * a max multi. (used to calculate the FSB freq.),
90 * and a current multi. (used to calculate the CPU freq.)
91 * - fsbFrequency = tscFrequency / multi
92 * - cpuFrequency = fsbFrequency * multi
93 */
94
95void scan_cpu(PlatformInfo_t *p)
96{
97uint64_ttscFrequency, fsbFrequency, cpuFrequency;
98uint64_tmsr, flex_ratio;
99uint8_tmaxcoef, maxdiv, currcoef, bus_ratio_max, currdiv;
100const char *newratio;
101int len, myfsb;
102uint8_t bus_ratio_min;
103uint32_t max_ratio, min_ratio;
104
105max_ratio = min_ratio = myfsb = bus_ratio_min = 0;
106maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;
107
108/* get cpuid values */
109do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);
110do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);
111do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);
112do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);
113do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);
114do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);
115if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {
116do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);
117}
118do_cpuid2(0x80000008, p->CPU.CPUID[CPUID_88]);
119#if DEBUG_CPU
120{
121inti;
122printf("CPUID Raw Values:\n");
123for (i=0; i<CPUID_MAX; i++) {
124printf("%02d: %08x-%08x-%08x-%08x\n", i,
125p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],
126p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);
127}
128}
129#endif
130p->CPU.Vendor= p->CPU.CPUID[CPUID_0][1];
131p->CPU.Signature= p->CPU.CPUID[CPUID_1][0];
132p->CPU.Stepping= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);
133p->CPU.Model= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);
134p->CPU.Family= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);
135p->CPU.ExtModel= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);
136p->CPU.ExtFamily= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);
137
138 p->CPU.Model += (p->CPU.ExtModel << 4);
139
140 if (p->CPU.Vendor == 0x756E6547 /* Intel */ &&
141 p->CPU.Family == 0x06 &&
142 p->CPU.Model >= CPUID_MODEL_NEHALEM &&
143 p->CPU.Model != CPUID_MODEL_ATOM // MSR is *NOT* available on the Intel Atom CPU
144 ){
145 msr = rdmsr64(MSR_CORE_THREAD_COUNT);// Undocumented MSR in Nehalem and newer CPUs
146 p->CPU.NoCores= bitfield((uint32_t)msr, 31, 16);// Using undocumented MSR to get actual values
147 p->CPU.NoThreads= bitfield((uint32_t)msr, 15, 0);// Using undocumented MSR to get actual values
148} else if (p->CPU.Vendor == 0x68747541 /* AMD */) {
149p->CPU.NoThreads= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);
150p->CPU.NoCores= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;
151} else {
152 p->CPU.NoThreads= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);// Use previous method for Cores and Threads
153 p->CPU.NoCores= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;
154}
155
156/* get brand string (if supported) */
157/* Copyright: from Apple's XNU cpuid.c */
158if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {
159uint32_treg[4];
160 char str[128], *s;
161/*
162 * The brand string 48 bytes (max), guaranteed to
163 * be NULL terminated.
164 */
165do_cpuid(0x80000002, reg);
166bcopy((char *)reg, &str[0], 16);
167do_cpuid(0x80000003, reg);
168bcopy((char *)reg, &str[16], 16);
169do_cpuid(0x80000004, reg);
170bcopy((char *)reg, &str[32], 16);
171for (s = str; *s != '\0'; s++) {
172if (*s != ' ') break;
173}
174
175strlcpy(p->CPU.BrandString,s, sizeof(p->CPU.BrandString));
176
177if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {
178 /*
179 * This string means we have a firmware-programmable brand string,
180 * and the firmware couldn't figure out what sort of CPU we have.
181 */
182 p->CPU.BrandString[0] = '\0';
183 }
184}
185
186/* setup features */
187if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {
188p->CPU.Features |= CPU_FEATURE_MMX;
189}
190if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {
191p->CPU.Features |= CPU_FEATURE_SSE;
192}
193if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {
194p->CPU.Features |= CPU_FEATURE_SSE2;
195}
196if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {
197p->CPU.Features |= CPU_FEATURE_SSE3;
198}
199if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {
200p->CPU.Features |= CPU_FEATURE_SSE41;
201}
202if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {
203p->CPU.Features |= CPU_FEATURE_SSE42;
204}
205if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {
206p->CPU.Features |= CPU_FEATURE_EM64T;
207}
208if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {
209p->CPU.Features |= CPU_FEATURE_MSR;
210}
211//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {
212if (p->CPU.NoThreads > p->CPU.NoCores) {
213p->CPU.Features |= CPU_FEATURE_HTT;
214}
215
216tscFrequency = measure_tsc_frequency();
217fsbFrequency = 0;
218cpuFrequency = 0;
219
220if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {
221int intelCPU = p->CPU.Model;
222if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {
223/* Nehalem CPU model */
224if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM ||
225 p->CPU.Model == CPU_MODEL_FIELDS ||
226 p->CPU.Model == CPU_MODEL_DALES ||
227 p->CPU.Model == CPU_MODEL_DALES_32NM ||
228 p->CPU.Model == CPU_MODEL_WESTMERE ||
229 p->CPU.Model == CPU_MODEL_NEHALEM_EX ||
230 p->CPU.Model == CPU_MODEL_WESTMERE_EX ||
231 p->CPU.Model == CPU_MODEL_SANDY ||
232 p->CPU.Model == CPU_MODEL_SANDY_XEON)) {
233msr = rdmsr64(MSR_PLATFORM_INFO);
234DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));
235bus_ratio_max = bitfield(msr, 14, 8);
236bus_ratio_min = bitfield(msr, 46, 40); //valv: not sure about this one (Remarq.1)
237msr = rdmsr64(MSR_FLEX_RATIO);
238DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));
239if (bitfield(msr, 16, 16)) {
240flex_ratio = bitfield(msr, 14, 8);
241/* bcc9: at least on the gigabyte h67ma-ud2h,
242 where the cpu multipler can't be changed to
243 allow overclocking, the flex_ratio msr has unexpected (to OSX)
244 contents. These contents cause mach_kernel to
245 fail to compute the bus ratio correctly, instead
246 causing the system to crash since tscGranularity
247 is inadvertently set to 0.
248*/
249if (flex_ratio == 0) {
250/* Clear bit 16 (evidently the
251 presence bit) */
252wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));
253msr = rdmsr64(MSR_FLEX_RATIO);
254verbose("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));
255} else {
256if (bus_ratio_max > flex_ratio) {
257bus_ratio_max = flex_ratio;
258}
259}
260}
261
262if (bus_ratio_max) {
263fsbFrequency = (tscFrequency / bus_ratio_max);
264}
265//valv: Turbo Ratio Limit
266if ((intelCPU != 0x2e) && (intelCPU != 0x2f)) {
267msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);
268cpuFrequency = bus_ratio_max * fsbFrequency;
269max_ratio = bus_ratio_max * 10;
270} else {
271cpuFrequency = tscFrequency;
272}
273if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4)) {
274max_ratio = atoi(newratio);
275max_ratio = (max_ratio * 10);
276if (len >= 3) max_ratio = (max_ratio + 5);
277
278verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);
279
280// extreme overclockers may love 320 ;)
281if ((max_ratio >= min_ratio) && (max_ratio <= 320)) {
282cpuFrequency = (fsbFrequency * max_ratio) / 10;
283if (len >= 3) maxdiv = 1;
284else maxdiv = 0;
285} else {
286max_ratio = (bus_ratio_max * 10);
287}
288}
289//valv: to be uncommented if Remarq.1 didn't stick
290/*if(bus_ratio_max > 0) bus_ratio = flex_ratio;*/
291p->CPU.MaxRatio = max_ratio;
292p->CPU.MinRatio = min_ratio;
293
294myfsb = fsbFrequency / 1000000;
295verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio);
296currcoef = bus_ratio_max;
297} else {
298msr = rdmsr64(MSR_IA32_PERF_STATUS);
299DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));
300currcoef = bitfield(msr, 12, 8);
301/* Non-integer bus ratio for the max-multi*/
302maxdiv = bitfield(msr, 46, 46);
303/* Non-integer bus ratio for the current-multi (undocumented)*/
304currdiv = bitfield(msr, 14, 14);
305
306if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) // This will always be model >= 3
307{
308/* On these models, maxcoef defines TSC freq */
309maxcoef = bitfield(msr, 44, 40);
310} else {
311/* On lower models, currcoef defines TSC freq */
312/* XXX */
313maxcoef = currcoef;
314}
315
316if (maxcoef) {
317if (maxdiv) {
318fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));
319} else {
320fsbFrequency = (tscFrequency / maxcoef);
321}
322if (currdiv) {
323cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);
324} else {
325cpuFrequency = (fsbFrequency * currcoef);
326}
327DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");
328}
329}
330}
331/* Mobile CPU */
332if (bitfield(rdmsr64(MSR_IA32_PLATFORM_ID) 28, 28)) {
333p->CPU.Features |= CPU_FEATURE_MOBILE;
334}
335}
336else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f)) {
337if(p->CPU.ExtFamily == 0x00 /* K8 */) {
338msr = rdmsr64(K8_FIDVID_STATUS);
339maxcoef = bitfield(msr, 21, 16) / 2 + 4;
340currcoef = bitfield(msr, 5, 0) / 2 + 4;
341
342if (maxcoef) {
343fsbFrequency = (tscFrequency / maxcoef);
344cpuFrequency = tscFrequency;
345}
346}
347}
348#if 0
349} else if(p->CPU.ExtFamily >= 0x01 /* K10+ */) {
350msr = rdmsr64(K10_COFVID_STATUS);
351if(p->CPU.ExtFamily == 0x01 /* K10 */)
352currcoef = bitfield(msr, 5, 0) + 0x10;
353else /* K11+ */
354currcoef = bitfield(msr, 5, 0) + 0x08;
355currdiv = 2 << (bitfield(msr, 8, 6);
356}
357
358if (currcoef) {
359if (currdiv) {
360fsbFrequency = ((tscFrequency * currdiv) / currcoef);
361DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);
362} else {
363fsbFrequency = (tscFrequency / currcoef);
364DBG("%d\n", currcoef);
365}
366fsbFrequency = (tscFrequency / currcoef);
367cpuFrequency = tscFrequency;
368}
369}
370
371if (!fsbFrequency) {
372fsbFrequency = (DEFAULT_FSB * 1000);
373cpuFrequency = tscFrequency;
374DBG("0 ! using the default value for FSB !\n");
375}
376#endif
377
378p->CPU.MaxCoef = maxcoef;
379p->CPU.MaxDiv = maxdiv;
380p->CPU.CurrCoef = currcoef;
381p->CPU.CurrDiv = currdiv;
382p->CPU.TSCFrequency = tscFrequency;
383p->CPU.FSBFrequency = fsbFrequency;
384p->CPU.CPUFrequency = cpuFrequency;
385
386DBG("CPU: Brand String: %s\n",p->CPU.BrandString);
387DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n",p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);
388DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n",p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);
389DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n",p->CPU.MaxCoef, p->CPU.CurrCoef);
390DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n",p->CPU.MaxDiv, p->CPU.CurrDiv);
391DBG("CPU: TSCFreq: %dMHz\n",p->CPU.TSCFrequency / 1000000);
392DBG("CPU: FSBFreq: %dMHz\n",p->CPU.FSBFrequency / 1000000);
393DBG("CPU: CPUFreq: %dMHz\n",p->CPU.CPUFrequency / 1000000);
394DBG("CPU: NoCores/NoThreads: %d/%d\n",p->CPU.NoCores, p->CPU.NoThreads);
395DBG("CPU: Features: 0x%08x\n",p->CPU.Features);
396#if DEBUG_CPU
397pause();
398#endif
399}
400

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Attachment to issue 92

Created: 8 years 7 months ago by Fumo Mofu