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View platform.h

1/*
2 * platform.h
3 * AsereBLN: reworked and extended
4 *
5 */
6
7#ifndef __LIBSAIO_PLATFORM_H
8#define __LIBSAIO_PLATFORM_H
9
10//#include "libsaio.h"
11
12extern bool platformCPUFeature(uint32_t);
13extern void scan_platform(void);
14extern void dumpPhysAddr(const char * title, void * a, int len);
15
16/* CPUID index into cpuid_raw */
17#define CPUID_00
18#define CPUID_11
19#define CPUID_22
20#define CPUID_33
21#define CPUID_44
22#define CPUID_805
23#define CPUID_816
24#define CPUID_887
25#define CPUID_MAX8
26
27#define CPU_MODEL_YONAH0x0E// Sossaman, Yonah
28#define CPU_MODEL_MEROM0x0F// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom
29#define CPU_MODEL_PENRYN0x17// Wolfdale, Yorkfield, Harpertown, Penryn
30#define CPU_MODEL_NEHALEM0x1A// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown
31#define CPU_MODEL_ATOM0x1C// Atom
32#define CPU_MODEL_FIELDS0x1E// Lynnfield, Clarksfield, Jasper Forest
33#define CPU_MODEL_DALES0x1F// Havendale, Auburndale
34#define CPU_MODEL_DALES_32NM0x25// Clarkdale, Arrandale
35#define CPU_MODEL_SANDY0x2A// Sandy Bridge
36#define CPU_MODEL_WESTMERE0x2C// Gulftown, Westmere-EP, Westmere-WS
37#define CPU_MODEL_SANDY_XEON0x2D// Sandy Bridge Xeon
38#define CPU_MODEL_NEHALEM_EX0x2E// Beckton
39#define CPU_MODEL_WESTMERE_EX0x2F
40
41/* CPU Features */
42#define CPU_FEATURE_MMX0x00000001// MMX Instruction Set
43#define CPU_FEATURE_SSE0x00000002// SSE Instruction Set
44#define CPU_FEATURE_SSE20x00000004// SSE2 Instruction Set
45#define CPU_FEATURE_SSE30x00000008// SSE3 Instruction Set
46#define CPU_FEATURE_SSE410x00000010// SSE41 Instruction Set
47#define CPU_FEATURE_SSE420x00000020// SSE42 Instruction Set
48#define CPU_FEATURE_EM64T0x00000040// 64Bit Support
49#define CPU_FEATURE_HTT0x00000080// HyperThreading
50#define CPU_FEATURE_MOBILE0x00000100// Mobile CPU
51#define CPU_FEATURE_MSR0x00000200// MSR Support
52
53/* SMBIOS Memory Types */
54#define SMB_MEM_TYPE_UNDEFINED0
55#define SMB_MEM_TYPE_OTHER1
56#define SMB_MEM_TYPE_UNKNOWN2
57#define SMB_MEM_TYPE_DRAM3
58#define SMB_MEM_TYPE_EDRAM4
59#define SMB_MEM_TYPE_VRAM5
60#define SMB_MEM_TYPE_SRAM6
61#define SMB_MEM_TYPE_RAM7
62#define SMB_MEM_TYPE_ROM8
63#define SMB_MEM_TYPE_FLASH9
64#define SMB_MEM_TYPE_EEPROM10
65#define SMB_MEM_TYPE_FEPROM11
66#define SMB_MEM_TYPE_EPROM12
67#define SMB_MEM_TYPE_CDRAM13
68#define SMB_MEM_TYPE_3DRAM14
69#define SMB_MEM_TYPE_SDRAM15
70#define SMB_MEM_TYPE_SGRAM16
71#define SMB_MEM_TYPE_RDRAM17
72#define SMB_MEM_TYPE_DDR18
73#define SMB_MEM_TYPE_DDR219
74#define SMB_MEM_TYPE_FBDIMM20
75#define SMB_MEM_TYPE_DDR324// Supported in 10.5.6+ AppleSMBIOS
76
77/* Memory Configuration Types */
78#define SMB_MEM_CHANNEL_UNKNOWN0
79#define SMB_MEM_CHANNEL_SINGLE1
80#define SMB_MEM_CHANNEL_DUAL2
81#define SMB_MEM_CHANNEL_TRIPLE3
82
83/* Maximum number of ram slots */
84#define MAX_RAM_SLOTS8
85#define RAM_SLOT_ENUMERATOR{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}
86
87/* Maximum number of SPD bytes */
88#define MAX_SPD_SIZE256
89
90/* Size of SMBIOS UUID in bytes */
91#define UUID_LEN16
92
93typedef struct _RamSlotInfo_t {
94 uint32_tModuleSize;// Size of Module in MB
95 uint32_tFrequency;// in Mhz
96 const char*Vendor;
97 const char*PartNo;
98 const char*SerialNo;
99 char*spd;// SPD Dump
100 boolInUse;
101 uint8_tType;
102 uint8_tBankConnections;// table type 6, see (3.3.7)
103 uint8_tBankConnCnt;
104} RamSlotInfo_t;
105
106typedef struct _PlatformInfo_t {
107struct CPU {
108uint32_tFeatures;// CPU Features like MMX, SSE2, VT, MobileCPU
109uint32_tVendor;// Vendor
110uint32_tSignature;// Signature
111uint32_tStepping;// Stepping
112uint32_tModel;// Model
113uint32_tExtModel;// Extended Model
114uint32_tFamily;// Family
115uint32_tExtFamily;// Extended Family
116uint32_tNoCores;// No Cores per Package
117uint32_tNoThreads;// Threads per Package
118uint8_tMaxCoef;// Max Multiplier
119uint8_tMaxDiv;
120uint8_tCurrCoef;// Current Multiplier
121uint8_tCurrDiv;
122uint64_tTSCFrequency;// TSC Frequency Hz
123uint64_tFSBFrequency;// FSB Frequency Hz
124uint64_tCPUFrequency;// CPU Frequency Hz
125uint32_tMaxRatio;// Max Bus Ratio
126uint32_tMinRatio;// Min Bus Ratio
127charBrandString[48];// 48 Byte Branding String
128uint32_tCPUID[CPUID_MAX][4];// CPUID 0..4, 80..81 Raw Values
129} CPU;
130
131struct RAM {
132uint64_tFrequency;// Ram Frequency
133uint32_tDivider;// Memory divider
134uint8_tCAS;// CAS 1/2/2.5/3/4/5/6/7
135uint8_tTRC;
136uint8_tTRP;
137uint8_tRAS;
138uint8_tChannels;// Channel Configuration Single,Dual or Triple
139uint8_tNoSlots;// Maximum no of slots available
140uint8_tType;// Standard SMBIOS v2.5 Memory Type
141RamSlotInfo_tDIMM[MAX_RAM_SLOTS];// Information about each slot
142} RAM;
143
144struct DMI {
145intMaxMemorySlots;// number of memory slots populated by SMBIOS
146intCntMemorySlots;// number of memory slots counted
147intMemoryModules;// number of memory modules installed
148intDIMM[MAX_RAM_SLOTS];// Information and SPD mapping for each slot
149} DMI;
150
151uint8_tType; // System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)
152uint8_t*UUID;
153} PlatformInfo_t;
154
155extern PlatformInfo_t Platform;
156
157#endif /* !__LIBSAIO_PLATFORM_H */
158

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Created: 8 years 7 months ago by Fumo Mofu