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View platform.h

1/*␊
2 * platform.h␊
3 * AsereBLN: reworked and extended␊
4 *␊
5 */␊
6␊
7#ifndef __LIBSAIO_PLATFORM_H␊
8#define __LIBSAIO_PLATFORM_H␊
9␊
10//#include "libsaio.h"␊
11␊
12extern bool platformCPUFeature(uint32_t);␊
13extern void scan_platform(void);␊
14extern void dumpPhysAddr(const char * title, void * a, int len);␊
15␊
16/* CPUID index into cpuid_raw */␊
17#define CPUID_0␉␉␉␉0␊
18#define CPUID_1␉␉␉␉1␊
19#define CPUID_2␉␉␉␉2␊
20#define CPUID_3␉␉␉␉3␊
21#define CPUID_4␉␉␉␉4␊
22#define CPUID_80␉␉␉5␊
23#define CPUID_81␉␉␉6␊
24#define CPUID_88␉␉␉7␊
25#define CPUID_MAX␉␉␉8␊
26␊
27#define CPU_MODEL_YONAH␉␉␉0x0E␉␉␉// Sossaman, Yonah␊
28#define CPU_MODEL_MEROM␉␉␉0x0F␉␉␉// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom␊
29#define CPU_MODEL_PENRYN␉␉0x17␉␉␉// Wolfdale, Yorkfield, Harpertown, Penryn␊
30#define CPU_MODEL_NEHALEM␉␉0x1A␉␉␉// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown␊
31#define CPU_MODEL_ATOM␉␉␉0x1C␉␉␉// Atom␊
32#define CPU_MODEL_FIELDS␉␉0x1E␉␉␉// Lynnfield, Clarksfield, Jasper Forest␊
33#define CPU_MODEL_DALES␉␉␉0x1F␉␉␉// Havendale, Auburndale␊
34#define CPU_MODEL_DALES_32NM␉0x25␉␉␉// Clarkdale, Arrandale␊
35#define CPU_MODEL_SANDY␉␉␉0x2A␉␉␉// Sandy Bridge␊
36#define CPU_MODEL_WESTMERE␉␉0x2C␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊
37#define CPU_MODEL_SANDY_XEON␉0x2D␉␉␉// Sandy Bridge Xeon␊
38#define CPU_MODEL_NEHALEM_EX␉0x2E␉␉␉// Beckton␊
39#define CPU_MODEL_WESTMERE_EX␉0x2F␊
40␊
41/* CPU Features */␊
42#define CPU_FEATURE_MMX␉␉␉0x00000001␉␉// MMX Instruction Set␊
43#define CPU_FEATURE_SSE␉␉␉0x00000002␉␉// SSE Instruction Set␊
44#define CPU_FEATURE_SSE2␉␉0x00000004␉␉// SSE2 Instruction Set␊
45#define CPU_FEATURE_SSE3␉␉0x00000008␉␉// SSE3 Instruction Set␊
46#define CPU_FEATURE_SSE41␉␉0x00000010␉␉// SSE41 Instruction Set␊
47#define CPU_FEATURE_SSE42␉␉0x00000020␉␉// SSE42 Instruction Set␊
48#define CPU_FEATURE_EM64T␉␉0x00000040␉␉// 64Bit Support␊
49#define CPU_FEATURE_HTT␉␉␉0x00000080␉␉// HyperThreading␊
50#define CPU_FEATURE_MOBILE␉␉0x00000100␉␉// Mobile CPU␊
51#define CPU_FEATURE_MSR␉␉␉0x00000200␉␉// MSR Support␊
52␊
53/* SMBIOS Memory Types */ ␊
54#define SMB_MEM_TYPE_UNDEFINED␉0␊
55#define SMB_MEM_TYPE_OTHER␉␉1␊
56#define SMB_MEM_TYPE_UNKNOWN␉2␊
57#define SMB_MEM_TYPE_DRAM␉␉3␊
58#define SMB_MEM_TYPE_EDRAM␉␉4␊
59#define SMB_MEM_TYPE_VRAM␉␉5␊
60#define SMB_MEM_TYPE_SRAM␉␉6␊
61#define SMB_MEM_TYPE_RAM␉␉7␊
62#define SMB_MEM_TYPE_ROM␉␉8␊
63#define SMB_MEM_TYPE_FLASH␉␉9␊
64#define SMB_MEM_TYPE_EEPROM␉␉10␊
65#define SMB_MEM_TYPE_FEPROM␉␉11␊
66#define SMB_MEM_TYPE_EPROM␉␉12␊
67#define SMB_MEM_TYPE_CDRAM␉␉13␊
68#define SMB_MEM_TYPE_3DRAM␉␉14␊
69#define SMB_MEM_TYPE_SDRAM␉␉15␊
70#define SMB_MEM_TYPE_SGRAM␉␉16␊
71#define SMB_MEM_TYPE_RDRAM␉␉17␊
72#define SMB_MEM_TYPE_DDR␉␉18␊
73#define SMB_MEM_TYPE_DDR2␉␉19␊
74#define SMB_MEM_TYPE_FBDIMM␉␉20␊
75#define SMB_MEM_TYPE_DDR3␉␉24␉␉␉␉// Supported in 10.5.6+ AppleSMBIOS␊
76␊
77/* Memory Configuration Types */ ␊
78#define SMB_MEM_CHANNEL_UNKNOWN␉␉0␊
79#define SMB_MEM_CHANNEL_SINGLE␉␉1␊
80#define SMB_MEM_CHANNEL_DUAL␉␉2␊
81#define SMB_MEM_CHANNEL_TRIPLE␉␉3␊
82␊
83/* Maximum number of ram slots */␊
84#define MAX_RAM_SLOTS␉␉␉8␊
85#define RAM_SLOT_ENUMERATOR␉␉{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}␊
86␊
87/* Maximum number of SPD bytes */␊
88#define MAX_SPD_SIZE␉␉␉256␊
89␊
90/* Size of SMBIOS UUID in bytes */␊
91#define UUID_LEN␉␉␉16␊
92␊
93typedef struct _RamSlotInfo_t {␊
94 uint32_t␉␉ModuleSize;␉␉␉␉␉// Size of Module in MB␊
95 uint32_t␉␉Frequency;␉␉␉␉␉// in Mhz␊
96 const char*␉␉Vendor;␊
97 const char*␉␉PartNo;␊
98 const char*␉␉SerialNo;␊
99 char*␉␉␉spd;␉␉␉␉␉␉// SPD Dump␊
100 bool␉␉␉InUse;␊
101 uint8_t␉␉␉Type;␊
102 uint8_t␉␉␉BankConnections;␉␉␉// table type 6, see (3.3.7)␊
103 uint8_t␉␉␉BankConnCnt;␊
104} RamSlotInfo_t;␊
105␊
106typedef struct _PlatformInfo_t {␊
107␉struct CPU {␊
108␉␉uint32_t␉␉Features;␉␉␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊
109␉␉uint32_t␉␉Vendor;␉␉␉␉␉// Vendor␊
110␉␉uint32_t␉␉Signature;␉␉␉␉// Signature␊
111␉␉uint32_t␉␉Stepping;␉␉␉␉// Stepping␊
112␉␉uint32_t␉␉Model;␉␉␉␉␉// Model␊
113␉␉uint32_t␉␉ExtModel;␉␉␉␉// Extended Model␊
114␉␉uint32_t␉␉Family;␉␉␉␉␉// Family␊
115␉␉uint32_t␉␉ExtFamily;␉␉␉␉// Extended Family␊
116␉␉uint32_t␉␉NoCores;␉␉␉␉// No Cores per Package␊
117␉␉uint32_t␉␉NoThreads;␉␉␉␉// Threads per Package␊
118␉␉uint8_t␉␉␉MaxCoef;␉␉␉␉// Max Multiplier␊
119␉␉uint8_t␉␉␉MaxDiv;␊
120␉␉uint8_t␉␉␉CurrCoef;␉␉␉␉// Current Multiplier␊
121␉␉uint8_t␉␉␉CurrDiv;␊
122␉␉uint64_t␉␉TSCFrequency;␉␉␉// TSC Frequency Hz␊
123␉␉uint64_t␉␉FSBFrequency;␉␉␉// FSB Frequency Hz␊
124␉␉uint64_t␉␉CPUFrequency;␉␉␉// CPU Frequency Hz␊
125␉␉uint32_t␉␉MaxRatio;␉␉␉␉// Max Bus Ratio␊
126␉␉uint32_t␉␉MinRatio;␉␉␉␉// Min Bus Ratio␊
127␉␉char␉␉␉BrandString[48];␉␉// 48 Byte Branding String␊
128␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊
129␉} CPU;␊
130␉␊
131␉struct RAM {␊
132␉␉uint64_t␉␉Frequency;␉␉␉␉// Ram Frequency␊
133␉␉uint32_t␉␉Divider;␉␉␉␉// Memory divider␊
134␉␉uint8_t␉␉␉CAS;␉␉␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊
135␉␉uint8_t␉␉␉TRC;␉␉␉␉␉␊
136␉␉uint8_t␉␉␉TRP;␊
137␉␉uint8_t␉␉␉RAS;␊
138␉␉uint8_t␉␉␉Channels;␉␉␉␉// Channel Configuration Single,Dual or Triple␊
139␉␉uint8_t␉␉␉NoSlots;␉␉␉␉// Maximum no of slots available␊
140␉␉uint8_t␉␉␉Type;␉␉␉␉␉// Standard SMBIOS v2.5 Memory Type␊
141␉␉RamSlotInfo_t␉DIMM[MAX_RAM_SLOTS];␉// Information about each slot␊
142␉} RAM;␊
143␉␊
144␉struct DMI {␊
145␉␉int␉␉␉MaxMemorySlots;␉␉␉␉// number of memory slots populated by SMBIOS␊
146␉␉int␉␉␉CntMemorySlots;␉␉␉␉// number of memory slots counted␊
147␉␉int␉␉␉MemoryModules;␉␉␉␉// number of memory modules installed␊
148␉␉int␉␉␉DIMM[MAX_RAM_SLOTS];␉␉// Information and SPD mapping for each slot␊
149␉} DMI;␊
150␉␊
151␉uint8_t␉␉␉␉Type; // System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)␊
152␉uint8_t␉␉␉␉*UUID;␊
153} PlatformInfo_t;␊
154␊
155extern PlatformInfo_t Platform;␊
156␊
157#endif /* !__LIBSAIO_PLATFORM_H */␊
158

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Attachment to issue 92

Created: 12 years 9 months ago by Fumo Mofu