Chameleon

Chameleon Commit Details

Date:2011-06-25 18:16:39 (8 years 22 days ago)
Author:Evan Lojewski
Commit:1066
Parents: 1065
Message:Removing even more code...
Changes:
D/branches/rewrite/i386/libsaio/smbios_getters.h
D/branches/rewrite/i386/libsaio/fake_efi.h
D/branches/rewrite/i386/libsaio/device_inject.h
D/branches/rewrite/i386/libsaio/bootstruct.c
D/branches/rewrite/i386/libsaio/nvidia.c
D/branches/rewrite/i386/libsaio/ati.c
D/branches/rewrite/i386/libsaio/bootstruct.h
D/branches/rewrite/i386/libsaio/nvidia.h
D/branches/rewrite/i386/libsaio/acpi_patcher.c
D/branches/rewrite/i386/libsaio/acpi_patcher.h
D/branches/rewrite/i386/libsaio/pci_setup.c
D/branches/rewrite/i386/libsaio/smbios.c
D/branches/rewrite/i386/libsaio/smbios_decode.c
D/branches/rewrite/i386/libsaio/smbios.h
D/branches/rewrite/i386/libsaio/pci_root.c
D/branches/rewrite/i386/libsaio/ati_reg.h
D/branches/rewrite/i386/libsaio/pci_root.h
D/branches/rewrite/i386/libsaio/usb.c
D/branches/rewrite/i386/libsaio/smbios_getters.c
D/branches/rewrite/i386/libsaio/fake_efi.c
D/branches/rewrite/i386/libsaio/device_inject.c
M/branches/rewrite/i386/libsaio/xml.c
M/branches/rewrite/i386/libsaio/console.c
M/branches/rewrite/i386/boot2/boot.c
M/branches/rewrite/i386/libsaio/dram_controllers.c
M/branches/rewrite/i386/libsaio/sys.c
M/branches/rewrite/i386/boot2/mboot.c
M/branches/rewrite/i386/libsaio/allocate.c
M/branches/rewrite/i386/libsaio/platform.c
M/branches/rewrite/i386/libsaio/spd.c
M/branches/rewrite/i386/libsaio/cpu.c
M/branches/rewrite/i386/libsaio/disk.c
M/branches/rewrite/i386/libsaio/bios.h
M/branches/rewrite/i386/libsaio/pci.c
M/branches/rewrite/i386/boot2/modules.c
M/branches/rewrite/i386/libsaio/stringTable.c
M/branches/rewrite/i386/libsaio/biosfn.c

File differences

branches/rewrite/i386/libsaio/smbios_getters.h
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#include "libsaio.h"
#include "smbios.h"
#include "platform.h"
#include "pci.h"
#ifndef __LIBSAIO_SMBIOS_GETTERS_H
#define __LIBSAIO_SMBIOS_GETTERS_H
#define SMBIOS_RANGE_START 0x000F0000
#define SMBIOS_RANGE_END 0x000FFFFF
#define NOT_AVAILABLE"N/A"
typedef enum {
kSMBString,
kSMBByte,
kSMBWord,
kSMBDWord
//kSMBQWord
} SMBValueType;
typedef union {
const char*string;
uint8_tbyte;
uint16_tword;
uint32_tdword;
//uint64_tqword;
} returnType;
extern bool getProcessorInformationExternalClock(returnType *value);
extern bool getProcessorInformationMaximumClock(returnType *value);
extern bool getSMBOemProcessorBusSpeed(returnType *value);
extern bool getSMBOemProcessorType(returnType *value);
extern bool getSMBMemoryDeviceMemoryType(returnType *value);
extern bool getSMBMemoryDeviceMemorySpeed(returnType *value);
extern bool getSMBMemoryDeviceManufacturer(returnType *value);
extern bool getSMBMemoryDeviceSerialNumber(returnType *value);
extern bool getSMBMemoryDevicePartNumber(returnType *value);
SMBEntryPoint *getAddressOfSmbiosTable(void);
#endif /* !__LIBSAIO_SMBIOS_GETTERS_H */
branches/rewrite/i386/libsaio/fake_efi.h
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/*
* Copyright 2007 David F. Elliott. All rights reserved.
*/
#ifndef __LIBSAIO_FAKE_EFI_H
#define __LIBSAIO_FAKE_EFI_H
/* Set up space for up to 10 configuration table entries */
#define MAX_CONFIGURATION_TABLE_ENTRIES 10
extern void setupFakeEfi(void);
#endif /* !__LIBSAIO_FAKE_EFI_H */
branches/rewrite/i386/libsaio/bootstruct.c
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/*
* Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved.
*
* @APPLE_LICENSE_HEADER_START@
*
* Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights
* Reserved. This file contains Original Code and/or Modifications of
* Original Code as defined in and that are subject to the Apple Public
* Source License Version 2.0 (the "License").You may not use this file
* except in compliance with the License. Please obtain a copy of the
* License at http://www.apple.com/publicsource and read it before using
* this file.
*
* The Original Code and all software distributed under the License are
* distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the
* License for the specific language governing rights and limitations
* under the License.
*
* @APPLE_LICENSE_HEADER_END@
*/
/*
* Copyright 1993 NeXT, Inc.
* All rights reserved.
*/
#include "libsaio.h"
#include "bootstruct.h"
/*==========================================================================
* Initialize the structure of parameters passed to
* the kernel by the booter.
*/
boot_args*bootArgs;
boot_args_pre_lion*bootArgsPreLion;
PrivateBootInfo_t*bootInfo;
Node*gMemoryMapNode;
static char platformName[64];
void initKernBootStruct( void )
{
Node *node;
int nameLen;
static int init_done = 0;
if ( !init_done )
{
bootArgs = (boot_args *)malloc(sizeof(boot_args));
bootArgsPreLion = (boot_args_pre_lion *)malloc(sizeof(boot_args_pre_lion));
bootInfo = (PrivateBootInfo_t *)malloc(sizeof(PrivateBootInfo_t));
if (bootArgs == 0 || bootInfo == 0)
stop("Couldn't allocate boot info\n");
bzero(bootArgs, sizeof(boot_args));
bzero(bootArgsPreLion, sizeof(boot_args_pre_lion));
bzero(bootInfo, sizeof(PrivateBootInfo_t));
// Get system memory map. Also update the size of the
// conventional/extended memory for backwards compatibility.
bootInfo->memoryMapCount =
getMemoryMap( bootInfo->memoryMap, kMemoryMapCountMax,
(unsigned long *) &bootInfo->convmem,
(unsigned long *) &bootInfo->extmem );
if ( bootInfo->memoryMapCount == 0 )
{
// BIOS did not provide a memory map, systems with
// discontiguous memory or unusual memory hole locations
// may have problems.
bootInfo->convmem = getConventionalMemorySize();
bootInfo->extmem = getExtendedMemorySize();
}
bootInfo->configEnd = bootInfo->config;
bootArgs->Video.v_display = VGA_TEXT_MODE;
DT__Initialize();
node = DT__FindNode("/", true);
if (node == 0) {
stop("Couldn't create root node");
}
getPlatformName(platformName);
nameLen = strlen(platformName) + 1;
DT__AddProperty(node, "compatible", nameLen, platformName);
DT__AddProperty(node, "model", nameLen, platformName);
gMemoryMapNode = DT__FindNode("/chosen/memory-map", true);
bootArgs->Version = kBootArgsVersion;
bootArgs->Revision = kBootArgsRevision;
bootArgsPreLion->Version = kBootArgsPreLionVersion;
bootArgsPreLion->Revision = kBootArgsPreLionRevision;
init_done = 1;
}
}
/* Copy boot args after kernel and record address. */
void
reserveKernBootStruct(void)
{
if ((gMacOSVersion[0] == '1') && (gMacOSVersion[1] == '0')
&& (gMacOSVersion[2] == '.') && (gMacOSVersion[3] == '7'))
{
void *oldAddr = bootArgs;
bootArgs = (boot_args *)AllocateKernelMemory(sizeof(boot_args));
bcopy(oldAddr, bootArgs, sizeof(boot_args));
}
else
{
void *oldAddr = bootArgsPreLion;
bootArgsPreLion = (boot_args_pre_lion *)AllocateKernelMemory(sizeof(boot_args_pre_lion));
bcopy(oldAddr, bootArgsPreLion, sizeof(boot_args_pre_lion));
}
}
void
finalizeBootStruct(void)
{
uint32_t size;
void *addr;
int i;
EfiMemoryRange *memoryMap;
MemoryRange *range;
int memoryMapCount = bootInfo->memoryMapCount;
if (memoryMapCount == 0) {
// XXX could make a two-part map here
stop("Unable to convert memory map into proper format\n");
}
// convert memory map to boot_args memory map
memoryMap = (EfiMemoryRange *)AllocateKernelMemory(sizeof(EfiMemoryRange) * memoryMapCount);
bootArgs->MemoryMap = (uint32_t)memoryMap;
bootArgs->MemoryMapSize = sizeof(EfiMemoryRange) * memoryMapCount;
bootArgs->MemoryMapDescriptorSize = sizeof(EfiMemoryRange);
bootArgs->MemoryMapDescriptorVersion = 0;
for (i=0; i<memoryMapCount; i++, memoryMap++) {
range = &bootInfo->memoryMap[i];
switch(range->type) {
case kMemoryRangeACPI:
memoryMap->Type = kEfiACPIReclaimMemory;
break;
case kMemoryRangeNVS:
memoryMap->Type = kEfiACPIMemoryNVS;
break;
case kMemoryRangeUsable:
memoryMap->Type = kEfiConventionalMemory;
break;
case kMemoryRangeReserved:
default:
memoryMap->Type = kEfiReservedMemoryType;
break;
}
memoryMap->PhysicalStart = range->base;
memoryMap->VirtualStart = range->base;
memoryMap->NumberOfPages = range->length >> I386_PGSHIFT;
memoryMap->Attribute = 0;
}
// copy bootFile into device tree
// XXX
// add PCI info somehow into device tree
// XXX
// Flatten device tree
DT__FlattenDeviceTree(0, &size);
addr = (void *)AllocateKernelMemory(size);
if (addr == 0) {
stop("Couldn't allocate device tree\n");
}
DT__FlattenDeviceTree((void **)&addr, &size);
bootArgs->deviceTreeP = (uint32_t)addr;
bootArgs->deviceTreeLength = size;
// Copy BootArgs values to older structure
memcpy(&bootArgsPreLion->CommandLine, &bootArgs->CommandLine, BOOT_LINE_LENGTH);
memcpy(&bootArgsPreLion->Video, &bootArgs->Video, sizeof(Boot_Video));
bootArgsPreLion->MemoryMap = bootArgs->MemoryMap;
bootArgsPreLion->MemoryMapSize = bootArgs->MemoryMapSize;
bootArgsPreLion->MemoryMapDescriptorSize = bootArgs->MemoryMapDescriptorSize;
bootArgsPreLion->MemoryMapDescriptorVersion = bootArgs->MemoryMapDescriptorVersion;
bootArgsPreLion->deviceTreeP = bootArgs->deviceTreeP;
bootArgsPreLion->deviceTreeLength = bootArgs->deviceTreeLength;
bootArgsPreLion->kaddr = bootArgs->kaddr;
bootArgsPreLion->ksize = bootArgs->ksize;
bootArgsPreLion->efiRuntimeServicesPageStart = bootArgs->efiRuntimeServicesPageStart;
bootArgsPreLion->efiRuntimeServicesPageCount = bootArgs->efiRuntimeServicesPageCount;
bootArgsPreLion->efiSystemTable = bootArgs->efiSystemTable;
bootArgsPreLion->efiMode = bootArgs->efiMode;
bootArgsPreLion->performanceDataStart = bootArgs->performanceDataStart;
bootArgsPreLion->performanceDataSize = bootArgs->performanceDataSize;
bootArgsPreLion->efiRuntimeServicesVirtualPageStart = bootArgs->efiRuntimeServicesVirtualPageStart;
}
branches/rewrite/i386/libsaio/bootstruct.h
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/*
* Copyright (c) 2002-2003 Apple Computer, Inc. All rights reserved.
*
* @APPLE_LICENSE_HEADER_START@
*
* Portions Copyright (c) 2002-2003 Apple Computer, Inc. All Rights
* Reserved. This file contains Original Code and/or Modifications of
* Original Code as defined in and that are subject to the Apple Public
* Source License Version 2.0 (the "License"). You may not use this file
* except in compliance with the License. Please obtain a copy of the
* License at http://www.apple.com/publicsource and read it before using
* this file.
*
* The Original Code and all software distributed under the License are
* distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the
* License for the specific language governing rights and limitations
* under the License.
*
* @APPLE_LICENSE_HEADER_END@
*/
#ifndef __BOOTSTRUCT_H
#define __BOOTSTRUCT_H
#include "bootargs.h"
#include "saio_types.h"
#include "bios.h"
#include "device_tree.h"
/*!
Kernel boot args global also used by booter for its own data.
*/
extern boot_args *bootArgs;
extern boot_args_pre_lion *bootArgsPreLion;
extern Node *gMemoryMapNode;
#define VGA_TEXT_MODE 0
//defined in /usr/../boot.h
//#define GRAPHICS_MODE 1
//#define FB_TEXT_MODE 2
/*
* Maximum number of boot drivers that can be loaded.
*/
#define NDRIVERS 500
#define CONFIG_SIZE (40 * 4096)
/*
* Max size for config data array, in bytes.
*/
#define IO_CONFIG_DATA_SIZE163840
#define kMemoryMapCountMax 40
/*
* PCI bus information.
*/
typedef struct _PCI_bus_info_t {
union {
struct {
unsigned char configMethod1 :1;
unsigned char configMethod2 :1;
unsigned char :2;
unsigned char specialCycle1 :1;
unsigned char specialCycle2 :1;
} s;
unsigned char d;
} u_bus;
unsigned char maxBusNum;
unsigned char majorVersion;
unsigned char minorVersion;
unsigned char BIOSPresent;
} PCI_bus_info_t;
typedef struct {
unsigned long address; // address where driver was loaded
unsigned long size; // number of bytes
unsigned long type; // driver type
} driver_config_t;
/*
* INT15, E820h - Query System Address Map.
*
* Documented in ACPI Specification Rev 2.0,
* Chapter 15 (System Address Map Interfaces).
*/
/*
* ACPI defined memory range types.
*/
enum {
kMemoryRangeUsable = 1, // RAM usable by the OS.
kMemoryRangeReserved = 2, // Reserved. (Do not use)
kMemoryRangeACPI = 3, // ACPI tables. Can be reclaimed.
kMemoryRangeNVS = 4, // ACPI NVS memory. (Do not use)
/* Undefined types should be treated as kMemoryRangeReserved */
};
/*!
PrivateBootInfo has fields used by the booter that used to be part of
KernelBootArgs_t *bootArgs. When the switch was made to EFI the structure
completely changed to boot_args *bootArgs. This (new to boot-132) structure
contains the fields the kernel no longer cares about but the booter still
uses internally. Some fields (e.g. the video information) remain interesting
to the kernel and are thus located in bootArgs although with different field names.
*/
typedef struct PrivateBootInfo {
int convmem; // conventional memory
int extmem; // extended memory
#if 0
int numBootDrivers; // number of drivers loaded
#endif
char bootFile[128]; // kernel file name
unsigned long memoryMapCount;
MemoryRange memoryMap[kMemoryMapCountMax];
PCI_bus_info_t pciInfo;
#if 0
driver_config_t driverConfig[NDRIVERS];
#endif
char * configEnd; // pointer to end of config files
char config[CONFIG_SIZE];
config_file_t bootConfig; // boot.plist
config_file_t overrideConfig; // additional boot.plist which can override bootConfig keys
config_file_t themeConfig; // theme.plist
config_file_t smbiosConfig; // smbios.plist
config_file_t helperConfig; // boot helper partition's boot.plist
config_file_t ramdiskConfig; // RAMDisk.plist
bool memDetect;
} PrivateBootInfo_t;
extern PrivateBootInfo_t *bootInfo;
#endif /* __BOOTSTRUCT_H */
branches/rewrite/i386/libsaio/acpi_patcher.c
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/*
* Copyright 2008 mackerintel
*/
#include "libsaio.h"
#include "boot.h"
#include "bootstruct.h"
#include "acpi.h"
#include "efi_tables.h"
#include "fake_efi.h"
#include "acpi_patcher.h"
#include "platform.h"
#include "cpu.h"
#include "aml_generator.h"
#ifndef DEBUG_ACPI
#define DEBUG_ACPI 0
#endif
#if DEBUG_ACPI==2
#define DBG(x...) {printf(x); sleep(1);}
#elif DEBUG_ACPI==1
#define DBG(x...) printf(x)
#else
#define DBG(x...)
#endif
// Slice: New signature compare function
boolean_t tableSign(char *table, const char *sgn)
{
int i;
for (i=0; i<4; i++) {
if ((table[i] &~0x20) != (sgn[i] &~0x20)) {
return false;
}
}
return true;
}
/* Gets the ACPI 1.0 RSDP address */
static struct acpi_2_rsdp* getAddressOfAcpiTable()
{
/* TODO: Before searching the BIOS space we are supposed to search the first 1K of the EBDA */
void *acpi_addr = (void*)ACPI_RANGE_START;
for(; acpi_addr <= (void*)ACPI_RANGE_END; acpi_addr += 16)
{
if(*(uint64_t *)acpi_addr == ACPI_SIGNATURE_UINT64_LE)
{
uint8_t csum = checksum8(acpi_addr, 20);
if(csum == 0)
{
// Only return the table if it is a true version 1.0 table (Revision 0)
if(((struct acpi_2_rsdp*)acpi_addr)->Revision == 0)
return acpi_addr;
}
}
}
return NULL;
}
/* Gets the ACPI 2.0 RSDP address */
static struct acpi_2_rsdp* getAddressOfAcpi20Table()
{
/* TODO: Before searching the BIOS space we are supposed to search the first 1K of the EBDA */
void *acpi_addr = (void*)ACPI_RANGE_START;
for(; acpi_addr <= (void*)ACPI_RANGE_END; acpi_addr += 16)
{
if(*(uint64_t *)acpi_addr == ACPI_SIGNATURE_UINT64_LE)
{
uint8_t csum = checksum8(acpi_addr, 20);
/* Only assume this is a 2.0 or better table if the revision is greater than 0
* NOTE: ACPI 3.0 spec only seems to say that 1.0 tables have revision 1
* and that the current revision is 2.. I am going to assume that rev > 0 is 2.0.
*/
if(csum == 0 && (((struct acpi_2_rsdp*)acpi_addr)->Revision > 0))
{
uint8_t csum2 = checksum8(acpi_addr, sizeof(struct acpi_2_rsdp));
if(csum2 == 0)
return acpi_addr;
}
}
}
return NULL;
}
/** The folowing ACPI Table search algo. should be reused anywhere needed:*/
int search_and_get_acpi_fd(const char * filename, const char ** outDirspec)
{
int fd = 0;
char dirSpec[512] = "";
// Try finding 'filename' in the usual places
// Start searching any potential location for ACPI Table
sprintf(dirSpec, "%s", filename);
fd = open(dirSpec, 0);
if (fd < 0)
{
sprintf(dirSpec, "/Extra/%s", filename);
fd = open(dirSpec, 0);
if (fd < 0)
{
sprintf(dirSpec, "bt(0,0)/Extra/%s", filename);
fd = open(dirSpec, 0);
}
}
if (fd < 0)
{
// NOT FOUND:
verbose("ACPI table not found: %s\n", filename);
*dirSpec = '\0';
}
if (outDirspec) *outDirspec = dirSpec;
return fd;
}
void *loadACPITable (const char * filename)
{
void *tableAddr;
const char * dirspec=NULL;
int fd = search_and_get_acpi_fd(filename, &dirspec);
if (fd>=0)
{
tableAddr=(void*)AllocateKernelMemory(file_size (fd));
if (tableAddr)
{
if (read (fd, tableAddr, file_size (fd))!=file_size (fd))
{
printf("Couldn't read table %s\n",dirspec);
free (tableAddr);
close (fd);
return NULL;
}
DBG("Table %s read and stored at: %x\n", dirspec, tableAddr);
close (fd);
return tableAddr;
}
close (fd);
printf("Couldn't allocate memory for table \n", dirspec);
}
//printf("Couldn't find table %s\n", filename);
return NULL;
}
uint8_tacpi_cpu_count = 0;
char* acpi_cpu_name[32];
void get_acpi_cpu_names(unsigned char* dsdt, uint32_t length)
{
uint32_t i;
for (i=0; i<length-7; i++)
{
if (dsdt[i] == 0x5B && dsdt[i+1] == 0x83) // ProcessorOP
{
uint32_t offset = i + 3 + (dsdt[i+2] >> 6);
bool add_name = true;
uint8_t j;
for (j=0; j<4; j++)
{
char c = dsdt[offset+j];
if (!aml_isvalidchar(c))
{
add_name = false;
verbose("Invalid character found in ProcessorOP 0x%x!\n", c);
break;
}
}
if (add_name)
{
acpi_cpu_name[acpi_cpu_count] = malloc(4);
memcpy(acpi_cpu_name[acpi_cpu_count], dsdt+offset, 4);
i = offset + 5;
verbose("Found ACPI CPU: %c%c%c%c\n", acpi_cpu_name[acpi_cpu_count][0], acpi_cpu_name[acpi_cpu_count][1], acpi_cpu_name[acpi_cpu_count][2], acpi_cpu_name[acpi_cpu_count][3]);
if (++acpi_cpu_count == 32) return;
}
}
}
}
struct acpi_2_ssdt *generate_cst_ssdt(struct acpi_2_fadt* fadt)
{
char ssdt_header[] =
{
0x53, 0x53, 0x44, 0x54, 0xE7, 0x00, 0x00, 0x00, /* SSDT.... */
0x01, 0x17, 0x50, 0x6D, 0x52, 0x65, 0x66, 0x41, /* ..PmRefA */
0x43, 0x70, 0x75, 0x43, 0x73, 0x74, 0x00, 0x00, /* CpuCst.. */
0x00, 0x10, 0x00, 0x00, 0x49, 0x4E, 0x54, 0x4C, /* ....INTL */
0x31, 0x03, 0x10, 0x20 /* 1.._*/
};
char cstate_resource_template[] =
{
0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x7F,
0x01, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x79, 0x00
};
if (Platform.CPU.Vendor != 0x756E6547) {
verbose ("Not an Intel platform: C-States will not be generated !!!\n");
return NULL;
}
if (fadt == NULL) {
verbose ("FACP not exists: C-States will not be generated !!!\n");
return NULL;
}
struct acpi_2_dsdt* dsdt = (void*)fadt->DSDT;
if (dsdt == NULL) {
verbose ("DSDT not found: C-States will not be generated !!!\n");
return NULL;
}
if (acpi_cpu_count == 0)
get_acpi_cpu_names((void*)dsdt, dsdt->Length);
if (acpi_cpu_count > 0)
{
bool c2_enabled = false;
bool c3_enabled = false;
bool c4_enabled = false;
getBoolForKey(kEnableC2States, &c2_enabled, &bootInfo->bootConfig);
getBoolForKey(kEnableC3States, &c3_enabled, &bootInfo->bootConfig);
getBoolForKey(kEnableC4States, &c4_enabled, &bootInfo->bootConfig);
c2_enabled = c2_enabled | (fadt->C2_Latency < 100);
c3_enabled = c3_enabled | (fadt->C3_Latency < 1000);
unsigned char cstates_count = 1 + (c2_enabled ? 1 : 0) + (c3_enabled ? 1 : 0);
struct aml_chunk* root = aml_create_node(NULL);
aml_add_buffer(root, ssdt_header, sizeof(ssdt_header)); // SSDT header
struct aml_chunk* scop = aml_add_scope(root, "\\_PR_");
struct aml_chunk* name = aml_add_name(scop, "CST_");
struct aml_chunk* pack = aml_add_package(name);
aml_add_byte(pack, cstates_count);
struct aml_chunk* tmpl = aml_add_package(pack);
cstate_resource_template[11] = 0x00; // C1
aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template));
aml_add_byte(tmpl, 0x01); // C1
aml_add_byte(tmpl, 0x01); // Latency
aml_add_word(tmpl, 0x03e8); // Power
// C2
if (c2_enabled)
{
tmpl = aml_add_package(pack);
cstate_resource_template[11] = 0x10; // C2
aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template));
aml_add_byte(tmpl, 0x02); // C2
aml_add_byte(tmpl, fadt->C2_Latency);
aml_add_word(tmpl, 0x01f4); // Power
}
// C4
if (c4_enabled)
{
tmpl = aml_add_package(pack);
cstate_resource_template[11] = 0x30; // C4
aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template));
aml_add_byte(tmpl, 0x04); // C4
aml_add_word(tmpl, fadt->C3_Latency / 2); // TODO: right latency for C4
aml_add_byte(tmpl, 0xfa); // Power
}
else
// C3
if (c3_enabled)
{
tmpl = aml_add_package(pack);
cstate_resource_template[11] = 0x20; // C3
aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template));
aml_add_byte(tmpl, 0x03); // C3
aml_add_word(tmpl, fadt->C3_Latency);
aml_add_word(tmpl, 0x015e); // Power
}
// Aliaces
int i;
for (i = 0; i < acpi_cpu_count; i++)
{
char name[9];
sprintf(name, "_PR_%c%c%c%c", acpi_cpu_name[i][0], acpi_cpu_name[i][1], acpi_cpu_name[i][2], acpi_cpu_name[i][3]);
scop = aml_add_scope(root, name);
aml_add_alias(scop, "CST_", "_CST");
}
aml_calculate_size(root);
struct acpi_2_ssdt *ssdt = (struct acpi_2_ssdt *)AllocateKernelMemory(root->Size);
aml_write_node(root, (void*)ssdt, 0);
ssdt->Length = root->Size;
ssdt->Checksum = 0;
ssdt->Checksum = 256 - checksum8(ssdt, ssdt->Length);
aml_destroy_node(root);
//dumpPhysAddr("C-States SSDT content: ", ssdt, ssdt->Length);
verbose ("SSDT with CPU C-States generated successfully\n");
return ssdt;
}
else
{
verbose ("ACPI CPUs not found: C-States not generated !!!\n");
}
return NULL;
}
struct acpi_2_ssdt *generate_pss_ssdt(struct acpi_2_dsdt* dsdt)
{
char ssdt_header[] =
{
0x53, 0x53, 0x44, 0x54, 0x7E, 0x00, 0x00, 0x00, /* SSDT.... */
0x01, 0x6A, 0x50, 0x6D, 0x52, 0x65, 0x66, 0x00, /* ..PmRef. */
0x43, 0x70, 0x75, 0x50, 0x6D, 0x00, 0x00, 0x00, /* CpuPm... */
0x00, 0x30, 0x00, 0x00, 0x49, 0x4E, 0x54, 0x4C, /* .0..INTL */
0x31, 0x03, 0x10, 0x20,/* 1.._*/
};
if (Platform.CPU.Vendor != 0x756E6547) {
verbose ("Not an Intel platform: P-States will not be generated !!!\n");
return NULL;
}
if (!(Platform.CPU.Features & CPU_FEATURE_MSR)) {
verbose ("Unsupported CPU: P-States will not be generated !!!\n");
return NULL;
}
if (acpi_cpu_count == 0)
get_acpi_cpu_names((void*)dsdt, dsdt->Length);
if (acpi_cpu_count > 0)
{
struct p_state initial, maximum, minimum, p_states[32];
uint8_t p_states_count = 0;
// Retrieving P-States, ported from code by superhai (c)
switch (Platform.CPU.Family) {
case 0x06:
{
switch (Platform.CPU.Model)
{
case 0x0D:// ???
case CPU_MODEL_YONAH:// Intel Mobile Core Solo, Duo
case CPU_MODEL_MEROM:// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx
case CPU_MODEL_PENRYN:// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx
case CPU_MODEL_ATOM:// Intel Atom (45nm)
{
bool cpu_dynamic_fsb = false;
if (rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 27))
{
wrmsr64(MSR_IA32_EXT_CONFIG, (rdmsr64(MSR_IA32_EXT_CONFIG) | (1 << 28)));
delay(1);
cpu_dynamic_fsb = rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 28);
}
bool cpu_noninteger_bus_ratio = (rdmsr64(MSR_IA32_PERF_STATUS) & (1ULL << 46));
initial.Control = rdmsr64(MSR_IA32_PERF_STATUS);
maximum.Control = ((rdmsr64(MSR_IA32_PERF_STATUS) >> 32) & 0x1F3F) | (0x4000 * cpu_noninteger_bus_ratio);
maximum.CID = ((maximum.FID & 0x1F) << 1) | cpu_noninteger_bus_ratio;
minimum.FID = ((rdmsr64(MSR_IA32_PERF_STATUS) >> 24) & 0x1F) | (0x80 * cpu_dynamic_fsb);
minimum.VID = ((rdmsr64(MSR_IA32_PERF_STATUS) >> 48) & 0x3F);
if (minimum.FID == 0)
{
uint64_t msr;
uint8_t i;
// Probe for lowest fid
for (i = maximum.FID; i >= 0x6; i--)
{
msr = rdmsr64(MSR_IA32_PERF_CONTROL);
wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (i << 8) | minimum.VID);
intel_waitforsts();
minimum.FID = (rdmsr64(MSR_IA32_PERF_STATUS) >> 8) & 0x1F;
delay(1);
}
msr = rdmsr64(MSR_IA32_PERF_CONTROL);
wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (maximum.FID << 8) | maximum.VID);
intel_waitforsts();
}
if (minimum.VID == maximum.VID)
{
uint64_t msr;
uint8_t i;
// Probe for lowest vid
for (i = maximum.VID; i > 0xA; i--)
{
msr = rdmsr64(MSR_IA32_PERF_CONTROL);
wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (minimum.FID << 8) | i);
intel_waitforsts();
minimum.VID = rdmsr64(MSR_IA32_PERF_STATUS) & 0x3F;
delay(1);
}
msr = rdmsr64(MSR_IA32_PERF_CONTROL);
wrmsr64(MSR_IA32_PERF_CONTROL, (msr & 0xFFFFFFFFFFFF0000ULL) | (maximum.FID << 8) | maximum.VID);
intel_waitforsts();
}
minimum.CID = ((minimum.FID & 0x1F) << 1) >> cpu_dynamic_fsb;
// Sanity check
if (maximum.CID < minimum.CID)
{
DBG("Insane FID values!");
p_states_count = 0;
}
else
{
// Finalize P-States
// Find how many P-States machine supports
p_states_count = maximum.CID - minimum.CID + 1;
if (p_states_count > 32)
p_states_count = 32;
uint8_t vidstep;
uint8_t i = 0, u, invalid = 0;
vidstep = ((maximum.VID << 2) - (minimum.VID << 2)) / (p_states_count - 1);
for (u = 0; u < p_states_count; u++)
{
i = u - invalid;
p_states[i].CID = maximum.CID - u;
p_states[i].FID = (p_states[i].CID >> 1);
if (p_states[i].FID < 0x6)
{
if (cpu_dynamic_fsb)
p_states[i].FID = (p_states[i].FID << 1) | 0x80;
}
else if (cpu_noninteger_bus_ratio)
{
p_states[i].FID = p_states[i].FID | (0x40 * (p_states[i].CID & 0x1));
}
if (i && p_states[i].FID == p_states[i-1].FID)
invalid++;
p_states[i].VID = ((maximum.VID << 2) - (vidstep * u)) >> 2;
uint32_t multiplier = p_states[i].FID & 0x1f;// = 0x08
bool half = p_states[i].FID & 0x40;// = 0x01
bool dfsb = p_states[i].FID & 0x80;// = 0x00
uint32_t fsb = Platform.CPU.FSBFrequency / 1000000; // = 400
uint32_t halffsb = (fsb + 1) >> 1;// = 200
uint32_t frequency = (multiplier * fsb);// = 3200
p_states[i].Frequency = (frequency + (half * halffsb)) >> dfsb;// = 3200 + 200 = 3400
}
p_states_count -= invalid;
}
break;
}
case CPU_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
case CPU_MODEL_NEHALEM:// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x
case CPU_MODEL_WESTMERE:// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
case CPU_MODEL_SANDY:// Intel Core i3, i5, i7 LGA1155 (32nm)
case CPU_MODEL_SANDY_XEON:// Intel Xeon E3
{
maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; // Seems it always contains maximum multiplier value (with turbo, that's we need)...
minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff;
verbose("P-States: min 0x%x, max 0x%x\n", minimum.Control, maximum.Control);
// Sanity check
if (maximum.Control < minimum.Control)
{
DBG("Insane control values!");
p_states_count = 0;
}
else
{
uint8_t i;
p_states_count = 0;
for (i = maximum.Control; i >= minimum.Control; i--)
{
p_states[p_states_count].Control = i;
p_states[p_states_count].CID = p_states[p_states_count].Control << 1;
p_states[p_states_count].Frequency = (Platform.CPU.FSBFrequency / 1000000) * i;
p_states_count++;
}
}
break;
}
default:
verbose ("Unsupported CPU: P-States not generated !!!\n");
break;
}
}
}
// Generating SSDT
if (p_states_count > 0)
{
int i;
struct aml_chunk* root = aml_create_node(NULL);
aml_add_buffer(root, ssdt_header, sizeof(ssdt_header)); // SSDT header
struct aml_chunk* scop = aml_add_scope(root, "\\_PR_");
struct aml_chunk* name = aml_add_name(scop, "PSS_");
struct aml_chunk* pack = aml_add_package(name);
for (i = 0; i < p_states_count; i++)
{
struct aml_chunk* pstt = aml_add_package(pack);
aml_add_dword(pstt, p_states[i].Frequency);
aml_add_dword(pstt, 0x00000000); // Power
aml_add_dword(pstt, 0x0000000A); // Latency
aml_add_dword(pstt, 0x0000000A); // Latency
aml_add_dword(pstt, p_states[i].Control);
aml_add_dword(pstt, i+1); // Status
}
// Add aliaces
for (i = 0; i < acpi_cpu_count; i++)
{
char name[9];
sprintf(name, "_PR_%c%c%c%c", acpi_cpu_name[i][0], acpi_cpu_name[i][1], acpi_cpu_name[i][2], acpi_cpu_name[i][3]);
scop = aml_add_scope(root, name);
aml_add_alias(scop, "PSS_", "_PSS");
}
aml_calculate_size(root);
struct acpi_2_ssdt *ssdt = (struct acpi_2_ssdt *)AllocateKernelMemory(root->Size);
aml_write_node(root, (void*)ssdt, 0);
ssdt->Length = root->Size;
ssdt->Checksum = 0;
ssdt->Checksum = 256 - checksum8(ssdt, ssdt->Length);
aml_destroy_node(root);
//dumpPhysAddr("P-States SSDT content: ", ssdt, ssdt->Length);
verbose ("SSDT with CPU P-States generated successfully\n");
return ssdt;
}
}
else
{
verbose ("ACPI CPUs not found: P-States not generated !!!\n");
}
return NULL;
}
struct acpi_2_fadt *patch_fadt(struct acpi_2_fadt *fadt, struct acpi_2_dsdt *new_dsdt)
{
extern void setupSystemType();
struct acpi_2_fadt *fadt_mod;
bool fadt_rev2_needed = false;
bool fix_restart;
const char * value;
// Restart Fix
if (Platform.CPU.Vendor == 0x756E6547) {/* Intel */
fix_restart = true;
getBoolForKey(kRestartFix, &fix_restart, &bootInfo->bootConfig);
} else {
verbose ("Not an Intel platform: Restart Fix not applied !!!\n");
fix_restart = false;
}
if (fix_restart) fadt_rev2_needed = true;
// Allocate new fadt table
if (fadt->Length < 0x84 && fadt_rev2_needed)
{
fadt_mod=(struct acpi_2_fadt *)AllocateKernelMemory(0x84);
memcpy(fadt_mod, fadt, fadt->Length);
fadt_mod->Length = 0x84;
fadt_mod->Revision = 0x02; // FADT rev 2 (ACPI 1.0B MS extensions)
}
else
{
fadt_mod=(struct acpi_2_fadt *)AllocateKernelMemory(fadt->Length);
memcpy(fadt_mod, fadt, fadt->Length);
}
// Determine system type / PM_Model
if ( (value=getStringForKey(kSystemType, &bootInfo->bootConfig))!=NULL)
{
if (Platform.Type > 6)
{
if(fadt_mod->PM_Profile<=6)
Platform.Type = fadt_mod->PM_Profile; // get the fadt if correct
else
Platform.Type = 1;/* Set a fixed value (Desktop) */
verbose("Error: system-type must be 0..6. Defaulting to %d !\n", Platform.Type);
}
else
Platform.Type = (unsigned char) strtoul(value, NULL, 10);
}
// Set PM_Profile from System-type if only user wanted this value to be forced
if (fadt_mod->PM_Profile != Platform.Type)
{
if (value)
{ // user has overriden the SystemType so take care of it in FACP
verbose("FADT: changing PM_Profile from 0x%02x to 0x%02x\n", fadt_mod->PM_Profile, Platform.Type);
fadt_mod->PM_Profile = Platform.Type;
}
else
{ // PM_Profile has a different value and no override has been set, so reflect the user value to ioregs
Platform.Type = fadt_mod->PM_Profile <= 6 ? fadt_mod->PM_Profile : 1;
}
}
// We now have to write the systemm-type in ioregs: we cannot do it before in setupDeviceTree()
// because we need to take care of facp original content, if it is correct.
setupSystemType();
// Patch FADT to fix restart
if (fix_restart)
{
fadt_mod->Flags|= 0x400;
fadt_mod->Reset_SpaceID= 0x01; // System I/O
fadt_mod->Reset_BitWidth= 0x08; // 1 byte
fadt_mod->Reset_BitOffset= 0x00; // Offset 0
fadt_mod->Reset_AccessWidth= 0x01; // Byte access
fadt_mod->Reset_Address= 0x0cf9; // Address of the register
fadt_mod->Reset_Value= 0x06; // Value to write to reset the system
verbose("FADT: Restart Fix applied!\n");
}
// Patch DSDT Address if we have loaded DSDT.aml
if(new_dsdt)
{
DBG("DSDT: Old @%x,%x, ",fadt_mod->DSDT,fadt_mod->X_DSDT);
fadt_mod->DSDT=(uint32_t)new_dsdt;
if ((uint32_t)(&(fadt_mod->X_DSDT))-(uint32_t)fadt_mod+8<=fadt_mod->Length)
fadt_mod->X_DSDT=(uint32_t)new_dsdt;
DBG("New @%x,%x\n",fadt_mod->DSDT,fadt_mod->X_DSDT);
verbose("FADT: Using custom DSDT!\n");
}
// Correct the checksum
fadt_mod->Checksum=0;
fadt_mod->Checksum=256-checksum8(fadt_mod,fadt_mod->Length);
return fadt_mod;
}
/* Setup ACPI without replacing DSDT. */
int setupAcpiNoMod()
{
//addConfigurationTable(&gEfiAcpiTableGuid, getAddressOfAcpiTable(), "ACPI");
//addConfigurationTable(&gEfiAcpi20TableGuid, getAddressOfAcpi20Table(), "ACPI_20");
/* XXX aserebln why uint32 cast if pointer is uint64 ? */
acpi10_p = (uint32_t)getAddressOfAcpiTable();
acpi20_p = (uint32_t)getAddressOfAcpi20Table();
addConfigurationTable(&gEfiAcpiTableGuid, &acpi10_p, "ACPI");
if(acpi20_p) addConfigurationTable(&gEfiAcpi20TableGuid, &acpi20_p, "ACPI_20");
return 1;
}
/* Setup ACPI. Replace DSDT if DSDT.aml is found */
int setupAcpi(void)
{
int version;
void *new_dsdt;
const char *filename;
char dirSpec[128];
int len = 0;
// Try using the file specified with the DSDT option
if (getValueForKey(kDSDT, &filename, &len, &bootInfo->bootConfig))
{
sprintf(dirSpec, filename);
}
else
{
sprintf(dirSpec, "DSDT.aml");
}
// Load replacement DSDT
new_dsdt = loadACPITable(dirSpec);
// Mozodojo: going to patch FACP and load SSDT's even if DSDT.aml is not present
/*if (!new_dsdt)
{
return setupAcpiNoMod();
}*/
// Mozodojo: Load additional SSDTs
struct acpi_2_ssdt *new_ssdt[32]; // 30 + 2 additional tables for pss & cst
int ssdt_count=0;
// SSDT Options
bool drop_ssdt=false, generate_pstates=false, generate_cstates=false;
getBoolForKey(kDropSSDT, &drop_ssdt, &bootInfo->bootConfig);
getBoolForKey(kGeneratePStates, &generate_pstates, &bootInfo->bootConfig);
getBoolForKey(kGenerateCStates, &generate_cstates, &bootInfo->bootConfig);
{
int i;
for (i=0; i<30; i++)
{
char filename[512];
sprintf(filename, i>0?"SSDT-%d.aml":"SSDT.aml", i);
if(new_ssdt[ssdt_count] = loadACPITable(filename))
{
ssdt_count++;
}
else
{
break;
}
}
}
// Do the same procedure for both versions of ACPI
for (version=0; version<2; version++) {
struct acpi_2_rsdp *rsdp, *rsdp_mod;
struct acpi_2_rsdt *rsdt, *rsdt_mod;
int rsdplength;
// Find original rsdp
rsdp=(struct acpi_2_rsdp *)(version?getAddressOfAcpi20Table():getAddressOfAcpiTable());
if (!rsdp)
{
DBG("No ACPI version %d found. Ignoring\n", version+1);
if (version)
addConfigurationTable(&gEfiAcpi20TableGuid, NULL, "ACPI_20");
else
addConfigurationTable(&gEfiAcpiTableGuid, NULL, "ACPI");
continue;
}
rsdplength=version?rsdp->Length:20;
DBG("RSDP version %d found @%x. Length=%d\n",version+1,rsdp,rsdplength);
/* FIXME: no check that memory allocation succeeded
* Copy and patch RSDP,RSDT, XSDT and FADT
* For more info see ACPI Specification pages 110 and following
*/
rsdp_mod=(struct acpi_2_rsdp *) AllocateKernelMemory(rsdplength);
memcpy(rsdp_mod, rsdp, rsdplength);
rsdt=(struct acpi_2_rsdt *)(rsdp->RsdtAddress);
DBG("RSDT @%x, Length %d\n",rsdt, rsdt->Length);
if (rsdt && (uint32_t)rsdt !=0xffffffff && rsdt->Length<0x10000)
{
uint32_t *rsdt_entries;
int rsdt_entries_num;
int dropoffset=0, i;
// mozo: using malloc cos I didn't found how to free already allocated kernel memory
rsdt_mod=(struct acpi_2_rsdt *)malloc(rsdt->Length);
memcpy (rsdt_mod, rsdt, rsdt->Length);
rsdp_mod->RsdtAddress=(uint32_t)rsdt_mod;
rsdt_entries_num=(rsdt_mod->Length-sizeof(struct acpi_2_rsdt))/4;
rsdt_entries=(uint32_t *)(rsdt_mod+1);
for (i=0;i<rsdt_entries_num;i++)
{
char *table=(char *)(rsdt_entries[i]);
if (!table)
continue;
DBG("TABLE %c%c%c%c,",table[0],table[1],table[2],table[3]);
rsdt_entries[i-dropoffset]=rsdt_entries[i];
if (drop_ssdt && tableSign(table, "SSDT"))
{
dropoffset++;
continue;
}
if (tableSign(table, "DSDT"))
{
DBG("DSDT found\n");
if(new_dsdt)
rsdt_entries[i-dropoffset]=(uint32_t)new_dsdt;
continue;
}
if (tableSign(table, "FACP"))
{
struct acpi_2_fadt *fadt, *fadt_mod;
fadt=(struct acpi_2_fadt *)rsdt_entries[i];
DBG("FADT found @%x, Length %d\n",fadt, fadt->Length);
if (!fadt || (uint32_t)fadt == 0xffffffff || fadt->Length>0x10000)
{
printf("FADT incorrect. Not modified\n");
continue;
}
fadt_mod = patch_fadt(fadt, new_dsdt);
rsdt_entries[i-dropoffset]=(uint32_t)fadt_mod;
// Generate _CST SSDT
if (generate_cstates && (new_ssdt[ssdt_count] = generate_cst_ssdt(fadt_mod)))
{
generate_cstates = false; // Generate SSDT only once!
ssdt_count++;
}
// Generating _PSS SSDT
if (generate_pstates && (new_ssdt[ssdt_count] = generate_pss_ssdt((void*)fadt_mod->DSDT)))
{
generate_pstates = false; // Generate SSDT only once!
ssdt_count++;
}
continue;
}
}
DBG("\n");
// Allocate rsdt in Kernel memory area
rsdt_mod->Length += 4*ssdt_count - 4*dropoffset;
struct acpi_2_rsdt *rsdt_copy = (struct acpi_2_rsdt *)AllocateKernelMemory(rsdt_mod->Length);
memcpy (rsdt_copy, rsdt_mod, rsdt_mod->Length);
free(rsdt_mod); rsdt_mod = rsdt_copy;
rsdp_mod->RsdtAddress=(uint32_t)rsdt_mod;
rsdt_entries_num=(rsdt_mod->Length-sizeof(struct acpi_2_rsdt))/4;
rsdt_entries=(uint32_t *)(rsdt_mod+1);
// Mozodojo: Insert additional SSDTs into RSDT
if(ssdt_count>0)
{
int j;
for (j=0; j<ssdt_count; j++)
rsdt_entries[i-dropoffset+j]=(uint32_t)new_ssdt[j];
verbose("RSDT: Added %d SSDT table(s)\n", ssdt_count);
}
// Correct the checksum of RSDT
DBG("RSDT: Original checksum %d, ", rsdt_mod->Checksum);
rsdt_mod->Checksum=0;
rsdt_mod->Checksum=256-checksum8(rsdt_mod,rsdt_mod->Length);
DBG("New checksum %d at %x\n", rsdt_mod->Checksum,rsdt_mod);
}
else
{
rsdp_mod->RsdtAddress=0;
printf("RSDT not found or RSDT incorrect\n");
}
if (version)
{
struct acpi_2_xsdt *xsdt, *xsdt_mod;
// FIXME: handle 64-bit address correctly
xsdt=(struct acpi_2_xsdt*) ((uint32_t)rsdp->XsdtAddress);
DBG("XSDT @%x;%x, Length=%d\n", (uint32_t)(rsdp->XsdtAddress>>32),(uint32_t)rsdp->XsdtAddress,
xsdt->Length);
if (xsdt && (uint64_t)rsdp->XsdtAddress<0xffffffff && xsdt->Length<0x10000)
{
uint64_t *xsdt_entries;
int xsdt_entries_num, i;
int dropoffset=0;
// mozo: using malloc cos I didn't found how to free already allocated kernel memory
xsdt_mod=(struct acpi_2_xsdt*)malloc(xsdt->Length);
memcpy(xsdt_mod, xsdt, xsdt->Length);
rsdp_mod->XsdtAddress=(uint32_t)xsdt_mod;
xsdt_entries_num=(xsdt_mod->Length-sizeof(struct acpi_2_xsdt))/8;
xsdt_entries=(uint64_t *)(xsdt_mod+1);
for (i=0;i<xsdt_entries_num;i++)
{
char *table=(char *)((uint32_t)(xsdt_entries[i]));
if (!table)
continue;
xsdt_entries[i-dropoffset]=xsdt_entries[i];
if (drop_ssdt && tableSign(table, "SSDT"))
{
dropoffset++;
continue;
}
if (tableSign(table, "DSDT"))
{
DBG("DSDT found\n");
if (new_dsdt)
xsdt_entries[i-dropoffset]=(uint32_t)new_dsdt;
DBG("TABLE %c%c%c%c@%x,",table[0],table[1],table[2],table[3],xsdt_entries[i]);
continue;
}
if (tableSign(table, "FACP"))
{
struct acpi_2_fadt *fadt, *fadt_mod;
fadt=(struct acpi_2_fadt *)(uint32_t)xsdt_entries[i];
DBG("FADT found @%x,%x, Length %d\n",(uint32_t)(xsdt_entries[i]>>32),fadt,
fadt->Length);
if (!fadt || (uint64_t)xsdt_entries[i] >= 0xffffffff || fadt->Length>0x10000)
{
verbose("FADT incorrect or after 4GB. Dropping XSDT\n");
goto drop_xsdt;
}
fadt_mod = patch_fadt(fadt, new_dsdt);
xsdt_entries[i-dropoffset]=(uint32_t)fadt_mod;
DBG("TABLE %c%c%c%c@%x,",table[0],table[1],table[2],table[3],xsdt_entries[i]);
// Generate _CST SSDT
if (generate_cstates && (new_ssdt[ssdt_count] = generate_cst_ssdt(fadt_mod)))
{
generate_cstates = false; // Generate SSDT only once!
ssdt_count++;
}
// Generating _PSS SSDT
if (generate_pstates && (new_ssdt[ssdt_count] = generate_pss_ssdt((void*)fadt_mod->DSDT)))
{
generate_pstates = false; // Generate SSDT only once!
ssdt_count++;
}
continue;
}
DBG("TABLE %c%c%c%c@%x,",table[0],table[1],table[2],table[3],xsdt_entries[i]);
}
// Allocate xsdt in Kernel memory area
xsdt_mod->Length += 8*ssdt_count - 8*dropoffset;
struct acpi_2_xsdt *xsdt_copy = (struct acpi_2_xsdt *)AllocateKernelMemory(xsdt_mod->Length);
memcpy(xsdt_copy, xsdt_mod, xsdt_mod->Length);
free(xsdt_mod); xsdt_mod = xsdt_copy;
rsdp_mod->XsdtAddress=(uint32_t)xsdt_mod;
xsdt_entries_num=(xsdt_mod->Length-sizeof(struct acpi_2_xsdt))/8;
xsdt_entries=(uint64_t *)(xsdt_mod+1);
// Mozodojo: Insert additional SSDTs into XSDT
if(ssdt_count>0)
{
int j;
for (j=0; j<ssdt_count; j++)
xsdt_entries[i-dropoffset+j]=(uint32_t)new_ssdt[j];
verbose("Added %d SSDT table(s) into XSDT\n", ssdt_count);
}
// Correct the checksum of XSDT
xsdt_mod->Checksum=0;
xsdt_mod->Checksum=256-checksum8(xsdt_mod,xsdt_mod->Length);
}
else
{
drop_xsdt:
DBG("About to drop XSDT\n");
/*FIXME: Now we just hope that if MacOS doesn't find XSDT it reverts to RSDT.
* A Better strategy would be to generate
*/
rsdp_mod->XsdtAddress=0xffffffffffffffffLL;
verbose("XSDT not found or XSDT incorrect\n");
}
}
// Correct the checksum of RSDP
DBG("RSDP: Original checksum %d, ", rsdp_mod->Checksum);
rsdp_mod->Checksum=0;
rsdp_mod->Checksum=256-checksum8(rsdp_mod,20);
DBG("New checksum %d\n", rsdp_mod->Checksum);
if (version)
{
DBG("RSDP: Original extended checksum %d", rsdp_mod->ExtendedChecksum);
rsdp_mod->ExtendedChecksum=0;
rsdp_mod->ExtendedChecksum=256-checksum8(rsdp_mod,rsdp_mod->Length);
DBG("New extended checksum %d\n", rsdp_mod->ExtendedChecksum);
}
//verbose("Patched ACPI version %d DSDT\n", version+1);
if (version)
{
/* XXX aserebln why uint32 cast if pointer is uint64 ? */
acpi20_p = (uint32_t)rsdp_mod;
addConfigurationTable(&gEfiAcpi20TableGuid, &acpi20_p, "ACPI_20");
}
else
{
/* XXX aserebln why uint32 cast if pointer is uint64 ? */
acpi10_p = (uint32_t)rsdp_mod;
addConfigurationTable(&gEfiAcpiTableGuid, &acpi10_p, "ACPI");
}
}
#if DEBUG_ACPI
printf("Press a key to continue... (DEBUG_ACPI)\n");
getchar();
#endif
return 1;
}
branches/rewrite/i386/libsaio/acpi_patcher.h
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/*
* Copyright 2008 mackerintel
*/
#ifndef __LIBSAIO_ACPI_PATCHER_H
#define __LIBSAIO_ACPI_PATCHER_H
#include "libsaio.h"
uint64_t acpi10_p;
uint64_t acpi20_p;
uint64_t smbios_p;
extern int setupAcpi();
extern EFI_STATUS addConfigurationTable();
extern EFI_GUID gEfiAcpiTableGuid;
extern EFI_GUID gEfiAcpi20TableGuid;
struct p_state
{
union
{
uint16_t Control;
struct
{
uint8_t VID;// Voltage ID
uint8_t FID;// Frequency ID
};
};
uint8_tCID;// Compare ID
uint32_tFrequency;
};
#endif /* !__LIBSAIO_ACPI_PATCHER_H */
branches/rewrite/i386/libsaio/pci_root.c
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/*
* Copyright 2009 netkas
*/
#include "libsaio.h"
#include "boot.h"
#include "bootstruct.h"
#ifndef DEBUG_PCIROOT
#define DEBUG_PCIROOT 1
#endif
#if DEBUG_PCIROOT
#define DBG(x...) printf(x)
#else
#define DBG(x...)
#endif
static int rootuid = 10; //value means function wasnt ran yet
static unsigned int findrootuid(unsigned char * dsdt, int len)
{
int i;
for (i=0; i<64 && i<len-5; i++) //not far than 64 symbols from pci root
{
if(dsdt[i] == '_' && dsdt[i+1] == 'U' && dsdt[i+2] == 'I' && dsdt[i+3] == 'D' && dsdt[i+5] == 0x08)
{
return dsdt[i+4];
}
}
return 11;
}
static unsigned int findpciroot(unsigned char * dsdt,int len)
{
int i;
for (i=0; i<len-4; i++) {
if(dsdt[i] == 'P' && dsdt[i+1] == 'C' && dsdt[i+2] == 'I' && (dsdt[i+3] == 0x08 || dsdt [i+4] == 0x08)) {
return findrootuid(dsdt+i, len-i);
}
}
return 10;
}
int getPciRootUID(void)
{
void *new_dsdt;
const char *val;
int len,fsize;
const char * dsdt_filename=NULL;
extern int search_and_get_acpi_fd(const char *, const char **);
if (rootuid < 10) return rootuid;
rootuid = 0;/* default uid = 0 */
if (getValueForKey(kPCIRootUID, &val, &len, &bootInfo->bootConfig)) {
if (isdigit(val[0])) rootuid = val[0] - '0';
goto out;
}
/* Chameleon compatibility */
else if (getValueForKey("PciRoot", &val, &len, &bootInfo->bootConfig)) {
if (isdigit(val[0])) rootuid = val[0] - '0';
goto out;
}
/* PCEFI compatibility */
else if (getValueForKey("-pci0", &val, &len, &bootInfo->bootConfig)) {
rootuid = 0;
goto out;
}
else if (getValueForKey("-pci1", &val, &len, &bootInfo->bootConfig)) {
rootuid = 1;
goto out;
}
int fd = search_and_get_acpi_fd("DSDT.aml", &dsdt_filename);
// Check booting partition
if (fd<0)
{
verbose("No DSDT found, using 0 as uid value.\n");
rootuid = 0;
goto out;
}
fsize = file_size(fd);
if ((new_dsdt = malloc(fsize)) == NULL) {
verbose("[ERROR] alloc DSDT memory failed\n");
close (fd);
goto out;
}
if (read (fd, new_dsdt, fsize) != fsize) {
verbose("[ERROR] read %s failed\n", dsdt_filename);
close (fd);
goto out;
}
close (fd);
rootuid = findpciroot(new_dsdt, fsize);
free(new_dsdt);
// make sure it really works:
if (rootuid == 11) rootuid=0; //usually when _UID isnt present, it means uid is zero
else if (rootuid < 0 || rootuid > 9)
{
printf("PciRoot uid value wasnt found, using 0, if you want it to be 1, use -PciRootUID flag");
rootuid = 0;
}
out:
verbose("Using PCI-Root-UID value: %d\n", rootuid);
return rootuid;
}
branches/rewrite/i386/libsaio/pci_root.h
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/*
* Copyright 2008 mackerintel
*/
#ifndef __LIBSAIO_PCI_ROOT_H
#define __LIBSAIO_PCI_ROOT_H
#include "libsaio.h"
extern int getPciRootUID(void);
#endif /* !__LIBSAIO_DSDT_PATCHER_H */
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/*
* usb.c
*
*
* Created by mackerintel on 12/20/08.
* Copyright 2008 mackerintel. All rights reserved.
*
*/
#include "libsaio.h"
#include "boot.h"
#include "bootstruct.h"
#include "pci.h"
#ifndef DEBUG_USB
#define DEBUG_USB 0
#endif
#if DEBUG_USB
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
struct pciList
{
pci_dt_t* pciDev;
struct pciList* next;
};
struct pciList* usbList = NULL;
int legacy_off (pci_dt_t *pci_dev);
int ehci_acquire (pci_dt_t *pci_dev);
int uhci_reset (pci_dt_t *pci_dev);
// Add usb device to the list
void notify_usb_dev(pci_dt_t *pci_dev)
{
struct pciList* current = usbList;
if(!usbList)
{
usbList = (struct pciList*)malloc(sizeof(struct pciList));
usbList->next = NULL;
usbList->pciDev = pci_dev;
}
else
{
while(current != NULL && current->next != NULL)
{
current = current->next;
}
current->next = (struct pciList*)malloc(sizeof(struct pciList));
current = current->next;
current->pciDev = pci_dev;
current->next = NULL;
}
}
// Loop through the list and call the apropriate patch function
int usb_loop()
{
int retVal = 1;
bool fix_ehci, fix_uhci, fix_usb, fix_legacy;
fix_ehci = fix_uhci = fix_usb = fix_legacy = false;
if (getBoolForKey(kUSBBusFix, &fix_usb, &bootInfo->bootConfig))
{
fix_ehci = fix_uhci = fix_legacy = fix_usb;// Disable all if none set
}
else
{
getBoolForKey(kEHCIacquire, &fix_ehci, &bootInfo->bootConfig);
getBoolForKey(kUHCIreset, &fix_uhci, &bootInfo->bootConfig);
getBoolForKey(kLegacyOff, &fix_legacy, &bootInfo->bootConfig);
}
struct pciList* current = usbList;
while(current)
{
switch (pci_config_read8(current->pciDev->dev.addr, PCI_CLASS_PROG))
{
// EHCI
case 0x20:
if(fix_ehci) retVal &= ehci_acquire(current->pciDev);
if(fix_legacy) retVal &= legacy_off(current->pciDev);
break;
// UHCI
case 0x00:
if (fix_uhci) retVal &= uhci_reset(current->pciDev);
break;
}
current = current->next;
}
return retVal;
}
int legacy_off (pci_dt_t *pci_dev)
{
// Set usb legacy off modification by Signal64
// NOTE: This *must* be called after the last file is loaded from the drive in the event that we are booting form usb.
// NOTE2: This should be called after any getc()/getchar() call. (aka, after the Wait=y keyworkd is used)
// AKA: Make this run immediatly before the kernel is called
uint32_tcapaddr, opaddr;
uint8_teecp;
uint32_tusbcmd, usbsts, usbintr;
uint32_tusblegsup, usblegctlsts;
int isOSowned;
int isBIOSowned;
verbose("Setting Legacy USB Off on controller [%04x:%04x] at %02x:%2x.%x\n",
pci_dev->vendor_id, pci_dev->device_id,
pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func);
// capaddr = Capability Registers = dev.addr + offset stored in dev.addr + 0x10 (USBBASE)
capaddr = pci_config_read32(pci_dev->dev.addr, 0x10);
// opaddr = Operational Registers = capaddr + offset (8bit CAPLENGTH in Capability Registers + offset 0)
opaddr = capaddr + *((unsigned char*)(capaddr));
// eecp = EHCI Extended Capabilities offset = capaddr HCCPARAMS bits 15:8
eecp=*((unsigned char*)(capaddr + 9));
DBG("capaddr=%x opaddr=%x eecp=%x\n", capaddr, opaddr, eecp);
usbcmd = *((unsigned int*)(opaddr));// Command Register
usbsts = *((unsigned int*)(opaddr + 4));// Status Register
usbintr = *((unsigned int*)(opaddr + 8));// Interrupt Enable Register
DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);
// read PCI Config 32bit USBLEGSUP (eecp+0)
usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);
// informational only
isBIOSowned = !!((usblegsup) & (1 << (16)));
isOSowned = !!((usblegsup) & (1 << (24)));
// read PCI Config 32bit USBLEGCTLSTS (eecp+4)
usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);
DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);
// Reset registers to Legacy OFF
DBG("Clearing USBLEGCTLSTS\n");
pci_config_write32(pci_dev->dev.addr, eecp + 4, 0);//usblegctlsts
// if delay value is in milliseconds it doesn't appear to work.
// setting value to anything up to 65535 does not add the expected delay here.
delay(100);
usbcmd = *((unsigned int*)(opaddr));
usbsts = *((unsigned int*)(opaddr + 4));
usbintr = *((unsigned int*)(opaddr + 8));
DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);
DBG("Clearing Registers\n");
// clear registers to default
usbcmd = (usbcmd & 0xffffff00);
*((unsigned int*)(opaddr)) = usbcmd;
*((unsigned int*)(opaddr + 8)) = 0;//usbintr - clear interrupt registers
*((unsigned int*)(opaddr + 4)) = 0x1000;//usbsts - clear status registers
pci_config_write32(pci_dev->dev.addr, eecp, 1);//usblegsup
// get the results
usbcmd = *((unsigned int*)(opaddr));
usbsts = *((unsigned int*)(opaddr + 4));
usbintr = *((unsigned int*)(opaddr + 8));
DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);
// read 32bit USBLEGSUP (eecp+0)
usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);
// informational only
isBIOSowned = !!((usblegsup) & (1 << (16)));
isOSowned = !!((usblegsup) & (1 << (24)));
// read 32bit USBLEGCTLSTS (eecp+4)
usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);
DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);
verbose("Legacy USB Off Done\n");
return 1;
}
int ehci_acquire (pci_dt_t *pci_dev)
{
intj, k;
uint32_tbase;
uint8_teecp;
uint8_tlegacy[8];
boolisOwnershipConflict;
boolalwaysHardBIOSReset;
alwaysHardBIOSReset = false;
if (!getBoolForKey(kEHCIhard, &alwaysHardBIOSReset, &bootInfo->bootConfig)) {
alwaysHardBIOSReset = true;
}
pci_config_write16(pci_dev->dev.addr, 0x04, 0x0002);
base = pci_config_read32(pci_dev->dev.addr, 0x10);
verbose("EHCI controller [%04x:%04x] at %02x:%2x.%x DMA @%x\n",
pci_dev->vendor_id, pci_dev->device_id,
pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func,
base);
if (*((unsigned char*)base) < 0xc)
{
DBG("Config space too small: no legacy implementation\n");
return 1;
}
eecp = *((unsigned char*)(base + 9));
if (!eecp) {
DBG("No extended capabilities: no legacy implementation\n");
return 1;
}
DBG("eecp=%x\n",eecp);
// bad way to do it
// pci_conf_write(pci_dev->dev.addr, eecp, 4, 0x01000001);
for (j = 0; j < 8; j++) {
legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);
DBG("%02x ", legacy[j]);
}
DBG("\n");
//Real Job: based on orByte's AppleUSBEHCI.cpp
//We try soft reset first - some systems hang on reboot with hard reset
// Definitely needed during reboot on 10.4.6
isOwnershipConflict = ((legacy[3] & 1 != 0) && (legacy[2] & 1 != 0));
if (!alwaysHardBIOSReset && isOwnershipConflict) {
DBG("EHCI - Ownership conflict - attempting soft reset ...\n");
DBG("EHCI - toggle OS Ownership to 0\n");
pci_config_write8(pci_dev->dev.addr, eecp + 3, 0);
for (k = 0; k < 25; k++) {
for (j = 0; j < 8; j++) {
legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);
}
if (legacy[3] == 0) {
break;
}
delay(10);
}
}
DBG("Found USBLEGSUP_ID - value %x:%x - writing OSOwned\n", legacy[3],legacy[2]);
pci_config_write8(pci_dev->dev.addr, eecp + 3, 1);
// wait for kEHCI_USBLEGSUP_BIOSOwned bit to clear
for (k = 0; k < 25; k++) {
for (j = 0;j < 8; j++) {
legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);
}
DBG ("%x:%x,",legacy[3],legacy[2]);
if (legacy[2] == 0) {
break;
}
delay(10);
}
for (j = 0;j < 8; j++) {
legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);
}
isOwnershipConflict = ((legacy[2]) != 0);
if (isOwnershipConflict) {
// Soft reset has failed. Assume SMI being ignored
// Hard reset
// Force Clear BIOS BIT
DBG("EHCI - Ownership conflict - attempting hard reset ...\n");
DBG ("%x:%x\n",legacy[3],legacy[2]);
DBG("EHCI - Force BIOS Ownership to 0\n");
pci_config_write8(pci_dev->dev.addr, eecp + 2, 0);
for (k = 0; k < 25; k++) {
for (j = 0; j < 8; j++) {
legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);
}
DBG ("%x:%x,",legacy[3],legacy[2]);
if ((legacy[2]) == 0) {
break;
}
delay(10);
}
// Disable further SMI events
for (j = 4; j < 8; j++) {
pci_config_write8(pci_dev->dev.addr, eecp + j, 0);
}
}
for (j = 0; j < 8; j++) {
legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);
}
DBG ("%x:%x\n",legacy[3],legacy[2]);
// Final Ownership Resolution Check...
if (legacy[2] & 1) {
DBG("EHCI controller unable to take control from BIOS\n");
return 0;
}
DBG("EHCI Acquire OS Ownership done\n");
return 1;
}
int uhci_reset (pci_dt_t *pci_dev)
{
uint32_t base, port_base;
base = pci_config_read32(pci_dev->dev.addr, 0x20);
port_base = (base >> 5) & 0x07ff;
verbose("UHCI controller [%04x:%04x] at %02x:%2x.%x base %x(%x)\n",
pci_dev->vendor_id, pci_dev->device_id,
pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func,
port_base, base);
pci_config_write16(pci_dev->dev.addr, 0xc0, 0x8f00);
outw (port_base, 0x0002);
delay(10);
outw (port_base+4,0);
delay(10);
outw (port_base,0);
return 1;
}
branches/rewrite/i386/libsaio/device_inject.c
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/*
*Copyright 2009 Jasmin Fazlic All rights reserved.
*/
/*
*Cleaned and merged by iNDi
*/
#include "libsaio.h"
#include "boot.h"
#include "bootstruct.h"
#include "pci.h"
#include "pci_root.h"
#include "device_inject.h"
#include "convert.h"
#ifndef DEBUG_INJECT
#define DEBUG_INJECT 0
#endif
#if DEBUG_INJECT
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
uint32_t devices_number = 1;
uint32_t builtin_set = 0;
struct DevPropString *string = 0;
uint8_t *stringdata = 0;
uint32_t stringlength = 0;
char *efi_inject_get_devprop_string(uint32_t *len)
{
if(string) {
*len = string->length;
return devprop_generate_string(string);
}
verbose("efi_inject_get_devprop_string NULL trying stringdata\n");
return NULL;
}
void setupDeviceProperties(Node *node)
{
const char *val;
uint8_t *binStr;
int cnt, cnt2;
static char DEVICE_PROPERTIES_PROP[] = "device-properties";
/* Generate devprop string.
*/
uint32_t strlength;
char *string = efi_inject_get_devprop_string(&strlength);
/* Use the static "device-properties" boot config key contents if available,
* otheriwse use the generated one.
*/
if (!getValueForKey(kDeviceProperties, &val, &cnt, &bootInfo->bootConfig) && string)
{
val = (const char*)string;
cnt = strlength * 2;
}
if (cnt > 1)
{
binStr = convertHexStr2Binary(val, &cnt2);
if (cnt2 > 0) DT__AddProperty(node, DEVICE_PROPERTIES_PROP, cnt2, binStr);
}
}
struct DevPropString *devprop_create_string(void)
{
string = (struct DevPropString*)malloc(sizeof(struct DevPropString));
if(string == NULL)
return NULL;
memset(string, 0, sizeof(struct DevPropString));
string->length = 12;
string->WHAT2 = 0x01000000;
return string;
}
struct DevPropDevice *devprop_add_device(struct DevPropString *string, char *path)
{
struct DevPropDevice*device;
const charpciroot_string[] = "PciRoot(0x";
const charpci_device_string[] = "Pci(0x";
if (string == NULL || path == NULL) {
return NULL;
}
device = malloc(sizeof(struct DevPropDevice));
if (strncmp(path, pciroot_string, strlen(pciroot_string))) {
printf("ERROR parsing device path\n");
return NULL;
}
memset(device, 0, sizeof(struct DevPropDevice));
device->acpi_dev_path._UID = getPciRootUID();
int numpaths = 0;
intx, curr = 0;
charbuff[] = "00";
for (x = 0; x < strlen(path); x++) {
if (!strncmp(&path[x], pci_device_string, strlen(pci_device_string))) {
x+=strlen(pci_device_string);
curr=x;
while(path[++x] != ',');
if(x-curr == 2)
sprintf(buff, "%c%c", path[curr], path[curr+1]);
else if(x-curr == 1)
sprintf(buff, "%c", path[curr]);
else
{
printf("ERROR parsing device path\n");
numpaths = 0;
break;
}
device->pci_dev_path[numpaths].device =ascii_hex_to_int(buff);
x += 3; // 0x
curr = x;
while(path[++x] != ')');
if(x-curr == 2)
sprintf(buff, "%c%c", path[curr], path[curr+1]);
else if(x-curr == 1)
sprintf(buff, "%c", path[curr]);
else
{
printf("ERROR parsing device path\n");
numpaths = 0;
break;
}
device->pci_dev_path[numpaths].function = ascii_hex_to_int(buff); // TODO: find dev from char *path
numpaths++;
}
}
if(!numpaths)
return NULL;
device->numentries = 0x00;
device->acpi_dev_path.length = 0x0c;
device->acpi_dev_path.type = 0x02;
device->acpi_dev_path.subtype = 0x01;
device->acpi_dev_path._HID = 0xd041030a;
device->num_pci_devpaths = numpaths;
device->length = 24 + (6*numpaths);
inti;
for(i = 0; i < numpaths; i++)
{
device->pci_dev_path[i].length = 0x06;
device->pci_dev_path[i].type = 0x01;
device->pci_dev_path[i].subtype = 0x01;
}
device->path_end.length = 0x04;
device->path_end.type = 0x7f;
device->path_end.subtype = 0xff;
device->string = string;
device->data = NULL;
string->length += device->length;
if(!string->entries)
if((string->entries = (struct DevPropDevice**)malloc(sizeof(device)))== NULL)
return 0;
string->entries[string->numentries++] = (struct DevPropDevice*)malloc(sizeof(device));
string->entries[string->numentries-1] = device;
return device;
}
int devprop_add_value(struct DevPropDevice *device, char *nm, uint8_t *vl, uint32_t len)
{
if(!nm || !vl || !len)
return 0;
uint32_t length = ((strlen(nm) * 2) + len + (2 * sizeof(uint32_t)) + 2);
uint8_t *data = (uint8_t*)malloc(length);
{
if(!data)
return 0;
memset(data, 0, length);
uint32_t off= 0;
data[off+1] = ((strlen(nm) * 2) + 6) >> 8;
data[off] = ((strlen(nm) * 2) + 6) & 0x00FF;
off += 4;
uint32_t i=0, l = strlen(nm);
for(i = 0 ; i < l ; i++, off += 2)
{
data[off] = *nm++;
}
off += 2;
l = len;
uint32_t *datalength = (uint32_t*)&data[off];
*datalength = l + 4;
off += 4;
for(i = 0 ; i < l ; i++, off++)
{
data[off] = *vl++;
}
}
uint32_t offset = device->length - (24 + (6 * device->num_pci_devpaths));
uint8_t *newdata = (uint8_t*)malloc((length + offset));
if(!newdata)
return 0;
if(device->data)
if(offset > 1)
memcpy(newdata, device->data, offset);
memcpy(newdata + offset, data, length);
device->length += length;
device->string->length += length;
device->numentries++;
if(!device->data)
device->data = (uint8_t*)malloc(sizeof(uint8_t));
else
free(device->data);
free(data);
device->data = newdata;
return 1;
}
char *devprop_generate_string(struct DevPropString *string)
{
char *buffer = (char*)malloc(string->length * 2);
char *ptr = buffer;
if(!buffer)
return NULL;
sprintf(buffer, "%08x%08x%04x%04x", dp_swap32(string->length), string->WHAT2,
dp_swap16(string->numentries), string->WHAT3);
buffer += 24;
int i = 0, x = 0;
while(i < string->numentries)
{
sprintf(buffer, "%08x%04x%04x", dp_swap32(string->entries[i]->length),
dp_swap16(string->entries[i]->numentries), string->entries[i]->WHAT2);
buffer += 16;
sprintf(buffer, "%02x%02x%04x%08x%08x", string->entries[i]->acpi_dev_path.type,
string->entries[i]->acpi_dev_path.subtype,
dp_swap16(string->entries[i]->acpi_dev_path.length),
string->entries[i]->acpi_dev_path._HID,
dp_swap32(string->entries[i]->acpi_dev_path._UID));
buffer += 24;
for(x=0;x < string->entries[i]->num_pci_devpaths; x++)
{
sprintf(buffer, "%02x%02x%04x%02x%02x", string->entries[i]->pci_dev_path[x].type,
string->entries[i]->pci_dev_path[x].subtype,
dp_swap16(string->entries[i]->pci_dev_path[x].length),
string->entries[i]->pci_dev_path[x].function,
string->entries[i]->pci_dev_path[x].device);
buffer += 12;
}
sprintf(buffer, "%02x%02x%04x", string->entries[i]->path_end.type,
string->entries[i]->path_end.subtype,
dp_swap16(string->entries[i]->path_end.length));
buffer += 8;
uint8_t *dataptr = string->entries[i]->data;
for(x = 0; x < (string->entries[i]->length) - (24 + (6 * string->entries[i]->num_pci_devpaths)) ; x++)
{
sprintf(buffer, "%02x", *dataptr++);
buffer += 2;
}
i++;
}
return ptr;
}
void devprop_free_string(struct DevPropString *string)
{
if(!string)
return;
int i;
for(i = 0; i < string->numentries; i++)
{
if(string->entries[i])
{
if(string->entries[i]->data)
{
free(string->entries[i]->data);
string->entries[i]->data = NULL;
}
free(string->entries[i]);
string->entries[i] = NULL;
}
}
free(string);
string = NULL;
}
/* a fine place for this code */
int devprop_add_network_template(struct DevPropDevice *device, uint16_t vendor_id)
{
if(!device)
return 0;
uint8_t builtin = 0x0;
if((vendor_id != 0x168c) && (builtin_set == 0))
{
builtin_set = 1;
builtin = 0x01;
}
if(!devprop_add_value(device, "built-in", (uint8_t*)&builtin, 1))
return 0;
devices_number++;
return 1;
}
void set_eth_builtin(pci_dt_t *eth_dev)
{
char *devicepath = get_pci_dev_path(eth_dev);
struct DevPropDevice *device = (struct DevPropDevice*)malloc(sizeof(struct DevPropDevice));
verbose("LAN Controller [%04x:%04x] :: %s\n", eth_dev->vendor_id, eth_dev->device_id, devicepath);
if (!string)
string = devprop_create_string();
device = devprop_add_device(string, devicepath);
if(device)
{
verbose("Setting up lan keys\n");
devprop_add_network_template(device, eth_dev->vendor_id);
stringdata = (uint8_t*)malloc(sizeof(uint8_t) * string->length);
if(stringdata)
{
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
}
}
}
branches/rewrite/i386/libsaio/device_inject.h
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/*
*Copyright 2009 Jasmin Fazlic All rights reserved.
*/
/*
*Cleaned and merged by iNDi
*/
#ifndef __LIBSAIO_DEVICE_INJECT_H
#define __LIBSAIO_DEVICE_INJECT_H
#define DP_ADD_TEMP_VAL(dev, val) devprop_add_value(dev, (char*)val[0], (uint8_t*)val[1], strlen(val[1]) + 1)
#define DP_ADD_TEMP_VAL_DATA(dev, val) devprop_add_value(dev, (char*)val.name, (uint8_t*)val.data, val.size)
#define MAX_PCI_DEV_PATHS 4
extern struct DevPropString *string;
extern uint8_t *stringdata;
extern uint32_t stringlength;
extern void setupDeviceProperties(Node *node);
struct ACPIDevPath {
uint8_ttype;// = 2 ACPI device-path
uint8_tsubtype;// = 1 ACPI Device-path
uint16_tlength;// = 0x0c
uint32_t_HID;// = 0xD041030A ?
uint32_t_UID;// = 0x00000000 PCI ROOT
};
struct PCIDevPath {
uint8_ttype;// = 1 Hardware device-path
uint8_tsubtype;// = 1 PCI
uint16_tlength;// = 6
uint8_tfunction;// pci func number
uint8_tdevice;// pci dev number
};
struct DevicePathEnd {
uint8_ttype;// = 0x7f
uint8_tsubtype;// = 0xff
uint16_tlength;// = 4;
};
struct DevPropDevice {
uint32_t length;
uint16_t numentries;
uint16_t WHAT2;// 0x0000 ?
struct ACPIDevPath acpi_dev_path;// = 0x02010c00 0xd041030a
struct PCIDevPath pci_dev_path[MAX_PCI_DEV_PATHS]; // = 0x01010600 func dev
struct DevicePathEnd path_end;// = 0x7fff0400
uint8_t *data;
// ------------------------
uint8_t num_pci_devpaths;
struct DevPropString *string;
// ------------------------
};
struct DevPropString {
uint32_t length;
uint32_t WHAT2;// 0x01000000 ?
uint16_t numentries;
uint16_t WHAT3;// 0x0000 ?
struct DevPropDevice **entries;
};
char*efi_inject_get_devprop_string(uint32_t *len);
intdevprop_add_network_template(struct DevPropDevice *device, uint16_t vendor_id);
struct DevPropString*devprop_create_string(void);
struct DevPropDevice*devprop_add_device(struct DevPropString *string, char *path);
intdevprop_add_value(struct DevPropDevice *device, char *nm, uint8_t *vl, uint32_t len);
char*devprop_generate_string(struct DevPropString *string);
voiddevprop_free_string(struct DevPropString *string);
#endif /* !__LIBSAIO_DEVICE_INJECT_H */
branches/rewrite/i386/libsaio/nvidia.c
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/*
* NVidia injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi
*
* NVidia injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* NVidia driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
/*
* DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
*
*
* Copyright 2005-2006 Erik Waling
* Copyright 2006 Stephane Marchesin
* Copyright 2007-2009 Stuart Bennett
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "libsaio.h"
#include "boot.h"
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#include "device_inject.h"
#include "nvidia.h"
#ifndef DEBUG_NVIDIA
#define DEBUG_NVIDIA 0
#endif
#if DEBUG_NVIDIA
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
#define NVIDIA_ROM_SIZE 0x10000
#define PATCH_ROM_SUCCESS 1
#define PATCH_ROM_SUCCESS_HAS_LVDS 2
#define PATCH_ROM_FAILED 0
#define MAX_NUM_DCB_ENTRIES 16
#define TYPE_GROUPED 0xff
extern uint32_t devices_number;
const char *nvidia_compatible_0[]={ "@0,compatible","NVDA,NVMac" };
const char *nvidia_compatible_1[]={ "@1,compatible","NVDA,NVMac" };
const char *nvidia_device_type_0[]={ "@0,device_type","display" };
const char *nvidia_device_type_1[]={ "@1,device_type","display" };
const char *nvidia_device_type[]={ "device_type","NVDA,Parent" };
const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
const char *nvidia_slot_name[]={ "AAPL,slot-name","Slot-1" };
//const char *nvidia_display_cfg_0[] = { "@0,display-cfg
static uint8_t default_NVCAP[]= {
0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
0x00, 0x00, 0x00, 0x00
};
#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )
static uint8_t default_dcfg_0[]={0xff, 0xff, 0xff, 0xff};
static uint8_t default_dcfg_1[]={0xff, 0xff, 0xff, 0xff};
#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )
#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )
static struct nv_chipsets_t NVKnownChipsets[] = {
{ 0x00000000, "Unknown" },
// 0040 - 004F
{ 0x10DE0040, "GeForce 6800 Ultra" },
{ 0x10DE0041, "GeForce 6800" },
{ 0x10DE0042, "GeForce 6800 LE" },
{ 0x10DE0043, "GeForce 6800 XE" },
{ 0x10DE0044, "GeForce 6800 XT" },
{ 0x10DE0045, "GeForce 6800 GT" },
{ 0x10DE0046, "GeForce 6800 GT" },
{ 0x10DE0047, "GeForce 6800 GS" },
{ 0x10DE0048, "GeForce 6800 XT" },
{ 0x10DE004D, "Quadro FX 3400" },
{ 0x10DE004E, "Quadro FX 4000" },
// 0050 - 005F
// 0060 - 006F
// 0070 - 007F
// 0080 - 008F
// 0090 - 009F
{ 0x10DE0090, "GeForce 7800 GTX" },
{ 0x10DE0091, "GeForce 7800 GTX" },
{ 0x10DE0092, "GeForce 7800 GT" },
{ 0x10DE0093, "GeForce 7800 GS" },
{ 0x10DE0095, "GeForce 7800 SLI" },
{ 0x10DE0098, "GeForce Go 7800" },
{ 0x10DE0099, "GeForce Go 7800 GTX" },
{ 0x10DE009D, "Quadro FX 4500" },
// 00A0 - 00AF
// 00B0 - 00BF
// 00C0 - 00CF
{ 0x10DE00C0, "GeForce 6800 GS" },
{ 0x10DE00C1, "GeForce 6800" },
{ 0x10DE00C2, "GeForce 6800 LE" },
{ 0x10DE00C3, "GeForce 6800 XT" },
{ 0x10DE00C8, "GeForce Go 6800" },
{ 0x10DE00C9, "GeForce Go 6800 Ultra" },
{ 0x10DE00CC, "Quadro FX Go1400" },
{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },
{ 0x10DE00CE, "Quadro FX 1400" },
// 00D0 - 00DF
// 00E0 - 00EF
// 00F0 - 00FF
{ 0x10DE00F1, "GeForce 6600 GT" },
{ 0x10DE00F2, "GeForce 6600" },
{ 0x10DE00F3, "GeForce 6200" },
{ 0x10DE00F4, "GeForce 6600 LE" },
{ 0x10DE00F5, "GeForce 7800 GS" },
{ 0x10DE00F6, "GeForce 6800 GS/XT" },
{ 0x10DE00F8, "Quadro FX 3400/4400" },
{ 0x10DE00F9, "GeForce 6800 Series GPU" },
// 0100 - 010F
// 0110 - 011F
// 0120 - 012F
// 0130 - 013F
// 0140 - 014F
{ 0x10DE0140, "GeForce 6600 GT" },
{ 0x10DE0141, "GeForce 6600" },
{ 0x10DE0142, "GeForce 6600 LE" },
{ 0x10DE0143, "GeForce 6600 VE" },
{ 0x10DE0144, "GeForce Go 6600" },
{ 0x10DE0145, "GeForce 6610 XL" },
{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },
{ 0x10DE0147, "GeForce 6700 XL" },
{ 0x10DE0148, "GeForce Go 6600" },
{ 0x10DE0149, "GeForce Go 6600 GT" },
{ 0x10DE014A, "Quadro NVS 440" },
{ 0x10DE014C, "Quadro FX 550" },
{ 0x10DE014D, "Quadro FX 550" },
{ 0x10DE014E, "Quadro FX 540" },
{ 0x10DE014F, "GeForce 6200" },
// 0150 - 015F
// 0160 - 016F
{ 0x10DE0160, "GeForce 6500" },
{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },
{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },
{ 0x10DE0163, "GeForce 6200 LE" },
{ 0x10DE0164, "GeForce Go 6200" },
{ 0x10DE0165, "Quadro NVS 285" },
{ 0x10DE0166, "GeForce Go 6400" },
{ 0x10DE0167, "GeForce Go 6200" },
{ 0x10DE0168, "GeForce Go 6400" },
{ 0x10DE0169, "GeForce 6250" },
{ 0x10DE016A, "GeForce 7100 GS" },
// 0170 - 017F
// 0180 - 018F
// 0190 - 019F
{ 0x10DE0191, "GeForce 8800 GTX" },
{ 0x10DE0193, "GeForce 8800 GTS" },
{ 0x10DE0194, "GeForce 8800 Ultra" },
{ 0x10DE0197, "Tesla C870" },
{ 0x10DE019D, "Quadro FX 5600" },
{ 0x10DE019E, "Quadro FX 4600" },
// 01A0 - 01AF
// 01B0 - 01BF
// 01C0 - 01CF
// 01D0 - 01DF
{ 0x10DE01D0, "GeForce 7350 LE" },
{ 0x10DE01D1, "GeForce 7300 LE" },
{ 0x10DE01D2, "GeForce 7550 LE" },
{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },
{ 0x10DE01D6, "GeForce Go 7200" },
{ 0x10DE01D7, "GeForce Go 7300" },
{ 0x10DE01D8, "GeForce Go 7400" },
{ 0x10DE01D9, "GeForce Go 7400 GS" },
{ 0x10DE01DA, "Quadro NVS 110M" },
{ 0x10DE01DB, "Quadro NVS 120M" },
{ 0x10DE01DC, "Quadro FX 350M" },
{ 0x10DE01DD, "GeForce 7500 LE" },
{ 0x10DE01DE, "Quadro FX 350" },
{ 0x10DE01DF, "GeForce 7300 GS" },
// 01E0 - 01EF
// 01F0 - 01FF
// 0200 - 020F
// 0210 - 021F
{ 0x10DE0211, "GeForce 6800" },
{ 0x10DE0212, "GeForce 6800 LE" },
{ 0x10DE0215, "GeForce 6800 GT" },
{ 0x10DE0218, "GeForce 6800 XT" },
// 0220 - 022F
{ 0x10DE0221, "GeForce 6200" },
{ 0x10DE0222, "GeForce 6200 A-LE" },
// 0230 - 023F
// 0240 - 024F
{ 0x10DE0240, "GeForce 6150" },
{ 0x10DE0241, "GeForce 6150 LE" },
{ 0x10DE0242, "GeForce 6100" },
{ 0x10DE0244, "GeForce Go 6150" },
{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },
{ 0x10DE0247, "GeForce Go 6100" },
// 0250 - 025F
// 0260 - 026F
// 0270 - 027F
// 0280 - 028F
// 0290 - 029F
{ 0x10DE0290, "GeForce 7900 GTX" },
{ 0x10DE0291, "GeForce 7900 GT/GTO" },
{ 0x10DE0292, "GeForce 7900 GS" },
{ 0x10DE0293, "GeForce 7950 GX2" },
{ 0x10DE0294, "GeForce 7950 GX2" },
{ 0x10DE0295, "GeForce 7950 GT" },
{ 0x10DE0298, "GeForce Go 7900 GS" },
{ 0x10DE0299, "GeForce Go 7900 GTX" },
{ 0x10DE029A, "Quadro FX 2500M" },
{ 0x10DE029B, "Quadro FX 1500M" },
{ 0x10DE029C, "Quadro FX 5500" },
{ 0x10DE029D, "Quadro FX 3500" },
{ 0x10DE029E, "Quadro FX 1500" },
{ 0x10DE029F, "Quadro FX 4500 X2" },
// 02A0 - 02AF
// 02B0 - 02BF
// 02C0 - 02CF
// 02D0 - 02DF
// 02E0 - 02EF
{ 0x10DE02E0, "GeForce 7600 GT" },
{ 0x10DE02E1, "GeForce 7600 GS" },
{ 0x10DE02E2, "GeForce 7300 GT" },
{ 0x10DE02E3, "GeForce 7900 GS" },
{ 0x10DE02E4, "GeForce 7950 GT" },
// 02F0 - 02FF
// 0300 - 030F
{ 0x10DE0301, "GeForce FX 5800 Ultra" },
{ 0x10DE0302, "GeForce FX 5800" },
{ 0x10DE0308, "Quadro FX 2000" },
{ 0x10DE0309, "Quadro FX 1000" },
// 0310 - 031F
{ 0x10DE0311, "GeForce FX 5600 Ultra" },
{ 0x10DE0312, "GeForce FX 5600" },
{ 0x10DE0314, "GeForce FX 5600XT" },
{ 0x10DE031A, "GeForce FX Go5600" },
{ 0x10DE031B, "GeForce FX Go5650" },
{ 0x10DE031C, "Quadro FX Go700" },
// 0320 - 032F
{ 0x10DE0324, "GeForce FX Go5200" },
{ 0x10DE0325, "GeForce FX Go5250" },
{ 0x10DE0326, "GeForce FX 5500" },
{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },
{ 0x10DE032A, "Quadro NVS 55/280 PCI" },
{ 0x10DE032B, "Quadro FX 500/600 PCI" },
{ 0x10DE032C, "GeForce FX Go53xx Series" },
{ 0x10DE032D, "GeForce FX Go5100" },
// 0330 - 033F
{ 0x10DE0330, "GeForce FX 5900 Ultra" },
{ 0x10DE0331, "GeForce FX 5900" },
{ 0x10DE0332, "GeForce FX 5900XT" },
{ 0x10DE0333, "GeForce FX 5950 Ultra" },
{ 0x10DE0334, "GeForce FX 5900ZT" },
{ 0x10DE0338, "Quadro FX 3000" },
{ 0x10DE033F, "Quadro FX 700" },
// 0340 - 034F
{ 0x10DE0341, "GeForce FX 5700 Ultra" },
{ 0x10DE0342, "GeForce FX 5700" },
{ 0x10DE0343, "GeForce FX 5700LE" },
{ 0x10DE0344, "GeForce FX 5700VE" },
{ 0x10DE0347, "GeForce FX Go5700" },
{ 0x10DE0348, "GeForce FX Go5700" },
{ 0x10DE034C, "Quadro FX Go1000" },
{ 0x10DE034E, "Quadro FX 1100" },
// 0350 - 035F
// 0360 - 036F
// 0370 - 037F
// 0380 - 038F
{ 0x10DE038B, "GeForce 7650 GS" },
// 0390 - 039F
{ 0x10DE0390, "GeForce 7650 GS" },
{ 0x10DE0391, "GeForce 7600 GT" },
{ 0x10DE0392, "GeForce 7600 GS" },
{ 0x10DE0393, "GeForce 7300 GT" },
{ 0x10DE0394, "GeForce 7600 LE" },
{ 0x10DE0395, "GeForce 7300 GT" },
{ 0x10DE0397, "GeForce Go 7700" },
{ 0x10DE0398, "GeForce Go 7600" },
{ 0x10DE0399, "GeForce Go 7600 GT"},
{ 0x10DE039A, "Quadro NVS 300M" },
{ 0x10DE039B, "GeForce Go 7900 SE" },
{ 0x10DE039C, "Quadro FX 550M" },
{ 0x10DE039E, "Quadro FX 560" },
// 03A0 - 03AF
// 03B0 - 03BF
// 03C0 - 03CF
// 03D0 - 03DF
{ 0x10DE03D0, "GeForce 6150SE nForce 430" },
{ 0x10DE03D1, "GeForce 6100 nForce 405" },
{ 0x10DE03D2, "GeForce 6100 nForce 400" },
{ 0x10DE03D5, "GeForce 6100 nForce 420" },
{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },
// 03E0 - 03EF
// 03F0 - 03FF
// 0400 - 040F
{ 0x10DE0400, "GeForce 8600 GTS" },
{ 0x10DE0401, "GeForce 8600 GT" },
{ 0x10DE0402, "GeForce 8600 GT" },
{ 0x10DE0403, "GeForce 8600 GS" },
{ 0x10DE0404, "GeForce 8400 GS" },
{ 0x10DE0405, "GeForce 9500M GS" },
{ 0x10DE0406, "GeForce 8300 GS" },
{ 0x10DE0407, "GeForce 8600M GT" },
{ 0x10DE0408, "GeForce 9650M GS" },
{ 0x10DE0409, "GeForce 8700M GT" },
{ 0x10DE040A, "Quadro FX 370" },
{ 0x10DE040B, "Quadro NVS 320M" },
{ 0x10DE040C, "Quadro FX 570M" },
{ 0x10DE040D, "Quadro FX 1600M" },
{ 0x10DE040E, "Quadro FX 570" },
{ 0x10DE040F, "Quadro FX 1700" },
// 0410 - 041F
{ 0x10DE0410, "GeForce GT 330" },
// 0420 - 042F
{ 0x10DE0420, "GeForce 8400 SE" },
{ 0x10DE0421, "GeForce 8500 GT" },
{ 0x10DE0422, "GeForce 8400 GS" },
{ 0x10DE0423, "GeForce 8300 GS" },
{ 0x10DE0424, "GeForce 8400 GS" },
{ 0x10DE0425, "GeForce 8600M GS" },
{ 0x10DE0426, "GeForce 8400M GT" },
{ 0x10DE0427, "GeForce 8400M GS" },
{ 0x10DE0428, "GeForce 8400M G" },
{ 0x10DE0429, "Quadro NVS 140M" },
{ 0x10DE042A, "Quadro NVS 130M" },
{ 0x10DE042B, "Quadro NVS 135M" },
{ 0x10DE042C, "GeForce 9400 GT" },
{ 0x10DE042D, "Quadro FX 360M" },
{ 0x10DE042E, "GeForce 9300M G" },
{ 0x10DE042F, "Quadro NVS 290" },
// 0430 - 043F
// 0440 - 044F
// 0450 - 045F
// 0460 - 046F
// 0470 - 047F
// 0480 - 048F
// 0490 - 049F
// 04A0 - 04AF
// 04B0 - 04BF
// 04C0 - 04CF
// 04D0 - 04DF
// 04E0 - 04EF
// 04F0 - 04FF
// 0500 - 050F
// 0510 - 051F
// 0520 - 052F
// 0530 - 053F
{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },
{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },
{ 0x10DE053E, "GeForce 7025 / nForce 630a" },
// 0540 - 054F
// 0550 - 055F
// 0560 - 056F
// 0570 - 057F
// 0580 - 058F
// 0590 - 059F
// 05A0 - 05AF
// 05B0 - 05BF
// 05C0 - 05CF
// 05D0 - 05DF
// 05E0 - 05EF
{ 0x10DE05E0, "GeForce GTX 295" },
{ 0x10DE05E1, "GeForce GTX 280" },
{ 0x10DE05E2, "GeForce GTX 260" },
{ 0x10DE05E3, "GeForce GTX 285" },
{ 0x10DE05E6, "GeForce GTX 275" },
{ 0x10DE05EA, "GeForce GTX 260" },
{ 0x10DE05EB, "GeForce GTX 295" },
{ 0x10DE05ED, "Quadroplex 2200 D2" },
// 05F0 - 05FF
{ 0x10DE05F8, "Quadroplex 2200 S4" },
{ 0x10DE05F9, "Quadro CX" },
{ 0x10DE05FD, "Quadro FX 5800" },
{ 0x10DE05FE, "Quadro FX 4800" },
{ 0x10DE05FF, "Quadro FX 3800" },
// 0600 - 060F
{ 0x10DE0600, "GeForce 8800 GTS 512" },
{ 0x10DE0601, "GeForce 9800 GT" },
{ 0x10DE0602, "GeForce 8800 GT" },
{ 0x10DE0603, "GeForce GT 230" },
{ 0x10DE0604, "GeForce 9800 GX2" },
{ 0x10DE0605, "GeForce 9800 GT" },
{ 0x10DE0606, "GeForce 8800 GS" },
{ 0x10DE0607, "GeForce GTS 240" },
{ 0x10DE0608, "GeForce 9800M GTX" },
{ 0x10DE0609, "GeForce 8800M GTS" },
{ 0x10DE060A, "GeForce GTX 280M" },
{ 0x10DE060B, "GeForce 9800M GT" },
{ 0x10DE060C, "GeForce 8800M GTX" },
{ 0x10DE060D, "GeForce 8800 GS" },
{ 0x10DE060F, "GeForce GTX 285M" },
// 0610 - 061F
{ 0x10DE0610, "GeForce 9600 GSO" },
{ 0x10DE0611, "GeForce 8800 GT" },
{ 0x10DE0612, "GeForce 9800 GTX" },
{ 0x10DE0613, "GeForce 9800 GTX+" },
{ 0x10DE0614, "GeForce 9800 GT" },
{ 0x10DE0615, "GeForce GTS 250" },
{ 0x10DE0617, "GeForce 9800M GTX" },
{ 0x10DE0618, "GeForce GTX 260M" },
{ 0x10DE0619, "Quadro FX 4700 X2" },
{ 0x10DE061A, "Quadro FX 3700" },
{ 0x10DE061B, "Quadro VX 200" },
{ 0x10DE061C, "Quadro FX 3600M" },
{ 0x10DE061D, "Quadro FX 2800M" },
{ 0x10DE061F, "Quadro FX 3800M" },
// 0620 - 062F
{ 0x10DE0622, "GeForce 9600 GT" },
{ 0x10DE0623, "GeForce 9600 GS" },
{ 0x10DE0625, "GeForce 9600 GSO 512"},
{ 0x10DE0626, "GeForce GT 130" },
{ 0x10DE0627, "GeForce GT 140" },
{ 0x10DE0628, "GeForce 9800M GTS" },
{ 0x10DE062A, "GeForce 9700M GTS" },
{ 0x10DE062C, "GeForce 9800M GTS" },
{ 0x10DE062D, "GeForce 9600 GT" },
{ 0x10DE062E, "GeForce 9600 GT" },
// 0630 - 063F
{ 0x10DE0631, "GeForce GTS 160M" },
{ 0x10DE0632, "GeForce GTS 150M" },
{ 0x10DE0635, "GeForce 9600 GSO" },
{ 0x10DE0637, "GeForce 9600 GT" },
{ 0x10DE0638, "Quadro FX 1800" },
{ 0x10DE063A, "Quadro FX 2700M" },
// 0640 - 064F
{ 0x10DE0640, "GeForce 9500 GT" },
{ 0x10DE0641, "GeForce 9400 GT" },
{ 0x10DE0642, "GeForce 8400 GS" },
{ 0x10DE0643, "GeForce 9500 GT" },
{ 0x10DE0644, "GeForce 9500 GS" },
{ 0x10DE0645, "GeForce 9500 GS" },
{ 0x10DE0646, "GeForce GT 120" },
{ 0x10DE0647, "GeForce 9600M GT" },
{ 0x10DE0648, "GeForce 9600M GS" },
{ 0x10DE0649, "GeForce 9600M GT" },
{ 0x10DE064A, "GeForce 9700M GT" },
{ 0x10DE064B, "GeForce 9500M G" },
{ 0x10DE064C, "GeForce 9650M GT" },
// 0650 - 065F
{ 0x10DE0651, "GeForce G 110M" },
{ 0x10DE0652, "GeForce GT 130M" },
{ 0x10DE0653, "GeForce GT 120M" },
{ 0x10DE0654, "GeForce GT 220M" },
{ 0x10DE0656, "GeForce 9650 S" },
{ 0x10DE0658, "Quadro FX 380" },
{ 0x10DE0659, "Quadro FX 580" },
{ 0x10DE065A, "Quadro FX 1700M" },
{ 0x10DE065B, "GeForce 9400 GT" },
{ 0x10DE065C, "Quadro FX 770M" },
{ 0x10DE065F, "GeForce G210" },
// 0660 - 066F
// 0670 - 067F
// 0680 - 068F
// 0690 - 069F
// 06A0 - 06AF
// 06B0 - 06BF
// 06C0 - 06CF
{ 0x10DE06C0, "GeForce GTX 480" },
{ 0x10DE06C3, "GeForce GTX D12U" },
{ 0x10DE06C4, "GeForce GTX 465" },
{ 0x10DE06CA, "GeForce GTX 480M" },
{ 0x10DE06CD, "GeForce GTX 470" },
// 06D0 - 06DF
{ 0x10DE06D1, "Tesla C2050" },// TODO: sub-device id: 0x0771
{ 0x10DE06D1, "Tesla C2070" },// TODO: sub-device id: 0x0772
{ 0x10DE06D2, "Tesla M2070" },
{ 0x10DE06D8, "Quadro 6000" },
{ 0x10DE06D9, "Quadro 5000" },
{ 0x10DE06DA, "Quadro 5000M" },
{ 0x10DE06DC, "Quadro 6000" },
{ 0x10DE06DD, "Quadro 4000" },
{ 0x10DE06DE, "Tesla M2050" },// TODO: sub-device id: 0x0846
{ 0x10DE06DE, "Tesla M2070" },// TODO: sub-device id: ?
// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070
// 06E0 - 06EF
{ 0x10DE06E0, "GeForce 9300 GE" },
{ 0x10DE06E1, "GeForce 9300 GS" },
{ 0x10DE06E2, "GeForce 8400" },
{ 0x10DE06E3, "GeForce 8400 SE" },
{ 0x10DE06E4, "GeForce 8400 GS" },
{ 0x10DE06E5, "GeForce 9300M GS" },
{ 0x10DE06E6, "GeForce G100" },
{ 0x10DE06E7, "GeForce 9300 SE" },
{ 0x10DE06E8, "GeForce 9200M GS" },
{ 0x10DE06E9, "GeForce 9300M GS" },
{ 0x10DE06EA, "Quadro NVS 150M" },
{ 0x10DE06EB, "Quadro NVS 160M" },
{ 0x10DE06EC, "GeForce G 105M" },
{ 0x10DE06EF, "GeForce G 103M" },
// 06F0 - 06FF
{ 0x10DE06F8, "Quadro NVS 420" },
{ 0x10DE06F9, "Quadro FX 370 LP" },
{ 0x10DE06FA, "Quadro NVS 450" },
{ 0x10DE06FB, "Quadro FX 370M" },
{ 0x10DE06FD, "Quadro NVS 295" },
// 0700 - 070F
// 0710 - 071F
// 0720 - 072F
// 0730 - 073F
// 0740 - 074F
// 0750 - 075F
// 0760 - 076F
// 0770 - 077F
// 0780 - 078F
// 0790 - 079F
// 07A0 - 07AF
// 07B0 - 07BF
// 07C0 - 07CF
// 07D0 - 07DF
// 07E0 - 07EF
{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },
{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },
{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },
{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },
{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },
// 07F0 - 07FF
// 0800 - 080F
// 0810 - 081F
// 0820 - 082F
// 0830 - 083F
// 0840 - 084F
{ 0x10DE0844, "GeForce 9100M G" },
{ 0x10DE0845, "GeForce 8200M G" },
{ 0x10DE0846, "GeForce 9200" },
{ 0x10DE0847, "GeForce 9100" },
{ 0x10DE0848, "GeForce 8300" },
{ 0x10DE0849, "GeForce 8200" },
{ 0x10DE084A, "nForce 730a" },
{ 0x10DE084B, "GeForce 9200" },
{ 0x10DE084C, "nForce 980a/780a SLI" },
{ 0x10DE084D, "nForce 750a SLI" },
{ 0x10DE084F, "GeForce 8100 / nForce 720a" },
// 0850 - 085F
// 0860 - 086F
{ 0x10DE0860, "GeForce 9400" },
{ 0x10DE0861, "GeForce 9400" },
{ 0x10DE0862, "GeForce 9400M G" },
{ 0x10DE0863, "GeForce 9400M" },
{ 0x10DE0864, "GeForce 9300" },
{ 0x10DE0865, "ION" },
{ 0x10DE0866, "GeForce 9400M G" },
{ 0x10DE0867, "GeForce 9400" },
{ 0x10DE0868, "nForce 760i SLI" },
{ 0x10DE086A, "GeForce 9400" },
{ 0x10DE086C, "GeForce 9300 / nForce 730i" },
{ 0x10DE086D, "GeForce 9200" },
{ 0x10DE086E, "GeForce 9100M G" },
{ 0x10DE086F, "GeForce 8200M G" },
// 0870 - 087F
{ 0x10DE0870, "GeForce 9400M" },
{ 0x10DE0871, "GeForce 9200" },
{ 0x10DE0872, "GeForce G102M" },
{ 0x10DE0873, "GeForce G102M" },
{ 0x10DE0874, "ION 9300M" },
{ 0x10DE0876, "ION" },
{ 0x10DE087A, "GeForce 9400" },
{ 0x10DE087D, "ION 9400M" },
{ 0x10DE087E, "ION LE" },
{ 0x10DE087F, "ION LE" },
// 0880 - 088F
// 0890 - 089F
// 08A0 - 08AF
// 08B0 - 08BF
// 08C0 - 08CF
// 08D0 - 08DF
// 08E0 - 08EF
// 08F0 - 08FF
// 0900 - 090F
// 0910 - 091F
// 0920 - 092F
// 0930 - 093F
// 0940 - 094F
// 0950 - 095F
// 0960 - 096F
// 0970 - 097F
// 0980 - 098F
// 0990 - 099F
// 09A0 - 09AF
// 09B0 - 09BF
// 09C0 - 09CF
// 09D0 - 09DF
// 09E0 - 09EF
// 09F0 - 09FF
// 0A00 - 0A0F
// 0A10 - 0A1F
// 0A20 - 0A2F
{ 0x10DE0A20, "GeForce GT220" },
{ 0x10DE0A22, "GeForce 315" },
{ 0x10DE0A23, "GeForce 210" },
{ 0x10DE0A28, "GeForce GT 230M" },
{ 0x10DE0A29, "GeForce GT 330M" },
{ 0x10DE0A2A, "GeForce GT 230M" },
{ 0x10DE0A2B, "GeForce GT 330M" },
{ 0x10DE0A2C, "NVS 5100M" },
{ 0x10DE0A2D, "GeForce GT 320M" },
// 0A30 - 0A3F
{ 0x10DE0A34, "GeForce GT 240M" },
{ 0x10DE0A35, "GeForce GT 325M" },
{ 0x10DE0A3C, "Quadro FX 880M" },
// 0A40 - 0A4F
// 0A50 - 0A5F
// 0A60 - 0A6F
{ 0x10DE0A60, "GeForce G210" },
{ 0x10DE0A62, "GeForce 205" },
{ 0x10DE0A63, "GeForce 310" },
{ 0x10DE0A64, "ION" },
{ 0x10DE0A65, "GeForce 210" },
{ 0x10DE0A66, "GeForce 310" },
{ 0x10DE0A67, "GeForce 315" },
{ 0x10DE0A68, "GeForce G105M" },
{ 0x10DE0A69, "GeForce G105M" },
{ 0x10DE0A6A, "NVS 2100M" },
{ 0x10DE0A6C, "NVS 3100M" },
{ 0x10DE0A6E, "GeForce 305M" },
{ 0x10DE0A6F, "ION" },
// 0A70 - 0A7F
{ 0x10DE0A70, "GeForce 310M" },
{ 0x10DE0A71, "GeForce 305M" },
{ 0x10DE0A72, "GeForce 310M" },
{ 0x10DE0A73, "GeForce 305M" },
{ 0x10DE0A74, "GeForce G210M" },
{ 0x10DE0A75, "GeForce G310M" },
{ 0x10DE0A78, "Quadro FX 380 LP" },
{ 0x10DE0A7C, "Quadro FX 380M" },
// 0A80 - 0A8F
// 0A90 - 0A9F
// 0AA0 - 0AAF
// 0AB0 - 0ABF
// 0AC0 - 0ACF
// 0AD0 - 0ADF
// 0AE0 - 0AEF
// 0AF0 - 0AFF
// 0B00 - 0B0F
// 0B10 - 0B1F
// 0B20 - 0B2F
// 0B30 - 0B3F
// 0B40 - 0B4F
// 0B50 - 0B5F
// 0B60 - 0B6F
// 0B70 - 0B7F
// 0B80 - 0B8F
// 0B90 - 0B9F
// 0BA0 - 0BAF
// 0BB0 - 0BBF
// 0BC0 - 0BCF
// 0BD0 - 0BDF
// 0BE0 - 0BEF
// 0BF0 - 0BFF
// 0C00 - 0C0F
// 0C10 - 0C1F
// 0C20 - 0C2F
// 0C30 - 0C3F
// 0C40 - 0C4F
// 0C50 - 0C5F
// 0C60 - 0C6F
// 0C70 - 0C7F
// 0C80 - 0C8F
// 0C90 - 0C9F
// 0CA0 - 0CAF
{ 0x10DE0CA0, "GeForce GT 330 " },
{ 0x10DE0CA2, "GeForce GT 320" },
{ 0x10DE0CA3, "GeForce GT 240" },
{ 0x10DE0CA4, "GeForce GT 340" },
{ 0x10DE0CA7, "GeForce GT 330" },
{ 0x10DE0CA8, "GeForce GTS 260M" },
{ 0x10DE0CA9, "GeForce GTS 250M" },
{ 0x10DE0CAC, "GeForce 315" },
{ 0x10DE0CAF, "GeForce GT 335M" },
// 0CB0 - 0CBF
{ 0x10DE0CB0, "GeForce GTS 350M" },
{ 0x10DE0CB1, "GeForce GTS 360M" },
{ 0x10DE0CBC, "Quadro FX 1800M" },
// 0CC0 - 0CCF
// 0CD0 - 0CDF
// 0CE0 - 0CEF
// 0CF0 - 0CFF
// 0D00 - 0D0F
// 0D10 - 0D1F
// 0D20 - 0D2F
// 0D30 - 0D3F
// 0D40 - 0D4F
// 0D50 - 0D5F
// 0D60 - 0D6F
// 0D70 - 0D7F
// 0D80 - 0D8F
// 0D90 - 0D9F
// 0DA0 - 0DAF
// 0DB0 - 0DBF
// 0DC0 - 0DCF
{ 0x10DE0DC0, "GeForce GT 440" },
{ 0x10DE0DC1, "D12-P1-35" },
{ 0x10DE0DC2, "D12-P1-35" },
{ 0x10DE0DC4, "GeForce GTS 450" },
{ 0x10DE0DC5, "GeForce GTS 450" },
{ 0x10DE0DC6, "GeForce GTS 450" },
{ 0x10DE0DCA, "GF10x" },
// 0DD0 - 0DDF
{ 0x10DE0DD1, "GeForce GTX 460M" },
{ 0x10DE0DD2, "GeForce GT 445M" },
{ 0x10DE0DD3, "GeForce GT 435M" },
{ 0x10DE0DD8, "Quadro 2000" },
{ 0x10DE0DDE, "GF106-ES" },
{ 0x10DE0DDF, "GF106-INT" },
// 0DE0 - 0DEF
{ 0x10DE0DE0, "GeForce GT 440" },
{ 0x10DE0DE1, "GeForce GT 430" },
{ 0x10DE0DE2, "GeForce GT 420" },
{ 0x10DE0DE5, "GeForce GT 530" },
{ 0x10DE0DEB, "GeForce GT 555M" },
{ 0x10DE0DEE, "GeForce GT 415M" },
// 0DF0 - 0DFF
{ 0x10DE0DF0, "GeForce GT 425M" },
{ 0x10DE0DF1, "GeForce GT 420M" },
{ 0x10DE0DF2, "GeForce GT 435M" },
{ 0x10DE0DF3, "GeForce GT 420M" },
{ 0x10DE0DF8, "Quadro 600" },
{ 0x10DE0DFE, "GF108 ES" },
{ 0x10DE0DFF, "GF108 INT" },
// 0E00 - 0E0F
// 0E10 - 0E1F
// 0E20 - 0E2F
{ 0x10DE0E21, "D12U-25" },
{ 0x10DE0E22, "GeForce GTX 460" },
{ 0x10DE0E23, "GeForce GTX 460 SE" },
{ 0x10DE0E24, "GeForce GTX 460" },
{ 0x10DE0E25, "D12U-50" },
// 0E30 - 0E3F
{ 0x10DE0E30, "GeForce GTX 470M" },
{ 0x10DE0E38, "GF104GL" },
{ 0x10DE0E3E, "GF104-ES" },
{ 0x10DE0E3F, "GF104-INT" },
// 0E40 - 0E4F
// 0E50 - 0E5F
// 0E60 - 0E6F
// 0E70 - 0E7F
// 0E80 - 0E8F
// 0E90 - 0E9F
// 0EA0 - 0EAF
// 0EB0 - 0EBF
// 0EC0 - 0ECF
// 0ED0 - 0EDF
// 0EE0 - 0EEF
// 0EF0 - 0EFF
// 0F00 - 0F0F
// 0F10 - 0F1F
// 0F20 - 0F2F
// 0F30 - 0F3F
// 0F40 - 0F4F
// 0F50 - 0F5F
// 0F60 - 0F6F
// 0F70 - 0F7F
// 0F80 - 0F8F
// 0F90 - 0F9F
// 0FA0 - 0FAF
// 0FB0 - 0FBF
// 0FC0 - 0FCF
// 0FD0 - 0FDF
// 0FE0 - 0FEF
// 0FF0 - 0FFF
// 1000 - 100F
// 1010 - 101F
// 1020 - 102F
// 1030 - 103F
// 1040 - 104F
{ 0x10DE1040, "GeForce GT 520" },
// 1050 - 105F
{ 0x10DE1050, "GeForce GT 520M" },
// 1060 - 106F
// 1070 - 107F
// 1080 - 108F
{ 0x10DE1080, "GeForce GTX 580" },
{ 0x10DE1081, "GeForce GTX 570" },
{ 0x10DE1082, "GeForce GTX 560 Ti" },
{ 0x10DE1083, "D13U" },
{ 0x10DE1088, "GeForce GTX 590" },
// 1090 - 109F
{ 0x10DE1098, "D13U" },
{ 0x10DE109A, "N12E-Q5" },
// 10A0 - 10AF
// 10B0 - 10BF
// 10C0 - 10CF
{ 0x10DE10C3, "GeForce 8400 GS" },
// 1200 -
{ 0x10DE1200, "GeForce GTX 560 Ti" },
{ 0x10DE1244, "GeForce GTX 550 Ti" },
{ 0x10DE1245, "GeForce GTS 450" },
};
static uint16_t swap16(uint16_t x)
{
return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));
}
static uint16_t read16(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[2];
ret[0] = ptr[offset+1];
ret[1] = ptr[offset];
return *((uint16_t*)&ret);
}
#if 0
static uint32_t swap32(uint32_t x)
{
return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);
}
static uint8_t read8(uint8_t *ptr, uint16_t offset)
{
return ptr[offset];
}
static uint32_t read32(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[4];
ret[0] = ptr[offset+3];
ret[1] = ptr[offset+2];
ret[2] = ptr[offset+1];
ret[3] = ptr[offset];
return *((uint32_t*)&ret);
}
#endif
static int patch_nvidia_rom(uint8_t *rom)
{
if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {
printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);
return PATCH_ROM_FAILED;
}
uint16_t dcbptr = swap16(read16(rom, 0x36));
if(!dcbptr) {
printf("no dcb table found\n");
return PATCH_ROM_FAILED;
}/* else
printf("dcb table at offset 0x%04x\n", dcbptr);
*/
uint8_t *dcbtable = &rom[dcbptr];
uint8_t dcbtable_version = dcbtable[0];
uint8_t headerlength = 0;
uint8_t recordlength = 0;
uint8_t numentries = 0;
if(dcbtable_version >= 0x20) {
uint32_t sig;
if(dcbtable_version >= 0x30) {
headerlength = dcbtable[1];
numentries = dcbtable[2];
recordlength = dcbtable[3];
sig = *(uint32_t *)&dcbtable[6];
} else {
sig = *(uint32_t *)&dcbtable[4];
headerlength = 8;
}
if (sig != 0x4edcbdcb) {
//Azi: match this with one below and add line number ?
printf("Bad display config block signature (0x%8x)\n", sig);
return PATCH_ROM_FAILED;
}
} else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */
char sig[8] = { 0 };
strncpy(sig, (char *)&dcbtable[-7], 7);
recordlength = 10;
if (strcmp(sig, "DEV_REC")) {
printf("Bad Display Configuration Block signature (%s)\n", sig);
return PATCH_ROM_FAILED;
}
} else {
printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);
return PATCH_ROM_FAILED;
}
if(numentries >= MAX_NUM_DCB_ENTRIES)
numentries = MAX_NUM_DCB_ENTRIES;
uint8_t num_outputs = 0, i=0;
struct dcbentry {
uint8_t type;
uint8_t index;
uint8_t *heads;
} entries[numentries];
for (i = 0; i < numentries; i++) {
uint32_t connection;
connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];
/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
continue;
if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */
continue;
if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */
continue;
entries[num_outputs].type = connection & 0xf;
entries[num_outputs].index = num_outputs;
entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);
}
int has_lvds = false;
uint8_t channel1 = 0, channel2 = 0;
for(i=0; i<num_outputs; i++) {
if(entries[i].type == 3) {
has_lvds = true;
//printf("found LVDS\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
}
// if we have a LVDS output, we group the rest to the second channel
if(has_lvds) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
continue;
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
} else {
//
int x;
// we loop twice as we need to generate two channels
for(x=0; x<=1; x++) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
continue;
// if type is TMDS, the prior output is ANALOG
// we always group ANALOG and TMDS
// if there is a TV output after TMDS, we group it to that channel as well
if(i && entries[i].type == 0x2) {
switch (x) {
case 0:
//printf("group channel 1\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if((entries[i-1].type == 0x0)) {
channel1 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
//printf("group tv1\n");
channel1 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
case 1:
//printf("group channel 2 : %d\n", i);
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if((entries[i-1].type == 0x0)) {
channel2 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
//printf("group tv2\n");
channel2 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
}
break;
}
}
}
}
// if we have left ungrouped outputs merge them to the empty channel
uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);
togroup = &channel2;
for(i=0; i<num_outputs;i++)
if(entries[i].type != TYPE_GROUPED) {
//printf("%d not grouped\n", i);
if(togroup)
*togroup |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
if(channel1 > channel2) {
uint8_t buff = channel1;
channel1 = channel2;
channel2 = buff;
}
default_NVCAP[6] = channel1;
default_NVCAP[8] = channel2;
// patching HEADS
for(i=0; i<num_outputs;i++) {
if(channel1 & (1 << i))
*entries[i].heads = 1;
else if(channel2 & (1 << i))
*entries[i].heads = 2;
}
return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);
}
static char *get_nvidia_model(uint32_t id) {
inti;
for (i=1; i< (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {
if (NVKnownChipsets[i].device == id) {
return NVKnownChipsets[i].name;
}
}
return NVKnownChipsets[0].name;
}
static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)
{
intfd;
intsize;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {
return 0;
}
size = file_size(fd);
if (size > bufsize) {
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);
size = bufsize;
}
size = read(fd, (char *)buf, size);
close(fd);
return size > 0 ? size : 0;
}
static int devprop_add_nvidia_template(struct DevPropDevice *device)
{
chartmp[16];
if(!device)
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_name_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_name_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type))
return 0;
// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!
// len = sprintf(tmp, "Slot-%x", devices_number);
sprintf(tmp, "Slot-%x",devices_number);
devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));
devices_number++;
return 1;
}
int hex2bin(const char *hex, uint8_t *bin, int len)
{
char*p;
inti;
charbuf[3];
if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {
printf("[ERROR] bin2hex input error\n");
return -1;
}
buf[2] = '\0';
p = (char *) hex;
for (i=0; i<len; i++) {
if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {
printf("[ERROR] bin2hex '%s' syntax error\n", hex);
return -2;
}
buf[0] = *p++;
buf[1] = *p++;
bin[i] = (unsigned char) strtoul(buf, NULL, 16);
}
return 0;
}
unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)
{
unsigned long long vram_size = 0;
if (nvCardType < NV_ARCH_50) {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
}
else if (nvCardType < NV_ARCH_C0) {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size |= (vram_size & 0xff) << 32;
vram_size &= 0xffffffff00ll;
}
else { // >= NV_ARCH_C0
vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;
vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);
}
// Workaround for GT 420/430 & 9600M GT
switch (nvda_dev->device_id)
{
case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430
case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420
case 0x0649: vram_size = 512*1024*1024; break; // 9600M GT
default: break;
}
return vram_size;
}
bool setup_nvidia_devprop(pci_dt_t *nvda_dev)
{
struct DevPropDevice*device;
char*devicepath;
option_rom_pci_header_t*rom_pci_header;
volatile uint8_t*regs;
uint8_t*rom;
uint8_t*nvRom;
uint8_tnvCardType;
unsigned long longvideoRam;
uint32_tnvBiosOveride;
uint32_tbar[7];
uint32_tboot_display;
intnvPatch;
intlen;
charbiosVersion[32];
charnvFilename[32];
charkNVCAP[12];
char*model;
const char*value;
booldoit;
devicepath = get_pci_dev_path(nvda_dev);
bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );
regs = (uint8_t *) (bar[0] & ~0x0f);
// get card type
nvCardType = (REG32(0) >> 20) & 0x1ff;
// Amount of VRAM in kilobytes
videoRam = mem_detect(regs, nvCardType, nvda_dev);
model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);
verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",
model, (uint32_t)(videoRam / 1024 / 1024),
(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,
devicepath);
rom = malloc(NVIDIA_ROM_SIZE);
sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id);
if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit) {
verbose("Looking for nvidia video bios file %s\n", nvFilename);
nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);
if (nvBiosOveride > 0) {
verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);
DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);
} else {
printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);
return false;
}
} else {
// Otherwise read bios from card