Chameleon

Chameleon Commit Details

Date:2011-08-01 05:13:00 (7 years 11 months ago)
Author:Azimutz
Commit:1251
Parents: 1250
Message:Sync with trunk (r1248).
Changes:
C/trunk/i386/boot0/boot0hfs.s → /branches/azimutz/trunkAutoResolution/i386/boot0/boot0hfs.s
C/trunk/package/Resources/Russian.lproj → /branches/azimutz/trunkAutoResolution/package/Resources/Russian.lproj
C/trunk/i386/boot0/boot0md.s → /branches/azimutz/trunkAutoResolution/i386/boot0/boot0md.s
M/branches/azimutz/trunkAutoResolution/i386/libsaio/cpu.h
M/branches/azimutz/trunkAutoResolution/i386/boot0/Makefile
M/branches/azimutz/trunkAutoResolution/CREDITS
M/branches/azimutz/trunkAutoResolution/doc/BootHelp.txt
M/branches/azimutz/trunkAutoResolution
M/branches/azimutz/trunkAutoResolution/i386/boot0/boot0.s
M/branches/azimutz/trunkAutoResolution/i386/boot2/boot.c
M/branches/azimutz/trunkAutoResolution/BLOCKERS
M/branches/azimutz/trunkAutoResolution/package/buildpkg.sh
M/branches/azimutz/trunkAutoResolution/i386/libsaio/nvidia.c
M/branches/azimutz/trunkAutoResolution/i386/boot2/boot.h
M/branches/azimutz/trunkAutoResolution/CHANGES
M/branches/azimutz/trunkAutoResolution/i386/libsaio/ati.c
M/branches/azimutz/trunkAutoResolution/i386/libsaio/stringTable.c
M/branches/azimutz/trunkAutoResolution/i386/boot2/drivers.c
M/branches/azimutz/trunkAutoResolution/Makefile
M/branches/azimutz/trunkAutoResolution/i386/libsaio/acpi_patcher.c
M/branches/azimutz/trunkAutoResolution/i386/libsaio/cpu.c
M/branches/azimutz/trunkAutoResolution/i386/boot0/Cconfig
M/branches/azimutz/trunkAutoResolution/i386/libsaio/platform.h

File differences

branches/azimutz/trunkAutoResolution/i386/libsaio/acpi_patcher.c
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uint8_tacpi_cpu_count = 0;
char* acpi_cpu_name[32];
uint32_t acpi_cpu_p_blk = 0;
void get_acpi_cpu_names(unsigned char* dsdt, uint32_t length)
{
acpi_cpu_name[acpi_cpu_count] = malloc(4);
memcpy(acpi_cpu_name[acpi_cpu_count], dsdt+offset, 4);
i = offset + 5;
if (acpi_cpu_count == 0)
acpi_cpu_p_blk = dsdt[i] | (dsdt[i+1] << 8);
verbose("Found ACPI CPU: %c%c%c%c\n", acpi_cpu_name[acpi_cpu_count][0], acpi_cpu_name[acpi_cpu_count][1], acpi_cpu_name[acpi_cpu_count][2], acpi_cpu_name[acpi_cpu_count][3]);
0x31, 0x03, 0x10, 0x20 /* 1.._*/
};
char cstate_resource_template[] =
char resource_template_register_fixedhw[] =
{
0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x7F,
0x01, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x79, 0x00
0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x01, 0x79, 0x00
};
char resource_template_register_systemio[] =
{
0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x01,
0x08, 0x00, 0x00, 0x15, 0x04, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x79, 0x00,
};
if (Platform.CPU.Vendor != 0x756E6547) {
verbose ("Not an Intel platform: C-States will not be generated !!!\n");
bool c2_enabled = false;
bool c3_enabled = false;
bool c4_enabled = false;
bool cst_using_sustemio = false;
getBoolForKey(kEnableC2States, &c2_enabled, &bootInfo->chameleonConfig);
getBoolForKey(kEnableC3States, &c3_enabled, &bootInfo->chameleonConfig);
getBoolForKey(kEnableC4States, &c4_enabled, &bootInfo->chameleonConfig);
getBoolForKey(kEnableC2State, &c2_enabled, &bootInfo->chameleonConfig);
getBoolForKey(kEnableC3State, &c3_enabled, &bootInfo->chameleonConfig);
getBoolForKey(kEnableC4State, &c4_enabled, &bootInfo->chameleonConfig);
getBoolForKey(kCSTUsingSystemIO, &cst_using_sustemio, &bootInfo->chameleonConfig);
c2_enabled = c2_enabled | (fadt->C2_Latency < 100);
c3_enabled = c3_enabled | (fadt->C3_Latency < 1000);
aml_add_byte(pack, cstates_count);
struct aml_chunk* tmpl = aml_add_package(pack);
cstate_resource_template[11] = 0x00; // C1
aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template));
aml_add_byte(tmpl, 0x01); // C1
aml_add_byte(tmpl, 0x01); // Latency
aml_add_word(tmpl, 0x03e8); // Power
if (cst_using_sustemio)
{
// C1
resource_template_register_fixedhw[8] = 0x00;
resource_template_register_fixedhw[9] = 0x00;
resource_template_register_fixedhw[18] = 0x00;
aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));
aml_add_byte(tmpl, 0x01); // C1
aml_add_word(tmpl, 0x0001); // Latency
aml_add_dword(tmpl, 0x000003e8); // Power
uint8_t p_blk_lo, p_blk_hi;
if (c2_enabled) // C2
{
p_blk_lo = acpi_cpu_p_blk + 4;
p_blk_hi = (acpi_cpu_p_blk + 4) >> 8;
tmpl = aml_add_package(pack);
resource_template_register_systemio[11] = p_blk_lo; // C2
resource_template_register_systemio[12] = p_blk_hi; // C2
aml_add_buffer(tmpl, resource_template_register_systemio, sizeof(resource_template_register_systemio));
aml_add_byte(tmpl, 0x02); // C2
aml_add_word(tmpl, 0x0040); // Latency
aml_add_dword(tmpl, 0x000001f4); // Power
}
if (c4_enabled) // C4
{
p_blk_lo = acpi_cpu_p_blk + 5;
p_blk_hi = (acpi_cpu_p_blk + 5) >> 8;
tmpl = aml_add_package(pack);
resource_template_register_systemio[11] = p_blk_lo; // C4
resource_template_register_systemio[12] = p_blk_hi; // C4
aml_add_buffer(tmpl, resource_template_register_systemio, sizeof(resource_template_register_systemio));
aml_add_byte(tmpl, 0x04); // C4
aml_add_word(tmpl, 0x0080); // Latency
aml_add_dword(tmpl, 0x000000C8); // Power
}
else if (c3_enabled) // C3
{
p_blk_lo = acpi_cpu_p_blk + 5;
p_blk_hi = (acpi_cpu_p_blk + 5) >> 8;
tmpl = aml_add_package(pack);
resource_template_register_systemio[11] = p_blk_lo; // C3
resource_template_register_systemio[12] = p_blk_hi; // C3
aml_add_buffer(tmpl, resource_template_register_systemio, sizeof(resource_template_register_systemio));
aml_add_byte(tmpl, 0x03); // C3
aml_add_word(tmpl, 0x0060); // Latency
aml_add_dword(tmpl, 0x0000015e); // Power
}
// C2
if (c2_enabled)
{
tmpl = aml_add_package(pack);
cstate_resource_template[11] = 0x10; // C2
aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template));
aml_add_byte(tmpl, 0x02); // C2
aml_add_byte(tmpl, fadt->C2_Latency);
aml_add_word(tmpl, 0x01f4); // Power
}
// C4
if (c4_enabled)
{
tmpl = aml_add_package(pack);
cstate_resource_template[11] = 0x30; // C4
aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template));
aml_add_byte(tmpl, 0x04); // C4
aml_add_word(tmpl, fadt->C3_Latency / 2); // TODO: right latency for C4
aml_add_byte(tmpl, 0xfa); // Power
}
else
// C3
if (c3_enabled)
{
tmpl = aml_add_package(pack);
cstate_resource_template[11] = 0x20; // C3
aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template));
aml_add_byte(tmpl, 0x03); // C3
aml_add_word(tmpl, fadt->C3_Latency);
aml_add_word(tmpl, 0x015e); // Power
}
}
else
{
// C1
resource_template_register_fixedhw[11] = 0x00; // C1
aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));
aml_add_byte(tmpl, 0x01); // C1
aml_add_word(tmpl, 0x0001); // Latency
aml_add_dword(tmpl, 0x000003e8); // Power
resource_template_register_fixedhw[18] = 0x03;
if (c2_enabled) // C2
{
tmpl = aml_add_package(pack);
resource_template_register_fixedhw[11] = 0x10; // C2
aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));
aml_add_byte(tmpl, 0x02); // C2
aml_add_word(tmpl, 0x0040); // Latency
aml_add_dword(tmpl, 0x000001f4); // Power
}
if (c4_enabled) // C4
{
tmpl = aml_add_package(pack);
resource_template_register_fixedhw[11] = 0x30; // C4
aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));
aml_add_byte(tmpl, 0x04); // C4
aml_add_word(tmpl, 0x0080); // Latency
aml_add_dword(tmpl, 0x000000C8); // Power
}
else if (c3_enabled)
{
tmpl = aml_add_package(pack);
resource_template_register_fixedhw[11] = 0x20; // C3
aml_add_buffer(tmpl, resource_template_register_fixedhw, sizeof(resource_template_register_fixedhw));
aml_add_byte(tmpl, 0x03); // C3
aml_add_word(tmpl, 0x0060); // Latency
aml_add_dword(tmpl, 0x0000015e); // Power
}
}
// Aliaces
int i;
branches/azimutz/trunkAutoResolution/i386/libsaio/nvidia.c
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/*
* NVidia injector
*NVidia injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi
*Copyright (C) 2009Jasmin Fazlic, iNDi
*
* NVidia injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*NVidia injector is free software: you can redistribute it and/or modify
*it under the terms of the GNU General Public License as published by
*the Free Software Foundation, either version 3 of the License, or
*(at your option) any later version.
*
* NVidia driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*NVidia driver and injector is distributed in the hope that it will be useful,
*but WITHOUT ANY WARRANTY; without even the implied warranty of
*MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*You should have received a copy of the GNU General Public License
*along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
/*
* DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
*
* SOFTWARE.
*/
#include "libsaio.h"
#include "boot.h"
#include "bootstruct.h"
#include "pci.h"
#define DBG(x...)
#endif
#define NVIDIA_ROM_SIZE 0x10000
#define PATCH_ROM_SUCCESS 1
#define PATCH_ROM_SUCCESS_HAS_LVDS 2
#define PATCH_ROM_FAILED 0
#define MAX_NUM_DCB_ENTRIES 16
#define NVIDIA_ROM_SIZE0x10000
#define PATCH_ROM_SUCCESS1
#define PATCH_ROM_SUCCESS_HAS_LVDS2
#define PATCH_ROM_FAILED0
#define MAX_NUM_DCB_ENTRIES16
#define TYPE_GROUPED0xff
#define TYPE_GROUPED 0xff
extern uint32_t devices_number;
const char *nvidia_compatible_0[]={ "@0,compatible","NVDA,NVMac" };
const char *nvidia_compatible_1[]={ "@1,compatible","NVDA,NVMac" };
const char *nvidia_device_type_0[]={ "@0,device_type","display" };
const char *nvidia_device_type_1[]={ "@1,device_type","display" };
const char *nvidia_device_type[]={ "device_type","NVDA,Parent" };
const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
const char *nvidia_slot_name[]={ "AAPL,slot-name","Slot-1" };
//const char *nvidia_display_cfg_0[] = { "@0,display-cfg
const char *nvidia_compatible_0[]={ "@0,compatible","NVDA,NVMac" };
const char *nvidia_compatible_1[]={ "@1,compatible","NVDA,NVMac" };
const char *nvidia_device_type_0[]={ "@0,device_type", "display" };
const char *nvidia_device_type_1[]={ "@1,device_type", "display" };
const char *nvidia_device_type[]={ "device_type","NVDA,Parent" };
const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
const char *nvidia_slot_name[]={ "AAPL,slot-name", "Slot-1" };
static uint8_t default_NVCAP[]= {
0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,
static struct nv_chipsets_t NVKnownChipsets[] = {
{ 0x00000000, "Unknown" },
// temporary placement
{ 0x10DE0DF4, "GeForce GT 450M" }, //Azi + issue #99
{ 0x10DE1251, "GeForce GTX 560M" }, // Asus G74SX
//========================================
// 0040 - 004F
{ 0x10DE0040, "GeForce 6800 Ultra" },
{ 0x10DE0041, "GeForce 6800" },
static uint16_t read16(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[2];
ret[0] = ptr[offset+1];
ret[1] = ptr[offset];
return *((uint16_t*)&ret);
}
return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);
}
static uint8_t read8(uint8_t *ptr, uint16_t offset)
static uint8_tread8(uint8_t *ptr, uint16_t offset)
{
return ptr[offset];
}
static uint32_t read32(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[4];
ret[0] = ptr[offset+3];
ret[1] = ptr[offset+2];
ret[2] = ptr[offset+1];
ret[3] = ptr[offset];
return *((uint32_t*)&ret);
}
#endif
}
uint16_t dcbptr = swap16(read16(rom, 0x36));
if(!dcbptr) {
if (!dcbptr) {
printf("no dcb table found\n");
return PATCH_ROM_FAILED;
}/* else
printf("dcb table at offset 0x%04x\n", dcbptr);
*/
uint8_t *dcbtable = &rom[dcbptr];
}
//else
//printf("dcb table at offset 0x%04x\n", dcbptr);
uint8_t *dcbtable = &rom[dcbptr];
uint8_t dcbtable_version = dcbtable[0];
uint8_t headerlength = 0;
uint8_t recordlength = 0;
uint8_t numentries = 0;
uint8_t headerlength = 0;
uint8_t numentries = 0;
uint8_t recordlength = 0;
if(dcbtable_version >= 0x20) {
if (dcbtable_version >= 0x20)
{
uint32_t sig;
if(dcbtable_version >= 0x30) {
if (dcbtable_version >= 0x30)
{
headerlength = dcbtable[1];
numentries = dcbtable[2];
numentries = dcbtable[2];
recordlength = dcbtable[3];
sig = *(uint32_t *)&dcbtable[6];
} else {
}
else
{
sig = *(uint32_t *)&dcbtable[4];
headerlength = 8;
}
if (sig != 0x4edcbdcb) {
//Azi: match this with one below and add line number ?
printf("Bad display config block signature (0x%8x)\n", sig);
if (sig != 0x4edcbdcb)
{
printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48
return PATCH_ROM_FAILED;
}
} else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */
}
else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */
{
char sig[8] = { 0 };
strncpy(sig, (char *)&dcbtable[-7], 7);
recordlength = 10;
if (strcmp(sig, "DEV_REC")) {
if (strcmp(sig, "DEV_REC"))
{
printf("Bad Display Configuration Block signature (%s)\n", sig);
return PATCH_ROM_FAILED;
}
} else {
}
else
{
printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);
return PATCH_ROM_FAILED;
}
if(numentries >= MAX_NUM_DCB_ENTRIES)
if (numentries >= MAX_NUM_DCB_ENTRIES)
numentries = MAX_NUM_DCB_ENTRIES;
uint8_t num_outputs = 0, i=0;
struct dcbentry {
uint8_t num_outputs = 0, i = 0;
struct dcbentry
{
uint8_t type;
uint8_t index;
uint8_t *heads;
} entries[numentries];
for (i = 0; i < numentries; i++) {
for (i = 0; i < numentries; i++)
{
uint32_t connection;
connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];
/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
continue;
entries[num_outputs].type = connection & 0xf;
entries[num_outputs].index = num_outputs;
entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);
}
int has_lvds = false;
uint8_t channel1 = 0, channel2 = 0;
for(i=0; i<num_outputs; i++) {
if(entries[i].type == 3) {
for (i = 0; i < num_outputs; i++)
{
if (entries[i].type == 3)
{
has_lvds = true;
//printf("found LVDS\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
}
// if we have a LVDS output, we group the rest to the second channel
if(has_lvds) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
if (has_lvds)
{
for (i = 0; i < num_outputs; i++)
{
if (entries[i].type == TYPE_GROUPED)
continue;
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
} else {
//
}
else
{
int x;
// we loop twice as we need to generate two channels
for(x=0; x<=1; x++) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
for (x = 0; x <= 1; x++)
{
for (i=0; i<num_outputs; i++)
{
if (entries[i].type == TYPE_GROUPED)
continue;
// if type is TMDS, the prior output is ANALOG
// we always group ANALOG and TMDS
// if there is a TV output after TMDS, we group it to that channel as well
if(i && entries[i].type == 0x2) {
switch (x) {
if (i && entries[i].type == 0x2)
{
switch (x)
{
case 0:
//printf("group channel 1\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if((entries[i-1].type == 0x0)) {
if ((entries[i-1].type == 0x0))
{
channel1 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )
{
//printf("group tv1\n");
channel1 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
case 1:
//printf("group channel 2 : %d\n", i);
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if((entries[i-1].type == 0x0)) {
if ((entries[i - 1].type == 0x0))
{
channel2 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )
{
//printf("group tv2\n");
channel2 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
}
break;
}
// if we have left ungrouped outputs merge them to the empty channel
uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);
togroup = &channel2;
for(i=0; i<num_outputs;i++)
if(entries[i].type != TYPE_GROUPED) {
for (i = 0; i < num_outputs; i++)
{
if (entries[i].type != TYPE_GROUPED)
{
//printf("%d not grouped\n", i);
if(togroup)
if (togroup)
{
*togroup |= ( 0x1 << entries[i].index);
}
entries[i].type = TYPE_GROUPED;
}
}
if(channel1 > channel2) {
if (channel1 > channel2)
{
uint8_t buff = channel1;
channel1 = channel2;
channel2 = buff;
default_NVCAP[8] = channel2;
// patching HEADS
for(i=0; i<num_outputs;i++) {
if(channel1 & (1 << i))
for (i = 0; i < num_outputs; i++)
{
if (channel1 & (1 << i))
{
*entries[i].heads = 1;
}
else if(channel2 & (1 << i))
{
*entries[i].heads = 2;
}
}
return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);
}
static char *get_nvidia_model(uint32_t id) {
inti;
for (i=1; i< (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {
if (NVKnownChipsets[i].device == id) {
static char *get_nvidia_model(uint32_t id)
{
int i;
for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {
if (NVKnownChipsets[i].device == id)
{
return NVKnownChipsets[i].name;
}
}
static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)
{
intfd;
intsize;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {
int fd;
int size;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)
{
return 0;
}
size = file_size(fd);
if (size > bufsize) {
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);
if (size > bufsize)
{
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",
filename, bufsize);
size = bufsize;
}
size = read(fd, (char *)buf, size);
close(fd);
return size > 0 ? size : 0;
}
static int devprop_add_nvidia_template(struct DevPropDevice *device)
{
chartmp[16];
if(!device)
char tmp[16];
if (!device)
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))
if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))
if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_name_0))
if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))
if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))
if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_name_1))
if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type))
if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))
return 0;
// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!
// len = sprintf(tmp, "Slot-%x", devices_number);
sprintf(tmp, "Slot-%x",devices_number);
devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));
devices_number++;
return 1;
}
int hex2bin(const char *hex, uint8_t *bin, int len)
{
char*p;
inti;
inti;
charbuf[3];
if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {
buf[2] = '\0';
p = (char *) hex;
for (i=0; i<len; i++) {
for (i = 0; i < len; i++)
{
if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {
printf("[ERROR] bin2hex '%s' syntax error\n", hex);
return -2;
{
unsigned long long vram_size = 0;
if (nvCardType < NV_ARCH_50) {
if (nvCardType < NV_ARCH_50)
{
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
}
else if (nvCardType < NV_ARCH_C0) {
else if (nvCardType < NV_ARCH_C0)
{
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size |= (vram_size & 0xff) << 32;
vram_size &= 0xffffffff00ll;
}
else { // >= NV_ARCH_C0
else // >= NV_ARCH_C0
{
vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;
vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);
}
// Workaround for GT 420/430 & 9600M GT
switch (nvda_dev->device_id)
{
case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430
case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420
case 0x0649: vram_size = 512*1024*1024; break; // 9600M GT
case 0x0649: vram_size = 512*1024*1024; break;// 9600M GT
default: break;
}
bool setup_nvidia_devprop(pci_dt_t *nvda_dev)
{
struct DevPropDevice*device;
char*devicepath;
option_rom_pci_header_t*rom_pci_header;
volatile uint8_t*regs;
uint8_t*rom;
uint8_t*nvRom;
uint8_tnvCardType;
unsigned long longvideoRam;
uint32_tnvBiosOveride;
uint32_tbar[7];
uint32_tboot_display;
intnvPatch;
intlen;
charbiosVersion[32];
charnvFilename[32];
charkNVCAP[12];
char*model;
const char*value;
booldoit;
struct DevPropDevice*device;
char*devicepath;
option_rom_pci_header_t *rom_pci_header;
volatile uint8_t*regs;
uint8_t*rom;
uint8_t*nvRom;
uint8_tnvCardType;
unsigned long longvideoRam;
uint32_tnvBiosOveride;
uint32_tbar[7];
uint32_tboot_display;
intnvPatch;
intlen;
charbiosVersion[32];
charnvFilename[32];
charkNVCAP[12];
char*model;
const char*value;
booldoit;
devicepath = get_pci_dev_path(nvda_dev);
bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );
regs = (uint8_t *) (bar[0] & ~0x0f);
// get card type
nvCardType = (REG32(0) >> 20) & 0x1ff;
// Amount of VRAM in kilobytes
videoRam = mem_detect(regs, nvCardType, nvda_dev);
model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);
verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",
verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",
model, (uint32_t)(videoRam / 1024 / 1024),
(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,
devicepath);
rom = malloc(NVIDIA_ROM_SIZE);
sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id);
if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit) {
sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,
(uint16_t)nvda_dev->device_id);
if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit)
{
verbose("Looking for nvidia video bios file %s\n", nvFilename);
nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);
if (nvBiosOveride > 0) {
if (nvBiosOveride > 0)
{
verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);
DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);
} else {
}
else
{
printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);
return false;
}
} else {
}
else
{
// Otherwise read bios from card
nvBiosOveride = 0;
// TODO: we should really check for the signature before copying the rom, i think.
// PRAMIN first
nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];
bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
if (rom[0] != 0x55 && rom[1] != 0xaa)
{
// PROM next
// Enable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;
nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];
bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// disable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
if (rom[0] != 0x55 && rom[1] != 0xaa)
{
// 0xC0000 last
bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
if (rom[0] != 0x55 && rom[1] != 0xaa)
{
printf("ERROR: Unable to locate nVidia Video BIOS\n");
return false;
} else {
}
else
{
DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
} else {
}
else
{
DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
} else {
}
else
{
DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
}
if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {
printf("ERROR: nVidia ROM Patching Failed!\n");
//return false;
}
rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);
// check for 'PCIR' sig
if (rom_pci_header->signature == 0x50434952) {
if (rom_pci_header->device_id != nvda_dev->device_id) {
if (rom_pci_header->signature == 0x50434952)
{
if (rom_pci_header->device_id != nvda_dev->device_id)
{
// Get Model from the OpROM
model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);
} else {
}
else
{
printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);
}
}
if (!string) {
string = devprop_create_string();
}
device = devprop_add_device(string, devicepath);
/* FIXME: for primary graphics card only */
boot_display = 1;
devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
if(nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {
if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {
uint8_t built_in = 0x01;
devprop_add_value(device, "@0,built-in", &built_in, 1);
}
// get bios version
const int MAX_BIOS_VERSION_LENGTH = 32;
char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);
memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);
int i, version_start;
int crlf_count = 0;
// only search the first 384 bytes
for(i = 0; i < 0x180; i++) {
if(rom[i] == 0x0D && rom[i+1] == 0x0A) {
for (i = 0; i < 0x180; i++)
{
if (rom[i] == 0x0D && rom[i+1] == 0x0A)
{
crlf_count++;
// second 0x0D0A was found, extract bios version
if(crlf_count == 2) {
if(rom[i-1] == 0x20) i--; // strip last " "
for(version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--) {
if (crlf_count == 2)
{
if (rom[i-1] == 0x20) i--; // strip last " "
for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)
{
// find start
if(rom[version_start] == 0x00) {
if (rom[version_start] == 0x00)
{
version_start++;
// strip "Version "
if(strncmp((const char*)rom+version_start, "Version ", 8) == 0) {
if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)
{
version_start += 8;
}
}
sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);
sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);
if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2) {
uint8_tnew_NVCAP[NVCAP_LEN];
if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) {
if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2)
{
uint8_t new_NVCAP[NVCAP_LEN];
if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)
{
verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);
memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);
}
}
if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2){
uint8_t new_dcfg0[DCFG0_LEN];
if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)
{
memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);
verbose("Using user supplied @0,display-cfg\n");
printf("@0,display-cfg: %02x%02x%02x%02x\n",
default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);
}
}
if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2){
uint8_t new_dcfg1[DCFG1_LEN];
if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)
{
memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);
verbose("Using user supplied @1,display-cfg\n");
printf("@1,display-cfg: %02x%02x%02x%02x\n",
default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);
}
}
#if DEBUG_NVCAP
printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",
default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],
default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],
default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],
default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],
default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);
if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2)
{
uint8_t new_dcfg0[DCFG0_LEN];
if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)
{
memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);
verbose("Using user supplied @0,display-cfg\n");
printf("@0,display-cfg: %02x%02x%02x%02x\n",
default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);
}
}
if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2)
{
uint8_t new_dcfg1[DCFG1_LEN];
if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)
{
memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);
verbose("Using user supplied @1,display-cfg\n");
printf("@1,display-cfg: %02x%02x%02x%02x\n",
default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);
}
}
#if DEBUG_NVCAP
printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",
default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],
default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],
default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],
default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],
default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);
#endif
devprop_add_nvidia_template(device);
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);
devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);
devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);
devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);
devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);
//add HDMI Audio back to nvidia
//http://forge.voodooprojects.org/p/chameleon/issues/67/
// uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};
// devprop_add_value(device, "@1,connector-type",connector_type_1, 4);
//end Nvidia HDMI Audio
if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit) {
devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);
devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);
//add HDMI Audio back to nvidia
//http://forge.voodooprojects.org/p/chameleon/issues/67/
//uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};
//devprop_add_value(device, "@1,connector-type",connector_type_1, 4);
//end Nvidia HDMI Audio
if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit)
{
devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));
}
stringdata = malloc(sizeof(uint8_t) * string->length);
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
branches/azimutz/trunkAutoResolution/i386/libsaio/ati.c
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*
*/
#include "libsaio.h"
#include "boot.h"
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#include "device_inject.h"
#include "ati_reg.h"
#defineOFFSET_TO_GET_ATOMBIOS_STRINGS_START0x6e
#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x6e
#define Reg32(reg)(*(volatile uint32_t *)(card->mmio + reg))
#define RegRead32(reg)(Reg32(reg))
#define RegWrite32(reg, value)(Reg32(reg) = value)
#define Reg32(reg)(*(volatile uint32_t *)(card->mmio + reg))
#define RegRead32(reg)(Reg32(reg))
#define RegWrite32(reg, value)(Reg32(reg) = value)
typedef enum {
kNul,
"Redwood",// RV830
"Juniper",// RV840
"Cypress",// RV870
"Hemlock",
"Hemlock",
/* Northern Islands */
"Barts",
"Caicos",
} config_name_t;
typedef struct {
uint16_tdevice_id;
uint32_tsubsys_id;
chip_family_tchip_family;
const char*model_name;
config_name_tcfg_name;
uint16_tdevice_id;
uint32_tsubsys_id;
chip_family_tchip_family;
const char*model_name;
config_name_tcfg_name;
} radeon_card_info_t;
static radeon_card_info_t radeon_cards[] = {
/* Earlier cards are not supported */
{ 0x9400,0x30001002,CHIP_FAMILY_R600,"ATI Radeon HD 2900 PRO",kNull},
{ 0x9400,0x25521002,CHIP_FAMILY_R600,"ATI Radeon HD 2900 XT",kNull},
{ 0x9440,0x24401682,CHIP_FAMILY_RV770,"ATI Radeon HD 4870",kMotmot},
{ 0x9440,0x24411682,CHIP_FAMILY_RV770,"ATI Radeon HD 4870",kMotmot},
{ 0x9440,0x24441682,CHIP_FAMILY_RV770,"ATI Radeon HD 4870",kMotmot},
{ 0x9440,0x24451682,CHIP_FAMILY_RV770,"ATI Radeon HD 4870",kMotmot},
{ 0x9441,0x24401682,CHIP_FAMILY_RV770,"ATI Radeon HD 4870 X2",kMotmot},
{ 0x9442,0x24701682,CHIP_FAMILY_RV770,"ATI Radeon HD 4850",kMotmot},
{ 0x9442,0x24711682,CHIP_FAMILY_RV770,"ATI Radeon HD 4850",kMotmot},
{ 0x9442,0x080110B0,CHIP_FAMILY_RV770,"ATI Radeon HD 4850",kMotmot},
{ 0x9442,0xE104174B,CHIP_FAMILY_RV770,"ATI Radeon HD 4850",kMotmot},
{ 0x944A,0x30001682,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x30001043,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x30001458,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x30001462,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x30001545,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x30001787,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x3000174B,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x300017AF,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944C,0x24801682,CHIP_FAMILY_RV770,"ATI Radeon HD 4830",kMotmot},
{ 0x944C,0x24811682,CHIP_FAMILY_RV770,"ATI Radeon HD 4830",kMotmot},
{ 0x944E,0x3260174B,CHIP_FAMILY_RV770,"ATI Radeon HD 4810 Series",kMotmot},
{ 0x944E,0x3261174B,CHIP_FAMILY_RV770,"ATI Radeon HD 4810 series",kMotmot},
{ 0x944E,0x30001787,CHIP_FAMILY_RV770,"ATI Radeon HD 4730 Series",kMotmot},
{ 0x944E,0x30101787,CHIP_FAMILY_RV770,"ATI Radeon HD 4810 Series",kMotmot},
{ 0x944E,0x31001787,CHIP_FAMILY_RV770,"ATI Radeon HD 4820",kMotmot},
{ 0x9490,0x30501787,CHIP_FAMILY_RV730,"ATI Radeon HD 4710",kNull},
{ 0x9490,0x4710174B,CHIP_FAMILY_RV730,"ATI Radeon HD 4710",kNull},
{ 0x9490,0x300017AF,CHIP_FAMILY_RV730,"ATI Radeon HD 4710",kNull},
{ 0x9498,0x30501787,CHIP_FAMILY_RV730,"ATI Radeon HD 4700",kNull},
{ 0x9498,0x31001787,CHIP_FAMILY_RV730,"ATI Radeon HD 4720",kNull},
{ 0x9498,0x24511682,CHIP_FAMILY_RV730,"ATI Radeon HD 4650",kNull},
{ 0x9498,0x24521682,CHIP_FAMILY_RV730,"ATI Radeon HD 4650",kNull},
{ 0x9498,0x24541682,CHIP_FAMILY_RV730,"ATI Radeon HD 4650",kNull},
{ 0x9498,0x29331682,CHIP_FAMILY_RV730,"ATI Radeon HD 4670",kNull},
{ 0x9498,0x29341682,CHIP_FAMILY_RV730,"ATI Radeon HD 4670",kNull},
{ 0x9498,0x21CF1458,CHIP_FAMILY_RV730,"ATI Radeon HD 4600 Series",kNull},
{ 0x94B3,0x29001682,CHIP_FAMILY_RV740,"ATI Radeon HD 4770",kFlicker},
{ 0x94B3,0x1170174B,CHIP_FAMILY_RV740,"ATI Radeon HD 4770",kFlicker},
{ 0x94B3,0x10020D00,CHIP_FAMILY_RV740,"ATI Radeon HD 4770",kFlicker},
{ 0x94C1,0x10021002,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 Pro",kNull},
{ 0x94C1,0x0D021002,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x0D021028,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 Pro",kNull},
{ 0x94C1,0x0D021028,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x21741458,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x10401462,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x10331462,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x10331462,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x11101462,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C3,0x37161642,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x30001642,CHIP_FAMILY_RV610,"ATI Radeon HD 3410",kNull},
{ 0x94C3,0x03421002,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x30001025,CHIP_FAMILY_RV610,"ATI Radeon HD 2350 Series",kNull},
{ 0x94C3,0x04021028,CHIP_FAMILY_RV610,"ATI Radeon HD 2400",kNull},
{ 0x94C3,0x03021028,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x04021028,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x216A1458,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x21721458,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x30001458,CHIP_FAMILY_RV610,"ATI Radeon HD 3410",kNull},
{ 0x94C3,0x11041462,CHIP_FAMILY_RV610,"ATI Radeon HD 2400",kNull},
{ 0x94C3,0x10411462,CHIP_FAMILY_RV610,"ATI Radeon HD 2400",kNull},
{ 0x94C3,0x11051462,CHIP_FAMILY_RV610,"ATI Radeon HD 2400",kNull},
{ 0x94C3,0x10321462,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x30001462,CHIP_FAMILY_RV610,"ATI Radeon HD 3410",kNull},
{ 0x94C3,0x3000148C,CHIP_FAMILY_RV610,"ATI Radeon HD 2350 Series",kNull},
{ 0x94C3,0x2247148C,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 LE",kNull},
{ 0x94C3,0x3000174B,CHIP_FAMILY_RV610,"ATI Radeon HD 2350 Series",kNull},
{ 0x94C3,0xE400174B,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0xE370174B,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0xE400174B,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0xE370174B,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0xE400174B,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x203817AF,CHIP_FAMILY_RV610,"ATI Radeon HD 2400",kNull},
{ 0x94C3,0x30001787,CHIP_FAMILY_RV610,"ATI Radeon HD 2350 Series",kNull},
{ 0x94C3,0x22471787,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 LE",kNull},
{ 0x94C3,0x01011A93,CHIP_FAMILY_RV610,"Qimonda Radeon HD 2400 PRO",kNull},
{ 0x9501,0x30001002,CHIP_FAMILY_RV670,"ATI Radeon HD 3690",kNull},
{ 0x9501,0x25421002,CHIP_FAMILY_RV670,"ATI Radeon HD 3870",kNull},
{ 0x9501,0x4750174B,CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9501,0x3000174B,CHIP_FAMILY_RV670,"Sapphire Radeon HD 3690",kNull},
{ 0x9501,0x30001787,CHIP_FAMILY_RV670,"ATI Radeon HD 3690",kNull},
{ 0x9505,0x30001002,CHIP_FAMILY_RV670,"ATI Radeon HD 3690",kNull},
{ 0x9505,0x25421002,CHIP_FAMILY_RV670,"ATI Radeon HD 3850",kNull},
{ 0x9505,0x30011043,CHIP_FAMILY_RV670,"ATI Radeon HD 4730",kNull},
{ 0x9505,0x3000148C,CHIP_FAMILY_RV670,"ATI Radeon HD 3850",kNull},
{ 0x9505,0x3002148C,CHIP_FAMILY_RV670,"ATI Radeon HD 4730",kNull},
{ 0x9505,0x3001148C,CHIP_FAMILY_RV670,"ATI Radeon HD 4730",kNull},
{ 0x9505,0x3003148C,CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9505,0x3004148C,CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9505,0x4730174B,CHIP_FAMILY_RV670,"ATI Radeon HD 4730",kNull},
{ 0x9505,0x3010174B,CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9505,0x3001174B,CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9505,0x3000174B,CHIP_FAMILY_RV670,"Sapphire Radeon HD 3690",kNull},
{ 0x9505,0x30001787,CHIP_FAMILY_RV670,"ATI Radeon HD 3690",kNull},
{ 0x9505,0x301017AF,CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9540,0x4590174B,CHIP_FAMILY_RV710,"ATI Radeon HD 4590",kNull},
{ 0x9540,0x30501787,CHIP_FAMILY_RV710,"ATI Radeon HD 4590",kNull},
{ 0x954F,0x29201682,CHIP_FAMILY_RV710,"ATI Radeon HD 4550",kNull},
{ 0x954F,0x29211682,CHIP_FAMILY_RV710,"ATI Radeon HD 4550",kNull},
{ 0x954F,0x30901682,CHIP_FAMILY_RV710,"XFX Radeon HD 4570",kNull},
{ 0x954F,0x4450174B,CHIP_FAMILY_RV710,"ATI Radeon HD 4450",kNull},
{ 0x954F,0x3000174B,CHIP_FAMILY_RV710,"ATI Radeon HD 4520",kNull},
{ 0x954F,0x30501787,CHIP_FAMILY_RV710,"ATI Radeon HD 4450",kNull},
{ 0x954F,0x31001787,CHIP_FAMILY_RV710,"ATI Radeon HD 4520",kNull},
{ 0x954F,0x4570174B,CHIP_FAMILY_RV710,"Sapphire Radeon HD4570",kNull},
{ 0x954F,0x301017AF,CHIP_FAMILY_RV710,"ATI Radeon HD 4450",kNull},
{ 0x9552,0x3000148C,CHIP_FAMILY_RV710,"ATI Radeon HD 4300/4500 Series",kNull},
{ 0x9552,0x3000174B,CHIP_FAMILY_RV710,"ATI Radeon HD 4300/4500 Series",kNull},
{ 0x9552,0x30001787,CHIP_FAMILY_RV710,"ATI Radeon HD 4300/4500 Series",kNull},
{ 0x9552,0x300017AF,CHIP_FAMILY_RV710,"ATI Radeon HD 4300/4500 Series",kNull},
{ 0x9581,0x95811002,CHIP_FAMILY_RV630,"ATI Radeon HD 3600 Series",kNull},
{ 0x9581,0x3000148C,CHIP_FAMILY_RV630,"ATI Radeon HD 3600 Series",kNull},
{ 0x9583,0x3000148C,CHIP_FAMILY_RV630,"ATI Radeon HD 3600 Series",kNull},
{ 0x9588,0x01021A93,CHIP_FAMILY_RV630,"Qimonda Radeon HD 2600 XT",kNull},
{ 0x9589,0x30001462,CHIP_FAMILY_RV630,"ATI Radeon HD 3610",kNull},
{ 0x9589,0x30001642,CHIP_FAMILY_RV630,"ATI Radeon HD 3610",kNull},
{ 0x9589,0x0E41174B,CHIP_FAMILY_RV630,"ATI Radeon HD 3600 Series",kNull},
{ 0x9589,0x30001787,CHIP_FAMILY_RV630,"ATI Radeon HD 3600 Series",kNull},
{ 0x9589,0x01001A93,CHIP_FAMILY_RV630,"Qimonda Radeon HD 2600 PRO",kNull},
{ 0x9591,0x2303148C,CHIP_FAMILY_RV635,"ATI Radeon HD 3600 Series",kNull},
{ 0x9598,0xB3831002,CHIP_FAMILY_RV635,"ATI All-in-Wonder HD",kNull},
{ 0x9598,0x30011043,CHIP_FAMILY_RV635,"ATI Radeon HD 4570",kNull},
{ 0x9598,0x30001043,CHIP_FAMILY_RV635,"HD3730",kNull},
{ 0x9598,0x3000148C,CHIP_FAMILY_RV635,"ATI Radeon HD 3730",kNull},
{ 0x9598,0x3031148C,CHIP_FAMILY_RV635,"ATI Radeon HD 4570",kNull},
{ 0x9598,0x3001148C,CHIP_FAMILY_RV635,"ATI Radeon HD 4580",kNull},
{ 0x9598,0x30011545,CHIP_FAMILY_RV635,"VisionTek Radeon HD 2600 Pro",kNull},
{ 0x9598,0x30001545,CHIP_FAMILY_RV635,"VisionTek Radeon HD 2600 XT",kNull},
{ 0x9598,0x4570174B,CHIP_FAMILY_RV635,"ATI Radeon HD 4570",kNull},
{ 0x9598,0x4580174B,CHIP_FAMILY_RV635,"ATI Radeon HD 4580",kNull},
{ 0x9598,0x4610174B,CHIP_FAMILY_RV635,"ATI Radeon HD 4610",kNull},
{ 0x9598,0x3000174B,CHIP_FAMILY_RV635,"Sapphire Radeon HD 3730",kNull},
{ 0x9598,0x3001174B,CHIP_FAMILY_RV635,"Sapphire Radeon HD 3750",kNull},
{ 0x9598,0x301017AF,CHIP_FAMILY_RV635,"ATI Radeon HD 4570",kNull},
{ 0x9598,0x301117AF,CHIP_FAMILY_RV635,"ATI Radeon HD 4580",kNull},
{ 0x9598,0x300117AF,CHIP_FAMILY_RV635,"ATI Radeon HD3750",kNull},
{ 0x9598,0x30501787,CHIP_FAMILY_RV635,"ATI Radeon HD 4610",kNull},
{ 0x95C0,0x3000148C,CHIP_FAMILY_RV620,"ATI Radeon HD 3550",kNull},
{ 0x95C0,0xE3901745,CHIP_FAMILY_RV620,"ATI Radeon HD 3550",kNull},
{ 0x95C0,0x3002174B,CHIP_FAMILY_RV620,"ATI Radeon HD 3570",kNull},
{ 0x95C0,0x3020174B,CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C0,0x3000174B,CHIP_FAMILY_RV620,"Sapphire Radeon HD 3550",kNull},
{ 0x95C5,0x3000148C,CHIP_FAMILY_RV620,"ATI Radeon HD 3450",kNull},
{ 0x95C5,0x3001148C,CHIP_FAMILY_RV620,"ATI Radeon HD 3550",kNull},
{ 0x95C5,0x3002148C,CHIP_FAMILY_RV620,"ATI Radeon HD 4230",kNull},
{ 0x95C5,0x3033148C,CHIP_FAMILY_RV620,"ATI Radeon HD 4230",kNull},
{ 0x95C5,0x3003148C,CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C5,0x3032148C,CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C5,0x3010174B,CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C5,0x4250174B,CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C5,0x30501787,CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C5,0x301017AF,CHIP_FAMILY_RV620,"ATI Radeon HD 4230",kNull},
{ 0x95C5,0x01051A93,CHIP_FAMILY_RV620,"Qimonda Radeon HD 3450",kNull},
{ 0x95C5,0x01041A93,CHIP_FAMILY_RV620,"Qimonda Radeon HD 3450",kNull},
{ 0x9400,0x30001002, CHIP_FAMILY_R600,"ATI Radeon HD 2900 PRO",kNull},
{ 0x9400,0x25521002, CHIP_FAMILY_R600,"ATI Radeon HD 2900 XT",kNull},
{ 0x9440,0x24401682, CHIP_FAMILY_RV770,"ATI Radeon HD 4870",kMotmot},
{ 0x9440,0x24411682, CHIP_FAMILY_RV770,"ATI Radeon HD 4870",kMotmot},
{ 0x9440,0x24441682, CHIP_FAMILY_RV770,"ATI Radeon HD 4870",kMotmot},
{ 0x9440,0x24451682, CHIP_FAMILY_RV770,"ATI Radeon HD 4870",kMotmot},
{ 0x9441,0x24401682, CHIP_FAMILY_RV770,"ATI Radeon HD 4870 X2",kMotmot},
{ 0x9442,0x24701682, CHIP_FAMILY_RV770,"ATI Radeon HD 4850",kMotmot},
{ 0x9442,0x24711682, CHIP_FAMILY_RV770,"ATI Radeon HD 4850",kMotmot},
{ 0x9442,0x080110B0, CHIP_FAMILY_RV770,"ATI Radeon HD 4850",kMotmot},
{ 0x9442,0xE104174B, CHIP_FAMILY_RV770,"ATI Radeon HD 4850",kMotmot},
{ 0x944A,0x30001682, CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x30001043, CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x30001458, CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x30001462, CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x30001545, CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x30001787, CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x3000174B, CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x300017AF, CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944C,0x24801682, CHIP_FAMILY_RV770,"ATI Radeon HD 4830",kMotmot},
{ 0x944C,0x24811682, CHIP_FAMILY_RV770,"ATI Radeon HD 4830",kMotmot},
{ 0x944E,0x3260174B, CHIP_FAMILY_RV770,"ATI Radeon HD 4810 Series",kMotmot},
{ 0x944E,0x3261174B, CHIP_FAMILY_RV770,"ATI Radeon HD 4810 series",kMotmot},
{ 0x944E,0x30001787, CHIP_FAMILY_RV770,"ATI Radeon HD 4730 Series",kMotmot},
{ 0x944E,0x30101787, CHIP_FAMILY_RV770,"ATI Radeon HD 4810 Series",kMotmot},
{ 0x944E,0x31001787, CHIP_FAMILY_RV770,"ATI Radeon HD 4820",kMotmot},
{ 0x9480,0x3628103C,CHIP_FAMILY_RV730,"ATI Radeon HD 4650M",kGliff},
{ 0x9480,0x9035104D,CHIP_FAMILY_RV730,"ATI Radeon HD 4650M",kGliff},
{ 0x9490,0x20031787, CHIP_FAMILY_RV730,"ATI Radeon HD 4670",kFlicker},
{ 0x9490,0x30501787, CHIP_FAMILY_RV730,"ATI Radeon HD 4710",kNull},
{ 0x9490,0x4710174B, CHIP_FAMILY_RV730,"ATI Radeon HD 4710",kNull},
{ 0x9490,0x300017AF, CHIP_FAMILY_RV730,"ATI Radeon HD 4710",kNull},
{ 0x9498,0x30501787, CHIP_FAMILY_RV730,"ATI Radeon HD 4700",kNull},
{ 0x9498,0x31001787, CHIP_FAMILY_RV730,"ATI Radeon HD 4720",kNull},
{ 0x9498,0x24511682, CHIP_FAMILY_RV730,"ATI Radeon HD 4650",kNull},
{ 0x9498,0x24521682, CHIP_FAMILY_RV730,"ATI Radeon HD 4650",kNull},
{ 0x9498,0x24541682, CHIP_FAMILY_RV730,"ATI Radeon HD 4650",kNull},
{ 0x9498,0x29331682, CHIP_FAMILY_RV730,"ATI Radeon HD 4670",kNull},
{ 0x9498,0x29341682, CHIP_FAMILY_RV730,"ATI Radeon HD 4670",kNull},
{ 0x9498,0x21CF1458, CHIP_FAMILY_RV730,"ATI Radeon HD 4600 Series",kNull},
{ 0x94B3,0x29001682, CHIP_FAMILY_RV740,"ATI Radeon HD 4770",kFlicker},
{ 0x94B3,0x1170174B, CHIP_FAMILY_RV740,"ATI Radeon HD 4770",kFlicker},
{ 0x94B3,0x10020D00, CHIP_FAMILY_RV740,"ATI Radeon HD 4770",kFlicker},
{ 0x94C1,0x10021002, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 Pro",kNull},
{ 0x94C1,0x0D021002, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x0D021028, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 Pro",kNull},
{ 0x94C1,0x0D021028, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x21741458, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x10401462, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x10331462, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x10331462, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x11101462, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C3,0x37161642, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x30001642, CHIP_FAMILY_RV610,"ATI Radeon HD 3410",kNull},
{ 0x94C3,0x03421002, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x30001025, CHIP_FAMILY_RV610,"ATI Radeon HD 2350 Series",kNull},
{ 0x94C3,0x04021028, CHIP_FAMILY_RV610,"ATI Radeon HD 2400",kNull},
{ 0x94C3,0x03021028, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x04021028, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x216A1458, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x21721458, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x30001458, CHIP_FAMILY_RV610,"ATI Radeon HD 3410",kNull},
{ 0x94C3,0x11041462, CHIP_FAMILY_RV610,"ATI Radeon HD 2400",kNull},
{ 0x94C3,0x10411462, CHIP_FAMILY_RV610,"ATI Radeon HD 2400",kNull},
{ 0x94C3,0x11051462, CHIP_FAMILY_RV610,"ATI Radeon HD 2400",kNull},
{ 0x94C3,0x10321462, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x30001462, CHIP_FAMILY_RV610,"ATI Radeon HD 3410",kNull},
{ 0x94C3,0x3000148C, CHIP_FAMILY_RV610,"ATI Radeon HD 2350 Series",kNull},
{ 0x94C3,0x2247148C, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 LE",kNull},
{ 0x94C3,0x3000174B, CHIP_FAMILY_RV610,"ATI Radeon HD 2350 Series",kNull},
{ 0x94C3,0xE400174B, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0xE370174B, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0xE400174B, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0xE370174B, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0xE400174B, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x203817AF, CHIP_FAMILY_RV610,"ATI Radeon HD 2400",kNull},
{ 0x94C3,0x30001787, CHIP_FAMILY_RV610,"ATI Radeon HD 2350 Series",kNull},
{ 0x94C3,0x22471787, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 LE",kNull},
{ 0x94C3,0x01011A93, CHIP_FAMILY_RV610,"Qimonda Radeon HD 2400 PRO",kNull},
{ 0x9501,0x30001002, CHIP_FAMILY_RV670,"ATI Radeon HD 3690",kNull},
{ 0x9501,0x25421002, CHIP_FAMILY_RV670,"ATI Radeon HD 3870",kNull},
{ 0x9501,0x4750174B, CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9501,0x3000174B, CHIP_FAMILY_RV670,"Sapphire Radeon HD 3690",kNull},
{ 0x9501,0x30001787, CHIP_FAMILY_RV670,"ATI Radeon HD 3690",kNull},
{ 0x9505,0x30001002, CHIP_FAMILY_RV670,"ATI Radeon HD 3690",kNull},
{ 0x9505,0x25421002, CHIP_FAMILY_RV670,"ATI Radeon HD 3850",kNull},
{ 0x9505,0x30011043, CHIP_FAMILY_RV670,"ATI Radeon HD 4730",kNull},
{ 0x9505,0x3000148C, CHIP_FAMILY_RV670,"ATI Radeon HD 3850",kNull},
{ 0x9505,0x3002148C, CHIP_FAMILY_RV670,"ATI Radeon HD 4730",kNull},
{ 0x9505,0x3001148C, CHIP_FAMILY_RV670,"ATI Radeon HD 4730",kNull},
{ 0x9505,0x3003148C, CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9505,0x3004148C, CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9505,0x4730174B, CHIP_FAMILY_RV670,"ATI Radeon HD 4730",kNull},
{ 0x9505,0x3010174B, CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9505,0x3001174B, CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9505,0x3000174B, CHIP_FAMILY_RV670,"Sapphire Radeon HD 3690",kNull},
{ 0x9505,0x30001787, CHIP_FAMILY_RV670,"ATI Radeon HD 3690",kNull},
{ 0x9505,0x301017AF, CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9540,0x4590174B, CHIP_FAMILY_RV710,"ATI Radeon HD 4590",kNull},
{ 0x9540,0x30501787, CHIP_FAMILY_RV710,"ATI Radeon HD 4590",kNull},
{ 0x954F,0x29201682, CHIP_FAMILY_RV710,"ATI Radeon HD 4550",kNull},
{ 0x954F,0x29211682, CHIP_FAMILY_RV710,"ATI Radeon HD 4550",kNull},
{ 0x954F,0x30901682, CHIP_FAMILY_RV710,"XFX Radeon HD 4570",kNull},
{ 0x954F,0x30501787, CHIP_FAMILY_RV710,"ATI Radeon HD 4450",kNull},
{ 0x954F,0x31001787, CHIP_FAMILY_RV710,"ATI Radeon HD 4520",kNull},
{ 0x954F,0x301017AF, CHIP_FAMILY_RV710,"ATI Radeon HD 4450",kNull},
{ 0x954F,0x4450174B, CHIP_FAMILY_RV710,"ATI Radeon HD 4450",kNull},
{ 0x954F,0x3000174B, CHIP_FAMILY_RV710,"ATI Radeon HD 4520",kNull},
{ 0x954F,0x4570174B, CHIP_FAMILY_RV710,"Sapphire Radeon HD 4570",kNull},
{ 0x954F,0xE990174B,CHIP_FAMILY_RV710,"Sapphire Radeon HD 4350",kNull},
{ 0x9552,0x3000148C, CHIP_FAMILY_RV710,"ATI Radeon HD 4300/4500 Series",kNull},
{ 0x9552,0x3000174B, CHIP_FAMILY_RV710,"ATI Radeon HD 4300/4500 Series",kNull},
{ 0x9552,0x30001787, CHIP_FAMILY_RV710,"ATI Radeon HD 4300/4500 Series",kNull},
{ 0x9552,0x300017AF, CHIP_FAMILY_RV710,"ATI Radeon HD 4300/4500 Series",kNull},
{ 0x9552,0x04341028, CHIP_FAMILY_RV710,"ATI Mobility Radeon 4330",kShrike},
{ 0x9553,0x1B321043, CHIP_FAMILY_RV710,"ATI Mobility Radeon HD 4570",kShrike/*??*/},
{ 0x9581,0x95811002, CHIP_FAMILY_RV630,"ATI Radeon HD 3600 Series",kNull},
{ 0x9581,0x3000148C, CHIP_FAMILY_RV630,"ATI Radeon HD 3600 Series",kNull},
{ 0x9583,0x3000148C, CHIP_FAMILY_RV630,"ATI Radeon HD 3600 Series",kNull},
{ 0x9588,0x01021A93, CHIP_FAMILY_RV630,"Qimonda Radeon HD 2600 XT",kNull},
{ 0x9589,0x30001462, CHIP_FAMILY_RV630,"ATI Radeon HD 3610",kNull},
{ 0x9589,0x30001642, CHIP_FAMILY_RV630,"ATI Radeon HD 3610",kNull},
{ 0x9589,0x0E41174B, CHIP_FAMILY_RV630,"ATI Radeon HD 3600 Series",kNull},
{ 0x9589,0x30001787, CHIP_FAMILY_RV630,"ATI Radeon HD 3600 Series",kNull},
{ 0x9589,0x01001A93, CHIP_FAMILY_RV630,"Qimonda Radeon HD 2600 PRO",kNull},
{ 0x9591,0x2303148C, CHIP_FAMILY_RV635,"ATI Radeon HD 3600 Series",kNull},
//Azi: most of the 9598 are rv630, according to http://developer.amd.com/gpu_assets/ATI_Device_IDs_xxx_xx.txt
{ 0x9598,0xB3831002, CHIP_FAMILY_RV635,"ATI All-in-Wonder HD",kNull},
{ 0x9598,0x30011043, CHIP_FAMILY_RV635,"ATI Radeon HD 4570",kNull},
{ 0x9598,0x30001043, CHIP_FAMILY_RV635,"HD3730",kNull},
{ 0x9598,0x3000148C, CHIP_FAMILY_RV635,"ATI Radeon HD 3730",kNull},
{ 0x9598,0x3031148C, CHIP_FAMILY_RV635,"ATI Radeon HD 4570",kNull},
{ 0x9598,0x3001148C, CHIP_FAMILY_RV635,"ATI Radeon HD 4580",kNull},
{ 0x9598,0x30011545, CHIP_FAMILY_RV635,"VisionTek Radeon HD 2600 Pro",kNull},
{ 0x9598,0x30001545, CHIP_FAMILY_RV635,"VisionTek Radeon HD 2600 XT",kNull},
{ 0x9598,0x4570174B, CHIP_FAMILY_RV635,"ATI Radeon HD 4570",kNull},
{ 0x9598,0x4580174B, CHIP_FAMILY_RV635,"ATI Radeon HD 4580",kNull},
{ 0x9598,0x4610174B, CHIP_FAMILY_RV635,"ATI Radeon HD 4610",kNull},
{ 0x9598,0x3000174B, CHIP_FAMILY_RV635,"Sapphire Radeon HD 3730",kNull},
{ 0x9598,0x3001174B, CHIP_FAMILY_RV635,"Sapphire Radeon HD 3750",kNull},
{ 0x9598,0x301017AF, CHIP_FAMILY_RV635,"ATI Radeon HD 4570",kNull},
{ 0x9598,0x301117AF, CHIP_FAMILY_RV635,"ATI Radeon HD 4580",kNull},
{ 0x9598,0x300117AF, CHIP_FAMILY_RV635,"ATI Radeon HD3750",kNull},
{ 0x9598,0x30501787, CHIP_FAMILY_RV635,"ATI Radeon HD 4610",kNull},
{ 0x95C0,0x3000148C, CHIP_FAMILY_RV620,"ATI Radeon HD 3550",kNull},
{ 0x95C0,0xE3901745, CHIP_FAMILY_RV620,"ATI Radeon HD 3550",kNull},
{ 0x95C0,0x3002174B, CHIP_FAMILY_RV620,"ATI Radeon HD 3570",kNull},
{ 0x95C0,0x3020174B, CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C0,0x3000174B, CHIP_FAMILY_RV620,"Sapphire Radeon HD 3550",kNull},
{ 0x95C5,0x3000148C, CHIP_FAMILY_RV620,"ATI Radeon HD 3450",kNull},
{ 0x95C5,0x3001148C, CHIP_FAMILY_RV620,"ATI Radeon HD 3550",kNull},
{ 0x95C5,0x3002148C, CHIP_FAMILY_RV620,"ATI Radeon HD 4230",kNull},
{ 0x95C5,0x3033148C, CHIP_FAMILY_RV620,"ATI Radeon HD 4230",kNull},
{ 0x95C5,0x3003148C, CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C5,0x3032148C, CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C5,0x3010174B, CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C5,0x4250174B, CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C5,0x30501787, CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C5,0x301017AF, CHIP_FAMILY_RV620,"ATI Radeon HD 4230",kNull},
{ 0x95C5,0x01051A93, CHIP_FAMILY_RV620,"Qimonda Radeon HD 3450",kNull},
{ 0x95C5,0x01041A93, CHIP_FAMILY_RV620,"Qimonda Radeon HD 3450",kNull},
/* Evergreen */
{ 0x6898,0x032E1043,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kUakari},
{ 0x6898,0xE140174B,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kUakari},
{ 0x6898,0x29611682,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kUakari},
{ 0x6898,0x0B001002,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kZonalis},
{ 0x6898,0x00D0106B,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kLangur},
{ 0x6899,0x21E41458,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5850",kUakari},
{ 0x6899,0x200A1787,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5850",kUakari},
{ 0x6899,0x22901787,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5850",kUakari},
{ 0x6899,0xE140174B,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5850",kUakari},
{ 0x689C,0x03521043,CHIP_FAMILY_HEMLOCK,"ASUS ARES",kUakari},
{ 0x689C,0x039E1043,CHIP_FAMILY_HEMLOCK,"ASUS EAH5870 Series",kUakari},
{ 0x689C,0x30201682,CHIP_FAMILY_HEMLOCK,"ATI Radeon HD 5970",kUakari},
{ 0x68B8,0xE147174B,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x21D71458,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x1482174B,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x29901682,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x29911682,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x200B1787,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x22881787,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x00CF106B,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kHoolock},
{ 0x68D8,0x301117AF,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5690",kNull},
{ 0x68D8,0x301017AF,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5730",kNull},
{ 0x68D8,0x30001787,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5730",kNull},
{ 0x68D8,0x5690174B,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5690",kNull},
{ 0x68D8,0x5730174B,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5730",kNull},
{ 0x68D8,0x21D91458,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5670",kBaboon},
{ 0x68D8,0x03561043,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5670",kBaboon},
{ 0x68D8,0xE151174B,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5670",kBaboon},
{ 0x68D9,0x301017AF,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5630",kNull},
{ 0x68DA,0x301017AF,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5630",kNull},
{ 0x68DA,0x30001787,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5630",kNull},
{ 0x68DA,0x5630174B,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5630",kNull},
{ 0x68E0,0x04561028,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5470M",kEulemur},
{ 0x68E1,0x1426103C,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5430M",kEulemur},
{ 0x68F9,0x301317AF,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5470",kNull},
{ 0x68F9,0x301117AF,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5470",kNull},
{ 0x68F9,0x301217AF,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5490",kNull},
{ 0x68F9,0x30001787,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5470",kNull},
{ 0x68F9,0x30021787,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5490",kNull},
{ 0x68F9,0x30011787,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5530",kNull},
{ 0x68F9,0x5470174B,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5470",kNull},
{ 0x68F9,0x5490174B,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5490",kNull},
{ 0x68F9,0x5530174B,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5530",kNull},
{ 0x6898,0x032E1043, CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kUakari},
{ 0x6898,0xE140174B, CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kUakari},
{ 0x6898,0x29611682, CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kUakari},
{ 0x6898,0x0B001002, CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kZonalis},
{ 0x6898,0x00D0106B, CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kLangur},
{ 0x6899,0x21E41458, CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5850",kUakari},
{ 0x6899,0x200A1787, CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5850",kUakari},
{ 0x6899,0x22901787, CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5850",kUakari},
{ 0x6899,0xE140174B, CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5850",kUakari},
{ 0x689C,0x03521043, CHIP_FAMILY_HEMLOCK,"ASUS ARES",kUakari},
{ 0x689C,0x039E1043, CHIP_FAMILY_HEMLOCK,"ASUS EAH5870 Series",kUakari},
{ 0x689C,0x30201682, CHIP_FAMILY_HEMLOCK,"ATI Radeon HD 5970",kUakari},
{ 0x68A8,0x050E1025,CHIP_FAMILY_CYPRESS,"AMD Radeon HD 6850M",kUakari}, // issue #89
{ 0x68B8,0xE147174B, CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x21D71458, CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x1482174B, CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x29901682, CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x29911682, CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x200B1787, CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x22881787, CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x00CF106B, CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kHoolock},
{ 0x68C0,0x1594103C,CHIP_FAMILY_REDWOOD,"AMD Radeon HD 6570M",kNull}, // issue #91
//Azi: from Slice { 0x100268C0, "ATI Radeon 5670 Series", "Galago"}
// http://www.insanelymac.com/forum/index.php?s=&showtopic=255866&view=findpost&p=1695482
{ 0x68C1,0x033E1025,CHIP_FAMILY_REDWOOD,"ATI Mobility Radeon HD 5650",kNull},
{ 0x68D8,0x301117AF, CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5690",kNull},
{ 0x68D8,0x301017AF, CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5730",kNull},
{ 0x68D8,0x30001787, CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5730",kNull},
{ 0x68D8,0x5690174B, CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5690",kNull},
{ 0x68D8,0x5730174B, CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5730",kNull},
{ 0x68D8,0x21D91458, CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5670",kBaboon},
{ 0x68D8,0x03561043, CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5670",kBaboon},
{ 0x68D8,0xE151174B, CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5670",kBaboon},
{ 0x68D9,0x301017AF, CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5630",kNull},
{ 0x68DA,0x301017AF, CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5630",kNull},
{ 0x68DA,0x30001787, CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5630",kNull},
{ 0x68DA,0x5630174B, CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5630",kNull},
{ 0x68E1,0x1426103C, CHIP_FAMILY_CEDAR,"ATI Radeon HD 5430M",kEulemur},
{ 0x68E0,0x1433103C, CHIP_FAMILY_CEDAR,"ATI Radeon HD 5470M",kEulemur},
{ 0x68E0,0x04561028, CHIP_FAMILY_CEDAR,"ATI Radeon HD 5470M",kEulemur},
{ 0x68F9, 0x20091787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5450", kEulemur },
{ 0x68F9, 0x22911787, CHIP_FAMILY_CEDAR, "ATI Radeon HD 5450", kEulemur },
{ 0x68F9,0x301317AF, CHIP_FAMILY_CEDAR,"ATI Radeon HD 5470",kNull},
{ 0x68F9,0x301117AF, CHIP_FAMILY_CEDAR,"ATI Radeon HD 5470",kNull},
{ 0x68F9,0x30001787, CHIP_FAMILY_CEDAR,"ATI Radeon HD 5470",kNull},
{ 0x68F9,0x5470174B, CHIP_FAMILY_CEDAR,"ATI Radeon HD 5470",kNull},
{ 0x68F9,0x301217AF, CHIP_FAMILY_CEDAR,"ATI Radeon HD 5490",kNull},
{ 0x68F9,0x30021787, CHIP_FAMILY_CEDAR,"ATI Radeon HD 5490",kNull},
{ 0x68F9,0x5490174B, CHIP_FAMILY_CEDAR,"ATI Radeon HD 5490",kNull},
{ 0x68F9,0x5530174B, CHIP_FAMILY_CEDAR,"ATI Radeon HD 5530",kNull},
{ 0x68F9,0x30011787, CHIP_FAMILY_CEDAR,"ATI Radeon HD 5530",kNull},
/* Northen Islands */
{ 0x6718,0x0B001002,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970",kNull},
{ 0x6718,0x31301682,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970",kNull},
{ 0x6718,0x67181002,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970",kNull},
{ 0x6738,0x67381002,CHIP_FAMILY_BARTS,"AMD Radeon HD 6870",kDuckweed},
{ 0x6739,0x67391002,CHIP_FAMILY_BARTS,"AMD Radeon HD 6850",kDuckweed},
{ 0x6739,0x21F81458,CHIP_FAMILY_BARTS,"AMD Radeon HD 6850",kDuckweed},
{ 0x6741,0x050E1025,CHIP_FAMILY_TURKS,"AMD Radeon HD 6650M",kNull}, // issue 121
{ 0x6741,0x1646103C,CHIP_FAMILY_TURKS,"AMD Radeon HD 6750M",kNull}, // issue 88
{ 0x6759,0xE193174B,CHIP_FAMILY_TURKS,"AMD Radeon HD 6570",kNull},
{ 0x6760,0x1CB21043,CHIP_FAMILY_RV730,"AMD Radeon HD 6470M",kNull},
/* standard/default models */
{ 0x9400,0x00000000,CHIP_FAMILY_R600,"ATI Radeon HD 2900 XT",kNull},
{ 0x9405,0x00000000,CHIP_FAMILY_R600,"ATI Radeon HD 2900 GT",kNull},
{ 0x9440,0x00000000,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x9441,0x00000000,CHIP_FAMILY_RV770,"ATI Radeon HD 4870 X2",kMotmot},
{ 0x9442,0x00000000,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x9443,0x00000000,CHIP_FAMILY_RV770,"ATI Radeon HD 4850 X2",kMotmot},
{ 0x944C,0x00000000,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944E,0x00000000,CHIP_FAMILY_RV770,"ATI Radeon HD 4700 Series",kMotmot},
{ 0x9450,0x00000000,CHIP_FAMILY_RV770,"AMD FireStream 9270",kMotmot},
{ 0x9452,0x00000000,CHIP_FAMILY_RV770,"AMD FireStream 9250",kMotmot},
{ 0x9460,0x00000000,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x9462,0x00000000,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x9490,0x00000000,CHIP_FAMILY_RV730,"ATI Radeon HD 4600 Series",kFlicker},
{ 0x9498,0x00000000,CHIP_FAMILY_RV730,"ATI Radeon HD 4600 Series",kFlicker},
{ 0x94B3,0x00000000,CHIP_FAMILY_RV740,"ATI Radeon HD 4770",kFlicker},
{ 0x94B4,0x00000000,CHIP_FAMILY_RV740,"ATI Radeon HD 4700 Series",kFlicker},
{ 0x94B5,0x00000000,CHIP_FAMILY_RV740,"ATI Radeon HD 4770",kFlicker},
{ 0x94C1,0x00000000,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 Series",kIago},
{ 0x94C3,0x00000000,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 Series",kIago},
{ 0x94C7,0x00000000,CHIP_FAMILY_RV610,"ATI Radeon HD 2350",kIago},
{ 0x94CC,0x00000000,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 Series",kIago},
{ 0x9501,0x00000000,CHIP_FAMILY_RV670,"ATI Radeon HD 3800 Series",kMegalodon},
{ 0x9505,0x00000000,CHIP_FAMILY_RV670,"ATI Radeon HD 3800 Series",kMegalodon},
{ 0x9507,0x00000000,CHIP_FAMILY_RV670,"ATI Radeon HD 3830",kMegalodon},
{ 0x950F,0x00000000,CHIP_FAMILY_RV670,"ATI Radeon HD 3870 X2",kMegalodon},
{ 0x9513,0x00000000,CHIP_FAMILY_RV670,"ATI Radeon HD 3850 X2",kMegalodon},
{ 0x9519,0x00000000,CHIP_FAMILY_RV670,"AMD FireStream 9170",kMegalodon},
{ 0x9540,0x00000000,CHIP_FAMILY_RV710,"ATI Radeon HD 4550",kNull},
{ 0x954F,0x00000000,CHIP_FAMILY_RV710,"ATI Radeon HD 4300/4500 Series",kNull},
{ 0x9588,0x00000000,CHIP_FAMILY_RV630,"ATI Radeon HD 2600 XT",kLamna},
{ 0x9589,0x00000000,CHIP_FAMILY_RV630,"ATI Radeon HD 2600 PRO",kLamna},
{ 0x958A,0x00000000,CHIP_FAMILY_RV630,"ATI Radeon HD 2600 X2 Series",kLamna},
{ 0x9598,0x00000000,CHIP_FAMILY_RV635,"ATI Radeon HD 3600 Series",kMegalodon},
{ 0x95C0,0x00000000,CHIP_FAMILY_RV620,"ATI Radeon HD 3400 Series",kIago},
{ 0x95C5,0x00000000,CHIP_FAMILY_RV620,"ATI Radeon HD 3400 Series",kIago},
{ 0x9610,0x00000000,CHIP_FAMILY_RS780,"ATI Radeon HD 3200 Graphics",kNull},
{ 0x9611,0x00000000,CHIP_FAMILY_RS780,"ATI Radeon 3100 Graphics",kNull},
{ 0x9614,0x00000000,CHIP_FAMILY_RS780,"ATI Radeon HD 3300 Graphics",kNull},
{ 0x9616,0x00000000,CHIP_FAMILY_RS780,"AMD 760G",kNull},
{ 0x9710,0x00000000,CHIP_FAMILY_RS880,"ATI Radeon HD 4200",kNull},
{ 0x9715,0x00000000,CHIP_FAMILY_RS880,"ATI Radeon HD 4250",kNull},
{ 0x9714,0x00000000,CHIP_FAMILY_RS880,"ATI Radeon HD 4290",kNull},
{ 0x9400,0x00000000, CHIP_FAMILY_R600,"ATI Radeon HD 2900 XT",kNull},
{ 0x9405,0x00000000, CHIP_FAMILY_R600,"ATI Radeon HD 2900 GT",kNull},
{ 0x9440,0x00000000, CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x9441,0x00000000, CHIP_FAMILY_RV770,"ATI Radeon HD 4870 X2",kMotmot},
{ 0x9442,0x00000000, CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x9443,0x00000000, CHIP_FAMILY_RV770,"ATI Radeon HD 4850 X2",kMotmot},
{ 0x944C,0x00000000, CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944E,0x00000000, CHIP_FAMILY_RV770,"ATI Radeon HD 4700 Series",kMotmot},
{ 0x9450,0x00000000, CHIP_FAMILY_RV770,"AMD FireStream 9270",kMotmot},
{ 0x9452,0x00000000, CHIP_FAMILY_RV770,"AMD FireStream 9250",kMotmot},
{ 0x9460,0x00000000, CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x9462,0x00000000, CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x9490,0x00000000, CHIP_FAMILY_RV730,"ATI Radeon HD 4600 Series",kFlicker},
{ 0x9498,0x00000000, CHIP_FAMILY_RV730,"ATI Radeon HD 4600 Series",kFlicker},
{ 0x94B3,0x00000000, CHIP_FAMILY_RV740,"ATI Radeon HD 4770",kFlicker},
{ 0x94B4,0x00000000, CHIP_FAMILY_RV740,"ATI Radeon HD 4700 Series",kFlicker},
{ 0x94B5,0x00000000, CHIP_FAMILY_RV740,"ATI Radeon HD 4770",kFlicker},
{ 0x94C1,0x00000000, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 Series",kIago},
{ 0x94C3,0x00000000, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 Series",kIago},
{ 0x94C7,0x00000000, CHIP_FAMILY_RV610,"ATI Radeon HD 2350",kIago},
{ 0x94CC,0x00000000, CHIP_FAMILY_RV610,"ATI Radeon HD 2400 Series",kIago},
{ 0x9501,0x00000000, CHIP_FAMILY_RV670,"ATI Radeon HD 3800 Series",kMegalodon},
{ 0x9505,0x00000000, CHIP_FAMILY_RV670,"ATI Radeon HD 3800 Series",kMegalodon},
{ 0x9507,0x00000000, CHIP_FAMILY_RV670,"ATI Radeon HD 3830",kMegalodon},
{ 0x950F,0x00000000, CHIP_FAMILY_RV670,"ATI Radeon HD 3870 X2",kMegalodon},
{ 0x9513,0x00000000, CHIP_FAMILY_RV670,"ATI Radeon HD 3850 X2",kMegalodon},
{ 0x9519,0x00000000, CHIP_FAMILY_RV670,"AMD FireStream 9170",kMegalodon},
{ 0x9540,0x00000000, CHIP_FAMILY_RV710,"ATI Radeon HD 4550",kNull},
{ 0x954F,0x00000000, CHIP_FAMILY_RV710,"ATI Radeon HD 4300/4500 Series",kNull},
{ 0x9588,0x00000000, CHIP_FAMILY_RV630,"ATI Radeon HD 2600 XT",kLamna},
{ 0x9589,0x00000000, CHIP_FAMILY_RV630,"ATI Radeon HD 2600 PRO",kLamna},
{ 0x958A,0x00000000, CHIP_FAMILY_RV630,"ATI Radeon HD 2600 X2 Series",kLamna},
{ 0x9598,0x00000000, CHIP_FAMILY_RV635,"ATI Radeon HD 3600 Series",kMegalodon},
{ 0x95C0,0x00000000, CHIP_FAMILY_RV620,"ATI Radeon HD 3400 Series",kIago},
{ 0x95C5,0x00000000, CHIP_FAMILY_RV620,"ATI Radeon HD 3400 Series",kIago},
{ 0x9610,0x00000000, CHIP_FAMILY_RS780,"ATI Radeon HD 3200 Graphics",kNull},
{ 0x9611,0x00000000, CHIP_FAMILY_RS780,"ATI Radeon 3100 Graphics",kNull},
{ 0x9614,0x00000000, CHIP_FAMILY_RS780,"ATI Radeon HD 3300 Graphics",kNull},
{ 0x9616,0x00000000, CHIP_FAMILY_RS780,"AMD 760G",kNull},
{ 0x9710,0x00000000, CHIP_FAMILY_RS880,"ATI Radeon HD 4200",kNull},
{ 0x9715,0x00000000, CHIP_FAMILY_RS880,"ATI Radeon HD 4250",kNull},
{ 0x9714,0x00000000, CHIP_FAMILY_RS880,"ATI Radeon HD 4290",kNull},
/* Evergreen */
{ 0x688D,0x00000000,CHIP_FAMILY_CYPRESS,"AMD FireStream 9350",kUakari},
{ 0x6898,0x00000000,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5800 Series",kUakari},
{ 0x6899,0x00000000,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5800 Series",kUakari},
{ 0x689E,0x00000000,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5800 Series",kUakari},
{ 0x689C,0x00000000,CHIP_FAMILY_HEMLOCK,"ATI Radeon HD 5900 Series",kUakari},
{ 0x68B9,0x00000000,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5600 Series",kVervet},
{ 0x68B8,0x00000000,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5700 Series",kVervet},
{ 0x68BE,0x00000000,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5700 Series",kVervet},
{ 0x68D8,0x00000000,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5600 Series",kBaboon},
{ 0x68D9,0x00000000,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5500 Series",kBaboon},
{ 0x68DA,0x00000000,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5500 Series",kBaboon},
{ 0x68F9,0x00000000,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5400 Series",kNull},
{ 0x688D,0x00000000, CHIP_FAMILY_CYPRESS,"AMD FireStream 9350",kUakari},
{ 0x6898,0x00000000, CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5800 Series",kUakari},
{ 0x6899,0x00000000, CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5800 Series",kUakari},
{ 0x689E,0x00000000, CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5800 Series",kUakari},
{ 0x689C,0x00000000, CHIP_FAMILY_HEMLOCK,"ATI Radeon HD 5900 Series",kUakari},
{ 0x68B9,0x00000000, CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5600 Series",kVervet},
{ 0x68B8,0x00000000, CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5700 Series",kVervet},
{ 0x68BE,0x00000000, CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5700 Series",kVervet},
{ 0x68D8,0x00000000, CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5600 Series",kBaboon},
{ 0x68D9,0x00000000, CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5500 Series",kBaboon},
{ 0x68DA,0x00000000, CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5500 Series",kBaboon},
{ 0x68F9,0x00000000, CHIP_FAMILY_CEDAR,"ATI Radeon HD 5400 Series",kNull},
/* Northen Islands */
{ 0x6718,0x00000000,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970 Series",kNull},
{ 0x6738,0x00000000,CHIP_FAMILY_BARTS,"AMD Radeon HD 6870 Series",kDuckweed},
{ 0x6739,0x00000000,CHIP_FAMILY_BARTS,"AMD Radeon HD 6850 Series",kDuckweed},
{ 0x673E,0x00000000,CHIP_FAMILY_BARTS,"AMD Radeon HD 6790 Series",kNull},
{ 0x6758,0x00000000,CHIP_FAMILY_TURKS,"AMD Radeon HD 6670 Series",kNull},
{ 0x6759,0x00000000,CHIP_FAMILY_TURKS,"AMD Radeon HD 6500 Series",kNull},
{ 0x6770,0x00000000,CHIP_FAMILY_CAICOS,"AMD Radeon HD 6400 Series",kNull},
{ 0x6779,0x00000000,CHIP_FAMILY_CAICOS,"AMD Radeon HD 6450 Series",kNull},
{ 0x0000,0x00000000,CHIP_FAMILY_UNKNOW,NULL,kNull}
};
typedef struct {
struct DevPropDevice*device;
radeon_card_info_t*info;
pci_dt_t *pci_dev;
pci_dt_t*pci_dev;
uint8_t*fb;
uint8_t*mmio;
uint8_t*io;
card_t *card;
/* Flags */
#define MKFLAG(n)(1 << n)
#define FLAGTRUEMKFLAG(0)
#define EVERGREENMKFLAG(1)
#define MKFLAG(n)(1 << n)
#define FLAGTRUEMKFLAG(0)
#define EVERGREENMKFLAG(1)
static uint8_t atN = 0;
//static uint8_t atN = 0;
typedef struct {
type_ttype;
uint32_tsize;
uint8_t*data;
type_ttype;
uint32_tsize;
uint8_t*data;
} value_t;
static value_t aty_name;
static value_t aty_nameparent;
//static value_t aty_model;
#define DATVAL(x){kPtr, sizeof(x), (uint8_t *)x}
#define STRVAL(x){kStr, sizeof(x), (uint8_t *)x}
#define BYTVAL(x){kCst, 1, (uint8_t *)x}
#define WRDVAL(x){kCst, 2, (uint8_t *)x}
#define DWRVAL(x){kCst, 4, (uint8_t *)x}
#define QWRVAL(x){kCst, 8, (uint8_t *)x}
#define NULVAL{kNul, 0, (uint8_t *)NULL}
#define DATVAL(x){kPtr, sizeof(x), (uint8_t *)x}
#define STRVAL(x){kStr, sizeof(x), (uint8_t *)x}
#define BYTVAL(x){kCst, 1, (uint8_t *)x}
#define WRDVAL(x){kCst, 2, (uint8_t *)x}
#define DWRVAL(x){kCst, 4, (uint8_t *)x}
#define QWRVAL(x){kCst, 8, (uint8_t *)x}
#define NULVAL{kNul, 0, (uint8_t *)NULL}
bool get_bootdisplay_val(value_t *val);
bool get_vrammemory_val(value_t *val);
bool get_vramtotalsize_val(value_t *val);
typedef struct {
uint32_tflags;
boolall_ports;
char*name;
bool(*get_value)(value_t *val);
value_tdefault_val;
uint32_tflags;
boolall_ports;
char*name;
bool(*get_value)(value_t *val);
value_tdefault_val;
} dev_prop_t;
dev_prop_t ati_devprop_list[] = {
{FLAGTRUE,false,"@0,AAPL,boot-display",get_bootdisplay_val,NULVAL},
//{FLAGTRUE,false,"@0,ATY,EFIDisplay",NULL,STRVAL("TMDSA")},
//{FLAGTRUE,true,"@0,AAPL,vram-memory",get_vrammemory_val,NULVAL},
//{FLAGTRUE,true,"@0,compatible",get_name_val,NULVAL},
//{FLAGTRUE,true,"@0,connector-type",get_conntype_val,NULVAL},
//{FLAGTRUE,true,"@0,device_type",NULL,STRVAL("display")},
//{FLAGTRUE,false,"@0,display-connect-flags",NULL,DWRVAL((uint32_t)0)},
//{FLAGTRUE,false,"@0,display-connect-flags", NULL,DWRVAL((uint32_t)0)},
//{FLAGTRUE,true,"@0,display-type",NULL,STRVAL("NONE")},
{FLAGTRUE,true,"@0,name",get_name_val,NULVAL},
//{FLAGTRUE,true,"@0,VRAM,memsize",get_vrammemsize_val,NULVAL},
//{FLAGTRUE,false,"AAPL,aux-power-connected",NULL,DWRVAL((uint32_t)1)},
//{FLAGTRUE,false,"AAPL,aux-power-connected", NULL,DWRVAL((uint32_t)1)},
//{FLAGTRUE,false,"AAPL,backlight-control",NULL,DWRVAL((uint32_t)0)},
{FLAGTRUE,false,"ATY,bin_image",get_binimage_val,NULVAL},
{FLAGTRUE,false,"ATY,Copyright",NULL,STRVAL("Copyright AMD Inc. All Rights Reserved. 2005-2010")},
{FLAGTRUE,false,"ATY,Copyright",NULL,STRVAL("Copyright AMD Inc. All Rights Reserved. 2005-2010") },
{FLAGTRUE,false,"ATY,Card#",get_romrevision_val,NULVAL},
{FLAGTRUE,false,"ATY,VendorID",NULL,WRDVAL((uint16_t)0x1002)},
{FLAGTRUE,false,"ATY,DeviceID",get_deviceid_val,NULVAL},
//{FLAGTRUE,false,"ATY,MCLK",get_mclk_val,NULVAL},
//{FLAGTRUE,false,"ATY,SCLK",get_sclk_val,NULVAL},
//{FLAGTRUE,false,"ATY,RefCLK",get_refclk_val,DWRVAL((uint32_t)0x0a8c)},
//{FLAGTRUE,false,"ATY,PlatformInfo",get_platforminfo_val,NULVAL},
{FLAGTRUE,false,"name",get_nameparent_val,NULVAL},
{FLAGTRUE,false,"device_type",get_nameparent_val,NULVAL},
{FLAGTRUE,false,"model",get_model_val,STRVAL("ATI Radeon")},
//{FLAGTRUE,false,"VRAM,totalsize",get_vramtotalsize_val,NULVAL},
{FLAGTRUE,false,NULL,NULL,NULVAL}
};
bool get_bootdisplay_val(value_t *val)
{
static uint32_t v = 0;
if (v)
return false;
if (!card->posted)
return false;
v = 1;
val->type = kCst;
val->size = 4;
val->data = (uint8_t *)&v;
return true;
}
val->type = aty_name.type;
val->size = aty_name.size;
val->data = aty_name.data;
return true;
}
val->type = aty_nameparent.type;
val->size = aty_nameparent.size;
val->data = aty_nameparent.data;
return true;
}
{
if (!card->info->model_name)
return false;
val->type = kStr;
val->size = strlen(card->info->model_name) + 1;
val->data = (uint8_t *)card->info->model_name;
return true;
}
bool get_conntype_val(value_t *val)
{
/*
Connector types:
0x4 : DisplayPort
0x400: DL DVI-I
0x800: HDMI
*/
//Connector types:
//0x4 : DisplayPort
//0x400: DL DVI-I
//0x800: HDMI
return false;
}
{
static int idx = -1;
static uint64_t memsize;
idx++;
memsize = ((uint64_t)card->vram_size << 32);
if (idx == 0)
memsize = memsize | (uint64_t)card->vram_size;
val->type = kCst;
val->size = 8;
val->data = (uint8_t *)&memsize;
return true;
}
{
if (!card->rom)
return false;
val->type = kPtr;
val->size = card->rom_size;
val->data = card->rom;
return true;
}
uint8_t *rev;
if (!card->rom)
return false;
rev = card->rom + *(uint8_t *)(card->rom + OFFSET_TO_GET_ATOMBIOS_STRINGS_START);
val->type = kPtr;
val->size = strlen((char *)rev);
val->data = malloc(val->size);
if (!val->data)
return false;
memcpy(val->data, rev, val->size);
return true;
}
val->type = kCst;
val->size = 2;
val->data = (uint8_t *)&card->pci_dev->device_id;
return true;
}
val->data = malloc(0x80);
if (!val->data)
return false;
bzero(val->data, 0x80);
val->type= kPtr;
val->size= 0x80;
val->data[0]= 1;
return true;
}
val->type = kCst;
val->size = 4;
val->data = (uint8_t *)&card->vram_size;
return true;
}
{
if (val->type == kPtr)
free(val->data);
bzero(val, sizeof(value_t));
}
{
value_t *val = malloc(sizeof(value_t));
int i, pnum;
for (i = 0; devprop_list[i].name != NULL; i++)
{
if ((devprop_list[i].flags == FLAGTRUE) || (devprop_list[i].flags | card->flags))
{
if (devprop_list[i].get_value && devprop_list[i].get_value(val))
{
devprop_add_value(card->device, devprop_list[i].name, val->data, val->size);
free_val(val);
if (devprop_list[i].all_ports)
{
for (pnum = 1; pnum < card->ports; pnum++)
else
{
if (devprop_list[i].default_val.type != kNul)
devprop_add_value(card->device, devprop_list[i].name,
devprop_list[i].default_val.type == kCst ?
(uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data,
{
devprop_add_value(card->device, devprop_list[i].name,
devprop_list[i].default_val.type == kCst ?
(uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data,
devprop_list[i].default_val.size);
}
if (devprop_list[i].all_ports)
{
for (pnum = 1; pnum < card->ports; pnum++)
if (devprop_list[i].default_val.type != kNul)
{
devprop_list[i].name[1] = 0x30 + pnum; // convert to ascii
devprop_add_value(card->device, devprop_list[i].name,
devprop_list[i].default_val.type == kCst ?
(uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data,
devprop_add_value(card->device, devprop_list[i].name,
devprop_list[i].default_val.type == kCst ?
(uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data,
devprop_list[i].default_val.size);
}
}
devprop_list[i].name[1] = 0x30; // write back our "@0," for a next possible card
}
}
}
}
free(val);
}
bool validate_rom(option_rom_header_t *rom_header, pci_dt_t *pci_dev)
{
option_rom_pci_header_t *rom_pci_header;
if (rom_header->signature != 0xaa55)
return false;
rom_pci_header = (option_rom_pci_header_t *)((uint8_t *)rom_header + rom_header->pci_header_offset);
if (rom_pci_header->signature != 0x52494350)
return false;
if (rom_pci_header->vendor_id != pci_dev->vendor_id || rom_pci_header->device_id != pci_dev->device_id)
return false;
return true;
}
bool load_vbios_file(const char *key, uint16_t vendor_id, uint16_t device_id, uint32_t subsys_id)
{
intfd;
int fd;
char file_name[24];
bool do_load = false;
getBoolForKey(key, &do_load, &bootInfo->chameleonConfig);
if (!do_load)
return false;
sprintf(file_name, "/Extra/%04x_%04x_%08x.rom", vendor_id, device_id, subsys_id);
if ((fd = open_bvdev("bt(0,0)", file_name, 0)) < 0)
return false;
card->rom_size = file_size(fd);
card->rom = malloc(card->rom_size);
if (!card->rom)
return false;
read(fd, (char *)card->rom, card->rom_size);
if (!validate_rom((option_rom_header_t *)card->rom, card->pci_dev))
card->rom = 0;
return false;
}
card->rom_size = ((option_rom_header_t *)card->rom)->rom_size * 512;
close(fd);
return true;
}
void get_vram_size(void)
{
chip_family_t chip_family = card->info->chip_family;
card->vram_size = 0;
if (chip_family >= CHIP_FAMILY_CEDAR)
/* size in MB on evergreen */
/* XXX watch for overflow!!! */
// size in MB on evergreen
// XXX watch for overflow!!!
card->vram_size = RegRead32(R600_CONFIG_MEMSIZE) * 1024 * 1024;
else
if (chip_family >= CHIP_FAMILY_R600)
bool read_vbios(bool from_pci)
{
option_rom_header_t *rom_addr;
if (from_pci)
{
rom_addr = (option_rom_header_t *)(pci_config_read32(card->pci_dev->dev.addr, PCI_ROM_ADDRESS) & ~0x7ff);
}
else
rom_addr = (option_rom_header_t *)0xc0000;
if (!validate_rom(rom_addr, card->pci_dev))
return false;
card->rom_size = rom_addr->rom_size * 512;
if (!card->rom_size)
return false;
card->rom = malloc(card->rom_size);
if (!card->rom)
return false;
memcpy(card->rom, (void *)rom_addr, card->rom_size);
return true;
}
{
bool ret = false;
chip_family_t chip_family = card->info->chip_family;
if (chip_family >= CHIP_FAMILY_RV770)
{
uint32_t viph_control= RegRead32(RADEON_VIPH_CONTROL);
uint32_t bus_cntl= RegRead32(RADEON_BUS_CNTL);
uint32_t d1vga_control= RegRead32(AVIVO_D1VGA_CONTROL);
uint32_t d2vga_control= RegRead32(AVIVO_D2VGA_CONTROL);
uint32_t vga_render_control= RegRead32(AVIVO_VGA_RENDER_CONTROL);
uint32_t vga_render_control = RegRead32(AVIVO_VGA_RENDER_CONTROL);
uint32_t rom_cntl= RegRead32(R600_ROM_CNTL);
uint32_t cg_spll_func_cntl= 0;
uint32_t cg_spll_status;
/* disable VIP */
// disable VIP
RegWrite32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
/* enable the rom */
// enable the rom
RegWrite32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
/* Disable VGA mode */
// Disable VGA mode
RegWrite32(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT)));
RegWrite32(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT)));
RegWrite32(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
if (chip_family == CHIP_FAMILY_RV730)
{
cg_spll_func_cntl = RegRead32(R600_CG_SPLL_FUNC_CNTL);
/* enable bypass mode */
// enable bypass mode
RegWrite32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | R600_SPLL_BYPASS_EN));
/* wait for SPLL_CHG_STATUS to change to 1 */
// wait for SPLL_CHG_STATUS to change to 1
cg_spll_status = 0;
while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
cg_spll_status = RegRead32(R600_CG_SPLL_STATUS);
RegWrite32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
}
else
RegWrite32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
ret = read_vbios(true);
/* restore regs */
// restore regs
if (chip_family == CHIP_FAMILY_RV730)
{
RegWrite32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
/* wait for SPLL_CHG_STATUS to change to 1 */
// wait for SPLL_CHG_STATUS to change to 1
cg_spll_status = 0;
while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
cg_spll_status = RegRead32(R600_CG_SPLL_STATUS);
uint32_t viph_control= RegRead32(RADEON_VIPH_CONTROL);
uint32_t bus_cntl= RegRead32(RADEON_BUS_CNTL);
uint32_t d1vga_control= RegRead32(AVIVO_D1VGA_CONTROL);
uint32_t d2vga_control = RegRead32(AVIVO_D2VGA_CONTROL);
uint32_t d2vga_control= RegRead32(AVIVO_D2VGA_CONTROL);
uint32_t vga_render_control= RegRead32(AVIVO_VGA_RENDER_CONTROL);
uint32_t rom_cntl= RegRead32(R600_ROM_CNTL);
uint32_t general_pwrmgt= RegRead32(R600_GENERAL_PWRMGT);
uint32_t low_vid_lower_gpio_cntl= RegRead32(R600_LOW_VID_LOWER_GPIO_CNTL);
uint32_t medium_vid_lower_gpio_cntl= RegRead32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
uint32_t medium_vid_lower_gpio_cntl = RegRead32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
uint32_t high_vid_lower_gpio_cntl= RegRead32(R600_HIGH_VID_LOWER_GPIO_CNTL);
uint32_t ctxsw_vid_lower_gpio_cntl= RegRead32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
uint32_t lower_gpio_enable= RegRead32(R600_LOWER_GPIO_ENABLE);
/* disable VIP */
// disable VIP
RegWrite32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
/* enable the rom */
// enable the rom
RegWrite32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
/* Disable VGA mode */
// Disable VGA mode
RegWrite32(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT)));
RegWrite32(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT)));
RegWrite32(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
RegWrite32(R600_HIGH_VID_LOWER_GPIO_CNTL, (high_vid_lower_gpio_cntl & ~0x400));
RegWrite32(R600_CTXSW_VID_LOWER_GPIO_CNTL, (ctxsw_vid_lower_gpio_cntl & ~0x400));
RegWrite32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
ret = read_vbios(true);
/* restore regs */
// restore regs
RegWrite32(RADEON_VIPH_CONTROL, viph_control);
RegWrite32(RADEON_BUS_CNTL, bus_cntl);
RegWrite32(AVIVO_D1VGA_CONTROL, d1vga_control);
RegWrite32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
RegWrite32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
RegWrite32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
}
return ret;
bool radeon_card_posted(void)
{
uint32_t reg;
/* first check CRTCs */
// first check CRTCs
reg = RegRead32(RADEON_CRTC_GEN_CNTL) | RegRead32(RADEON_CRTC2_GEN_CNTL);
if (reg & RADEON_CRTC_EN)
return true;
/* then check MEM_SIZE, in case something turned the crtcs off */
// then check MEM_SIZE, in case something turned the crtcs off
reg = RegRead32(R600_CONFIG_MEMSIZE);
if (reg)
return true;
return false;
}
#if 0
bool devprop_add_pci_config_space(void)
{
int offset;
uint8_t *config_space = malloc(0x100);
if (!config_space)
return false;
for (offset = 0; offset < 0x100; offset += 4)
config_space[offset / 4] = pci_config_read32(card->pci_dev->dev.addr, offset);
devprop_add_value(card->device, "ATY,PCIConfigSpace", config_space, 0x100);
free(config_space);
return true;
}
#endif
static bool init_card(pci_dt_t *pci_dev)
{
char name[24];
char name_parent[24];
int i;
bool add_vbios = true;
booladd_vbios = true;
charname[24];
charname_parent[24];
inti;
intn_ports = 0;
card = malloc(sizeof(card_t));
if (!card)
return false;
bzero(card, sizeof(card_t));
card->pci_dev = pci_dev;
for (i = 0; radeon_cards[i].device_id ; i++)
{
if (radeon_cards[i].device_id == pci_dev->device_id)
{
card->info = &radeon_cards[i];
if ((radeon_cards[i].subsys_id == 0x00000000) ||
if ((radeon_cards[i].subsys_id == 0x00000000) ||
(radeon_cards[i].subsys_id == pci_dev->subsys_id.subsys_id))
break;
}
}
if (!card->info->device_id || !card->info->cfg_name)
{
printf("Unsupported card!\n");
return false;
}
card->fb= (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_0) & ~0x0f);
card->mmio= (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_2) & ~0x0f);
card->io= (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_4) & ~0x03);
verbose("Framebuffer @0x%08X MMIO @0x%08X I/O Port @0x%08X ROM Addr @0x%08X\n",
verbose("Framebuffer @0x%08X MMIO @0x%08XI/O Port @0x%08X ROM Addr @0x%08X\n",
card->fb, card->mmio, card->io, pci_config_read32(pci_dev->dev.addr, PCI_ROM_ADDRESS));
card->posted= radeon_card_posted();
card->posted = radeon_card_posted();
verbose("ATI card %s, ", card->posted ? "POSTed" : "non-POSTed");
get_vram_size();
getBoolForKey(kATYbinimage, &add_vbios, &bootInfo->chameleonConfig);
if (add_vbios)
{
if (!load_vbios_file(kUseAtiROM, pci_dev->vendor_id, pci_dev->device_id, pci_dev->subsys_id.subsys_id))
{
verbose("reading VBIOS from %s", card->posted ? "legacy space" : "PCI ROM");
read_disabled_vbios();
verbose("\n");
}
card->ports = 2; // default
if (card->info->chip_family >= CHIP_FAMILY_CEDAR)
{
card->flags |= EVERGREEN;
card->ports = 3;
}
atN = 0;
//atN = 0;
card->cfg_name = getStringForKey(kAtiConfig, &bootInfo->chameleonConfig);
if (!card->cfg_name)
{
if (strcmp(card->cfg_name, card_configs[i].name) == 0)
card->ports = card_configs[i].ports;
}
if (card->info->chip_family >= CHIP_FAMILY_CEDAR)
{
card->flags |= EVERGREEN;
card->ports = 3; //Azi: not sure of the usefulness ??
}
getIntForKey(kAtiPorts, &n_ports, &bootInfo->bootConfig);
if (n_ports > 0)
card->ports = n_ports;
sprintf(name, "ATY,%s", card->cfg_name);
aty_name.type = kStr;
aty_name.size = strlen(name) + 1;
aty_name.data = (uint8_t *)name;
sprintf(name_parent, "ATY,%sParent", card->cfg_name);
aty_nameparent.type = kStr;
aty_nameparent.size = strlen(name_parent) + 1;
aty_nameparent.data = (uint8_t *)name_parent;
return true;
}
bool setup_ati_devprop(pci_dt_t *ati_dev)
{
char *devicepath;
if (!init_card(ati_dev))
return false;
/* ------------------------------------------------- */
/* Find a better way to do this (in device_inject.c) */
// -------------------------------------------------
// Find a better way to do this (in device_inject.c)
if (!string)
string = devprop_create_string();
devicepath = get_pci_dev_path(ati_dev);
card->device = devprop_add_device(string, devicepath);
if (!card->device)
return false;
/* ------------------------------------------------- */
// -------------------------------------------------
#if 0
uint64_t fb= (uint32_t)card->fb;
uint64_t mmio= (uint32_t)card->mmio;
devprop_add_value(card->device, "ATY,RegisterSpaceOffset", &mmio, 8);
devprop_add_value(card->device, "ATY,IOSpaceOffset", &io, 8);
#endif
devprop_add_list(ati_devprop_list);
/* ------------------------------------------------- */
/* Find a better way to do this (in device_inject.c) */
stringdata = malloc(string->length);
// -------------------------------------------------
// Find a better way to do this (in device_inject.c)
//Azi: XXX tried to fix a malloc error in vain; this is related to XCode 4 compilation!
stringdata = malloc(sizeof(uint8_t) * string->length);
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
/* ------------------------------------------------- */
verbose("ATI %s %s %dMB (%s) [%04x:%04x] (subsys [%04x:%04x]):: %s\n",
chip_family_name[card->info->chip_family], card->info->model_name,
(uint32_t)(card->vram_size / (1024 * 1024)), card->cfg_name,
// -------------------------------------------------
verbose("ATI %s %s %dMB (%s) [%04x:%04x] (subsys [%04x:%04x]):: %s\n",
chip_family_name[card->info->chip_family], card->info->model_name,
(uint32_t)(card->vram_size / (1024 * 1024)), card->cfg_name,
ati_dev->vendor_id, ati_dev->device_id,
ati_dev->subsys_id.subsys.vendor_id, ati_dev->subsys_id.subsys.device_id,
ati_dev->subsys_id.subsys.vendor_id, ati_dev->subsys_id.subsys.device_id,
devicepath);
free(card);
return true;
}
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unsigned long pollCount;
uint64_t retval = 0;
int i;
/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT
* counter 2. We run this loop 3 times to make sure the cache
* is hot and we take the minimum delta from all of the runs.
* Hz so we need to convert our milliseconds to seconds. Since we're
* dividing by the milliseconds, we simply multiply by 1000.
*/
/* Unlike linux, we're not limited to 32-bit, but we do need to take care
* that we're going to multiply by 1000 first so we do need at least some
* arithmetic headroom. For now, 32-bit should be enough.
return retval;
}
#if 0
/*
* DFE: Measures the Max Performance Frequency in Hz (64-bit)
*/
static uint64_t measure_mperf_frequency(void)
{
uint64_t mperfStart;
uint64_t mperfEnd;
uint64_t mperfDelta = 0xffffffffffffffffULL;
unsigned long pollCount;
uint64_t retval = 0;
int i;
/* Time how many MPERF ticks elapse in 30 msec using the 8254 PIT
* counter 2. We run this loop 3 times to make sure the cache
* is hot and we take the minimum delta from all of the runs.
* That is to say that we're biased towards measuring the minimum
* number of MPERF ticks that occur while waiting for the timer to
* expire.
*/
for(i = 0; i < 10; ++i)
{
enable_PIT2();
set_PIT2_mode0(CALIBRATE_LATCH);
mperfStart = rdmsr64(MSR_AMD_MPERF);
pollCount = poll_PIT2_gate();
mperfEnd = rdmsr64(MSR_AMD_MPERF);
/* The poll loop must have run at least a few times for accuracy */
if(pollCount <= 1)
continue;
/* The MPERF must increment at LEAST once every millisecond. We
* should have waited exactly 30 msec so the MPERF delta should
* be >= 30. Anything less and the processor is way too slow.
*/
if((mperfEnd - mperfStart) <= CALIBRATE_TIME_MSEC)
continue;
// tscDelta = MIN(tscDelta, (tscEnd - tscStart))
if( (mperfEnd - mperfStart) < mperfDelta )
mperfDelta = mperfEnd - mperfStart;
}
/* mperfDelta is now the least number of MPERF ticks the processor made in
* a timespan of 0.03 s (e.g. 30 milliseconds)
*/
if(mperfDelta > (1ULL<<32))
retval = 0;
else
{
retval = mperfDelta * 1000 / 30;
}
disable_PIT2();
return retval;
}
#endif
/*
* Measures the Actual Performance Frequency in Hz (64-bit)
*/
static uint64_t measure_aperf_frequency(void)
{
uint64_t aperfStart;
uint64_t aperfEnd;
uint64_t aperfDelta = 0xffffffffffffffffULL;
unsigned long pollCount;
uint64_t retval = 0;
int i;
/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT
* counter 2. We run this loop 3 times to make sure the cache
* is hot and we take the minimum delta from all of the runs.
* That is to say that we're biased towards measuring the minimum
* number of APERF ticks that occur while waiting for the timer to
* expire.
*/
for(i = 0; i < 10; ++i)
{
enable_PIT2();
set_PIT2_mode0(CALIBRATE_LATCH);
aperfStart = rdmsr64(MSR_AMD_APERF);
pollCount = poll_PIT2_gate();
aperfEnd = rdmsr64(MSR_AMD_APERF);
/* The poll loop must have run at least a few times for accuracy */
if(pollCount <= 1)
continue;
/* The TSC must increment at LEAST once every millisecond. We
* should have waited exactly 30 msec so the APERF delta should
* be >= 30. Anything less and the processor is way too slow.
*/
if((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)
continue;
// tscDelta = MIN(tscDelta, (tscEnd - tscStart))
if( (aperfEnd - aperfStart) < aperfDelta )
aperfDelta = aperfEnd - aperfStart;
}
/* mperfDelta is now the least number of MPERF ticks the processor made in
* a timespan of 0.03 s (e.g. 30 milliseconds)
*/
if(aperfDelta > (1ULL<<32))
retval = 0;
else
{
retval = aperfDelta * 1000 / 30;
}
disable_PIT2();
return retval;
}
/*
* Calculates the FSB and CPU frequencies using specific MSRs for each CPU
* - multi. is read from a specific MSR. In the case of Intel, there is:
* a max multi. (used to calculate the FSB freq.),
int len, myfsb;
uint8_t bus_ratio_min;
uint32_t max_ratio, min_ratio;
max_ratio = min_ratio = myfsb = bus_ratio_min = 0;
maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;
/* get cpuid values */
do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);
do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);
do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);
do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);
do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);
do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);
do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);
if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {
if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8) {
do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);
do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);
}
else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {
do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);
}
#if DEBUG_CPU
{
inti;
printf("CPUID Raw Values:\n");
for (i=0; i<CPUID_MAX; i++) {
printf("%02d: %08x-%08x-%08x-%08x\n", i,
p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],
p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);
p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],
p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);
}
}
#endif
p->CPU.Model += (p->CPU.ExtModel << 4);
if (p->CPU.Vendor == 0x756E6547 /* Intel */ &&
if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&
p->CPU.Family == 0x06 &&
p->CPU.Model >= CPUID_MODEL_NEHALEM &&
p->CPU.Model != CPUID_MODEL_ATOM // MSR is *NOT* available on the Intel Atom CPU
){
)
{
msr = rdmsr64(MSR_CORE_THREAD_COUNT);// Undocumented MSR in Nehalem and newer CPUs
p->CPU.NoCores= bitfield((uint32_t)msr, 31, 16);// Using undocumented MSR to get actual values
p->CPU.NoThreads= bitfield((uint32_t)msr, 15, 0);// Using undocumented MSR to get actual values
} else {
}
else if (p->CPU.Vendor == CPUID_VENDOR_AMD)
{
p->CPU.NoThreads= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);
p->CPU.NoCores= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;
}
else
{
p->CPU.NoThreads= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);// Use previous method for Cores and Threads
p->CPU.NoCores= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;
}
strlcpy(p->CPU.BrandString,s, sizeof(p->CPU.BrandString));
if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {
/*
* This string means we have a firmware-programmable brand string,
* and the firmware couldn't figure out what sort of CPU we have.
*/
p->CPU.BrandString[0] = '\0';
}
/*
* This string means we have a firmware-programmable brand string,
* and the firmware couldn't figure out what sort of CPU we have.
*/
p->CPU.BrandString[0] = '\0';
}
}
/* setup features */
if (p->CPU.NoThreads > p->CPU.NoCores) {
p->CPU.Features |= CPU_FEATURE_HTT;
}
tscFrequency = measure_tsc_frequency();
fsbFrequency = 0;
cpuFrequency = 0;
if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {
if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {
int intelCPU = p->CPU.Model;
if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {
/* Nehalem CPU model */
p->CPU.Model == CPU_MODEL_SANDY ||
p->CPU.Model == CPU_MODEL_SANDY_XEON)) {
msr = rdmsr64(MSR_PLATFORM_INFO);
DBG("msr(%d): platform_info %08x\n", __LINE__, msr & 0xffffffff);
bus_ratio_max = (msr >> 8) & 0xff;
bus_ratio_min = (msr >> 40) & 0xff; //valv: not sure about this one (Remarq.1)
DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));
bus_ratio_max = bitfield(msr, 14, 8);
bus_ratio_min = bitfield(msr, 46, 40