Chameleon

Chameleon Commit Details

Date:2010-05-09 08:52:28 (3 years 1 month ago)
Author:Evan Lojewski
Commit:148
Parents: 147
Message:915resolution code
Changes:
A/branches/meklort/i386/libsaio/shortatombios.h
A/branches/meklort/i386/libsaio/resolution.c
A/branches/meklort/i386/libsaio/resolution.h
M/branches/meklort/i386/boot2/boot.c
M/branches/meklort/i386/boot2/kernel_patcher.c
M/branches/meklort/i386/boot2/boot.h
M/branches/meklort/i386/libsaio/Makefile

File differences

branches/meklort/i386/libsaio/shortatombios.h
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/****************************************************************************/␉␊
/*Portion I: Definitions shared between VBIOS and Driver */␊
/****************************************************************************/␊
␊
␊
#ifndef _SHORT_ATOMBIOS_H␊
#define _SHORT_ATOMBIOS_H␊
␊
#define ATOM_VERSION_MAJOR 0x00020000␊
#define ATOM_VERSION_MINOR 0x00000002␊
␊
#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)␊
␊
typedef unsigned char␉␉BOOLEAN;␊
typedef signed char␉␉␉INT8;␊
typedef unsigned char␉␉UINT8;␊
typedef signed short␉␉INT16;␊
typedef unsigned short␉␉UINT16;␊
typedef signed long␉␉␉INT32;␊
typedef unsigned long␉␉UINT32;␊
typedef unsigned char␉␉CHAR8;␊
typedef unsigned short␉␉CHAR16;␊
typedef unsigned short␉␉USHORT;␊
typedef unsigned char␉␉UCHAR;␊
typedef␉unsigned long␉␉ULONG;␊
␊
#pragma pack(1) /* BIOS data must use byte aligment */␊
␊
/* Define offset to location of ROM header. */␊
␊
#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER␉␉0x00000048L␊
#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE␉␉␉␉ 0x00000002L␊
␊
typedef struct _ATOM_COMMON_TABLE_HEADER␊
{␊
␉USHORT usStructureSize;␊
␉UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */␊
␉UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */␊
/*Image can't be updated, while Driver needs to carry the new table! */␊
} ATOM_COMMON_TABLE_HEADER;␊
␊
typedef struct _ATOM_ROM_HEADER␊
{␊
␉ATOM_COMMON_TABLE_HEADER␉␉sHeader;␊
␉UCHAR␉ uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, ␊
␉␉␉␉␉␉␉␉␉␉␉ + atombios should init it as "ATOM", don't change the position */␊
␉USHORT usBiosRuntimeSegmentAddress;␊
␉USHORT usProtectedModeInfoOffset;␊
␉USHORT usConfigFilenameOffset;␊
␉USHORT usCRC_BlockOffset;␊
␉USHORT usBIOS_BootupMessageOffset;␊
␉USHORT usInt10Offset;␊
␉USHORT usPciBusDevInitCode;␊
␉USHORT usIoBaseAddress;␊
␉USHORT usSubsystemVendorID;␊
␉USHORT usSubsystemID;␊
␉USHORT usPCI_InfoOffset; ␊
␉USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */␊
␉USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */␊
␉UCHAR ucExtendedFunctionCode;␊
␉UCHAR ucReserved;␊
} ATOM_ROM_HEADER;␊
␊
/****************************************************************************/␉␊
// Structure used in Data.mtb␊
/****************************************************************************/␉␊
typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES␊
{␊
␉USHORT UtilityPipeLine;␉ // Offest for the utility to get parser info,Don't change this position!␊
␉USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios ␊
␉USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios␊
␉USHORT StandardVESA_Timing; // Only used by Bios␊
␉USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4␊
␉USHORT DAC_Info; // Will be obsolete from R600␊
␉USHORT LVDS_Info; // Shared by various SW components,latest version 1.1 ␊
␉USHORT TMDS_Info; // Will be obsolete from R600␊
␉USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 ␊
␉USHORT SupportedDevicesInfo; // Will be obsolete from R600␊
␉USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 ␊
␉USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600␊
␉USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1␊
␉USHORT VESA_ToInternalModeLUT; // Only used by Bios␊
␉USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600␊
␉USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600␊
␉USHORT CompassionateData; // Will be obsolete from R600␊
␉USHORT SaveRestoreInfo; // Only used by Bios␊
␉USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info␊
␉USHORT OemInfo; // Defined and used by external SW, should be obsolete soon␊
␉USHORT XTMDS_Info; // Will be obsolete from R600␊
␉USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used␊
␉USHORT Object_Header; // Shared by various SW components,latest version 1.1␊
␉USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!!␊
␉USHORT MC_InitParameter; // Only used by command table␊
␉USHORT ASIC_VDDC_Info;␉␉␉␉␉␉// Will be obsolete from R600␊
␉USHORT ASIC_InternalSS_Info;␉␉␉// New tabel name from R600, used to be called "ASIC_MVDDC_Info"␊
␉USHORT TV_VideoMode;␉␉␉␉␉␉␉// Only used by command table␊
␉USHORT VRAM_Info;␉␉␉␉␉␉␉␉// Only used by command table, latest version 1.3␊
␉USHORT MemoryTrainingInfo;␉␉␉␉// Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1␊
␉USHORT IntegratedSystemInfo;␉␉␉// Shared by various SW components␊
␉USHORT ASIC_ProfilingInfo;␉␉␉␉// New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600␊
␉USHORT VoltageObjectInfo;␉␉␉␉// Shared by various SW components, latest version 1.1␊
␉USHORT␉␉␉␉PowerSourceInfo;␉␉␉␉␉// Shared by various SW components, latest versoin 1.1␊
} ATOM_MASTER_LIST_OF_DATA_TABLES;␊
␊
typedef struct _ATOM_MASTER_DATA_TABLE␊
{ ␊
␉ATOM_COMMON_TABLE_HEADER sHeader; ␊
␉ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables;␊
} ATOM_MASTER_DATA_TABLE;␊
␊
typedef union _ATOM_MODE_MISC_INFO_ACCESS␊
{ ␊
␉USHORT usAccess;␊
} ATOM_MODE_MISC_INFO_ACCESS;␊
␊
/****************************************************************************/␉␊
// Structure used in StandardVESA_TimingTable␊
// AnalogTV_InfoTable ␊
// ComponentVideoInfoTable␊
/****************************************************************************/␉␊
typedef struct _ATOM_MODE_TIMING␊
{␊
␉USHORT usCRTC_H_Total;␊
␉USHORT usCRTC_H_Disp;␊
␉USHORT usCRTC_H_SyncStart;␊
␉USHORT usCRTC_H_SyncWidth;␊
␉USHORT usCRTC_V_Total;␊
␉USHORT usCRTC_V_Disp;␊
␉USHORT usCRTC_V_SyncStart;␊
␉USHORT usCRTC_V_SyncWidth;␊
␉USHORT usPixelClock;␉␉␉␉␉ //in 10Khz unit␊
␉ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;␊
␉USHORT usCRTC_OverscanRight;␊
␉USHORT usCRTC_OverscanLeft;␊
␉USHORT usCRTC_OverscanBottom;␊
␉USHORT usCRTC_OverscanTop;␊
␉USHORT usReserve;␊
␉UCHAR ucInternalModeNumber;␊
␉UCHAR ucRefreshRate;␊
} ATOM_MODE_TIMING;␊
␊
typedef struct _ATOM_DTD_FORMAT␊
{␊
␉USHORT usPixClk;␊
␉USHORT usHActive;␊
␉USHORT usHBlanking_Time;␊
␉USHORT usVActive;␊
␉USHORT usVBlanking_Time;␉␉␉␊
␉USHORT usHSyncOffset;␊
␉USHORT usHSyncWidth;␊
␉USHORT usVSyncOffset;␊
␉USHORT usVSyncWidth;␊
␉USHORT usImageHSize;␊
␉USHORT usImageVSize;␊
␉UCHAR ucHBorder;␊
␉UCHAR ucVBorder;␊
␉ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;␊
␉UCHAR ucInternalModeNumber;␊
␉UCHAR ucRefreshRate;␊
} ATOM_DTD_FORMAT;␊
␊
typedef struct _ATOM_LVDS_INFO_V12␊
{␊
␉ATOM_COMMON_TABLE_HEADER sHeader; ␊
␉ATOM_DTD_FORMAT sLCDTiming;␊
␉USHORT usExtInfoTableOffset;␊
␉USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.␊
␉USHORT usOffDelayInMs;␊
␉UCHAR ucPowerSequenceDigOntoDEin10Ms;␊
␉UCHAR ucPowerSequenceDEtoBLOnin10Ms;␊
␉UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}␊
␉␉␉␉␉␉␉␉␉␉␉␉// Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}␊
␉ // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}␊
␉ // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}␊
␉UCHAR ucPanelDefaultRefreshRate;␊
␉UCHAR ucPanelIdentification;␊
␉UCHAR ucSS_Id;␊
␉USHORT usLCDVenderID;␊
␉USHORT usLCDProductID;␊
␉UCHAR ucLCDPanel_SpecialHandlingCap; ␊
␉UCHAR␉␉␉␉␉␉␉␉ucPanelInfoSize;␉␉␉␉␉// start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable␊
␉UCHAR ucReserved[2];␊
} ATOM_LVDS_INFO_V12;␊
␉␊
␉␊
typedef struct _ATOM_STANDARD_VESA_TIMING␊
{␊
␉ATOM_COMMON_TABLE_HEADER sHeader; ␊
␉char * ␉␉␉␉ aModeTimings; // 16 is not the real array number, just for initial allocation␊
} ATOM_STANDARD_VESA_TIMING;␊
␊
#endif
branches/meklort/i386/libsaio/Makefile
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␉smbios_patcher.o fake_efi.o ext2fs.o \␊
␉hpet.o spd.o usb.o pci_setup.o \␊
␉device_inject.o nvidia.o ati.o pci_root.o \␊
␉convert.o mem.o␊
␉convert.o mem.o edid.o resolution.o␊
␊
␊
SAIO_EXTERN_OBJS = console.o␊
branches/meklort/i386/libsaio/resolution.c
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/*␊
* resolution.h␊
* ␊
*␉NOTE: I don't beleive this code is production ready / should be in trunk␊
* Atleast, not in it's current state. ␊
*␊
* Created by Evan Lojewski on 3/4/10.␊
* Copyright 2009. All rights reserved.␊
*␊
*/␊
#ifndef _RESOLUTION_H_␊
#define _RESOLUTION_H_␊
␊
#include "libsaio.h"␊
#include "edid.h"␊
#include "resolution.h"␊
␊
␊
void patchVideoBios()␊
{␉␉␊
␉UInt32 x = 0, y = 0, bp = 0;␊
␉␊
␉getResolution(&x, &y, &bp);␊
␉␊
␉␊
␉if (x != 0 &&␊
␉␉y != 0 && ␊
␉␉bp != 0)␊
␉{␊
␉␉vbios_map * map;␊
␉␉␊
␉␉map = open_vbios(CT_UNKWN);␊
␉␉if(map)␊
␉␉{␊
␉␉␉unlock_vbios(map);␊
␉␉␉␊
␉␉␉set_mode(map, x, y, bp, 0, 0);␊
␉␉␉␊
␉␉␉relock_vbios(map);␊
␉␉␉␊
␉␉␉close_vbios(map);␊
␉␉}␊
␉}␉␉␊
␉␊
}␊
␊
␊
/* Copied from 915 resolution created by steve tomljenovic␊
*␊
* This code is based on the techniques used in :␊
*␊
* - 855patch. Many thanks to Christian Zietz (czietz gmx net)␊
* for demonstrating how to shadow the VBIOS into system RAM␊
* and then modify it.␊
*␊
* - 1280patch by Andrew Tipton (andrewtipton null li).␊
*␊
* - 855resolution by Alain Poirier␊
*␊
* This source code is into the public domain.␊
*/␊
␊
/**␊
**␊
**/␊
␊
#define CONFIG_MECH_ONE_ADDR␉0xCF8␊
#define CONFIG_MECH_ONE_DATA␉0xCFC␊
␊
int freqs[] = { 60, 75, 85 };␊
␊
UInt32 get_chipset_id(void)␊
{␊
␉outl(CONFIG_MECH_ONE_ADDR, 0x80000000);␊
␉return inl(CONFIG_MECH_ONE_DATA);␊
}␊
␊
chipset_type get_chipset(UInt32 id)␊
{␊
␉chipset_type type;␊
␉␉␊
␉switch (id) {␊
␉␉case 0x35758086:␊
␉␉␉type = CT_830;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0x25608086:␊
␉␉␉type = CT_845G;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0x35808086:␊
␉␉␉type = CT_855GM;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0x25708086:␊
␉␉␉type = CT_865G;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0x25808086:␊
␉␉␉type = CT_915G;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0x25908086:␊
␉␉␉type = CT_915GM;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0x27708086:␊
␉␉␉type = CT_945G;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0x27a08086:␊
␉␉␉type = CT_945GM;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0x27ac8086:␊
␉␉␉type = CT_945GME;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0x29708086:␊
␉␉␉type = CT_946GZ;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0x27748086:␊
␉␉␉type = CT_955X;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0x277c8086:␊
␉␉␉type = CT_975X;␊
␉␉␉break;␊
␊
␉␉case 0x29a08086:␊
␉␉␉type = CT_G965;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0x29908086:␊
␉␉␉type = CT_Q965;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0x81008086:␊
␉␉␉type = CT_500;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0x2e108086:␊
␉␉case 0X2e908086:␊
␉␉␉type = CT_B43;␊
␉␉␉break;␊
␊
␉␉case 0x2e208086:␊
␉␉␉type = CT_P45;␊
␉␉␉break;␊
␊
␉␉case 0x2e308086:␊
␉␉␉type = CT_G41;␊
␉␉␉break;␊
␉␉␉␉␉␊
␉␉case 0x29c08086:␊
␉␉␉type = CT_G31;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0x29208086:␊
␉␉␉type = CT_G45;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0xA0108086:␊
␉␉␉type = CT_3150;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0x2a008086:␊
␉␉␉type = CT_965GM;␊
␉␉␉break;␊
␉␉␉␊
␉␉case 0x29e08086:␊
␉␉␉type = CT_X48;␊
␉␉␉break;␉␉␉␊
␉␉␉␉␊
␉␉case 0x2a408086:␊
␉␉␉type = CT_GM45;␊
␉␉␉break;␊
␉␉␉␊
␉␉␉␊
␉␉default:␊
␉␉␉if((id & 0x0000FFFF) == 0x00008086) // Intel chipset␊
␉␉␉{␊
␉␉␉␉//printf("Unknown chipset 0x%llX, please email id to meklort@gmail.com", id);␊
␉␉␉␉//getc();␊
␉␉␉␉type = CT_UNKWN_INTEL;␊
␊
␉␉␉}␊
␉␉␉type = CT_UNKWN;␊
␉␉␉break;␊
␉}␊
␉return type;␊
}␊
␊
vbios_resolution_type1 * map_type1_resolution(vbios_map * map, UInt16 res)␊
{␊
␉vbios_resolution_type1 * ptr = ((vbios_resolution_type1*)(map->bios_ptr + res)); ␊
␉return ptr;␊
}␊
␊
vbios_resolution_type2 * map_type2_resolution(vbios_map * map, UInt16 res)␊
{␊
␉vbios_resolution_type2 * ptr = ((vbios_resolution_type2*)(map->bios_ptr + res)); ␊
␉return ptr;␊
}␊
␊
vbios_resolution_type3 * map_type3_resolution(vbios_map * map, UInt16 res)␊
{␊
␉vbios_resolution_type3 * ptr = ((vbios_resolution_type3*)(map->bios_ptr + res)); ␊
␉return ptr;␊
}␊
␊
char detect_bios_type(vbios_map * map, char modeline, int entry_size)␊
{␊
␉UInt32 i;␊
␉UInt16 r1, r2;␊
␉␊
␉r1 = r2 = 32000;␊
␉␊
␉for (i=0; i < map->mode_table_size; i++)␊
␉{␊
␉␉if (map->mode_table[i].resolution <= r1)␊
␉␉{␊
␉␉␉r1 = map->mode_table[i].resolution;␊
␉␉}␊
␉␉else␊
␉␉{␊
␉␉␉if (map->mode_table[i].resolution <= r2)␊
␉␉␉{␊
␉␉␉␉r2 = map->mode_table[i].resolution;␊
␉␉␉}␊
␉␉}␊
␉␉␊
␉␉/*printf("r1 = %d r2 = %d\n", r1, r2);*/␊
␉}␊
␉␊
␉return (r2-r1-6) % entry_size == 0;␊
}␊
␊
void close_vbios(vbios_map * map);␊
␊
char detect_ati_bios_type(vbios_map * map)␊
{␉␊
␉return map->mode_table_size % sizeof(ATOM_MODE_TIMING) == 0;␊
}␊
␊
␊
vbios_map * open_vbios(chipset_type forced_chipset)␊
{␊
␉UInt32 z;␊
␉vbios_map * map = malloc(sizeof(vbios_map));␊
␉for(z=0; z<sizeof(vbios_map); z++) ((char*)map)[z]=0;␊
␉/*␊
␉ * Determine chipset␊
␉ */␊
␉␊
␉if (forced_chipset == CT_UNKWN)␊
␉{␊
␉␉map->chipset_id = get_chipset_id();␊
␉␉map->chipset = get_chipset(map->chipset_id);␊
␉}␊
␉else if (forced_chipset != CT_UNKWN)␊
␉{␊
␉␉map->chipset = forced_chipset;␊
␉}␊
␉␊
␉␊
␉if (map->chipset == CT_UNKWN)␊
␉{␊
␉␉//verbose("Unknown chipset type.\n");␊
␉␉//verbose("915resolution only works with Intel 800/900 series graphic chipsets.\n");␊
␉␉//verbose("Chipset Id: %x\n", map->chipset_id);␊
␉␉close_vbios(map);␊
␉␉return 0;␊
␉}␊
␉␊
␉␊
␉/*␊
␉ * Map the video bios to memory␊
␉ */␊
␉map->bios_ptr=(char*)VBIOS_START;␊
␉␊
␉/*␊
␉ * check if we have ATI Radeon␊
␉ */␊
␉map->ati_tables.base = map->bios_ptr;␊
␉map->ati_tables.AtomRomHeader = (ATOM_ROM_HEADER *) (map->bios_ptr + *(unsigned short *) (map->bios_ptr + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)); ␊
␉if (strcmp ((char *) map->ati_tables.AtomRomHeader->uaFirmWareSignature, "ATOM") == 0)␊
␉{␊
␉␉// ATI Radeon Card␊
␉␉map->bios = BT_ATI_1;␊
␉␉␊
␉␉map->ati_tables.MasterDataTables = (unsigned short *) &((ATOM_MASTER_DATA_TABLE *) (map->bios_ptr + map->ati_tables.AtomRomHeader->usMasterDataTableOffset))->ListOfDataTables;␊
␉␉unsigned short std_vesa_offset = (unsigned short) ((ATOM_MASTER_LIST_OF_DATA_TABLES *)map->ati_tables.MasterDataTables)->StandardVESA_Timing;␊
␉␉ATOM_STANDARD_VESA_TIMING * std_vesa = (ATOM_STANDARD_VESA_TIMING *) (map->bios_ptr + std_vesa_offset);␊
␉␉␊
␉␉map->ati_mode_table = (char *) &std_vesa->aModeTimings;␊
␉␉if (map->ati_mode_table == 0)␊
␉␉{␊
␉␉␉printf("Unable to locate the mode table.\n");␊
␉␉␉printf("Please run the program 'dump_bios' as root and\n");␊
␉␉␉printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊
␉␉␉printf("Chipset: %d\n", map->chipset);␊
␉␉␉close_vbios(map);␊
␉␉␉return 0;␊
␉␉}␊
␉␉map->mode_table_size = std_vesa->sHeader.usStructureSize - sizeof(ATOM_COMMON_TABLE_HEADER);␊
␉␉␊
␉␉if (!detect_ati_bios_type(map)) map->bios = BT_ATI_2;␊
␉␉␊
␉}␊
␉else {␊
␉␉␊
␉␉/*␊
␉␉ * check if we have NVIDIA␊
␉␉ */␊
␊
␉␉int i = 0;␊
␉␉while (i < 512)␊
␉␉{ // we don't need to look through the whole bios, just the firs 512 bytes␊
␉␉␉if ((␉map->bios_ptr[i] == 'N') ␊
␉␉␉␉&& (map->bios_ptr[i+1] == 'V') ␊
␉␉␉␉&& (map->bios_ptr[i+2] == 'I') ␊
␉␉␉␉&& (map->bios_ptr[i+3] == 'D')) ␊
␉␉␉{␊
␉␉␉␉map->bios = BT_NVDA;␊
␉␉␉␉unsigned short nv_data_table_offset = 0;␊
␉␉␉␉unsigned short * nv_data_table;␊
␉␉␉␉NV_VESA_TABLE * std_vesa;␊
␉␉␉␉␊
␉␉␉␉int i = 0;␊
␉␉␉␉␊
␉␉␉␉while (i < 0x300)␊
␉␉␉␉{ //We don't need to look for the table in the whole bios, the 768 first bytes only␊
␉␉␉␉␉if ((␉map->bios_ptr[i] == 0x44) ␊
␉␉␉␉␉␉&& (map->bios_ptr[i+1] == 0x01) ␊
␉␉␉␉␉␉&& (map->bios_ptr[i+2] == 0x04) ␊
␉␉␉␉␉␉&& (map->bios_ptr[i+3] == 0x00))␊
␉␉␉␉␉{␊
␉␉␉␉␉␉nv_data_table_offset = (unsigned short) (map->bios_ptr[i+4] | (map->bios_ptr[i+5] << 8));␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉}␊
␉␉␉␉␉i++;␊
␉␉␉␉}␊
␉␉␉␉␊
␉␉␉␉nv_data_table = (unsigned short *) (map->bios_ptr + (nv_data_table_offset + OFFSET_TO_VESA_TABLE_INDEX));␊
␉␉␉␉std_vesa = (NV_VESA_TABLE *) (map->bios_ptr + *nv_data_table);␊
␉␉␉␉␊
␉␉␉␉map->nv_mode_table = (char *) std_vesa->sModelines;␊
␉␉␉␉if (map->nv_mode_table == 0)␊
␉␉␉␉{␊
␉␉␉␉␉printf("Unable to locate the mode table.\n");␊
␉␉␉␉␉printf("Please run the program 'dump_bios' as root and\n");␊
␉␉␉␉␉printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊
␉␉␉␉␉printf("Chipset: %s\n", map->chipset);␊
␉␉␉␉␉close_vbios(map);␊
␉␉␉␉␉return 0;␊
␉␉␉␉}␊
␉␉␉␉map->mode_table_size = std_vesa->sHeader.usTable_Size;␊
␉␉␉␉␊
␉␉␉␉break;␊
␉␉␉}␊
␉␉␉i++;␊
␉␉}␊
␉}␊
␉␊
␉␊
␉/*␊
␉ * check if we have Intel␊
␉ */␊
␉␊
␉/*if (map->chipset == CT_UNKWN && memmem(map->bios_ptr, VBIOS_SIZE, INTEL_SIGNATURE, strlen(INTEL_SIGNATURE))) {␊
␉ printf( "Intel chipset detected. However, 915resolution was unable to determine the chipset type.\n");␊
␉ ␊
␉ printf("Chipset Id: %x\n", map->chipset_id);␊
␉ ␊
␉ printf("Please report this problem to stomljen@yahoo.com\n");␊
␉ ␊
␉ close_vbios(map);␊
␉ return 0;␊
␉ }*/␊
␉␊
␉/*␊
␉ * check for others␊
␉ */␊
␉␊
␊
␉␊
␉/*␊
␉ * Figure out where the mode table is ␊
␉ */␊
␉if ((map->bios != BT_ATI_1) && (map->bios != BT_NVDA)) ␊
␉{␊
␉␉char* p = map->bios_ptr + 16;␊
␉␉char* limit = map->bios_ptr + VBIOS_SIZE - (3 * sizeof(vbios_mode));␊
␉␉␊
␉␉while (p < limit && map->mode_table == 0)␊
␉␉{␊
␉␉␉vbios_mode * mode_ptr = (vbios_mode *) p;␊
␉␉␉␊
␉␉␉if (((mode_ptr[0].mode & 0xf0) == 0x30) && ((mode_ptr[1].mode & 0xf0) == 0x30) &&␊
␉␉␉␉((mode_ptr[2].mode & 0xf0) == 0x30) && ((mode_ptr[3].mode & 0xf0) == 0x30))␊
␉␉␉{␊
␉␉␉␉map->mode_table = mode_ptr;␊
␉␉␉}␊
␉␉␉␊
␉␉␉p++;␊
␉␉}␊
␉␉␊
␉␉if (map->mode_table == 0) ␊
␉␉{␊
␉␉␉close_vbios(map);␊
␉␉␉return 0;␊
␉␉}␊
␉}␊
␉␊
␉␊
␉/*␊
␉ * Determine size of mode table␊
␉ */␊
␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊
␉{␊
␉␉vbios_mode * mode_ptr = map->mode_table;␊
␉␉␊
␉␉while (mode_ptr->mode != 0xff)␊
␉␉{␊
␉␉␉map->mode_table_size++;␊
␉␉␉mode_ptr++;␊
␉␉}␊
␉}␊
␉␊
␉/*␊
␉ * Figure out what type of bios we have␊
␉ * order of detection is important␊
␉ */␊
␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊
␉{␊
␉␉if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type3)))␊
␉␉{␊
␉␉␉map->bios = BT_3;␊
␉␉}␊
␉␉else if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type2)))␊
␉␉{␊
␉␉␉map->bios = BT_2;␊
␉␉}␊
␉␉else if (detect_bios_type(map, FALSE, sizeof(vbios_resolution_type1)))␊
␉␉{␊
␉␉␉map->bios = BT_1;␊
␉␉}␊
␉␉else {␊
␉␉␉return 0;␊
␉␉}␊
␉}␊
␉␊
␉return map;␊
}␊
␊
void close_vbios(vbios_map * map)␊
{␊
␉free(map);␊
}␊
␊
void unlock_vbios(vbios_map * map)␊
{␊
␉␊
␉map->unlocked = TRUE;␊
␊
␉switch (map->chipset) {␊
␉␉case CT_UNKWN:␊
␉␉␉break;␊
␉␉case CT_830:␊
␉␉case CT_855GM:␊
␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊
␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 2);␊
␉␉␉␊
␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊
␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊
␉␉␉break;␊
␉␉case CT_845G:␊
␉␉case CT_865G:␊
␉␉case CT_915G:␊
␉␉case CT_915GM:␊
␉␉case CT_945G:␊
␉␉case CT_945GM:␊
␉␉case CT_945GME:␊
␉␉case CT_946GZ:␊
␉␉case CT_G965:␊
␉␉case CT_Q965:␊
␉␉case CT_965GM:␊
␉␉case CT_975X:␊
␉␉case CT_P35:␊
␉␉case CT_955X:␊
␉␉case CT_X48:␊
␉␉case CT_B43:␊
␉␉case CT_Q45:␊
␉␉case CT_P45:␊
␉␉case CT_GM45:␊
␉␉case CT_G45:␊
␉␉case CT_G41:␊
␉␉case CT_G31:␊
␉␉case CT_500:␊
␉␉case CT_3150:␊
␉␉case CT_UNKWN_INTEL:␉// Assume newer intel chipset is the same as before␊
␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊
␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);␊
␉␉␉map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);␊
␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊
␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, 0x33);␊
␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊
␉␉␉break;␊
␉}␊
␉␊
#if DEBUG␊
␉{␊
␉␉UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊
␉␉verbose("unlock PAM: (0x%08x)\n", t);␊
␉}␊
#endif␊
}␊
␊
void relock_vbios(vbios_map * map)␊
{␊
␉␊
␉map->unlocked = FALSE;␊
␉␊
␉switch (map->chipset)␊
␉{␊
␉␉case CT_UNKWN:␊
␉␉␉break;␊
␉␉case CT_830:␊
␉␉case CT_855GM:␊
␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊
␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b1);␊
␉␉␉break;␊
␉␉case CT_845G:␊
␉␉case CT_865G:␊
␉␉case CT_915G:␊
␉␉case CT_915GM:␊
␉␉case CT_945G:␊
␉␉case CT_945GM:␊
␉␉case CT_945GME:␊
␉␉case CT_946GZ:␊
␉␉case CT_G965:␊
␉␉case CT_955X:␊
␉␉case CT_G45:␊
␉␉case CT_Q965:␊
␉␉case CT_965GM:␊
␉␉case CT_975X:␊
␉␉case CT_P35:␊
␉␉case CT_X48:␊
␉␉case CT_B43:␊
␉␉case CT_Q45:␊
␉␉case CT_P45:␊
␉␉case CT_GM45:␊
␉␉case CT_G41:␊
␉␉case CT_G31:␊
␉␉case CT_500:␊
␉␉case CT_3150:␊
␉␉case CT_UNKWN_INTEL:␊
␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊
␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, map->b1);␊
␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b2);␊
␉␉␉break;␊
␉}␊
␉␊
#if DEBUG␊
␉{␊
UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊
␉␉verbose("relock PAM: (0x%08x)\n", t);␊
␉}␊
#endif␊
}␊
␊
␊
int getMode(edid_mode *mode)␊
{␊
␉char* edidInfo = readEDID();␊
␉␉␉␊
␉if(!edidInfo) return 1;␊
␉␉␊
␉mode->pixel_clock = (edidInfo[55] << 8) | edidInfo[54];␊
␉mode->h_active = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);␊
␉mode->h_blanking = ((edidInfo[58] & 0x0F) << 8) | edidInfo[57];␊
␉mode->v_active = edidInfo[59] | ((edidInfo[61] & 0xF0) << 4);␊
␉mode->v_blanking = ((edidInfo[61] & 0x0F) << 8) | edidInfo[60];␊
␉mode->h_sync_offset = ((edidInfo[65] & 0xC0) >> 2) | edidInfo[62];␊
␉mode->h_sync_width = (edidInfo[65] & 0x30) | edidInfo[63];␊
␉mode->v_sync_offset = (edidInfo[65] & 0x0C) | ((edidInfo[64] & 0x0C) >> 2);␊
␉mode->v_sync_width = ((edidInfo[65] & 0x3) << 2) | (edidInfo[64] & 0x03);␊
␉␉␊
␉␉␊
␉free( edidInfo );␊
␉␉␊
␉if(!mode->h_active) return 1;␊
␉␊
␉return 0;␊
␉␉␊
}␊
␊
␊
static void gtf_timings(UInt32 x, UInt32 y, UInt32 freq,␊
␉␉␉␉␉␉unsigned long *clock,␊
␉␉␉␉␉␉UInt16 *hsyncstart, UInt16 *hsyncend, UInt16 *hblank,␊
␉␉␉␉␉␉UInt16 *vsyncstart, UInt16 *vsyncend, UInt16 *vblank)␊
{␊
␉UInt32 hbl, vbl, vfreq;␊
␉␊
␉vbl = y + (y+1)/(20000.0/(11*freq) - 1) + 1.5;␊
␉vfreq = vbl * freq;␊
␉hbl = 16 * (int)(x * (30.0 - 300000.0 / vfreq) /␊
␉␉␉␉␉ + (70.0 + 300000.0 / vfreq) / 16.0 + 0.5);␊
␉␊
␉*vsyncstart = y;␊
␉*vsyncend = y + 3;␊
␉*vblank = vbl - 1;␊
␉*hsyncstart = x + hbl / 2 - (x + hbl + 50) / 100 * 8 - 1;␊
␉*hsyncend = x + hbl / 2 - 1;␊
␉*hblank = x + hbl - 1;␊
␉*clock = (x + hbl) * vfreq / 1000;␊
}␊
␊
void set_mode(vbios_map * map, /*UInt32 mode,*/ UInt32 x, UInt32 y, UInt32 bp, UInt32 htotal, UInt32 vtotal) {␊
␉UInt32 xprev, yprev;␊
␉UInt32 i = 0, j;␊
␉// patch first available mode␊
␉␊
␉//␉for (i=0; i < map->mode_table_size; i++) {␊
␉//␉␉if (map->mode_table[0].mode == mode) {␊
␉switch(map->bios) {␊
␉␉case BT_1:␊
␉␉{␊
␉␉␉vbios_resolution_type1 * res = map_type1_resolution(map, map->mode_table[i].resolution);␊
␉␉␉␊
␉␉␉if (bp) {␊
␉␉␉␉map->mode_table[i].bits_per_pixel = bp;␊
␉␉␉}␊
␉␉␉␊
␉␉␉res->x2 = (htotal?(((htotal-x) >> 8) & 0x0f) : (res->x2 & 0x0f)) | ((x >> 4) & 0xf0);␊
␉␉␉res->x1 = (x & 0xff);␊
␉␉␉␊
␉␉␉res->y2 = (vtotal?(((vtotal-y) >> 8) & 0x0f) : (res->y2 & 0x0f)) | ((y >> 4) & 0xf0);␊
␉␉␉res->y1 = (y & 0xff);␊
␉␉␉if (htotal)␊
␉␉␉␉res->x_total = ((htotal-x) & 0xff);␊
␉␉␉␊
␉␉␉if (vtotal)␊
␉␉␉␉res->y_total = ((vtotal-y) & 0xff);␊
␉␉␉␊
␉␉␉break;␊
␉␉}␊
␉␉case BT_2:␊
␉␉{␊
␉␉␉vbios_resolution_type2 * res = map_type2_resolution(map, map->mode_table[i].resolution);␊
␉␉␉␊
␉␉␉res->xchars = x / 8;␊
␉␉␉res->ychars = y / 16 - 1;␊
␉␉␉xprev = res->modelines[0].x1;␊
␉␉␉yprev = res->modelines[0].y1;␊
␉␉␉␊
␉␉␉for(j=0; j < 3; j++) {␊
␉␉␉␉vbios_modeline_type2 * modeline = &res->modelines[j];␊
␉␉␉␉␊
␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev) {␊
␉␉␉␉␉modeline->x1 = modeline->x2 = x-1;␊
␉␉␉␉␉modeline->y1 = modeline->y2 = y-1;␊
␉␉␉␉␉␊
␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊
␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊
␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊
␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊
␉␉␉␉␉␊
␉␉␉␉␉if (htotal)␊
␉␉␉␉␉␉modeline->htotal = htotal;␊
␉␉␉␉␉else␊
␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊
␉␉␉␉␉␊
␉␉␉␉␉if (vtotal)␊
␉␉␉␉␉␉modeline->vtotal = vtotal;␊
␉␉␉␉␉else␊
␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊
␉␉␉␉}␊
␉␉␉}␊
␉␉␉break;␊
␉␉}␊
␉␉case BT_3:␊
␉␉{␊
␉␉␉vbios_resolution_type3 * res = map_type3_resolution(map, map->mode_table[i].resolution);␊
␉␉␉␊
␉␉␉xprev = res->modelines[0].x1;␊
␉␉␉yprev = res->modelines[0].y1;␊
␉␉␉␊
␉␉␉for (j=0; j < 3; j++) {␊
␉␉␉␉vbios_modeline_type3 * modeline = &res->modelines[j];␊
␉␉␉␉␊
␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev) {␊
␉␉␉␉␉modeline->x1 = modeline->x2 = x-1;␊
␉␉␉␉␉modeline->y1 = modeline->y2 = y-1;␊
␉␉␉␉␉␊
␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊
␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊
␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊
␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊
␉␉␉␉␉if (htotal)␊
␉␉␉␉␉␉modeline->htotal = htotal;␊
␉␉␉␉␉else␊
␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊
␉␉␉␉␉if (vtotal)␊
␉␉␉␉␉␉modeline->vtotal = vtotal;␊
␉␉␉␉␉else␊
␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊
␉␉␉␉␉␊
␉␉␉␉␉modeline->timing_h = y-1;␊
␉␉␉␉␉modeline->timing_v = x-1;␊
␉␉␉␉}␊
␉␉␉}␊
␉␉␉break;␊
␉␉}␊
␉␉case BT_ATI_1:␊
␉␉{␊
␉␉␉edid_mode mode;␊
␉␉␉␉␊
␉␉␉ATOM_MODE_TIMING *mode_timing = (ATOM_MODE_TIMING *) map->ati_mode_table;␊
␊
␉␉␉//if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {␊
␉␉␉if (!getMode(&mode)) {␊
␉␉␉␉mode_timing->usCRTC_H_Total = mode.h_active + mode.h_blanking;␊
␉␉␉␉mode_timing->usCRTC_H_Disp = mode.h_active;␊
␉␉␉␉mode_timing->usCRTC_H_SyncStart = mode.h_active + mode.h_sync_offset;␊
␉␉␉␉mode_timing->usCRTC_H_SyncWidth = mode.h_sync_width;␊
␉␉␉␉␉␊
␉␉␉␉mode_timing->usCRTC_V_Total = mode.v_active + mode.v_blanking;␊
␉␉␉␉mode_timing->usCRTC_V_Disp = mode.v_active;␊
␉␉␉␉mode_timing->usCRTC_V_SyncStart = mode.v_active + mode.v_sync_offset;␊
␉␉␉␉mode_timing->usCRTC_V_SyncWidth = mode.v_sync_width;␊
␊
␉␉␉␉mode_timing->usPixelClock = mode.pixel_clock;␊
␉␉␉}␊
␉␉␉/*else␊
␉␉␉{␊
␉␉␉␉vbios_modeline_type2 modeline;␊
␊
␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊
␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊
␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊
␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊
␊
␉␉␉␉mode_timing->usCRTC_H_Total = x + modeline.hblank;␊
␉␉␉␉mode_timing->usCRTC_H_Disp = x;␊
␉␉␉␉mode_timing->usCRTC_H_SyncStart = modeline.hsyncstart;␊
␉␉␉␉mode_timing->usCRTC_H_SyncWidth = modeline.hsyncend - modeline.hsyncstart;␊
␊
␉␉␉␉mode_timing->usCRTC_V_Total = y + modeline.vblank;␊
␉␉␉␉mode_timing->usCRTC_V_Disp = y;␊
␉␉␉␉mode_timing->usCRTC_V_SyncStart = modeline.vsyncstart;␊
␉␉␉␉mode_timing->usCRTC_V_SyncWidth = modeline.vsyncend - modeline.vsyncstart;␊
␉␉␉␉␉␉␉␉␉␉␉␉␊
␉␉␉␉mode_timing->usPixelClock = modeline.clock;␊
␉␉␉ }*/␊
␉␊
␉␉␉break;␊
␉␉}␊
␉␉case BT_ATI_2:␊
␉␉{␊
␉␉␉edid_mode mode;␊
␉␉␉␉␉␉␊
␉␉␉ATOM_DTD_FORMAT *mode_timing = (ATOM_DTD_FORMAT *) map->ati_mode_table;␊
␉␉␉␊
␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊
␉␉␉if (!getMode(&mode)) {␊
␉␉␉␉mode_timing->usHBlanking_Time = mode.h_blanking;␊
␉␉␉␉mode_timing->usHActive = mode.h_active;␊
␉␉␉␉mode_timing->usHSyncOffset = mode.h_sync_offset;␊
␉␉␉␉mode_timing->usHSyncWidth = mode.h_sync_width;␊
␉␉␉␉␉␉␉␉␉␉␊
␉␉␉␉mode_timing->usVBlanking_Time = mode.v_blanking;␊
␉␉␉␉mode_timing->usVActive = mode.v_active;␊
␉␉␉␉mode_timing->usVSyncOffset = mode.v_sync_offset;␊
␉␉␉␉mode_timing->usVSyncWidth = mode.v_sync_width;␊
␉␉␉␉␉␉␉␉␉␉␊
␉␉␉␉mode_timing->usPixClk = mode.pixel_clock;␊
␉␉␉}␊
␉␉␉/*else␊
␉␉␉{␊
␉␉␉␉vbios_modeline_type2 modeline;␊
␉␉␉␊
␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊
␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊
␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊
␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊
␉␉␉␉␉␉␉␉␉␉␉␊
␉␉␉␉mode_timing->usHBlanking_Time = modeline.hblank;␊
␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHActive = x;␊
␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHSyncOffset = modeline.hsyncstart - x;␊
␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊
␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉␊
␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVBlanking_Time = modeline.vblank;␊
␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVActive = y;␊
␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVSyncOffset = modeline.vsyncstart - y;␊
␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊
␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉␊
␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usPixClk = modeline.clock;␊
␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉}*/␊
␉␉␉␉␊
␉␉␉␊
␉␉␉break;␊
␉␉}␊
␉␉case BT_NVDA:␊
␉␉{␊
␉␉␉edid_mode mode;␊
␉␉␉␊
␉␉␉NV_MODELINE *mode_timing = (NV_MODELINE *) map->nv_mode_table;␊
␉␉␉␊
␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊
␉␉␉if (!getMode(&mode)) {␊
␉␉␉␉mode_timing[i].usH_Total = mode.h_active + mode.h_blanking;␊
␉␉␉␉mode_timing[i].usH_Active = mode.h_active;␊
␉␉␉␉mode_timing[i].usH_SyncStart = mode.h_active + mode.h_sync_offset;␊
␉␉␉␉mode_timing[i].usH_SyncEnd = mode.h_active + mode.h_sync_offset + mode.h_sync_width;␊
␉␉␉␉␊
␉␉␉␉mode_timing[i].usV_Total = mode.v_active + mode.v_blanking;␊
␉␉␉␉mode_timing[i].usV_Active = mode.v_active;␊
␉␉␉␉mode_timing[i].usV_SyncStart = mode.v_active + mode.v_sync_offset;␊
␉␉␉␉mode_timing[i].usV_SyncEnd = mode.v_active + mode.v_sync_offset + mode.v_sync_width;␊
␉␉␉␉␊
␉␉␉␉mode_timing[i].usPixel_Clock = mode.pixel_clock;␊
␉␉␉}␊
␉␉␉/*else␊
␉␉␉ {␊
␉␉␉ vbios_modeline_type2 modeline;␊
␉␉␉ ␊
␉␉␉ cvt_timings(x, y, freqs[0], &modeline.clock,␊
␉␉␉ &modeline.hsyncstart, &modeline.hsyncend,␊
␉␉␉ &modeline.hblank, &modeline.vsyncstart,␊
␉␉␉ &modeline.vsyncend, &modeline.vblank, 0);␊
␉␉␉ ␊
␉␉␉ mode_timing[i].usH_Total = x + modeline.hblank - 1;␊
␉␉␉ mode_timing[i].usH_Active = x;␊
␉␉␉ mode_timing[i].usH_SyncStart = modeline.hsyncstart - 1;␊
␉␉␉ mode_timing[i].usH_SyncEnd = modeline.hsyncend - 1;␊
␉␉␉ ␊
␉␉␉ mode_timing[i].usV_Total = y + modeline.vblank - 1;␊
␉␉␉ mode_timing[i].usV_Active = y;␊
␉␉␉ mode_timing[i].usV_SyncStart = modeline.vsyncstart - 1;␊
␉␉␉ mode_timing[i].usV_SyncEnd = modeline.vsyncend - 1;␊
␉␉␉ ␊
␉␉␉ mode_timing[i].usPixel_Clock = modeline.clock;␊
␉␉␉ }*/␊
␉␉␉break;␊
␉␉}␊
␉␉case BT_UNKWN:␊
␉␉{␊
␉␉␉break;␊
␉␉}␊
␉}␊
␉//␉␉}␊
␉//␉}␊
}␊
␊
#endif // _RESOLUTION_H_
branches/meklort/i386/libsaio/resolution.h
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/*␊
* resolution.h␊
* ␊
*␊
* Created by Evan Lojewski on 3/4/10.␊
* Copyright 2009. All rights reserved.␊
*␊
*/␊
␊
#include "shortatombios.h"␊
#include "edid.h"␊
␊
#ifndef __RESOLUTION_H␊
#define __RESOLUTION_H␊
␊
typedef struct _edid_mode {␊
␉unsigned short pixel_clock;␊
␉unsigned short h_active;␊
␉unsigned short h_blanking;␊
␉unsigned short v_active;␊
␉unsigned short v_blanking;␊
␉unsigned short h_sync_offset;␊
␉unsigned short h_sync_width;␊
␉unsigned short v_sync_offset;␊
␉unsigned short v_sync_width;␊
} edid_mode;␊
␊
␊
␊
void patchVideoBios();␊
␊
␊
␊
/* Copied from 915 resolution created by steve tomljenovic␊
*␊
* This code is based on the techniques used in :␊
*␊
* - 855patch. Many thanks to Christian Zietz (czietz gmx net)␊
* for demonstrating how to shadow the VBIOS into system RAM␊
* and then modify it.␊
*␊
* - 1280patch by Andrew Tipton (andrewtipton null li).␊
*␊
* - 855resolution by Alain Poirier␊
*␊
* This source code is into the public domain.␊
*/␊
␊
#define VBIOS_START 0xc0000␊
#define VBIOS_SIZE 0x10000␊
␊
#define FALSE 0␊
#define TRUE 1␊
␊
#define MODE_TABLE_OFFSET_845G 617␊
␊
␊
#define ATI_SIGNATURE1 "ATI MOBILITY RADEON"␊
#define ATI_SIGNATURE2 "ATI Technologies Inc"␊
#define NVIDIA_SIGNATURE "NVIDIA Corp"␊
#define INTEL_SIGNATURE "Intel Corp"␊
␊
␊
␊
/*␊
* NVidia Defines and structures␊
*/␊
␊
#define OFFSET_TO_VESA_TABLE_INDEX 2␊
␊
typedef struct {␊
␉unsigned char␉ucTable_Major;␊
␉unsigned char␉ucTable_Minor;␊
␉unsigned char␉ucTable_Rev;␊
␉unsigned short␉usTable_Size;␊
} NV_COMMON_TABLE_HEADER;␊
␊
typedef struct {␊
␉short reserved1;␊
␉short reserved2;␊
␉short reserved3;␊
} NV_RESERVED;␊
␊
typedef struct {␊
␉unsigned short␉usPixel_Clock;␊
␉unsigned short␉usH_Active;␊
␉NV_RESERVED␉␉reserved1;␊
␉unsigned short␉usH_SyncStart;␊
␉unsigned short␉usH_SyncEnd;␊
␉unsigned short␉usH_Total;␊
␉unsigned short␉usV_Active;␊
␉NV_RESERVED␉␉reserved2;␊
␉unsigned short␉usV_SyncStart;␊
␉unsigned short␉usV_SyncEnd;␊
␉unsigned short␉usV_Total;␊
␉unsigned short␉reserved3;␊
} NV_MODELINE;␊
␊
typedef struct {␊
␉NV_COMMON_TABLE_HEADER␉sHeader;␊
␉NV_MODELINE␉*␉␉␉sModelines;␊
} NV_VESA_TABLE;␊
␊
/*---*/␊
␊
␊
typedef enum {␊
␉CT_UNKWN, CT_UNKWN_INTEL, CT_830, CT_845G, CT_855GM, CT_865G, ␊
␉CT_915G, CT_915GM, CT_945G, CT_945GM, CT_945GME, CT_946GZ, ␊
␉CT_955X, CT_G965, CT_Q965, CT_965GM, CT_975X, ␊
␉CT_P35, CT_X48, CT_B43, CT_Q45, CT_P45,␊
␉CT_GM45, CT_G41, CT_G31, CT_G45, CT_500, CT_3150␊
} chipset_type;␊
␊
␊
␊
typedef enum {␊
␉BT_UNKWN, BT_1, BT_2, BT_3, BT_ATI_1, BT_ATI_2, BT_NVDA␊
} bios_type;␊
␊
␊
typedef struct {␊
␉char *base;␊
␉ATOM_ROM_HEADER *AtomRomHeader;␊
␉unsigned short *MasterCommandTables;␊
␉unsigned short *MasterDataTables;␊
} bios_tables_t;␊
␊
typedef struct {␊
␉UInt8 mode;␊
␉UInt8 bits_per_pixel;␊
␉UInt16 resolution;␊
␉UInt8 unknown;␊
} __attribute__((packed)) vbios_mode;␊
␊
typedef struct {␊
␉UInt8 unknow1[2];␊
␉UInt8 x1;␊
␉UInt8 x_total;␊
␉UInt8 x2;␊
␉UInt8 y1;␊
␉UInt8 y_total;␊
␉UInt8 y2;␊
} __attribute__((packed)) vbios_resolution_type1;␊
␊
typedef struct {␊
␉unsigned long clock;␊
␉␊
␉UInt16 x1;␊
␉UInt16 htotal;␊
␉UInt16 x2;␊
␉UInt16 hblank;␊
␉UInt16 hsyncstart;␊
␉UInt16 hsyncend;␊
␉UInt16 y1;␊
UInt16 vtotal;␊
UInt16 y2;␊
␉UInt16 vblank;␊
␉UInt16 vsyncstart;␊
␉UInt16 vsyncend;␊
} __attribute__((packed)) vbios_modeline_type2;␊
␊
typedef struct {␊
␉UInt8 xchars;␊
␉UInt8 ychars;␊
␉UInt8 unknown[4];␊
␉␊
␉vbios_modeline_type2 modelines[];␊
} __attribute__((packed)) vbios_resolution_type2;␊
␊
typedef struct {␊
␉unsigned long clock;␊
␉␊
␉UInt16 x1;␊
␉UInt16 htotal;␊
␉UInt16 x2;␊
␉UInt16 hblank;␊
␉UInt16 hsyncstart;␊
␉UInt16 hsyncend;␊
␉␊
␉UInt16 y1;␊
␉UInt16 vtotal;␊
␉UInt16 y2;␊
␉UInt16 vblank;␊
␉UInt16 vsyncstart;␊
␉UInt16 vsyncend;␊
␉␊
␉UInt16 timing_h;␊
␉UInt16 timing_v;␊
␉␊
␉UInt8 unknown[6];␊
} __attribute__((packed)) vbios_modeline_type3;␊
␊
typedef struct {␊
␉unsigned char unknown[6];␊
␉␊
vbios_modeline_type3 modelines[];␊
} __attribute__((packed)) vbios_resolution_type3;␊
␊
typedef struct {␊
␉UInt32 chipset_id;␊
␉chipset_type chipset;␊
␉bios_type bios;␊
␉␊
␉bios_tables_t ati_tables;␊
␊
␉␊
␉UInt32 bios_fd;␊
␉char* bios_ptr;␊
␉␊
␉vbios_mode * mode_table;␊
␉char * ati_mode_table;␊
␉char * nv_mode_table;␊
␊
␉UInt32 mode_table_size;␊
␉UInt8 b1, b2;␊
␉␊
␉UInt8 unlocked;␊
} vbios_map;␊
␊
␊
␊
vbios_map * open_vbios(chipset_type);␊
void close_vbios (vbios_map*);␊
void unlock_vbios(vbios_map*);␊
void relock_vbios(vbios_map*);␊
void set_mode(vbios_map*, UInt32, UInt32, UInt32, UInt32, UInt32);␊
␊
#endif //__RESOLUTION_H␊
branches/meklort/i386/boot2/boot.c
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#include "ramdisk.h"␊
#include "gui.h"␊
#include "platform.h"␊
#include "resolution.h"␊
␊
long gBootMode; /* defaults to 0 == kBootModeNormal */␊
bool gOverrideKernel;␊
// Override useGUI default␊
getBoolForKey(kGUIKey, &useGUI, &bootInfo->bootConfig);␊
if (useGUI) {␊
␉␉patchVideoBios();␊
/* XXX AsereBLN handle error */␊
␉initGUI();␊
␉␉initGUI();␊
}␊
␊
setBootGlobals(bvChain);␊
branches/meklort/i386/boot2/boot.h
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#define kRenamePartition␉"Rename Partition"␉/* disk.c */␊
#define kUseMemDetect␉ "UseMemDetect"␉ /* platform.c */␊
#define kRestartFix "RestartFix" /* dsdt_patcher.c */␊
#define kScreenWidth␉␉"ScreenWidth"␉␉/* edid.h */␊
#define kScreenHeight␉␉"ScreenHeight"␉␉/* edid.h */␊
␊
/*␊
* Flags to the booter or kernel␊
branches/meklort/i386/boot2/kernel_patcher.c
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**/␊
void patch_kernel_32(void* kernelData)␊
{␊
␉patch_pmCPUExitHaltToOff(kernelData);␊
␉//patch_pmCPUExitHaltToOff(kernelData);␉// Not working as intended, disabled for now␊
␉patch_cpuid_set_info(kernelData);␊
␊
}␊

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