Chameleon

Chameleon Commit Details

Date:2010-07-12 20:05:55 (13 years 9 months ago)
Author:valv
Commit:177
Parents: 176
Message:call the cpu/freq detection code late in the booter. Thanks Kabyl. New FSB detection code, plus a FixFSB and busratio keys. Added support for newer intel CPUs (Core i7/i5/i3). More nVidia Device-IDs added. Got rid of some annoying verbose messages. Healed DSDT dependency. Better CPU injection.
Changes:
M/branches/valv/i386/libsa/libsa.h
M/branches/valv/i386/libsaio/cpu.c
M/branches/valv/i386/libsaio/platform.h
M/branches/valv/version
M/branches/valv/i386/libsaio/nvidia.c
M/branches/valv/i386/boot2/boot.h
M/branches/valv/i386/libsaio/cpu.h
M/branches/valv/i386/libsaio/saio_internal.h
M/branches/valv/i386/boot2/options.c
M/branches/valv/i386/libsaio/stringTable.c
M/branches/valv/i386/libsaio/915resolution.c
M/branches/valv/i386/libsaio/smbios_patcher.c
M/branches/valv/revision
M/branches/valv/i386/libsaio/dsdt_patcher.c
M/branches/valv/i386/boot2/boot.c

File differences

branches/valv/version
1
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2.0-RC5pre11AnVAL2␊
2.0-RC5-AnVAL4␊
branches/valv/i386/libsaio/smbios_patcher.c
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␊
static int sm_get_cputype (const char *name, int table_num)␊
{␊
␉if (Platform.CPU.NoCores == 1) {␊
␉␉return 0x0201; // <01 02> Intel Core Solo/Duo?␊
␉} else if (Platform.CPU.NoCores == 2) {␊
␉␉return 0x0301; // <01 03> Intel Core 2 Duo␊
␉} else if (Platform.CPU.NoCores >= 4) {␊
␉␉return 0x0501; // <01 05> Quad-Core Intel Xeon␊
␉if (Platform.CPU.Vendor == 0x756E6547) {␊
␉␉int cores = Platform.CPU.NoCores;␊
␉␉int intelPM = Platform.CPU.Model; //+ (Platform.CPU.ExtModel<< 4);//verify this␊
␊
␉␉switch (intelPM) {␊
␉␉␉case 13:␉␉␉␉␉// Pentium M model D␊
␉␉␉␉return 0x0101;␊
␉␉␉␉break;␊
␉␉␉case 14:␉␉␉␉␉// Core Solo/Duo, "Yonah", 65nm␊
␉␉␉␉return 0x0201;␊
␉␉␉␉break;␊
␉␉␉case 15:␉␉␉␉␉// Pentium 4, Core 2, Xeon, "Merom", "Conroe", 65nm␊
␉␉␉␉switch (cores) {␊
␉␉␉␉␉case 1:␉␉␉␉// Core Solo␊
␉␉␉␉␉␉return 0x0201;␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉case 2:␉␉␉␉// Core 2, 65nm␊
␉␉␉␉␉␉return 0x0301;␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉case 4:␉␉␉␉// Quad Core, Xeon␊
␉␉␉␉␉␉return 0x0501;␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉default:␊
␉␉␉␉␉␉return 0x0301;␊
␉␉␉␉␉␉break;␊
␉␉␉␉}␊
/*␉␉␉␉if (cores == 1)␊
␉␉␉␉␉return 0x0201;␉␉// Core Solo␊
␉␉␉␉else if (cores == 2)␊
␉␉␉␉␉return 0x0301;␉␉// Core 2, 65nm␊
␉␉␉␉else if (cores == 4)␊
␉␉␉␉␉return 0x0501;␉␉// Quad-Core Xeon␊
␉␉␉␉else␊
␉␉␉␉␉return 0x0301;*/␊
␉␉␉␉break;␊
␉␉␉case 21:␉␉␉␉␉// EP80579 integrated processor␊
␉␉␉␉return 0x0301;␉␉␉// ???␊
␉␉␉␉break;␊
␉␉␉case 22:␉␉␉␉␉// Core 2 Solo, "Merom-L", "Conroe-L", 45nm␊
␉␉␉␉return 0x0201;␉␉␉// ???␊
␉␉␉␉break;␊
␉␉␉case 23:␉␉␉␉␉// Core 2 Extreme, Xeon, "Penryn", "Wolfdale", 45nm␊
␉␉␉␉return 0x0301;␊
␉␉␉␉break;␊
␉␉␉case 26:␉␉␉␉␉// Nehalem, Xeon 5500, "Bloomfield", 45nm␊
␉␉␉␉return 0x0701;␊
␉␉␉␉break;␊
␉␉␉case 29:␉␉␉␉␉// Six-Core Xeon 7400, "Dunnington", 45nm␊
␉␉␉␉return 0x0401;␊
␉␉␉␉break;␊
␉␉␉case 30:␉␉␉␉␉// Nehalem, Xeon, "Lynnfield", "Clarksfield", "Jasper", 45nm␊
␉␉␉␉return 0x0701;␊
␉␉␉␉break;␊
␉␉␉case 31:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊
␉␉␉␉return 0x0601;␊
␉␉␉␉break;␊
␉␉␉case 37:␉␉␉␉␉// Nehalem, "Clarkdale", 32nm␊
␉␉␉␉return 0x0301;␉␉␉// ???␊
␉␉␉␉break;␊
␉␉␉case 44:␉␉␉␉␉// Nehalem, "Gulftown", 32nm␊
␉␉␉␉return 0x0601;␊
␉␉␉␉break;␊
␉␉␉case 46:␉␉␉␉␉// "Nehalem-ex", "Beckton", 45nm␊
␉␉␉␉return 0x0301;␉␉␉// ???␊
␉␉␉␉break;␊
␉␉␉default:␊
␉␉␉␉goto core_ident;␊
␉␉}␊
␉} else {␊
␉␉return 0x0301; // Default to Core 2 Duo␊
␉␉core_ident:␊
␉␉if (Platform.CPU.NoCores == 1) {␊
␉␉␉return 0x0201; // Core Solo␊
␉␉} else if (Platform.CPU.NoCores == 2) {␊
␉␉␉return 0x0301; // Core 2 Duo␊
␉␉} else if (Platform.CPU.NoCores >= 4) {␊
␉␉␉return 0x0501; // Quad-Core Xeon␊
␉␉} else {␊
␉␉␉return 0x0301; // Core 2 Duo␊
␉␉}␊
␉}␊
}␊
␊
branches/valv/i386/libsaio/dsdt_patcher.c
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␉if (fd>=0) goto success_fd;␊
␉␊
␉// NOT FOUND:␊
␉verbose("ACPI Table not found: %s\n", filename);␊
␉//verbose("ACPI Table not found: %s\n", filename);␊
␉if (outDirspec) *outDirspec = "";␊
␉return -1;␊
␉// FOUND␊
␉␉␉fd=open (dirspec,0);␊
␉␉␉if (fd<0)␊
␉␉␉{␊
␉␉␉␉verbose("SSDT Table not found: %s\n", filename);␊
␉␉␉␉//verbose("SSDT Table not found: %s\n", filename);␊
␉␉␉␉return NULL;␊
␉␉␉}␊
␉␉}␊
␉ else␊
␉ Platform.Type = (unsigned char) strtoul(value, NULL, 10);␊
␉}␊
␉// Set Preferred_PM_Profile from System-type if only if user wanted this value to be forced␊
␉// Set Preferred_PM_Profile from System-type only if user wanted this value to be forced␊
␉if (fadt_mod->Preferred_PM_Profile != Platform.Type) ␊
␉{␊
␉ if (value) ␊
␉␉verbose("FADT: Restart Fix applied !\n");␊
␉}␊
␊
␉if (new_dsdt)␊
␉{␊
␊
␉// Patch FACS Address␊
␉fadt_mod->FIRMWARE_CTRL=(uint32_t)fadt->FIRMWARE_CTRL;␊
␉if ((uint32_t)(&(fadt_mod->X_FIRMWARE_CTRL))-(uint32_t)fadt_mod+8<=fadt_mod->Length)␊
␉␉fadt_mod->X_DSDT=(uint32_t)new_dsdt;␊
␊
␉DBG("New @%x,%x\n",fadt_mod->DSDT,fadt_mod->X_DSDT);␊
␉␉verbose("FADT: Custom DSDT used !\n");␊
␉}␊
␊
␉// Correct the checksum␊
␉fadt_mod->Checksum=0;␊
␉␉}␊
␉␉curssdt=0;␊
␉}␊
␊
/*␊
␉if (!new_dsdt)␊
␉␉return setupAcpiNoMod();␊
␊
*/␊
␉DBG("New ACPI tables Loaded in memory\n");␊
␉␉␉␊
␉// Do the same procedure for both versions of ACPI␊
branches/valv/i386/libsaio/nvidia.c
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␉{ 0x10DE0046, "GeForce 6800 GT" },␊
␉{ 0x10DE0047, "GeForce 6800 GS" },␊
␉{ 0x10DE0048, "GeForce 6800 XT" },␊
␉{ 0x10DE004D, "Quadro FX 3400" },␊
␉{ 0x10DE004E, "Quadro FX 4000" },␊
␉{ 0x10DE0090, "GeForce 7800 GTX" },␊
␉{ 0x10DE0091, "GeForce 7800 GTX" },␊
␉{ 0x10DE00CC, "Quadro FX Go1400" },␊
␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊
␉{ 0x10DE00CE, "Quadro FX 1400" },␊
␉{ 0x10DE00F1, "GeForce 6600 GT" },␊
␉{ 0x10DE00F2, "GeForce 6600" },␊
␉{ 0x10DE00F3, "GeForce 6200" },␊
␉{ 0x10DE00F4, "GeForce 6600 LE" },␊
␉{ 0x10DE00F5, "GeForce 7800 GS" },␊
␉{ 0x10DE00F6, "GeForce 6800 GS/XT" },␊
␉{ 0x10DE00F8, "Quadro FX 3400/4400" },␊
␉{ 0x10DE00F9, "GeForce 6800 Series GPU" },␊
␉{ 0x10DE0140, "GeForce 6600 GT" },␊
␉{ 0x10DE0141, "GeForce 6600" },␊
␉{ 0x10DE0142, "GeForce 6600 LE" },␊
␉{ 0x10DE0147, "GeForce 6700 XL" },␊
␉{ 0x10DE0148, "GeForce Go 6600" },␊
␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊
␉{ 0x10DE014A, "Quadro NVS 440" },␊
␉{ 0x10DE014C, "Quadro FX 550" },␊
␉{ 0x10DE014D, "Quadro FX 550" },␊
␉{ 0x10DE014E, "Quadro FX 540" },␊
␉{ 0x10DE0191, "GeForce 8800 GTX" },␊
␉{ 0x10DE0193, "GeForce 8800 GTS" },␊
␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊
␉{ 0x10DE0197, "Tesla C870" },␊
␉{ 0x10DE019D, "Quadro FX 5600" },␊
␉{ 0x10DE019E, "Quadro FX 4600" },␊
␉{ 0x10DE01D0, "GeForce 7350 LE" },␊
␉{ 0x10DE01D1, "GeForce 7300 LE" },␊
␉{ 0x10DE01D3, "GeForce 7300 SE" },␊
␉{ 0x10DE01D2, "GeForce 7550 LE" },␊
␉{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },␊
␉{ 0x10DE01D6, "GeForce Go 7200" },␊
␉{ 0x10DE01D7, "GeForce Go 7300" },␊
␉{ 0x10DE01D8, "GeForce Go 7400" },␊
␉{ 0x10DE0241, "GeForce 6150 LE" },␊
␉{ 0x10DE0242, "GeForce 6100" },␊
␉{ 0x10DE0244, "GeForce Go 6150" },␊
␉{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },␊
␉{ 0x10DE0247, "GeForce Go 6100" },␊
␉{ 0x10DE0290, "GeForce 7900 GTX" },␊
␉{ 0x10DE0291, "GeForce 7900 GT" },␊
␉{ 0x10DE0291, "GeForce 7900 GT/GTO" },␊
␉{ 0x10DE0292, "GeForce 7900 GS" },␊
␉{ 0x10DE0293, "GeForce 7950 GX2" },␊
␉{ 0x10DE0294, "GeForce 7950 GX2" },␊
␉{ 0x10DE0295, "GeForce 7950 GT" },␊
␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊
␉{ 0x10DE0299, "GeForce Go 7900 GTX" },␊
␉{ 0x10DE029A, "Quadro FX 2500M" },␊
␉{ 0x10DE029D, "Quadro FX 3500" },␊
␉{ 0x10DE029E, "Quadro FX 1500" },␊
␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊
␉{ 0x10DE02E0, "GeForce 7600 GT" },␊
␉{ 0x10DE02E1, "GeForce 7600 GS" },␊
␉{ 0x10DE02E2, "GeForce 7300 GT" },␊
␉{ 0x10DE02E3, "GeForce 7900 GS" },␊
␉{ 0x10DE02E4, "GeForce 7950 GT" },␊
␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊
␉{ 0x10DE0302, "GeForce FX 5800" },␊
␉{ 0x10DE0308, "Quadro FX 2000" },␊
␉{ 0x10DE0348, "GeForce FX Go5700" },␊
␉{ 0x10DE034C, "Quadro FX Go1000" },␊
␉{ 0x10DE034E, "Quadro FX 1100" },␊
␉{ 0x10DE038B, "GeForce 7650 GS" },␊
␉{ 0x10DE0390, "GeForce 7650 GS" },␊
␉{ 0x10DE0391, "GeForce 7600 GT" },␊
␉{ 0x10DE0392, "GeForce 7600 GS" },␊
␉{ 0x10DE0393, "GeForce 7300 GT" },␊
␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊
␉{ 0x10DE039C, "Quadro FX 550M" },␊
␉{ 0x10DE039E, "Quadro FX 560" },␊
␉{ 0x10DE03D0, "GeForce 6150SE nForce 430" },␊
␉{ 0x10DE03D1, "GeForce 6100 nForce 405" },␊
␉{ 0x10DE03D2, "GeForce 6100 nForce 400" },␊
␉{ 0x10DE03D5, "GeForce 6100 nForce 420" },␊
␉{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },␊
␉{ 0x10DE0400, "GeForce 8600 GTS" },␊
␉{ 0x10DE0401, "GeForce 8600 GT" },␊
␉{ 0x10DE0402, "GeForce 8600 GT" },␊
␉{ 0x10DE0403, "GeForce 8600 GS" },␊
␉{ 0x10DE0404, "GeForce 8400 GS" },␊
␉{ 0x10DE0405, "GeForce 9500M GS" },␊
␉{ 0x10DE0406, "GeForce 8300 GS" },␊
␉{ 0x10DE0407, "GeForce 8600M GT" },␊
␉{ 0x10DE0408, "GeForce 9650M GS" },␊
␉{ 0x10DE0409, "GeForce 8700M GT" },␊
␉{ 0x10DE040D, "Quadro FX 1600M" },␊
␉{ 0x10DE040E, "Quadro FX 570" },␊
␉{ 0x10DE040F, "Quadro FX 1700" },␊
␉{ 0x10DE0410, "GeForce GT 330" },␊
␉{ 0x10DE0420, "GeForce 8400 SE" },␊
␉{ 0x10DE0421, "GeForce 8500 GT" },␊
␉{ 0x10DE0422, "GeForce 8400 GS" },␊
␉{ 0x10DE042D, "Quadro FX 360M" },␊
␉{ 0x10DE042E, "GeForce 9300M G" },␊
␉{ 0x10DE042F, "Quadro NVS 290" },␊
␉{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },␊
␉{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },␊
␉{ 0x10DE053E, "GeForce 7025 / nForce 630a" },␊
␉{ 0x10DE05E0, "GeForce GTX 295" },␊
␉{ 0x10DE05E1, "GeForce GTX 280" },␊
␉{ 0x10DE05E2, "GeForce GTX 260" },␊
␉{ 0x10DE05E6, "GeForce GTX 275" },␊
␉{ 0x10DE05EA, "GeForce GTX 260" },␊
␉{ 0x10DE05EB, "GeForce GTX 295" },␊
␉{ 0x10DE05ED, "Quadroplex 2200 D2" },␊
␉{ 0x10DE05F8, "Quadroplex 2200 S4" },␊
␉{ 0x10DE05F9, "Quadro CX" },␊
␉{ 0x10DE05FD, "Quadro FX 5800" },␊
␉{ 0x10DE05FE, "Quadro FX 4800" },␊
␉{ 0x10DE05FF, "Quadro FX 3800" },␊
␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊
␉{ 0x10DE0601, "GeForce 9800 GT" },␊
␉{ 0x10DE0602, "GeForce 8800 GT" },␊
␉{ 0x10DE0603, "GeForce GT 230" },␊
␉{ 0x10DE0604, "GeForce 9800 GX2" },␊
␉{ 0x10DE0605, "GeForce 9800 GT" },␊
␉{ 0x10DE0606, "GeForce 8800 GS" },␊
␉{ 0x10DE060D, "GeForce 8800 GS" },␊
␉{ 0x10DE0610, "GeForce 9600 GSO" },␊
␉{ 0x10DE0611, "GeForce 8800 GT" },␊
␉{ 0x10DE0612, "GeForce 9800 GTX" },␊
␉{ 0x10DE0613, "GeForce 9800 GTX+" },␊
␉{ 0x10DE0612, "GeForce 9800 GTX / GeForce 9800 GTX+" },␊
␉{ 0x10DE0614, "GeForce 9800 GT" },␊
␉{ 0x10DE0615, "GeForce GTS 250" },␊
␉{ 0x10DE0617, "GeForce 9800M GTX" },␊
␉{ 0x10DE0618, "GeForce GTX 260M" },␉␊
␉{ 0x10DE0619, "Quadro FX 4700 X2" },␊
␉{ 0x10DE061A, "Quadro FX 3700" },␊
␉{ 0x10DE061B, "Quadro VX 200" },␊
␉{ 0x10DE061C, "Quadro FX 3600M" },␊
␉{ 0x10DE061D, "Quadro FX 2800M" },␊
␉{ 0x10DE061F, "Quadro FX 3800M" },␊
␉{ 0x10DE0628, "GeForce 9800M GTS" },␊
␉{ 0x10DE062A, "GeForce 9700M GTS" },␊
␉{ 0x10DE062C, "GeForce 9800M GTS" },␊
␉{ 0x10DE062D, "GeForce 9600 GT" },␊
␉{ 0x10DE062E, "GeForce 9600 GT" },␊
␉{ 0x10DE0635, "GeForce 9600 GSO" },␊
␉{ 0x10DE0637, "GeForce 9600 GT" },␊
␉{ 0x10DE0638, "Quadro FX 1800" },␊
␉{ 0x10DE0640, "GeForce 9500 GT" },␊
␉{ 0x10DE0641, "GeForce 9400 GT" },␊
␉{ 0x10DE0642, "GeForce 8400 GS" },␊
␉{ 0x10DE065A, "Quadro FX 1700M" },␊
␉{ 0x10DE065B, "GeForce 9400 GT" },␊
␉{ 0x10DE065C, "Quadro FX 770M" },␊
␉{ 0x10DE065F, "GeForce G210" },␊
␉{ 0x10DE06E0, "GeForce 9300 GE" },␊
␉{ 0x10DE06E1, "GeForce 9300 GS" },␊
␉{ 0x10DE06E2, "GeForce 8400" },␊
␉{ 0x10DE06E3, "GeForce 8400 SE" },␊
␉{ 0x10DE06E4, "GeForce 8400 GS" },␊
␉{ 0x10DE06E5, "GeForce 9300M GS" },␊
␉{ 0x10DE06E6, "GeForce G100" },␊
␉{ 0x10DE06E7, "GeForce 9300 SE" },␊
␉{ 0x10DE06E8, "GeForce 9200M GS" },␊
␉{ 0x10DE06E9, "GeForce 9300M GS" },␊
␉{ 0x10DE06EA, "Quadro NVS 150M" },␊
␉{ 0x10DE06F9, "Quadro FX 370 LP" },␊
␉{ 0x10DE06FA, "Quadro NVS 450" },␊
␉{ 0x10DE06FD, "Quadro NVS 295" },␊
{ 0x10DE087D, "ION 9400M" },␊
{ 0x10DE087E, "ION LE" },␊
␉{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },␊
␉{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },␊
␉{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },␊
␉{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },␊
␉{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },␊
␉{ 0x10DE0846, "GeForce 9200" },␊
␉{ 0x10DE0847, "GeForce 9100" },␊
␉{ 0x10DE0848, "GeForce 8300" },␊
␉{ 0x10DE0849, "GeForce 8200" },␊
␉{ 0x10DE084A, "nForce 730a" },␊
␉{ 0x10DE084B, "GeForce 9200" },␊
␉{ 0x10DE084C, "nForce 980a/780a SLI" },␊
␉{ 0x10DE084D, "nForce 750a SLI" },␊
␉{ 0x10DE084F, "GeForce 8100 / nForce 720a" },␊
␉{ 0x10DE0860, "GeForce 9400" },␊
␉{ 0x10DE0861, "GeForce 9400" },␊
␉{ 0x10DE0864, "GeForce 9300" },␊
␉{ 0x10DE0865, "ION" },␊
␉{ 0x10DE0868, "nForce 760i SLI" },␊
␉{ 0x10DE086A, "GeForce 9400" },␊
␉{ 0x10DE086C, "GeForce 9300 / nForce 730i" },␊
␉{ 0x10DE086D, "GeForce 9200" },␊
␉{ 0x10DE0871, "GeForce 9200" },␊
␉{ 0x10DE0874, "ION" },␊
␉{ 0x10DE0876, "ION" },␊
␉{ 0x10DE087A, "GeForce 9400" },␊
{ 0x10DE087D, "ION 9400M" },␊
{ 0x10DE087E, "ION LE" },␊
␉{ 0x10DE087F, "ION LE" },␊
␉{ 0x10DE0A20, "GeForce GT220" },␊
␉{ 0x10DE0A23, "GeForce 210" },␊
␉{ 0x10DE0A28, "GeForce GT 230M" },␊
␉{ 0x10DE0A2A, "GeForce GT 230M" },␊
␉{ 0x10DE0A34, "GeForce GT 240M" },␊
␉{ 0x10DE0A60, "GeForce G210" },␊
␉{ 0x10DE0A62, "GeForce 205" },␊
␉{ 0x10DE0A63, "GeForce 310" },␊
␉{ 0x10DE0A64, "ION" },␊
␉{ 0x10DE0A65, "GeForce 210" },␊
␉{ 0x10DE0A66, "GeForce 310" },␊
␉{ 0x10DE0A74, "GeForce G210M" },␊
␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊
␉{ 0x10DE0CA0, "GeForce GT 330 " },␊
␉{ 0x10DE0CA2, "GeForce GT 320" },␊
␉{ 0x10DE0CA3, "GeForce GT 240" },␊
␉{ 0x10DE0CA4, "GeForce GT 340" },␊
␉{ 0x10DE0CA7, "GeForce GT 330" },␊
␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊
␉{ 0x10DE0CA9, "GeForce GTS 250M" }␊
};␊
branches/valv/i386/libsaio/cpu.c
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#include "libsaio.h"␊
#include "platform.h"␊
#include "cpu.h"␊
#include "boot.h"␊
#include "bootstruct.h"␊
␊
#ifndef DEBUG_CPU␊
#define DEBUG_CPU 0␊
␉ : "a" (selector), "c" (selector2));␊
}␊
␊
/*static inline unsigned long long rdmsr46(unsigned int msr, unsigned low, unsigned high)␊
{␊
␉//unsigned low, high;␊
␉asm volatile("rdmsr" : "=a" (low), "=d" (high));␊
␉return ((low) | ((uint64_t)(high) << 32));␊
}*/␊
␊
// DFE: enable_PIT2 and disable_PIT2 come from older xnu␊
␊
/*␊
␊
void scan_cpu(PlatformInfo_t *p)␊
{␊
␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊
␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency, minfsb, maxfsb;␊
␉uint64_t␉msr, flex_ratio;␊
␉int␉␉␉bus_ratio;␊
␉uint8_t␉␉maxcoef, maxdiv, currcoef, currdiv;␊
␉bool␉␉fix_fsb;␊
//␉const uint32_t fsb_cloud[] = {266666667, 133333333, 200000000, 166666667, 333333333, 100000000, 400000000, 0};␊
//␉uint32_t␉lo, hi;␊
␊
␉maxcoef = maxdiv = currcoef = currdiv = 0;␊
␊
␉tscFrequency = measure_tsc_frequency();␊
␉fsbFrequency = 0;␊
␉cpuFrequency = 0;␊
␉minfsb = 183000000;␊
␉maxfsb = 185000000;␊
␉fix_fsb = false;␊
␊
␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊
␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊
␉␉␉/* Nehalem CPU model */␊
␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == 0x1a || p->CPU.Model == 0x1e)) {␊
␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, msr & 0xffffffff);␊
␉␉␉␉currcoef = (msr >> 8) & 0xff;␊
␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, msr & 0xffffffff);␊
␉␉␉␉if ((msr >> 16) & 0x01) {␊
␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊
␉␉␉␉␉if (currcoef > flex_ratio) {␊
␉␉␉␉␉␉currcoef = flex_ratio;␊
␉␉␉␉␉}␊
␉␉␉␉}␊
␉␉␉if (p->CPU.Family == 0x06) {␊
/* TODO: Split detection algo into sections, maybe relying on ExtModel, like this:␊
␉␉␉␉if (p->CPU.ExtModel == 0x1) {␊
␉␉␉␉} else if (p->CPU.ExtModel == 0x2) {␊
␉␉␉␉}*/␊
␉␉␉␉int intelCPU = p->CPU.Model;␊
␉␉␉␉int bus;␊
␊
␉␉␉␉if (currcoef) {␊
␉␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
␉␉␉␉switch (intelCPU) {␊
␉␉␉␉␉case 0x1a:␉␉// Core i7 LGA1366, Xeon 550, 45nm␊
// TODO: 0x1e needs to be split to avoid 860 & 875k collision.␊
␉␉␉␉␉case 0x1e:␉␉// Core i7, i5 LGA1156, "Lynnfield", "Jasper", 45nm␊
␉␉␉␉␉case 0x1f:␉␉// Core i7, i5, Nehalem␊
␉␉␉␉␉case 0x25:␉␉// Core i7, i5, i3 LGA1156, "Westmere", 32nm␊
␉␉␉␉␉case 0x2c:␉␉// Core i7 LGA1366, Six-core, "Westmere", 32nm␊
␉␉␉␉␉case 0x2e:␉␉// Core i7, Nehalem-Ex, Xeon␊
␉␉␉␉␉case 0x2f:␊
␉␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
␉␉␉␉␉␉currcoef = (msr >> 8) & 0xff;␊
␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
␉␉␉␉␉␉if ((msr >> 16) & 0x01) {␊
␉␉␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊
␉␉␉␉␉␉␉if (currcoef > flex_ratio) {␊
␉␉␉␉␉␉␉␉currcoef = flex_ratio;␊
␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (currcoef) {␊
␉␉␉␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉cpuFrequency = tscFrequency;␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉case 0xe:␉␉// Core Duo/Solo, Pentium M DC␊
␉␉␉␉␉case 0xf:␉␉// Core Xeon, Core 2 DC, 65nm␊
␉␉␉␉␉case 0x16:␉␉// Celeron, Core 2 SC, 65nm␊
␉␉␉␉␉case 0x17:␉␉// Core 2 Duo/Extreme, Xeon, 45nm␊
␉␉␉␉␉case 0x1c:␉␉// Atom :)␊
␉␉␉␉␉case 0x27:␉␉// Atom Lincroft, 45nm␊
␉␉␉␉␉␉␉␉getBoolForKey(kFixFSB, &fix_fsb, &bootInfo->bootConfig);␊
␉␉␉␉␉␉␉␉if (fix_fsb) {␊
␉␉␉␉␉␉␉␉␉msr = rdmsr64(MSR_FSB_FREQ);␊
␉␉␉␉␉␉␉␉␉bus = (msr >> 0) & 0x7;␊
␉␉␉␉␉␉␉␉␉switch (bus) {␊
␉␉␉␉␉␉␉␉␉␉case 0:␊
␉␉␉␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊
␉␉␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉␉␉case 1:␊
␉␉␉␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊
␉␉␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉␉␉case 2:␊
␉␉␉␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
␉␉␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉␉␉case 3:␊
␉␉␉␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊
␉␉␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉␉␉case 4:␊
␉␉␉␉␉␉␉␉␉␉␉fsbFrequency = 333333333;␊
␉␉␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉␉␉case 5:␊
␉␉␉␉␉␉␉␉␉␉␉fsbFrequency = 100000000;␊
␉␉␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉␉␉case 6:␊
␉␉␉␉␉␉␉␉␉␉␉fsbFrequency = 400000000;␊
␉␉␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉␉␉default:␊
␉␉␉␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
␉␉␉␉␉␉␉␉␉␉␉DBG("Defaulting the FSB frequency to 200Mhz \n");␊
␉␉␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉␉␉␉verbose("CPU: FSB Fix applied !\n");␊
␉␉␉␉␉␉␉␉␉if (!getIntForKey(kbusratio, &bus_ratio, &bootInfo->bootConfig)) {␊
␉␉␉␉␉␉␉␉␉␉verbose("CPU: using oldschool cpu freq detection !\n");␊
␉␉␉␉␉␉␉␉␉␉goto oldschool;␊
␉␉␉␉␉␉␉␉␉} else␊
␉␉␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * (bus_ratio / 10));␊
␉␉␉␉␉␉␉␉␉␉␊
␉␉␉␉␉␉␉␉␉if (((fsbFrequency) > (minfsb) && (fsbFrequency) < (maxfsb)) || (!fsbFrequency)) {␊
␉␉␉␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
␉␉␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉␉␉} else {␊
␉␉␉␉␉␉␉␉␉verbose("CPU: No FSB Fix applied ! fall back to oldschool \n");␊
␉␉␉␉␉␉␉␉␉goto oldschool;␊
␉␉␉␉␉␉␉␉}␊
/*␉␉␉␉␉␉␉␉msr = rdmsr64(IA32_PERF_STATUS);␊
␉␉␉␉␉␉␉␉currdiv = (msr >> 14) & 0x01;␊
␉␉␉␉␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊
␉␉␉␉␉␉␉␉lo = (uint32_t)rdmsr64(IA32_PERF_STATUS);␊
␉␉␉␉␉␉␉␉hi = (uint32_t)(rdmsr64(IA32_PERF_STATUS) >> 32);␊
␉␉␉␉␉␉␉␉if (lo >> 31) {␊
␉␉␉␉␉␉␉␉␉currcoef = (hi >> 8) & 0x1f;␊
␉␉␉␉␉␉␉␉} else {␊
␉␉␉␉␉␉␉␉␉lo = (uint32_t)rdmsr64(MSR_IA32_PLATFORM_ID);␊
␉␉␉␉␉␉␉␉␉currcoef = (lo >> 8) & 0x1f;␊
␉␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉␉␉if (maxdiv) {␊
␉␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * (currcoef + 1));␊
␉␉␉␉␉␉␉␉} else {␊
␉␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
␉␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉␉␉if (currdiv) {␊
␉␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
␉␉␉␉␉␉␉␉} else {␊
␉␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
␉␉␉␉␉␉␉␉}*/␊
␉␉␉␉␉␉␉␉//cpuFrequency = tscFrequency;␊
␉␉␉␉␉␉␉␉break;␊
/*␉␉␉␉␉case 0x17:␉␉// Core 2 Duo/Extreme, Xeon, 45nm␊
␉␉␉␉␉␉lo = (uint32_t)rdmsr64(IA32_PERF_STATUS);␊
␉␉␉␉␉␉hi = (uint32_t)(rdmsr64(IA32_PERF_STATUS) >> 32);␊
␉␉␉␉␉␉//rdmsr46(IA32_PERF_STATUS, lo, hi);␊
␉␉␉␉␉␉if (lo >> 31) {␊
␉␉␉␉␉␉␉currcoef = (hi >> 8) & 0x1f;␊
␉␉␉␉␉␉} else {␊
␉␉␉␉␉␉␉lo = (uint32_t)rdmsr64(MSR_IA32_PLATFORM_ID);␊
␉␉␉␉␉␉//␉hi = (uint32_t)(rdmsr64(MSR_IA32_PLATFORM_ID) >> 32);␊
␉␉␉␉␉␉//␉rdmsr46(MSR_IA32_PLATFORM_ID, lo, hi);␊
␉␉␉␉␉␉␉currcoef = (lo >> 8) & 0x1f;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉fsbFrequency = ((fsb_cloud[lo & 0x7]) * 2);␊
␉␉␉␉␉␉//cpuFrequency = (fsbFrequency * currcoef);␊
␉␉␉␉␉␉if (!fsbFrequency) {␊
␉␉␉␉␉␉␉fsbFrequency = (DEFAULT_FSB * 2000);␊
␉␉␉␉␉␉␉DBG("0 ! Defaulting the FSB frequency to 200Mhz !\n");␊
␉␉␉␉␉␉}*/␊
␉␉␉␉␉case 0x1d:␉␉// Xeon MP MP 7400␊
␉␉␉␉␉default:␊
␉␉␉␉␉␉goto oldschool;␊
␉␉␉␉␉␉break;␊
␉␉␉␉}␊
␉␉␉␉cpuFrequency = tscFrequency;␊
␉␉␉} else {␊
␉␉␉␉msr = rdmsr64(IA32_PERF_STATUS);␊
␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, msr & 0xffffffff);␊
␉␉␉␉currcoef = (msr >> 8) & 0x1f;␊
␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊
␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
␉␉␉␉currdiv = (msr >> 14) & 0x01;␊
oldschool:␊
␉␉␉␉␉msr = rdmsr64(IA32_PERF_STATUS);␊
␉␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, msr & 0xffffffff);␊
␉␉␉␉␉currcoef = (msr >> 8) & 0x1f;␊
␉␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
␉␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊
␉␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
␉␉␉␉␉currdiv = (msr >> 14) & 0x01;␊
␊
␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) // This will always be model >= 3␊
␉␉␉␉{␊
␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
␉␉␉␉␉maxcoef = (msr >> 40) & 0x1f;␊
␉␉␉␉} else {␊
␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
␉␉␉␉␉/* XXX */␊
␉␉␉␉␉maxcoef = currcoef;␊
␉␉␉␉}␊
␊
␉␉␉␉if (maxcoef) {␊
␉␉␉␉␉if (maxdiv) {␊
␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
␉␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) // This will always be model >= 3␊
␉␉␉␉␉{␊
␉␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
␉␉␉␉␉␉maxcoef = (msr >> 40) & 0x1f;␊
␉␉␉␉␉} else {␊
␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
␉␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
␉␉␉␉␉␉/* XXX */␊
␉␉␉␉␉␉maxcoef = currcoef;␊
␉␉␉␉␉}␊
␉␉␉␉␉if (currdiv) {␊
␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
␊
␉␉␉␉␉if (maxcoef) {␊
␉␉␉␉␉␉if (!fix_fsb) {␊
␉␉␉␉␉␉␉if (maxdiv) {␊
␉␉␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
␉␉␉␉␉␉␉} else {␊
␉␉␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (currdiv) {␊
␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
␉␉␉␉␉␉} else {␊
␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
␉␉␉␉␉}␊
␉␉␉␉␉/*if (p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e)␊
␉␉␉␉␉{␊
␉␉␉␉␉␉maxcoef = (msr >> 40) & 0x1f;␊
␉␉␉␉␉␉if (maxcoef) {␊
␉␉␉␉␉␉␉if (maxdiv) {␊
␉␉␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
␉␉␉␉␉␉␉} else {␊
␉␉␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉␉if (currdiv) {␊
␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
␉␉␉␉␉␉␉} else {␊
␉␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (((fsbFrequency) > (minfsb) && (fsbFrequency) < (maxfsb)) || (!fsbFrequency)) {␊
␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
␉␉␉␉␉␉␉DBG("Defaulting FSB frequency to 200Mhz !\n");␊
␉␉␉␉␉␉}␊
␉␉␉␉␉}␊
␉␉␉␉␉if (p->CPU.Family == 0x0f) {␊
␉␉␉␉␉␉msr = rdmsr64(0x0000002C); // Xeon related register.␊
␉␉␉␉␉␉int bus;␊
␉␉␉␉␉␉bus = (msr >> 16) & 0x7;␊
␉␉␉␉␉␉switch (bus) {␊
␉␉␉␉␉␉␉case 0:␊
␉␉␉␉␉␉␉␉if (p->CPU.Model == 2) {␊
␉␉␉␉␉␉␉␉␉fsbFrequency = 100000000;␊
␉␉␉␉␉␉␉␉} else {␊
␉␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊
␉␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉case 1:␊
␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊
␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉case 2:␊
␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉case 3:␊
␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊
␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉case 4:␊
␉␉␉␉␉␉␉␉fsbFrequency = 333333333;␊
␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉default:␊
␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉} else {␊
␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
␉␉␉␉␉␉fsbFrequency = 100000000;␊
␉␉␉␉␉␉DBG("Defaulting FSB frequency to 100Mhz !\n");␊
␉␉␉␉␉}*/␊
␉␉␉␉␉if (((fsbFrequency) > (minfsb) && (fsbFrequency) < (maxfsb)) || (!fsbFrequency)) {␊
␉␉␉␉␉␉fsbFrequency = 200000000;␊
␉␉␉␉␉␉DBG("Defaulting FSB frequency to 200Mhz !\n");␊
␉␉␉␉␉}␊
␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
␉␉␉␉}␊
␉␉␉}␊
␉␉}␊
␉␉/* Mobile CPU ? */␊
␊
␉␉// Mobile CPU ?␊
␉␉if (rdmsr64(0x17) & (1<<28)) {␊
␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
␉␉}␊
branches/valv/i386/libsaio/platform.h
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␉␉uint64_t␉␉CPUFrequency;␉␉// CPU Frequency Hz␊
␉␉uint32_t␉␉BrandString[16];␉// 48 Byte Branding String␊
␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊
//␉␉uint32_t␉␉fsb_cloud;␊
//␉␉uint32_t␉␉lo, hi;␊
␉} CPU;␊
␊
␉struct RAM {␊
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#define __LIBSAIO_CPU_H␊
␊
#include "libsaio.h"␊
␊
extern void scan_cpu(PlatformInfo_t *);␊
␊
#define bit(n)␉␉␉(1UL << (n))␊
#define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊
#define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊
␊
#define␉IA32_PERF_STATUS␉0x198␊
#define MSR_FLEX_RATIO␉␉0x194␊
#define␉MSR_PLATFORM_INFO␉0xCE␊
#define K8_FIDVID_STATUS␉0xC0010042␊
#define K10_COFVID_STATUS␉0xC0010071␊
#define MSR_FSB_FREQ␉␉␉0x000000cd␊
#define MSR_IA32_PLATFORM_ID␉0x00000017␊
#define␉IA32_PERF_STATUS␉␉0x198␊
#define MSR_FLEX_RATIO␉␉␉0x194␊
#define␉MSR_PLATFORM_INFO␉␉0xCE␊
#define K8_FIDVID_STATUS␉␉0xC0010042␊
#define K10_COFVID_STATUS␉␉0xC0010071␊
␊
#define DEFAULT_FSB␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊
␊
branches/valv/i386/libsaio/915resolution.c
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␉␉ */␊
␉␊
␉if (map->chipset == CT_UNKWN) {␊
␉␉/*␊
␉␉printf("Unknown chipset type and unrecognized bios.\n");␊
/*␉␉printf("Unknown chipset type and unrecognized bios.\n");␊
␉␉ ␊
␉␉printf("915resolution only works with Intel 800/900 series graphic chipsets.\n");␊
␉␉*/␊
*/␊
␉␉printf("Chipset Id: %x\n", map->chipset_id);␊
␉␉close_vbios(map);␊
␉␉return 0;␊
branches/valv/i386/libsaio/stringTable.c
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}␊
␊
/*␊
// valv: getFloatForKey Begin␊
bool getFloatForKey( const char *key, float *value, config_file_t *config )␊
{␊
const char *val;␊
int size;␊
float sum;␊
␊
if (getValueForKey(key, &val, &size, config))␊
␉{␊
␉␉if ( size )␊
␉␉{␊
␉␉␉if (*val == '-')␊
␉␉␉{␊
␉␉␉␉return false;␊
␉␉␉}␊
␉␉␉␊
␉␉␉for (sum = 0; size > 0; size--)␊
␉␉␉{␊
␉␉␉␉if (*val < '2.5' || *val > '19.5')␊
␉␉␉␉␉return false;␊
␉␉␉␉␊
␉␉␉␉sum = strtof(*val++ - '0');␊
␉␉␉}␊
␉␉␉␊
␉␉␉*value = sum;␊
␉␉␉return true;␊
␉␉}␊
␉}␊
return false;␊
}␊
// valv: getFloatForKey End␊
*/␊
␊
/*␊
*␊
*/␊
␊
int loadSystemConfig(config_file_t *config)␊
{␊
␉char *dirspec[] = {␊
␉␉"bt(0,0)/Extra/com.apple.Boot.plist",␊
␉␉"/Extra/com.apple.Boot.plist",␊
␉␉"bt(0,0)/Extra/com.apple.Boot.plist",␊
␉␉"/Library/Preferences/SystemConfiguration/com.apple.Boot.plist",␊
␉␉"/com.apple.boot.P/Library/Preferences/SystemConfiguration/com.apple.Boot.plist",␊
␉␉"/com.apple.boot.R/Library/Preferences/SystemConfiguration/com.apple.Boot.plist",␊
branches/valv/i386/libsaio/saio_internal.h
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extern bool getValueForKey(const char *key, const char **val, int *size, config_file_t *configBuff);␊
extern const char * getStringForKey(const char * key, config_file_t *config);␊
extern bool getBoolForKey(const char *key, bool *val, config_file_t *configBuff);␊
/*extern bool getFloatForKey(const char *key, float *val, config_file_t *configBuff);*/␊
extern bool getIntForKey(const char *key, int *val, config_file_t *configBuff);␊
extern bool getColorForKey(const char *key, unsigned int *val, config_file_t *configBuff);␊
extern bool␉ getDimensionForKey( const char *key, unsigned int *value, config_file_t *config, unsigned int dimension_max, unsigned int object_size );␊
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printf("after video_mode\n");␊
#endif␊
␊
// Scan and record the system's hardware information.␊
scan_platform();␊
␊
// First get info for boot volume.␊
scanBootVolumes(gBIOSDev, 0);␊
bvChain = getBVChainForBIOSDev(gBIOSDev);␊
// Load boot.plist config file␊
status = loadSystemConfig(&bootInfo->bootConfig);␊
␊
// Scan and record the system's hardware information.␊
scan_platform();␊
␊
if (getBoolForKey(kQuietBootKey, &quiet, &bootInfo->bootConfig) && quiet) {␊
gBootMode |= kBootModeQuiet;␊
}␊
branches/valv/i386/boot2/boot.h
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#define kGUIKey␉␉␉"GUI"␊
#define kBootBannerKey␉␉"Boot Banner"␊
#define kWaitForKeypressKey␉"Wait"␊
/* AsereBLN: added the other keys */␊
/* AsereBLN: added these keys */␊
#define kUseAtiROM␉␉"UseAtiROM"␉␉/* ati.c */␊
#define kWake␉␉␉"Wake"␉␉␉/* boot.c */␊
#define kForceWake␉␉"ForceWake"␉␉/* boot.c */␊
#define kHidePartition␉␉"Hide Partition"␉/* disk.c */␊
#define kRenamePartition␉"Rename Partition"␉/* disk.c */␊
#define kUseMemDetect␉␉"UseMemDetect"␉␉/* platform.c */␊
#define kRestartFix␉␉"RestartFix"␉␉/* dsdt_patcher.c */␊
/* valv: added those keys */␊
#define kFixFSB␉␉"FixFSB"␉␉/* cpu.c */␊
#define kbusratio␉␉"busratio"␉␉/* cpu.c */␊
␊
/*␊
* Flags to the booter or kernel␊
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␉␉␉if (key == 0x1F00) alts = true;␊
␉␉␉if (key == 0x2F00) altv = true;␊
␉␉␉if (key == 0x2D00) altx = true;␊
␉␉␉if (key == 0x0403) x32 = true;␉␊
␉␉␉if (key == 0x0705) x64 = true;␉␉␉␊
␉␉␉if (key == 0x0403) x32 = true;␊
␉␉␉if (key == 0x0705) x64 = true;␊
␉␉}␊
␉␉if (f8) {␊
␉␉␉gBootMode &= ~kBootModeQuiet;␊
␉␉␉*(gBootArgsPtr++) = ' ';␊
␉␉␉*(gBootArgsPtr++) = '-';␊
␉␉␉*(gBootArgsPtr++) = 'f';␊
␉␉}␉␉␊
␉␉}␊
␉␉if ((shiftf) && (gBootArgsPtr + 3 < gBootArgsEnd)) {␊
␉␉␉*(gBootArgsPtr++) = ' ';␊
␉␉␉*(gBootArgsPtr++) = '-';␊
␉␉␉*(gBootArgsPtr++) = ' ';␊
␉␉␉*(gBootArgsPtr++) = '-';␊
␉␉␉*(gBootArgsPtr++) = 's';␊
␉␉}␉␊
␉␉}␊
␉␉if ((altv) && (gBootArgsPtr + 3 < gBootArgsEnd)) {␊
␉␉␉*(gBootArgsPtr++) = ' ';␊
␉␉␉*(gBootArgsPtr++) = '-';␊
␉␉␉*(gBootArgsPtr++) = 'v';␉␉␉␊
␉}␊
␉␉␉*(gBootArgsPtr++) = 'v';␊
␉␉}␊
␉␉if ((altx) && (gBootArgsPtr + 3 < gBootArgsEnd)) {␊
␉␉␉*(gBootArgsPtr++) = ' ';␊
␉␉␉*(gBootArgsPtr++) = '-';␊
␉␉␉*(gBootArgsPtr++) = '3';␊
␉␉␉*(gBootArgsPtr++) = '2';␊
␉␉}␊
␉␉␊
␉␉if ((x64) && (gBootArgsPtr + 5 < gBootArgsEnd)) {␊
␉␉␉*(gBootArgsPtr++) = ' ';␊
␉␉␉*(gBootArgsPtr++) = '-';␊
␉␉int key;␊
␉␉while (readKeyboardStatus()) {␊
␉␉␉key = bgetc ();␊
␉␉␉if (key == 0x4200) f8 = true;␉␉␊
␉␉␉if (key == 0x4200) f8 = true;␊
␉␉}␊
␉␉if (f8) {␊
␉␉␉gBootMode &= ~kBootModeQuiet;␊
␉␉␉timeout = 0;␊
␉␉}␉␉␊
␉␉}␊
␉}␊
#endif␊
␊
␉␉verbose("Scanning device %x...", gBIOSDev);␊
␉}␊
␊
␉// When booting from CD, default to hard drive boot when possible. ␊
␉// When booting from CD, default to hard drive boot when possible.␊
␉if (isCDROM && firstRun) {␊
␉␉const char *val;␊
␉␉char *prompt;␊
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#include <stdbool.h>␊
␊
/*␊
* cpu.c␊
*/␊
/*#define rdmsr46(msr, val1, val2)␉␉␉␉␉\␊
do {␉␉␉␉␉␉␉␉\␊
␉uint64_t val = rdmsr64((msr));␉␉␉\␊
␉(val1) = (uint32_t)val;␉␉␉␉␉\␊
␉(val2) = (uint32_t)(val >> 32);␉␉␉␉\␊
} while (0)*/␊
␊
/*␊
* ctype stuff (aserebln)␊
*/␊
static inline int isupper(char c)␊
extern unsigned long long strtouq(const char *nptr, char ** endptr, int base);␊
␊
/*␊
* strtod.c␊
*/␊
extern double strtod(const char *string, char ** endPtr);␊
␊
/*␊
* prf.c␊
*/␊
extern void prf(const char * fmt, va_list ap, void (*putfn_p)(),␊
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