Chameleon

Chameleon Commit Details

Date:2012-04-05 13:12:36 (12 years 15 days ago)
Author:ErmaC
Commit:1918
Parents: 1917
Message:Merge IVY Bridge stuff from Chimera Branch.
Changes:
M/branches/ErmaC/Trunk/i386/libsaio/cpu.c
M/branches/ErmaC/Trunk/i386/libsaio/platform.h
M/branches/ErmaC/Trunk/i386/libsaio/smbios_getters.c
M/branches/ErmaC/Trunk/i386/libsaio/device_inject.c
M/branches/ErmaC/Trunk/i386/libsa/zalloc.c
M/branches/ErmaC/Trunk/i386/libsaio/cpu.h
M/branches/ErmaC/Trunk/i386/util/bdmesg.c
M/branches/ErmaC/Trunk/i386/libsaio/sys.c
M/branches/ErmaC/Trunk/i386/libsaio/acpi_patcher.c
M/branches/ErmaC/Trunk/i386/libsaio/allocate.c

File differences

branches/ErmaC/Trunk/i386/libsaio/acpi_patcher.c
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␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx␊
␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
␉␉␉␉␉case CPU_MODEL_SANDY:␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉case CPU_MODEL_SANDY_XEON:␉// Intel Xeon E3␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉␉{␊
␉␉␉␉␉␉maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; // Seems it always contains maximum multiplier value (with turbo, that's we need)...␊
␉␉␉␉␉␉minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff;␊
branches/ErmaC/Trunk/i386/libsaio/allocate.c
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{␊
long addr;␊
␊
if (gImageLastKernelAddr == 0) {␊
if (gImageLastKernelAddr == 0)␊
␉{␊
gImageLastKernelAddr = RoundPage( bootArgs->kaddr +␊
bootArgs->ksize );␊
}␊
addr = gImageLastKernelAddr;␊
gImageLastKernelAddr += RoundPage(inSize);␊
␊
if ( gImageLastKernelAddr >= (KERNEL_ADDR + KERNEL_LEN) ) {␊
if ( gImageLastKernelAddr >= (KERNEL_ADDR + KERNEL_LEN) )␊
␉{␊
stop ("AllocateKernelMemory error");␊
}␊
␊
branches/ErmaC/Trunk/i386/libsaio/device_inject.c
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␊
char *efi_inject_get_devprop_string(uint32_t *len)␊
{␊
␉if(string) {␊
␉if(string)␊
␉{␊
␉␉*len = string->length;␊
␉␉return devprop_generate_string(string);␊
␉}␊
␉string = (struct DevPropString*)malloc(sizeof(struct DevPropString));␊
␉␊
␉if(string == NULL)␊
␉{␊
␉␉return NULL;␊
␉}␊
␉␊
␉memset(string, 0, sizeof(struct DevPropString));␊
␉string->length = 12;␊
␉string->WHAT2 = 0x01000000;␊
␉return string;␊
}␊
␊
␊
struct DevPropDevice *devprop_add_device(struct DevPropString *string, char *path)␊
{␊
␉struct DevPropDevice␉*device;␊
␉␉return NULL;␊
␉}␊
␉device = malloc(sizeof(struct DevPropDevice));␊
␊
␉if (!device) {␊
return NULL;␊
}␊
␉if (strncmp(path, pciroot_string, strlen(pciroot_string))) {␊
free(device);␊
␉␉printf("ERROR parsing device path\n");␊
␉␉return NULL;␊
␉}␊
␉int␉␉x, curr = 0;␊
␉char␉buff[] = "00";␊
␊
␉for (x = 0; x < strlen(path); x++) {␊
␉␉if (!strncmp(&path[x], pci_device_string, strlen(pci_device_string))) {␊
␉for (x = 0; x < strlen(path); x++)␊
␉{␊
␉␉if (!strncmp(&path[x], pci_device_string, strlen(pci_device_string)))␊
␉␉{␊
␉␉␉x+=strlen(pci_device_string);␊
␉␉␉curr=x;␊
␉␉␉while(path[++x] != ',');␊
␉␉␉if(x-curr == 2)␊
␉␉␉{␊
␉␉␉␉sprintf(buff, "%c%c", path[curr], path[curr+1]);␊
␉␉␉}␊
␉␉␉else if(x-curr == 1)␊
␉␉␉{␊
␉␉␉␉sprintf(buff, "%c", path[curr]);␊
␉␉␉}␊
␉␉␉else ␊
␉␉␉{␊
␉␉␉␉printf("ERROR parsing device path\n");␊
␉␉␉curr = x;␊
␉␉␉while(path[++x] != ')');␊
␉␉␉if(x-curr == 2)␊
␉␉␉{␊
␉␉␉␉sprintf(buff, "%c%c", path[curr], path[curr+1]);␊
␉␉␉}␊
␉␉␉else if(x-curr == 1)␊
␉␉␉{␊
␉␉␉␉sprintf(buff, "%c", path[curr]);␊
␉␉␉}␊
␉␉␉else␊
␉␉␉{␊
␉␉␉␉printf("ERROR parsing device path\n");␊
␉}␊
␉␊
␉if(!numpaths)␊
␉{␊
free(device);␊
␉␉return NULL;␊
␉}␊
␉␊
␉device->numentries = 0x00;␊
␉␊
␉string->length += device->length;␊
␉␊
␉if(!string->entries)␊
␉{␊
␉␉if((string->entries = (struct DevPropDevice**)malloc(sizeof(device)))== NULL)␊
␉␉␉return 0;␊
␉␉{␊
free(device);␊
␉␉␉return NULL;␊
␉␉}␊
␉}␊
␉␊
␉string->entries[string->numentries++] = (struct DevPropDevice*)malloc(sizeof(device));␊
␉string->entries[string->numentries-1] = device;␊
{␊
␉␊
␉if(!nm || !vl || !len)␊
␉{␊
␉␉return 0;␊
␉}␊
␉␊
␉uint32_t length = ((strlen(nm) * 2) + len + (2 * sizeof(uint32_t)) + 2);␊
␉uint8_t *data = (uint8_t*)malloc(length);␊
␉{␊
␉␉if(!data)␊
␉␉{␊
␉␉␉return 0;␊
␉␉}␊
␉␉␊
␉␉memset(data, 0, length);␊
␉␉uint32_t off= 0;␊
␉␊
␉uint8_t *newdata = (uint8_t*)malloc((length + offset));␊
␉if(!newdata)␊
␉{␊
␉␉return 0;␊
␉}␊
␉if(device->data)␊
␉{␊
␉␉if(offset > 1)␊
␉␉{␊
␉␉␉memcpy(newdata, device->data, offset);␊
␊
␉␉}␊
␉}␊
␉␊
␉memcpy(newdata + offset, data, length);␊
␉␊
␉device->length += length;␊
␉device->numentries++;␊
␉␊
␉if(!device->data)␊
␉{␊
␉␉device->data = (uint8_t*)malloc(sizeof(uint8_t));␊
␉}␊
␉else␊
␉{␊
␉␉free(device->data);␊
␉}␊
␉␊
␉free(data);␊
␉device->data = newdata;␊
␉char *ptr = buffer;␊
␉␊
␉if(!buffer)␊
␉{␊
␉␉return NULL;␊
␉}␊
␊
␉sprintf(buffer, "%08x%08x%04x%04x", dp_swap32(string->length), string->WHAT2,␊
␉␉␉dp_swap16(string->numentries), string->WHAT3);␊
␉␉␊
␉␉buffer += 8;␊
␉␉uint8_t *dataptr = string->entries[i]->data;␊
␉␉for(x = 0; x < (string->entries[i]->length) - (24 + (6 * string->entries[i]->num_pci_devpaths)) ; x++)␊
␉␉for(x = 0; (uint32_t)x < (string->entries[i]->length) - (24 + (6 * string->entries[i]->num_pci_devpaths)) ; x++)␊
␉␉{␊
␉␉␉sprintf(buffer, "%02x", *dataptr++);␊
␉␉␉buffer += 2;␊
void devprop_free_string(struct DevPropString *string)␊
{␊
␉if(!string)␊
␉{␊
␉␉return;␊
␉}␊
␉␊
␉int i;␊
␉for(i = 0; i < string->numentries; i++)␊
␊
int devprop_add_network_template(struct DevPropDevice *device, uint16_t vendor_id)␊
{␊
␉if(!device)␊
␉␉return 0;␊
␉uint8_t builtin = 0x0;␊
␉if((vendor_id != 0x168c) && (builtin_set == 0)) ␊
␉␊
␉if(device)␊
␉{␊
␉␉builtin_set = 1;␊
␉␉builtin = 0x01;␊
␉␉␊
␉␉if((vendor_id != 0x168c) && (builtin_set == 0)) ␊
␉␉{␊
␉␉␉builtin_set = 1;␊
␉␉␉builtin = 0x01;␊
␉␉}␊
␉␉␊
␉␉if(!devprop_add_value(device, "built-in", (uint8_t*)&builtin, 1))␊
␉␉{␊
␉␉␉return 0;␊
␉␉}␊
␉␉␊
␉␉devices_number++;␊
␉␉return 1;␊
␉}␊
␉if(!devprop_add_value(device, "built-in", (uint8_t*)&builtin, 1))␊
␉else␊
␉{␊
␉␉return 0;␊
␉devices_number++;␊
␉return 1;␊
␉}␊
␉␊
}␊
␊
void set_eth_builtin(pci_dt_t *eth_dev)␊
branches/ErmaC/Trunk/i386/libsaio/sys.c
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FSReadFile readFile;␊
BVRef bvr;␊
unsigned long length, length2;␊
␊
␊
// Resolve the boot volume from the file spec.␊
␊
if ((bvr = getBootVolumeRef(fileSpec, &filePath)) == NULL)␊
return -1;␊
␊
␊
*binary = (void *)kLoadAddr;␊
␊
␊
// Read file into load buffer. The data in the load buffer will be␊
// overwritten by the next LoadFile() call.␊
␊
gFSLoadAddress = (void *) LOAD_ADDR;␊
␊
readFile = bvr->fs_readfile;␊
␊
␊
if (readFile != NULL) {␊
// Read the first 4096 bytes (fat header)␊
length = readFile(bvr, (char *)filePath, *binary, 0, 0x1000);␊
ThinFatFile(binary, &length);␊
}␊
}␊
␊
␊
return length;␊
}␊
␊
int read(int fdesc, char * buf, int count)␊
{␊
struct iob * io;␊
␊
␊
if ((io = iob_from_fdesc(fdesc)) == NULL)␊
return (-1);␊
␊
␉␉for ( bvr = chain; bvr; bvr = bvr->next )␊
␉␉␉if ( bvr->part_no == multiboot_partition && bvr->biosdev == gBIOSDev ) ␊
␉␉␉␉return bvr;␊
␉␊
␊
␉/*␊
␉ * Checking "Default Partition" key in system configuration - use format: hd(x,y), the volume UUID or label -␊
␉ * to override the default selection.␊
}␊
free(val);␊
}␊
␉␊
␊
␉/*␊
␉ * Scannig the volume chain backwards and trying to find ␊
␉ * a HFS+ volume with valid boot record signature.␊
␉␉␉&& ! gBIOSBootVolume␊
␉␉␉&& bvr->biosdev == gBIOSDev )␊
␉␉␉bvr2 = bvr;␊
␉} ␊
␉}␊
␉␊
␉␊
␉/*␊
branches/ErmaC/Trunk/i386/libsaio/cpu.c
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␉␉int intelCPU = p->CPU.Model;␊
␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊
␉␉␉/* Nehalem CPU model */␊
␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_FIELDS ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES_32NM ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_NEHALEM_EX ||␊
␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM␉␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_FIELDS␉␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES␉␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES_32NM␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_NEHALEM_EX␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDY ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDY_XEON)) {␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDYBRIDGE ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_JAKETOWN␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE␉)) {␊
␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
␉␉␉␉bus_ratio_max = bitfield(msr, 14, 8);␊
branches/ErmaC/Trunk/i386/libsaio/platform.h
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#define CPU_MODEL_ATOM␉␉␉0x1C␉␉␉// Atom␊
#define CPU_MODEL_FIELDS␉␉0x1E␉␉␉// Lynnfield, Clarksfield, Jasper Forest␊
#define CPU_MODEL_DALES␉␉␉0x1F␉␉␉// Havendale, Auburndale␊
#define CPU_MODEL_DALES_32NM␉0x25␉␉␉// Clarkdale, Arrandale␊
#define CPU_MODEL_SANDY␉␉␉0x2A␉␉␉// Sandy Bridge␊
#define CPU_MODEL_DALES_32NM␉␉0x25␉␉␉// Clarkdale, Arrandale␊
#define CPU_MODEL_SANDYBRIDGE␉␉0x2A␉␉␉// Sandy Bridge␊
#define CPU_MODEL_WESTMERE␉␉0x2C␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊
#define CPU_MODEL_SANDY_XEON␉0x2D␉␉␉// Sandy Bridge Xeon␊
#define CPU_MODEL_NEHALEM_EX␉0x2E␉␉␉// Beckton␊
#define CPU_MODEL_WESTMERE_EX␉0x2F␊
#define CPU_MODEL_JAKETOWN␉␉0x2D␉␉␉// Sandy Bridge-E, Sandy Bridge-EP ␊
#define CPU_MODEL_NEHALEM_EX␉␉0x2E␉␉␉// Beckton␊
#define CPU_MODEL_WESTMERE_EX␉␉0x2F␊
#define CPU_MODEL_IVYBRIDGE␉␉0x3A␉␉␉// Ivy Bridge␊
␊
/* CPU Features */␊
#define CPU_FEATURE_MMX␉␉␉0x00000001␉␉// MMX Instruction Set␊
branches/ErmaC/Trunk/i386/libsaio/cpu.h
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#define CPUID_MODEL_ATOM␉␉28␉// Intel Atom (45nm)␊
#define CPUID_MODEL_FIELDS␉␉30␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
#define CPUID_MODEL_DALES␉␉31␉// Havendale, Auburndale␊
#define CPUID_MODEL_DALES_32NM␉37␉// Intel Core i3, i5 LGA1156 (32nm)␊
#define CPUID_MODEL_SANDY␉␉42␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
#define CPUID_MODEL_WESTMERE␉44␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
#define CPUID_MODEL_NEHALEM_EX␉46␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
#define CPUID_MODEL_WESTMERE_EX␉47␉// Intel Xeon E7␊
#define CPUID_MODEL_DALES_32NM␉␉37␉// Intel Core i3, i5 LGA1156 (32nm)␊
#define CPUID_MODEL_SANDYBRIDGE␉␉42␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
#define CPUID_MODEL_WESTMERE␉␉44␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
#define CPUID_MODEL_JAKETOWN␉␉45␉// Intel Xeon E5 LGA2011 (22nm)␊
#define CPUID_MODEL_NEHALEM_EX␉␉46␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
#define CPUID_MODEL_WESTMERE_EX␉␉47␉// Intel Xeon E7␊
#define CPUID_MODEL_IVYBRIDGE␉␉58␉// Intel Core i5, i7 LGA1155 (22nm)␊
␊
␊
static inline uint64_t rdtsc64(void)␊
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␉␉␉␉{␊
␉␉␉␉␉␉// set external clock to 0 for SANDY␊
␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's. ␊
␉␉␉␉␉case CPU_MODEL_SANDY_XEON: ␊
␉␉␉␉␉case CPU_MODEL_SANDY:␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE: ␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
␉␉␉␉␉␉value->word = 0;␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉default:␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊
␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊
␉␉␉␉␉␉else␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊
␉␉␉␉␉␉else␊
␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊
␉␉␉␉␉␉␉else␊
␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_DALES:␊
␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_SANDY:␉␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
case CPU_MODEL_SANDY_XEON:␉␉␉// Intel Xeon E3␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
␉␉␉␉␉␉␉value->word = 0x0901;␉␉␉// Core i3␊
␉␉␉␉␉␉␉else␊
␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊
␉␉␉␉␉␉value->word = 0x0501;␉␉␉␉// Core i7␊
␉␉␉␉␉␉return true;␊
␉␉␉␉}␊
␉␉␉}␊
␉␉}␊
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smallestSize = 0;␊
bestFit = -1;␊
#endif␊
␊
␊
␉for (i = 0; i < availableNodes; i++)␊
␉{␊
␉␉// find node with equal size, or if not found,␊
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␉const UInt8 *msglog = CFDataGetBytePtr((CFDataRef)bootLog);␍␊
␉if (msglog)␍␊
␉␉printf("%s\n", msglog);␍␊
␍␊
␍␊
CFRelease(bootLog);␍␊
␉return 0;␍␊
}␍␊
␍␊

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Revision: 1918