Chameleon

Chameleon Commit Details

Date:2012-05-03 17:39:07 (11 years 11 months ago)
Author:MacMan
Commit:1930
Parents: 1929
Message:Chimera 1.9.2 changes: Fixed CPU processor speed detection on SandyBridge family CPUs. Fixed invalid FSB speed reported on SandyBridge family CPUs. Fixed reporting of P-States: minimum and maximum on SandyBridge family CPUs. Improved bdmesg output. Added 7 Series and X79 SMbus controller device ids.
Changes:
M/branches/Chimera/i386/libsaio/cpu.c
M/branches/Chimera/i386/libsaio/platform.h
M/branches/Chimera/i386/libsaio/smbios_getters.c
M/branches/Chimera/version
M/branches/Chimera/i386/libsaio/cpu.h
M/branches/Chimera/i386/libsaio/smbios.c
M/branches/Chimera/i386/libsaio/acpi_patcher.c
M/branches/Chimera/i386/libsaio/spd.c

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branches/Chimera/version
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1.9.2␊
branches/Chimera/i386/libsaio/acpi_patcher.c
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␉if (acpi_cpu_count > 0) ␊
␉{␊
␉␉struct p_state initial, maximum, minimum, p_states[32];␊
␉␉uint8_t p_states_count = 0;␉␉␊
␉␉uint8_t p_states_count = 0;␊
␉␉uint64_t msr = 0;␊
␉␉␊
␉␉// Retrieving P-States, ported from code by superhai (c)␊
␉␉switch (Platform.CPU.Family) {␊
␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx␊
␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
␉␉␉␉␉{␊
␉␉␉␉␉␉maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; // Seems it always contains maximum multiplier value (with turbo, that's we need)...␊
␉␉␉␉␉␉minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff;␊
␉␉␉␉␉␉␊
␉␉␉␉␉␉verbose("P-States: min %d, max %d\n", minimum.Control, maximum.Control);␉␉␉␊
␉␉␉␉␉␉␊
␉␉␉␉␉␉// Sanity check␊
␉␉␉␉␉␉if (maximum.Control < minimum.Control) ␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉DBG("Insane control values!");␊
␉␉␉␉␉␉␉p_states_count = 0;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉else␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉uint8_t i;␊
␉␉␉␉␉␉␉p_states_count = 0;␊
␉␉␉␉␉␉␉␊
␉␉␉␉␉␉␉for (i = maximum.Control; i >= minimum.Control; i--) ␊
␉␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉␉p_states[p_states_count].Control = i;␊
␉␉␉␉␉␉␉␉p_states[p_states_count].CID = p_states[p_states_count].Control << 1;␊
␉␉␉␉␉␉␉␉p_states[p_states_count].Frequency = (Platform.CPU.FSBFrequency / 1000000) * i;␊
␉␉␉␉␉␉␉␉p_states_count++;␊
␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉verbose("Number of P-States Generated: %d\n", p_states_count);␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉}␉␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉␉{␊
␉␉␉␉␉␉maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; // Seems it always contains maximum multiplier value (with turbo, that's we need)...␊
␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
␉␉␉␉␉␉initial.Control = bitfield(msr, 15, 8);␊
␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
␉␉␉␉␉␉maximum.Control = bitfield(msr, 15, 8);␊
␉␉␉␉␉␉minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff;␊
␉␉␉␉␉␉␊
␉␉␉␉␉␉verbose("P-States: min 0x%x, max 0x%x\n", minimum.Control, maximum.Control);␉␉␉␊
␉␉␉␉␉␉verbose("P-States: min %d, max %d\n", minimum.Control, maximum.Control);␊
␉␉␉␉␉␉␊
␉␉␉␉␉␉// Sanity check␊
␉␉␉␉␉␉if (maximum.Control < minimum.Control) ␊
␉␉␉␉␉␉␉␉p_states_count++;␊
␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉␊
␉␉␉␉␉␉verbose("Number of P-States Generated: %d\n", p_states_count);␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉}␉␊
␉␉␉␉␉default:␊
␉const char *filename;␊
␉char dirSpec[128];␊
␉int len = 0;␊
␉␊
␉// always reset cpu count to 0 when injecting new acpi␊
␉acpi_cpu_count = 0;␊
␊
␉// Try using the file specified with the DSDT option␊
␉if (getValueForKey(kDSDT, &filename, &len, &bootInfo->chameleonConfig))␊
branches/Chimera/i386/libsaio/spd.c
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␉{0x8086, 0x3A60, "ICH10B",␉␉read_smb_intel },␊
␉{0x8086, 0x3B30, "5 Series",␉read_smb_intel },␊
␉{0x8086, 0x1C22, "6 Series",␉read_smb_intel },␊
␉{0x8086, 0x1E22, "7 Series",␉read_smb_intel },␊
␉{0x8086, 0x1D70, "X79",␉␉␉read_smb_intel },␊
␉{0x8086, 0x5032, "EP80579",␉␉read_smb_intel }␊
␊
};␊
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*/␊
void scan_cpu(PlatformInfo_t *p)␊
{␊
␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊
␉uint64_t␉msr, flex_ratio;␊
␉uint8_t␉␉maxcoef, maxdiv, currcoef, bus_ratio_max, currdiv;␊
␉uint64_t␉tscFrequency = 0;␊
␉uint64_t␉fsbFrequency = 0;␊
␉uint64_t␉cpuFrequency =0;␊
␉uint64_t␉msr = 0;␊
␉uint64_t␉flex_ratio = 0;␊
␉uint32_t␉max_ratio = 0;␊
␉uint32_t␉min_ratio = 0;␊
␉uint8_t␉␉bus_ratio_max = 0;␊
␉uint8_t␉␉bus_ratio_min = 0;␊
␉uint8_t␉␉currdiv = 0;␊
␉uint8_t␉␉currcoef = 0;␊
␉uint8_t␉␉maxdiv = 0;␊
␉uint8_t␉␉maxcoef = 0;␊
␊
␉const char␉*newratio;␊
␉int␉␉␉len, myfsb;␊
␉uint8_t␉␉bus_ratio_min;␊
␉uint32_t␉max_ratio, min_ratio;␊
␉int␉␉␉len = 0;␊
␉␊
␉max_ratio = min_ratio = myfsb = bus_ratio_min = 0;␊
␉maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;␊
␉␊
␉/* get cpuid values */␊
␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
␉}␊
␉␊
␉tscFrequency = measure_tsc_frequency();␊
␉fsbFrequency = 0;␊
␉cpuFrequency = 0;␊
␉␊
␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊
␉␉int intelCPU = p->CPU.Model;␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_JAKETOWN␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE␉)) {␊
␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
␉␉␉␉bus_ratio_max = bitfield(msr, 14, 8);␊
␉␉␉␉bus_ratio_min = bitfield(msr, 46, 40); //valv: not sure about this one (Remarq.1)␊
//␉␉␉␉DBG("MSR_PLATFORM_INFO: 0x%x\n", bitfield(msr, 63, 0));␊
␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␉//MacMan: Changed bitfield to match Apple tsc.c␊
␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40);␉//MacMan: Changed bitfield to match Apple tsc.c␊
␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
//␉␉␉␉DBG("MSR_FLEX_RATIO: 0x%x\n", bitfield(msr, 31, 0));␊
␉␉␉␉if (bitfield(msr, 16, 16)) {␊
␉␉␉␉␉flex_ratio = bitfield(msr, 14, 8);␊
␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊
␉␉␉␉␉ where the cpu multipler can't be changed to␊
␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
␉␉␉␉␉ contents.␉These contents cause mach_kernel to␊
␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊
␉␉␉␉␉ causing the system to crash since tscGranularity␊
␉␉␉␉␉ is inadvertently set to 0.␊
␉␉␉␉␉ */␊
␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␉//MacMan: Changed bitfield to match Apple tsc.c␊
␉␉␉␉␉if (flex_ratio == 0) {␊
␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊
␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
␉␉␉␉␉␉verbose("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
//␉␉␉␉␉␉DBG("Null flex ratio detected. MSR_FLEX_RATIO now: %08x\n", bitfield(msr, 31, 0));␊
␉␉␉␉␉} else {␊
␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊
␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
␉␉␉␉if (bus_ratio_max) {␊
␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
␉␉␉␉}␊
␉␉␉␉//valv: Turbo Ratio Limit␊
␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f)) {␊
␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
␉␉␉␉} else {␊
␉␉␉␉␉cpuFrequency = tscFrequency;␊
␊
␉␉␉␉//MacMan: Turbo Ratio Limit␊
␉␉␉␉switch (intelCPU) ␊
␉␉␉␉{␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx␊
␉␉␉␉␉{␊
␉␉␉␉␉␉cpuFrequency = tscFrequency;␊
␉␉␉␉␉␉DBG("cpu.c (%d)CPU_MODEL_NEHALEM_EX or CPU_MODEL_WESTMERE_EX Found\n", __LINE__);␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉}␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉␉{␊
␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
␉␉␉␉␉␉currcoef = bitfield(msr, 15, 8);␊
␉␉␉␉␉␉cpuFrequency = currcoef * fsbFrequency;␊
␉␉␉␉␉␉maxcoef = bus_ratio_max;␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉}␊
␉␉␉␉␉default:␊
␉␉␉␉␉{␊
␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
␉␉␉␉␉␉currcoef = bitfield(msr, 7, 0);␊
␉␉␉␉␉␉cpuFrequency = currcoef * fsbFrequency;␊
␉␉␉␉␉␉maxcoef = bus_ratio_max;␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉}␊
␉␉␉␉}␊
␉␉␉␉␉␉␊
␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4)) {␊
␉␉␉␉␉max_ratio = atoi(newratio);␊
␉␉␉␉␉max_ratio = (max_ratio * 10);␊
␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
␉␉␉␉␉␊
␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
␉␉␉␉␉DBG("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
␉␉␉␉␉␊
␉␉␉␉␉// extreme overclockers may love 320 ;)␊
␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320)) {␊
␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
␉␉␉␉␉}␊
␉␉␉␉}␊
␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
␉␉␉␉/*if (bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊
␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
␉␉␉␉p->CPU.MinRatio = min_ratio;␊
␊
␉␉␉␉p->CPU.MaxRatio = bus_ratio_max;␊
␉␉␉␉p->CPU.MinRatio = bus_ratio_min;␊
␉␉␉␉␊
␉␉␉␉myfsb = fsbFrequency / 1000000;␊
␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio);␊
␉␉␉␉currcoef = bus_ratio_max;␊
␉␉␉} else {␊
␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
␉␉␉␉DBG("MSR_IA32_PERF_STATUS: 0x%08x\n", bitfield(msr, 31, 0));␊
␉␉␉␉currcoef = bitfield(msr, 12, 8);␊
␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
#endif␊
␉␊
␉p->CPU.MaxCoef = maxcoef;␊
␉p->CPU.MaxDiv = maxdiv;␊
␉if (maxdiv == 0){␊
␉␉p->CPU.MaxDiv = bus_ratio_max;␊
␉}␊
␉else {␊
␉␉p->CPU.MaxDiv = maxdiv;␊
␉}␊
␉p->CPU.CurrCoef = currcoef;␊
␉p->CPU.CurrDiv = currdiv;␊
␉if (currdiv == 0){␊
␉␉p->CPU.CurrDiv = currcoef;␊
␉}␊
␉else {␊
␉␉p->CPU.CurrDiv = currdiv;␊
␉}␊
␉p->CPU.TSCFrequency = tscFrequency;␊
␉p->CPU.FSBFrequency = fsbFrequency;␊
␉p->CPU.CPUFrequency = cpuFrequency;␊
␉␊
␉// keep formatted with spaces instead of tabs␊
␉DBG("CPU: Brand String: %s\n", p->CPU.BrandString);␊
DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊
DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);␊
DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);␊
DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊
DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊
DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊
DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊
DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊
#if DEBUG_CPU␊
␉DBG("CPU: Brand String: %s\n", p->CPU.BrandString);␊
DBG("CPU: Vendor: 0x%x\n",␉␉␉␉ p->CPU.Vendor);␊
␉DBG("CPU: Family / ExtFamily: 0x%x / 0x%x\n",␉␉ p->CPU.Family, p->CPU.ExtFamily);␊
DBG("CPU: Model / ExtModel / Stepping: 0x%x / 0x%x / 0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
DBG("CPU: Number of Cores / Threads: %d / %d\n", p->CPU.NoCores, p->CPU.NoThreads);␊
DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊
DBG("CPU: TSC Frequency: %d MHz\n", p->CPU.TSCFrequency / 1000000);␊
DBG("CPU: FSB Frequency: %d MHz\n", p->CPU.FSBFrequency / 1000000);␊
DBG("CPU: CPU Frequency: %d MHz\n", p->CPU.CPUFrequency / 1000000);␊
␉DBG("CPU: Minimum Bus Ratio: %d\n", p->CPU.MinRatio);␊
DBG("CPU: Maximum Bus Ratio: %d\n", p->CPU.MaxRatio);␊
␉DBG("CPU: Current Bus Ratio: %d\n", p->CPU.CurrCoef);␊
//␉DBG("CPU: Maximum Multiplier: %d\n",␉␉␉␉ p->CPU.MaxCoef);␊
// DBG("CPU: Maximum Divider: %d\n",␉␉␉␉ p->CPU.MaxDiv);␊
//␉DBG("CPU: Current Divider: %d\n",␉␉␉␉ p->CPU.CurrDiv);␊
␊
#if DEBUG_CPU ␊
␉pause();␊
#endif␊
}␊
branches/Chimera/i386/libsaio/platform.h
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#define CPU_MODEL_DALES_32NM␉0x25␉␉␉// Clarkdale, Arrandale␊
#define CPU_MODEL_SANDYBRIDGE␉0x2A␉␉␉// Sandy Bridge␊
#define CPU_MODEL_WESTMERE␉␉0x2C␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊
#define CPU_MODEL_JAKETOWN␉␉0x2D␉␉␉// Sandy Bridge-E, Sandy Bridge-EP ␊
#define CPU_MODEL_JAKETOWN␉␉0x2D␉␉␉// Sandy Bridge-E, Sandy Bridge-EP␊
#define CPU_MODEL_NEHALEM_EX␉0x2E␉␉␉// Beckton␊
#define CPU_MODEL_WESTMERE_EX␉0x2F␊
#define CPU_MODEL_WESTMERE_EX␉0x2F␉␉␉// Westmere-EX␊
#define CPU_MODEL_IVYBRIDGE␉␉0x3A␉␉␉// Ivy Bridge␊
␊
/* CPU Features */␊
branches/Chimera/i386/libsaio/cpu.h
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␊
#define CPU_STRING_UNKNOWN␉␉"Unknown CPU Type"␊
␊
#define␉MSR_IA32_PERF_STATUS␉0x00000198␊
#define MSR_CORE_THREAD_COUNT␉0x35␉// Undocumented. Nehalem and newer only ␊
#define MSR_FLEX_RATIO␉␉␉0x194␉// Undocumented. ␊
#define MSR_IA32_EXT_CONFIG␉␉0xEE␉// Undocumented. Core Solo and Core Duo only␊
#define MSR_PKG_CST_CONFIG_CTL␉0xE2␊
#define␉MSR_IA32_PERF_STATUS␉0x198␊
#define MSR_IA32_PERF_CONTROL␉0x199␊
#define MSR_IA32_EXT_CONFIG␉␉0x00EE␊
#define MSR_FLEX_RATIO␉␉␉0x194␊
#define MSR_IA32_PLATFORM_ID␉0x17␊
#define␉MSR_PLATFORM_INFO␉␉0xCE␊
#define MSR_TURBO_RATIO_LIMIT␉0x1AD␊
#define␉MSR_PLATFORM_INFO␉␉0xCE␊
#define MSR_CORE_THREAD_COUNT␉0x35␉␉␉// Undocumented␊
#define MSR_IA32_PLATFORM_ID␉0x17␊
␊
␊
#define K8_FIDVID_STATUS␉␉0xC0010042␊
#define K10_COFVID_STATUS␉␉0xC0010071␊
␊
branches/Chimera/i386/libsaio/smbios.c
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void addSMBOemProcessorBusSpeed(SMBStructPtrs *structPtr)␊
{␊
␉SMBOemProcessorBusSpeed *p = (SMBOemProcessorBusSpeed *)structPtr->new;␊
␊
␉␊
␉switch (Platform.CPU.Family) ␊
␉{␊
␉␉case 0x06:␊
␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉␉break;␊
␊
␉␉␉␉default:␊
␉␉␉␉default:␉␉␉␉␉␊
␉␉␉␉␉return;␊
␉␉␉}␊
␉␉}␊
branches/Chimera/i386/libsaio/smbios_getters.c
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␉␉␉␉␉␉value->word = qpibusspeed;␊
␉␉␉␉␉␉return true;␊
␉␉␉␉␉}␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉␉{␊
␉␉␉␉␉␉int busspeed;␊
␉␉␉␉␉␉busspeed = 100;␊
␉␉␉␉␉␉value->word = busspeed;␊
␉␉␉␉␉␉return true;␊
␉␉␉␉␉}␊
␉␉␉␉}␊
␉␉␉}␊
␉␉}␊
␊
bool getSMBOemProcessorType(returnType *value)␊
{␊
␉static bool done = false;␉␉␊
␉␉␊
␉value->word = simpleGetSMBOemProcessorType();␊
␊
␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊
␉{␊
␉␉if (!done)␊
␉␉{␊
␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊
␉␉␉done = true;␊
␉␉}␊
␉␉␊
␉␉switch (Platform.CPU.Family) ␊
␉␉{␊
␉␉␉case 0x06:␊
␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊
case CPU_MODEL_JAKETOWN:␉␉␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
case CPU_MODEL_JAKETOWN:␉␉␉// Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊
␉␉␉␉␉␉else␊
␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7, Xeon E3-12xx LGA1155 (32nm)␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
␉␉␉␉␉␉␉value->word = 0x0901;␉␉␉// Core i3␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊
␉␉␉␉␉␉else␊
␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
␉␉␉␉␉␉␉␉value->word = 0x0901;␉␉␉// Core i3␊
␉␉␉␉␉␉else␊
␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊
␉␉␉␉␉␉␉else␊

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