Chameleon

Chameleon Commit Details

Date:2012-05-08 23:34:26 (8 years 3 months ago)
Author:ErmaC
Commit:1953
Parents: 1952
Message:sync with trunk
Changes:
M/branches/ErmaC/Trunk/i386/libsaio/cpu.c
M/branches/ErmaC/Trunk/i386/libsaio/nvidia.c
M/branches/ErmaC/Trunk/i386/boot2/boot.h
M/branches/ErmaC/Trunk/i386/libsaio/cpu.h
M/branches/ErmaC/Trunk/i386/libsaio/smbios.c
M/branches/ErmaC/Trunk/CREDITS
M/branches/ErmaC/Trunk/doc/BootHelp.txt
M/branches/ErmaC/Trunk/i386/libsaio/saio_types.h

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branches/ErmaC/Trunk/i386/libsaio/nvidia.c
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#define PATCH_ROM_FAILED0
#define MAX_NUM_DCB_ENTRIES16
#define TYPE_GROUPED0xff
#define READ_BYTE(rom, offset) (*(u_char *)(rom + offset))
#define READ_LE_SHORT(rom, offset) (READ_BYTE(rom, offset+1) << 8 | READ_BYTE(rom, offset))
#define READ_LE_INT(rom, offset) (READ_LE_SHORT(rom, offset+2) << 16 | READ_LE_SHORT(rom, offset))
#define WRITE_LE_SHORT(data) (((data) << 8 & 0xff00) | ((data) >> 8 & 0x00ff ))
#define WRITE_LE_INT(data) (WRITE_LE_SHORT(data) << 16 | WRITE_LE_SHORT(data >> 16))
extern uint32_t devices_number;
// 12D0 - 12DF
// 12E0 - 12EF
// 12F0 - 12FF
};
#define READ_BYTE(rom, offset) (*(u_char *)(rom + offset))
#define READ_LE_SHORT(rom, offset) (READ_BYTE(rom, offset+1) << 8 | READ_BYTE(rom, offset))
#define READ_LE_INT(rom, offset) (READ_LE_SHORT(rom, offset+2) << 16 | READ_LE_SHORT(rom, offset))
#define WRITE_LE_SHORT(data) (((data) << 8 & 0xff00) | ((data) >> 8 & 0x00ff ))
#define WRITE_LE_INT(data) (WRITE_LE_SHORT(data) << 16 | WRITE_LE_SHORT(data >> 16))
static int patch_nvidia_rom(uint8_t *rom)
{
{
uint32_t connection;
connection = READ_LE_INT(dcbtable,headerlength + recordlength * i);
/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
continue;
return vram_size;
}
static bool checkNvRomSig(uint8_t * aRom){
return aRom != NULL && (aRom[0] == 0x55 && aRom[1] == 0xaa);
}
bool setup_nvidia_devprop(pci_dt_t *nvda_dev)
{
struct DevPropDevice*device;
// Otherwise read bios from card
nvBiosOveride = 0;
// TODO: we should really check for the signature before copying the rom, i think.
// PRAMIN first
// PROM next
// Enable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;
nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];
bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// disable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa)
// PROM first
// Enable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;
nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];
// Valid Signature ?
if (checkNvRomSig(nvRom))
{
// PRAMIN first
nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];
bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);
bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);
DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
else
{
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa)
{
// disable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;
//PRAM next
nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];
if(checkNvRomSig(nvRom))
{
bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);
DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
else
{
// 0xC0000 last
bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa)
if (!checkNvRomSig(rom))
{
printf("ERROR: Unable to locate nVidia Video BIOS\n");
return false;
}
else
{
DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
}
else
{
DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
}
else
{
DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
}
else
{
DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
}//end PRAM check
}//end PROM check
}//end load rom from bios
if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {
printf("ERROR: nVidia ROM Patching Failed!\n");
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);
devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);
devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);
//devprop_add_value(device, "@1,connector-type", connector_type_1, 4); // fixme
//devprop_add_value(device, "@0,display-cfg", display_cfg_0, 4);
//devprop_add_value(device, "@1,display-cfg", display_cfg_1, 4);
devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);
devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);
//add HDMI Audio back to nvidia
//http://forge.voodooprojects.org/p/chameleon/issues/67/
//uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};
//devprop_add_value(device, "@1,connector-type",connector_type_1, 4);
//end Nvidia HDMI Audio
if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit)
{
devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));
}
//add HDMI Audio back to nvidia
doit = false;
//http://forge.voodooprojects.org/p/chameleon/issues/67/
if(getBoolForKey(kEnableHDMIAudio, &doit, &bootInfo->chameleonConfig) && doit){
uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};
devprop_add_value(device, "@1,connector-type",connector_type_1, 4);
}
//end Nvidia HDMI Audio
stringdata = malloc(sizeof(uint8_t) * string->length);
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
branches/ErmaC/Trunk/i386/libsaio/cpu.c
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ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)),
ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))
};
//int_enabled = ml_set_interrupts_enabled(FALSE);
restart:
if (attempts >= 9) // increase to up to 9 attempts.
// This will flash-reboot. TODO: Use tscPanic instead.
set_PIT2(0);// reset timer 2 to be zero
disable_PIT2();// turn off PIT 2
//ml_set_interrupts_enabled(int_enabled);
return intermediate;
}
/*
* DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer
*/
}
tscFrequency = measure_tsc_frequency();
DBG("cpu freq classic = 0x%016llx\n", tscFrequency);
if ( tscFrequency < 1000 )//TEST
/* if usual method failed */
if ( tscFrequency < 1000 )
{
tscFrequency = timeRDTSC() * 20;//measure_tsc_frequency();
// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);
tscFrequency = timeRDTSC() * 20;
}
else{
// DBG("cpu freq timeRDTSC = 0x%016llxn", timeRDTSC() * 20);
}
fsbFrequency = 0;
cpuFrequency = 0;
cpuFrequency = tscFrequency;
DBG("0 ! using the default value for FSB !\n");
}
DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);
#endif
p->CPU.MaxCoef = maxcoef;
branches/ErmaC/Trunk/i386/libsaio/cpu.h
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* bit 0 gates the clock,
* bit 1 gates output to speaker.
*/
inline static void
enable_PIT2(void)
static inline void enable_PIT2(void)
{
/* Enable gate, disable speaker */
__asm__ volatile(
: : : "%al" );
}
inline static void
disable_PIT2(void)
static inline void disable_PIT2(void)
{
/* Disable gate and output to speaker */
__asm__ volatile(
return result;
}
#endif /* !__LIBSAIO_CPU_H */
branches/ErmaC/Trunk/i386/libsaio/smbios.c
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defaultSystemInfo.family= kDefaultiMacFamily;
break;
case CPU_MODEL_SANDYBRIDGE:// Intel Core i3, i5, i7 LGA1155 (32nm)
case CPU_MODEL_IVYBRIDGE:// Intel Core i3, i5, i7 LGA1155 (22nm)
case CPU_MODEL_SANDYBRIDGE:// Intel Core i3, i5, i7 LGA1155 (32nm)
case CPU_MODEL_JAKETOWN:// Intel Core i7, Xeon E5 LGA2011 (32nm)
case CPU_MODEL_IVYBRIDGE:// Intel Core i3, i5, i7 LGA1155 (22nm)
defaultBIOSInfo.version= kDefaultiMacSandyBIOSVersion;
defaultSystemInfo.productName= kDefaultiMacSandy;
defaultSystemInfo.family= kDefaultiMacFamily;
case CPU_MODEL_WESTMERE:// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
case CPU_MODEL_JAKETOWN:// Intel Core i7, Xeon E5 LGA2011 (32nm)
defaultBIOSInfo.version= kDefaultMacProWestmereBIOSVersion;
defaultBIOSInfo.releaseDate= kDefaultMacProWestmereBIOSReleaseDate;
defaultSystemInfo.productName= kDefaultMacProWestmere;
branches/ErmaC/Trunk/i386/libsaio/saio_types.h
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typedef struct Tag Tag, *TagPtr;
typedef struct {
charplist[4096];// buffer for plist
charplist[163840];// buffer for plist
TagPtrdictionary;// buffer for xml dictionary
boolcanOverride;// flag to mark a dictionary can be overriden
} config_file_t;
branches/ErmaC/Trunk/i386/boot2/boot.h
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#define kUseNvidiaROM"UseNvidiaROM"/* nvidia.c */
#define kVBIOS"VBIOS"/* nvidia.c */
#define kHDMI"HDMI"/* nvidia.c */
#define kDcfg0"display_0"/* nvidia.c */
#define kDcfg1"display_1"/* nvidia.c */
#define kEthernetBuiltIn"EthernetBuiltIn"/* pci_setup.c */
#define kGraphicsEnabler"GraphicsEnabler"/* pci_setup.c */
#define kEnableHDMIAudio"EnableHDMIAudio"/*ati.c && nvidia.c */
#define kForceHPET"ForceHPET"/* pci_setup.c */
#define kMD0Image"md0"/* ramdisk.h */
branches/ErmaC/Trunk/CREDITS
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Developers:
----------
zef, Turbo, dfe, netkas, mackerintel, mercurysquad, fassl, Kabyl, Crazor, Dense, Turbo, kaitek, iNDi, munky, JrCs, asereBLN, rekursor, mozodojo, meklort, AnV, valv, AzimutZ, Slice, cosmo1t, cparm
zef, Turbo, dfe, netkas, mackerintel, mercurysquad, fassl, Kabyl, Crazor, Dense, kaitek, iNDi, munky, JrCs, asereBLN, rekursor, mozodojo, meklort, AnV, valv, AzimutZ, Slice, cosmo1t, cparm, Conti
Thanks to:
---------
branches/ErmaC/Trunk/doc/BootHelp.txt
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VBIOS=Yes|No Inject NVIDIA VBIOS into device-properties.
display_0=<value> Inject alternate value of display-cfg into NVDA,Display-A@0 (HEX).
display_1=<value> Inject alternate value of display-cfg into NVDA,Display-B@1 (HEX).
EnableHDMIAudio=Yes Inject HDMI audio for NVIDIA
EthernetBuiltIn=Yes|No Automatic "built-in"=yes device-properties generation
for ethernet interfaces.

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Revision: 1953