Chameleon

Chameleon Commit Details

Date:2012-08-05 14:47:51 (2 years 27 days ago)
Author:armel cadet-petit
Commit:2038
Parents: 2037
Message:Added ivy bridge support to the core (only)
Changes:
M/branches/cparm/i386/libsaio/cpu.c
M/branches/cparm/i386/libsaio/cpuid.h

File differences

branches/cparm/i386/libsaio/cpuid.h
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#define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */
#define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */
#define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */
#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */
#define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */
#define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */
#define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */
#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */
#define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */
#define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */
#define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */
#define CPUID_FEATURE_xAPIC _HBit(21) /* Extended APIC Mode */
#define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */
#define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */
#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */
#define CPUID_FEATURE_AES _HBit(25) /* AES instructions */
#define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */
#define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */
#define CPUID_FEATURE_AVX1_0_HBit(28) /* AVX 1.0 instructions */
#define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */
#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */
#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */
#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */
#define CPUID_FEATURE_AVX1_0_HBit(28) /* AVX 1.0 instructions */
#define CPUID_FEATURE_F16C_HBit(29) /* Float16 convert instructions */
#define CPUID_FEATURE_RDRAND_HBit(30) /* RDRAND instruction */
/*
* Leaf 7, subleaf 0 additional features.
* Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
*/
#define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)/* FS/GS base read/write */
#define CPUID_LEAF7_FEATURE_SMEP _Bit(7)/* Supervisor Mode Execute Protect */
#define CPUID_LEAF7_FEATURE_ENFSTRG _Bit(9)/* ENhanced Fast STRinG copy */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
*/
#define CPUID_MODEL_DALES_32NM0x25/* Clarkdale, Arrandale */
#define CPUID_MODEL_WESTMERE0x2C/* Gulftown, Westmere-EP, Westmere-WS */
#define CPUID_MODEL_WESTMERE_EX0x2F
/* Additional internal models go here */
#define CPUID_MODEL_SANDYBRIDGE0x2A
#define CPUID_MODEL_JAKETOWN0x2D
#define CPUID_MODEL_IVYBRIDGE0x3A
typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
uint64_tcpuid_extfeatures;
uint32_tcpuid_signature;
uint8_t cpuid_brand;
uint8_tcpuid_processor_flag;
uint32_tcache_size[LCACHE_MAX];
uint32_tcache_linesize;
cpuid_thermal_leaf_t*cpuid_thermal_leafp;
cpuid_arch_perf_leaf_t*cpuid_arch_perf_leafp;
cpuid_xsave_leaf_t*cpuid_xsave_leafp;
uint32_tcpuid_leaf7_features;
} i386_cpu_info_t;
branches/cparm/i386/libsaio/cpu.c
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case CPUID_MODEL_NEHALEM_EX:
case CPUID_MODEL_SANDYBRIDGE:
case CPUID_MODEL_JAKETOWN:
case CPUID_MODEL_IVYBRIDGE:
{
msr = rdmsr64(MSR_CORE_THREAD_COUNT);
NoThreads = bitfield((uint32_t)msr, 15, 0);
Model == CPUID_MODEL_NEHALEM_EX ||
Model == CPUID_MODEL_WESTMERE_EX ||
Model == CPUID_MODEL_SANDYBRIDGE ||
Model == CPUID_MODEL_JAKETOWN))
Model == CPUID_MODEL_JAKETOWN ||
Model == CPUID_MODEL_IVYBRIDGE))
{
uint8_tbus_ratio_max = 0;
uint64_tflex_ratio = 0;

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Revision: 2038