Chameleon

Chameleon Commit Details

Date:2012-11-20 21:21:54 (6 years 6 months ago)
Author:ErmaC
Commit:2129
Parents: 2128
Message:Sync with trunk. Merge dmazar's patch for Resolution module (Core processors) http://forum.voodooprojects.org/index.php/topic,2754.0.html Few SubIDs for 10DE0FC6.
Changes:
M/branches/ErmaC/Trunk/i386/libsa/libsa.h
M/branches/ErmaC/Trunk/i386/libsaio/fake_efi.c
M/branches/ErmaC/Trunk/i386/libsaio/nvidia.c
M/branches/ErmaC/Trunk/i386/modules/Resolution/915resolution.c
M/branches/ErmaC/Trunk/i386/modules/Resolution/edid.c
M/branches/ErmaC/Trunk/i386/modules/Resolution/915resolution.h

File differences

branches/ErmaC/Trunk/i386/libsaio/nvidia.c
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// 0FC0 - 0FCF
{ 0x10DE0FC2,0x103C0936,"HP GeForce GT 630" },
{ 0x10DE0FC2,0x174B0630,"PC Panther GeForce GT 630" },
{ 0x10DE0FC6,0x10B00FC6,"Gainward GeForce GTX 650" },
{ 0x10DE0FC6,0x10DE0973,"nVidia GeForce GTX 650" },
{ 0x10DE0FC6,0x14583553,"Gigabyte GeForce GTX 650" },
{ 0x10DE0FC6,0x14583555,"Gigabyte GeForce GTX 650" },
{ 0x10DE0FC6,0x15690FC6,"Palit GeForce GTX 650" },
{ 0x10DE0FC6,0x19DA1288,"Zotac GeForce GTX 650" },
// 0FD0 - 0FDF
{ 0x10DE0FD1,0x10280552,"Dell GeForce GT 650M" },
{ 0x10DE0FD1,0x10280566,"Dell GeForce GT 650M" },
{ 0x10DE11BE,0x15587102,"Clevo Quadro K3000M" },
// 11C0 - 11CF
{ 0x10DE11C0,0x10DE0995,"Inno3D GeForce GTX660" },
{ 0x10DE11C6,0x10DE1016,"nVidia GeForce GTX 650 Ti" },
{ 0x10DE11C6,0x156911C6,"Palit GeForce GTX 650 Ti" },
// 11D0 - 11DF
// 11E0 - 11EF
// 11F0 - 11FF
{ 0x10DE0840,NV_SUB_IDS,"GeForce 8200M" },
{ 0x10DE0844,NV_SUB_IDS,"GeForce 9100M G" },
{ 0x10DE0845,NV_SUB_IDS,"GeForce 8200M G" },
{ 0x10DE0846,NV_SUB_IDS,"GeForce 9200" },
{ 0x10DE0846,NV_SUB_IDS,"GeForce 9200" }, // Tesla M2050 ??
{ 0x10DE0847,NV_SUB_IDS,"GeForce 9100" },
{ 0x10DE0848,NV_SUB_IDS,"GeForce 8300" },
{ 0x10DE0849,NV_SUB_IDS,"GeForce 8200" },
{ 0x10DE087A,NV_SUB_IDS,"GeForce 9400" },
{ 0x10DE087D,NV_SUB_IDS,"ION 9400M" },
{ 0x10DE087E,NV_SUB_IDS,"ION LE" },
{ 0x10DE087F,NV_SUB_IDS,"ION LE" },
{ 0x10DE087F,NV_SUB_IDS,"ION LE" }, // Tesla M2070-Q ??
// 0880 - 088F
// 0890 - 089F
// 08A0 - 08AF
// 0FF0 - 0FFF
{ 0x10DE0FFB,NV_SUB_IDS,"Quadro K2000M" },
{ 0x10DE0FFC,NV_SUB_IDS,"Quadro K1000M" },
{ 0x10DE0FFD,NV_SUB_IDS,"NVS 510" },
{ 0x10DE0FFF,NV_SUB_IDS,"Quadro 410" },
// 1000 - 100F
// 1010 - 101F
branches/ErmaC/Trunk/i386/libsaio/fake_efi.c
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/*
* Copyright 2007 David F. Elliott. All rights reserved.
*/
#include "saio_types.h"
#include "libsaio.h"
#include "boot.h"
#include "bootstruct.h"
struct fake_efi_pages *fakeEfiPages = (struct fake_efi_pages*)AllocateKernelMemory(sizeof(struct fake_efi_pages));
// Zero out all the tables in case fields are added later
bzero(fakeEfiPages, sizeof(struct fake_efi_pages));
//bzero(fakeEfiPages, sizeof(struct fake_efi_pages));
// --------------------------------------------------------------------
// Initialize some machine code that will return EFI_UNSUPPORTED for
struct fake_efi_pages *fakeEfiPages = (struct fake_efi_pages*)AllocateKernelMemory(sizeof(struct fake_efi_pages));
// Zero out all the tables in case fields are added later
bzero(fakeEfiPages, sizeof(struct fake_efi_pages));
//bzero(fakeEfiPages, sizeof(struct fake_efi_pages));
// --------------------------------------------------------------------
// Initialize some machine code that will return EFI_UNSUPPORTED for
branches/ErmaC/Trunk/i386/modules/Resolution/915resolution.c
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void patchVideoBios()
{
{
UInt32 x = 0, y = 0, bp = 0;
verbose("Resolution:\n");
getResolution(&x, &y, &bp);
verbose("getResolution: %dx%dx%d\n", (int)x, (int)y, (int)bp);
if (x != 0 &&
y != 0 &&
}
static const UInt8 nvda_pattern[] = {
0x44, 0x01, 0x04, 0x00
};
static const char nvda_string[] = "NVID";
/* Copied from 915 resolution created by steve tomljenovic
*
* This code is based on the techniques used in :
type = CT_GM45;
break;
//
// Core processors
// http://pci-ids.ucw.cz/read/PC/8086
//
case 0x00408086: // Core Processor DRAM Controller
case 0x00448086: // Core Processor DRAM Controller
case 0x00488086: // Core Processor DRAM Controller
case 0x00698086: // Core Processor DRAM Controller
case 0x01008086: // 2nd Generation Core Processor Family DRAM Controller
case 0x01048086: // 2nd Generation Core Processor Family DRAM Controller
case 0x01088086: // Xeon E3-1200 2nd Generation Core Processor Family DRAM Controller
case 0x010c8086: // Xeon E3-1200 2nd Generation Core Processor Family DRAM Controller
case 0x01508086: // 3rd Generation Core Processor Family DRAM Controller
case 0x01548086: // 3rd Generation Core Processor Family DRAM Controller
case 0x01588086: // 3rd Generation Core Processor Family DRAM Controller
case 0x015c8086: // 3rd Generation Core Processor Family DRAM Controller
verbose(" core proc identified\n");
type = CT_CORE_PROC;
break;
default:
if((id & 0x0000FFFF) == 0x00008086) // Intel chipset
if (map->chipset == CT_UNKNOWN)
{
//verbose("Unknown chipset type.\n");
verbose(" Unknown chipset type: %08x.\n", map->chipset_id);
//verbose("915resolution only works with Intel 800/900 series graphic chipsets.\n");
//verbose("Chipset Id: %x\n", map->chipset_id);
close_vbios(map);
return 0;
}
else
{
verbose(" Detected chipset/proc id (DRAM controller): %08x\n", map->chipset_id);
}
verbose(" VBios: ");
/*
* Map the video bios to memory
*/
map->ati_tables.AtomRomHeader = (ATOM_ROM_HEADER *) (map->bios_ptr + *(unsigned short *) (map->bios_ptr + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER));
if (strcmp ((char *) map->ati_tables.AtomRomHeader->uaFirmWareSignature, "ATOM") == 0)
{
verbose("ATI");
// ATI Radeon Card
map->bios = BT_ATI_1;
}
map->mode_table_size = std_vesa->sHeader.usStructureSize - sizeof(ATOM_COMMON_TABLE_HEADER);
if (!detect_ati_bios_type(map)) map->bios = BT_ATI_2;
if (!detect_ati_bios_type(map))
{
map->bios = BT_ATI_2;
}
if (map->bios == BT_ATI_1)
{
verbose(", BT_ATI_1\n");
}
else
{
verbose(", BT_ATI_2\n");
}
}
else {
else
{
/*
* check if we have NVIDIA
&& (map->bios_ptr[i+2] == 'I')
&& (map->bios_ptr[i+3] == 'D'))
{
map->bios = BT_NVDA;
unsigned short nv_data_table_offset = 0;
unsigned short * nv_data_table;
NV_VESA_TABLE * std_vesa;
verbose("nVidia\n");
map->bios = BT_NVDA;
int i = 0;
while (i < 0x300)
{ //We don't need to look for the table in the whole bios, the 768 first bytes only
if ((map->bios_ptr[i] == 0x44)
/*
* Figure out where the mode table is
*/
if ((map->bios != BT_ATI_1) && (map->bios != BT_NVDA))
if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))
{
char* p = map->bios_ptr + 16;
char* limit = map->bios_ptr + VBIOS_SIZE - (3 * sizeof(vbios_mode));
verbose("Other");
while (p < limit && map->mode_table == 0)
{
vbios_mode * mode_ptr = (vbios_mode *) p;
if (map->mode_table == 0)
{
verbose(", mode table not found");
close_vbios(map);
return 0;
}
else
{
verbose(", mode_table: 0x%p", map->mode_table);
}
}
map->mode_table_size++;
mode_ptr++;
}
verbose(", mode_table_size: 0x%x", map->mode_table_size);
}
/*
if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type3)))
{
map->bios = BT_3;
verbose(", BT_3\n");
}
else if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type2)))
{
map->bios = BT_2;
verbose(", BT_2\n");
}
else if (detect_bios_type(map, FALSE, sizeof(vbios_resolution_type1)))
{
map->bios = BT_1;
verbose(", BT_1\n");
}
else {
verbose(" - unknown\n");
return 0;
}
}
case CT_G31:
case CT_500:
case CT_3150:
case CT_UNKNOWN_INTEL:// Assume newer intel chipset is the same as before
outl(CONFIG_MECH_ONE_ADDR, 0x80000090);
map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);
map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);
outb(CONFIG_MECH_ONE_DATA + 1, 0x33);
outb(CONFIG_MECH_ONE_DATA + 2, 0x33);
break;
case CT_CORE_PROC: // Core procs - PAM regs are 80h - 86h
case CT_UNKNOWN_INTEL:// Assume newer intel chipset is the same as before
outl(CONFIG_MECH_ONE_ADDR, 0x80000080);
map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);
map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);
outl(CONFIG_MECH_ONE_ADDR, 0x80000080);
outb(CONFIG_MECH_ONE_DATA + 1, 0x33);
outb(CONFIG_MECH_ONE_DATA + 2, 0x33);
break;
default:
break;
}
case CT_G31:
case CT_500:
case CT_3150:
case CT_UNKNOWN_INTEL:
outl(CONFIG_MECH_ONE_ADDR, 0x80000090);
outb(CONFIG_MECH_ONE_DATA + 1, map->b1);
outb(CONFIG_MECH_ONE_DATA + 2, map->b2);
break;
case CT_CORE_PROC:
case CT_UNKNOWN_INTEL:
outl(CONFIG_MECH_ONE_ADDR, 0x80000080);
outb(CONFIG_MECH_ONE_DATA + 1, map->b1);
outb(CONFIG_MECH_ONE_DATA + 2, map->b2);
default:
break;
}
if(!edidInfo) return 1;
//Slice
if(!fb_parse_edid((struct EDID *)edidInfo, mode))
if(!fb_parse_edid((struct EDID *)edidInfo, mode) || !mode->h_active)
{
free( edidInfo );
return 1;
*/
free( edidInfo );
if(!mode->h_active) return 1;
if(!mode->h_active)
{
return 1;
}
return 0;
}
vfreq = vbl * freq;
hbl = 16 * (int)(x * (30.0 - 300000.0 / vfreq) /
+ (70.0 + 300000.0 / vfreq) / 16.0 + 0.5);
*vsyncstart = y;
*vsyncend = y + 3;
*vblank = vbl - 1;
//for (i=0; i < map->mode_table_size; i++) {
//if (map->mode_table[0].mode == mode) {
verbose(" Patching: ");
switch(map->bios) {
case BT_INTEL:
verbose("BT_INTEL - not supported\n");
return;
case BT_1:
{
verbose("BT_1 patched.\n");
vbios_resolution_type1 * res = map_type1_resolution(map, map->mode_table[i].resolution);
if (bp) {
if (bp)
{
map->mode_table[i].bits_per_pixel = bp;
}
res->y2 = (vtotal?(((vtotal-y) >> 8) & 0x0f) : (res->y2 & 0x0f)) | ((y >> 4) & 0xf0);
res->y1 = (y & 0xff);
if (htotal)
{
res->x_total = ((htotal-x) & 0xff);
}
if (vtotal)
{
res->y_total = ((vtotal-y) & 0xff);
}
break;
}
case BT_2:
&modeline->vsyncend, &modeline->vblank);
if (htotal)
{
modeline->htotal = htotal;
}
else
{
modeline->htotal = modeline->hblank;
}
if (vtotal)
{
modeline->vtotal = vtotal;
}
else
{
modeline->vtotal = modeline->vblank;
}
}
}
verbose("BT_1 patched.\n");
break;
}
case BT_3:
&modeline->hblank, &modeline->vsyncstart,
&modeline->vsyncend, &modeline->vblank);
if (htotal)
{
modeline->htotal = htotal;
}
else
{
modeline->htotal = modeline->hblank;
}
if (vtotal)
{
modeline->vtotal = vtotal;
}
else
{
modeline->vtotal = modeline->vblank;
}
modeline->timing_h = y-1;
modeline->timing_v = x-1;
}
}
verbose("BT_3 patched.\n");
break;
}
case BT_ATI_1:
{
verbose("BT_ATI_1");
edid_mode mode;
ATOM_MODE_TIMING *mode_timing = (ATOM_MODE_TIMING *) map->ati_mode_table;
//if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {
if (!getMode(&mode)) {
//if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force){
if (!getMode(&mode))
{
verbose("\n Edid detailed timing descriptor found: %dx%d\n vbios mode 0 patched!\n", mode.h_active, mode.v_active);
mode_timing->usCRTC_H_Total = mode.h_active + mode.h_blanking;
mode_timing->usCRTC_H_Disp = mode.h_active;
mode_timing->usCRTC_H_SyncStart = mode.h_active + mode.h_sync_offset;
mode_timing->usPixelClock = mode.pixel_clock;
}
else
{
verbose(" Edid not found or invalid - vbios not patched!\n");
}
/*else
{
vbios_modeline_type2 modeline;
}
case BT_ATI_2:
{
verbose("BT_ATI_2");
edid_mode mode;
ATOM_DTD_FORMAT *mode_timing = (ATOM_DTD_FORMAT *) map->ati_mode_table;
/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/
if (!getMode(&mode)) {
verbose("\n Edid detailed timing descriptor found: %dx%d\n vbios mode 0 patched!\n", mode.h_active, mode.v_active);
mode_timing->usHBlanking_Time = mode.h_blanking;
mode_timing->usHActive = mode.h_active;
mode_timing->usHSyncOffset = mode.h_sync_offset;
mode_timing->usPixClk = mode.pixel_clock;
}
else
{
verbose(" Edid not found or invalid - vbios not patched!\n");
}
/*else
{
vbios_modeline_type2 modeline;
&modeline.vsyncend, &modeline.vblank, 0);
mode_timing->usHBlanking_Time = modeline.hblank;
+mode_timing->usHActive = x;
+mode_timing->usHSyncOffset = modeline.hsyncstart - x;
+mode_timing->usHSyncWidth = modeline.hsyncend - modeline.hsyncstart;
+
+mode_timing->usVBlanking_Time = modeline.vblank;
+mode_timing->usVActive = y;
+mode_timing->usVSyncOffset = modeline.vsyncstart - y;
+mode_timing->usVSyncWidth = modeline.hsyncend - modeline.hsyncstart;
+
+mode_timing->usPixClk = modeline.clock;
+}*/
mode_timing->usHActive = x;
mode_timing->usHSyncOffset = modeline.hsyncstart - x;
mode_timing->usHSyncWidth = modeline.hsyncend - modeline.hsyncstart;
mode_timing->usVBlanking_Time = modeline.vblank;
mode_timing->usVActive = y;
mode_timing->usVSyncOffset = modeline.vsyncstart - y;
mode_timing->usVSyncWidth = modeline.hsyncend - modeline.hsyncstart;
mode_timing->usPixClk = modeline.clock;
}*/
break;
}
case BT_NVDA:
{
verbose("BT_NVDA");
edid_mode mode;
NV_MODELINE *mode_timing = (NV_MODELINE *) map->nv_mode_table;
/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/
if (!getMode(&mode)) {
if (!getMode(&mode))
{
verbose("\n Edid detailed timing descriptor found: %dx%d\n vbios mode %d patched!\n", mode.h_active, mode.v_active, i);
mode_timing[i].usH_Total = mode.h_active + mode.h_blanking;
mode_timing[i].usH_Active = mode.h_active;
mode_timing[i].usH_SyncStart = mode.h_active + mode.h_sync_offset;
mode_timing[i].usPixel_Clock = mode.pixel_clock;
}
else
{
verbose(" Edid not found or invalid - vbios not patched!\n");
}
/*else
{
vbios_modeline_type2 modeline;
}
case BT_UNKNOWN:
{
verbose(" Unknown - vbios not patched\n");
break;
}
default:
branches/ErmaC/Trunk/i386/modules/Resolution/edid.c
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all_null |= edid[i];
}
if (csum == 0x00 && all_null) {
if (csum == 0x00 && all_null)
{
/* checksum passed, everything's good */
err = 1;
}
else
{
msglog(" edid_checksum error ");
}
return err;
}
err = 0;
}
if (err == 0)
{
msglog(" edid_check_header error ");
}
return err;
}
//------------------------------------------------------------------------
int edid_is_timing_block(unsigned char *block)
{
if ((block[0] != 0x00) || (block[1] != 0x00) ||
(block[2] != 0x00) || (block[4] != 0x00))
if ((block[0] != 0x00) || (block[1] != 0x00) || (block[2] != 0x00) || (block[4] != 0x00))
{
return 1;
}
else
{
return 0;
}
}
//----------------------------------------------------------------------------------
{
int i;
unsigned char *block;
msglog(" Parse Edid:");
if(!verifyEDID((unsigned char *)edid))
{
msglog(" error\n");
return 0;
}
if(!verifyEDID((unsigned char *)edid)) return 1;
block = (unsigned char *)edid + DETAILED_TIMING_DESCRIPTIONS_START; //54
for (i = 0; i < 4; i++, block += DETAILED_TIMING_DESCRIPTION_SIZE) {
if (edid_is_timing_block(block)) {
msglog(" descriptor block %d is timing descriptor ", i);
var->h_active = H_ACTIVE;
var->v_active = V_ACTIVE;
var->h_sync_offset = H_SYNC_OFFSET;
var->h_blanking = H_BLANKING;
var->v_blanking = V_BLANKING;
var->pixel_clock = PIXEL_CLOCK;
var->h_sync_width = H_SYNC_WIDTH;
var->v_sync_offset = V_SYNC_OFFSET;
var->v_sync_width = V_SYNC_WIDTH;
/*
var->xres = var->xres_virtual = H_ACTIVE;
void getResolution(UInt32* x, UInt32* y, UInt32* bp)
{
//int val;
static UInt32 xResolution, yResolution, bpResolution;
static UInt32 xResolution, yResolution, bpResolution = 32;// assume 32bits
/*
if(getIntForKey(kScreenWidth, &val, &bootInfo->chameleonConfig))
{
yResolution = val;
}
*/
bpResolution = 32;// assume 32bits
if(!xResolution || !yResolution || !bpResolution)
{
char* edidInfo = readEDID();
if(!edidInfo) return;
edid_mode mode;
// TODO: check *all* resolutions reported and either use the highest, or the native resolution (if there is a flag for that)
//xResolution = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);
*y = yResolution;
*bp = bpResolution;
msglog("Best mode: %dx%dx%d\n", *x, *y, *bp);
}
char* readEDID()
bzero( edidInfo, EDID_BLOCK_SIZE);
status = getEDID(edidInfo, blocks_left);
/*
msglog("Buffer location: 0x%X status: %d\n", SEG(edidInfo) << 16 | OFF(edidInfo), status);
int j, i;
for (j = 0; j < 8; j++) {
for(i = 0; i < 16; i++) msglog("0x%02X ", edidInfo[((i+1) * (j + 1)) - 1]);
for(i = 0; i < 16; i++) msglog(" 0x%02X", edidInfo[((i+1) * (j + 1)) - 1]);
msglog("\n");
}
*/
if(status == 0)
{
//if( edidInfo[0] == 0x00 || edidInfo[0] == 0xFF)
{
blocks_left--;
int reported = edidInfo[ EDID_V1_BLOCKS_TO_GO_OFFSET ];
if ( reported > blocks_left )
{
msglog("EDID claims %d more blocks left\n", reported);
}
)
{
msglog("Last reported %d\n", last_reported);
msglog( "EDID blocks left is wrong.\n"
msglog("EDID blocks left is wrong.\n"
"Your EDID is probably invalid.\n");
return 0;
}
return 0;
}
}
blocks_left = 0;
blocks_left = 0;
} while(blocks_left);
char* ret = malloc(sizeof(edidInfo));
int getEDID( void * edidBlock, UInt8 block)
{
biosBuf_t bb;
bzero(&bb, sizeof(bb));
bb.intno = 0x10;
bb.eax.rr = 0x4F15;
bb.intno = 0x10;
bb.eax.rr = 0x4F15;
bb.ebx.r.l= 0x01;
bb.edx.rr = block;
bb.es = SEG( edidBlock );
bb.edi.rr = OFF( edidBlock );
bios( &bb );
return(bb.eax.r.h);
bb.es = SEG( edidBlock );
bb.edi.rr = OFF( edidBlock );
bios( &bb );
return(bb.eax.r.h);
}
branches/ErmaC/Trunk/i386/modules/Resolution/915resolution.h
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CT_915G, CT_915GM, CT_945G, CT_945GM, CT_945GME, CT_946GZ,
CT_955X, CT_G965, CT_Q965, CT_965GM, CT_975X,
CT_P35, CT_X48, CT_B43, CT_Q45, CT_P45,
CT_GM45, CT_G41, CT_G31, CT_G45, CT_500, CT_3150
CT_GM45, CT_G41, CT_G31, CT_G45, CT_500, CT_3150,
CT_CORE_PROC
} chipset_type;
typedef struct {
char *base;
ATOM_ROM_HEADER *AtomRomHeader;
unsigned short *MasterCommandTables;
unsigned short *MasterDataTables;
char*base;
ATOM_ROM_HEADER*AtomRomHeader;
unsigned short*MasterCommandTables;
unsigned short*MasterDataTables;
} bios_tables_t;
typedef struct {
UInt16 hsyncstart;
UInt16 hsyncend;
UInt16 y1;
UInt16 vtotal;
UInt16 y2;
UInt16 vtotal;
UInt16 y2;
UInt16 vblank;
UInt16 vsyncstart;
UInt16 vsyncend;
typedef struct {
unsigned char unknown[6];
vbios_modeline_type3 modelines[];
vbios_modeline_type3 modelines[];
} __attribute__((packed)) vbios_resolution_type3;
typedef struct {
UInt8 unlocked;
} vbios_map;
vbios_map * open_vbios(chipset_type);
void close_vbios (vbios_map*);
void unlock_vbios(vbios_map*);
branches/ErmaC/Trunk/i386/libsa/libsa.h
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#ifndef bzero
extern void bzero(void * dst, size_t len);
extern void __bzero(void * dst, size_t len);
#else
#error bzero is defined.
#endif
extern void * memset(void * dst, int c, size_t n);

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Revision: 2129