Chameleon

Chameleon Commit Details

Date:2014-01-27 16:07:02 (5 years 8 months ago)
Author:ErmaC
Commit:2349
Parents: 2348
Message:merge CPU header define from xnu source for future use.
Changes:
M/trunk/i386/libsaio/smbios.h
M/trunk/i386/libsaio/acpi_patcher.c
M/trunk/i386/libsaio/smbios_getters.c
M/trunk/i386/libsaio/cpu.h
M/trunk/i386/libsaio/smbios.c
M/trunk/i386/libsaio/smbios_decode.c

File differences

trunk/i386/libsaio/acpi_patcher.c
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return tableAddr;
}
close (fd);
printf("Couldn't allocate memory for table \n", dirspec);
verbose("Couldn't allocate memory for table \n", dirspec);
}
//printf("Couldn't find table %s\n", filename);
return NULL;
verbose("Found ACPI CPU: %c%c%c%c\n", acpi_cpu_name[acpi_cpu_count][0], acpi_cpu_name[acpi_cpu_count][1], acpi_cpu_name[acpi_cpu_count][2], acpi_cpu_name[acpi_cpu_count][3]);
if (++acpi_cpu_count == 32)
{
if (++acpi_cpu_count == 32) {
return;
}
}
aml_add_byte(pack, cstates_count);
AML_CHUNK* tmpl = aml_add_package(pack);
if (cst_using_systemio)
{
if (cst_using_systemio) {
// C1
resource_template_register_fixedhw[8] = 0x00;
resource_template_register_fixedhw[9] = 0x00;
verbose ("SSDT with CPU C-States generated successfully\n");
return ssdt;
}
else
{
} else {
verbose ("ACPI CPUs not found: C-States not generated !!!\n");
}
DBG("P-States: Insane FID values!");
p_states_count = 0;
} else {
uint8_t vidstep;
uint8_t i = 0, u, invalid = 0;
// Finalize P-States
// Find how many P-States machine supports
p_states_count = maximum.CID - minimum.CID + 1;
p_states_count = (uint8_t)(maximum.CID - minimum.CID + 1);
if (p_states_count > 32) {
p_states_count = 32;
}
uint8_t vidstep;
uint8_t i = 0, u, invalid = 0;
vidstep = ((maximum.VID << 2) - (minimum.VID << 2)) / (p_states_count - 1);
for (u = 0; u < p_states_count; u++) {
i = u - invalid;
p_states[i].CID = maximum.CID - u;
p_states[i].FID = (p_states[i].CID >> 1);
p_states[i].FID = (uint8_t)(p_states[i].CID >> 1);
if (p_states[i].FID < 0x6) {
if (cpu_dynamic_fsb) {
if (i && p_states[i].FID == p_states[i-1].FID) {
invalid++;
}
p_states[i].VID = ((maximum.VID << 2) - (vidstep * u)) >> 2;
uint32_t multiplier = p_states[i].FID & 0x1f;// = 0x08
bool half = p_states[i].FID & 0x40;// = 0x01
bool dfsb = p_states[i].FID & 0x80;// = 0x00
uint32_t fsb = Platform.CPU.FSBFrequency / 1000000; // = 400
uint32_t fsb = (uint32_t)(Platform.CPU.FSBFrequency / 1000000); // = 400
uint32_t halffsb = (fsb + 1) >> 1;// = 200
uint32_t frequency = (multiplier * fsb);// = 3200
p_states[i].Frequency = (frequency + (half * halffsb)) >> dfsb;// = 3200 + 200 = 3400
p_states[i].Frequency = (uint32_t)(frequency + (half * halffsb)) >> dfsb;// = 3200 + 200 = 3400
}
p_states_count -= invalid;
case CPU_MODEL_HASWELL://
case CPU_MODEL_IVYBRIDGE_XEON: //
//case CPU_MODEL_HASWELL_H://
case CPU_MODEL_HASWELL_MB://
case CPU_MODEL_HASWELL_SVR://
case CPU_MODEL_HASWELL_ULT://
case CPU_MODEL_CRYSTALWELL://
{
if ((Platform.CPU.Model == CPU_MODEL_SANDYBRIDGE) || (Platform.CPU.Model == CPU_MODEL_JAKETOWN) ||
(Platform.CPU.Model == CPU_MODEL_IVYBRIDGE) || (Platform.CPU.Model == CPU_MODEL_HASWELL) ||
(Platform.CPU.Model == CPU_MODEL_IVYBRIDGE_XEON) || (Platform.CPU.Model == CPU_MODEL_HASWELL_MB) ||
(Platform.CPU.Model == CPU_MODEL_IVYBRIDGE_XEON) || (Platform.CPU.Model == CPU_MODEL_HASWELL_SVR) ||
(Platform.CPU.Model == CPU_MODEL_HASWELL_ULT) || (Platform.CPU.Model == CPU_MODEL_CRYSTALWELL))
{
maximum.Control = (rdmsr64(MSR_IA32_PERF_STATUS) >> 8) & 0xff;
break;
}
default:
verbose ("Unsupported CPU: P-States not generated !!! Unknown CPU Type\n");
verbose ("Unsupported CPU (0x%X): P-States not generated !!!\n", Platform.CPU.Family);
break;
}
}
AML_CHUNK* root = aml_create_node(NULL);
aml_add_buffer(root, ssdt_header, sizeof(ssdt_header)); // SSDT header
AML_CHUNK* scop = aml_add_scope(root, "\\_PR_");
AML_CHUNK* name = aml_add_name(scop, "PSS_");
AML_CHUNK* pack = aml_add_package(name);
ssdt->Length = root->Size;
ssdt->Checksum = 0;
ssdt->Checksum = 256 - checksum8(ssdt, ssdt->Length);
ssdt->Checksum = 256 - (uint8_t)(checksum8(ssdt, ssdt->Length));
aml_destroy_node(root);
{
extern void setupSystemType();
struct acpi_2_fadt *fadt_mod;
struct acpi_2_fadt *fadt_mod = NULL;
bool fadt_rev2_needed = false;
bool fix_restart;
bool fix_restart_ps2;
DBG("New @%x,%x\n",fadt_mod->DSDT,fadt_mod->X_DSDT);
verbose("FADT: Using custom DSDT!\n");
DBG("FADT: Using custom DSDT!\n");
}
// Correct the checksum
//addConfigurationTable(&gEfiAcpiTableGuid, getAddressOfAcpiTable(), "ACPI");
//addConfigurationTable(&gEfiAcpi20TableGuid, getAddressOfAcpi20Table(), "ACPI_20");
/* XXX aserebln why uint32 cast if pointer is uint64 ? */
acpi10_p = (uint32_t)getAddressOfAcpiTable();
acpi20_p = (uint32_t)getAddressOfAcpi20Table();
acpi10_p = (uint64_t)(uint32_t)getAddressOfAcpiTable();
acpi20_p = (uint64_t)(uint32_t)getAddressOfAcpi20Table();
addConfigurationTable(&gEfiAcpiTableGuid, &acpi10_p, "ACPI");
if(acpi20_p) addConfigurationTable(&gEfiAcpi20TableGuid, &acpi20_p, "ACPI_20");
if(acpi20_p) {
addConfigurationTable(&gEfiAcpi20TableGuid, &acpi20_p, "ACPI_20");
}
return 1;
}
rsdt_entries[i-dropoffset+j]=(uint32_t)new_ssdt[j];
}
verbose("RSDT: Added %d SSDT table(s)\n", ssdt_count);
DBG("RSDT: Added %d SSDT table(s)\n", ssdt_count);
}
DBG("New checksum %d at %x\n", rsdt_mod->Checksum,rsdt_mod);
} else {
rsdp_mod->RsdtAddress=0;
printf("RSDT not found or incorrect\n");
verbose("RSDT not found or RSDT incorrect\n");
}
if (version) {
xsdt_entries[i-dropoffset]=(uint32_t)new_dsdt;
}
DBG("TABLE %c%c%c%c@%x,",table[0],table[1],table[2],table[3],xsdt_entries[i]);
DBG("TABLE %c%c%c%c@%x \n", table[0],table[1],table[2],table[3],xsdt_entries[i]);
continue;
}
struct acpi_2_fadt *fadt, *fadt_mod;
fadt=(struct acpi_2_fadt *)(uint32_t)xsdt_entries[i];
DBG("FADT found @%x,%x, Length %d\n",(uint32_t)(xsdt_entries[i]>>32),fadt,
DBG("FADT found @%x%x, Length %d\n",(uint32_t)(xsdt_entries[i]>>32),fadt,
fadt->Length);
if (!fadt || (uint64_t)xsdt_entries[i] >= 0xffffffff || fadt->Length>0x10000) {
verbose("FADT incorrect or after 4GB. Dropping XSDT\n");
DBG("FADT incorrect or after 4GB. Dropping XSDT\n");
goto drop_xsdt;
}
fadt_mod = patch_fadt(fadt, new_dsdt);
xsdt_entries[i-dropoffset]=(uint32_t)fadt_mod;
DBG("TABLE %c%c%c%c@%x,",table[0],table[1],table[2],table[3],xsdt_entries[i]);
DBG("TABLE %c%c%c%c@%x \n", table[0],table[1],table[2],table[3],xsdt_entries[i]);
// Generate _CST SSDT
if (generate_cstates && (new_ssdt[ssdt_count] = generate_cst_ssdt(fadt_mod))) {
continue;
}
DBG("TABLE %c%c%c%c@%x,",table[0],table[1],table[2],table[3],xsdt_entries[i]);
DBG("TABLE %c%c%c%c@%x \n", table[0],table[1],table[2],table[3],xsdt_entries[i]);
}
xsdt_entries[i-dropoffset+j]=(uint32_t)new_ssdt[j];
}
verbose("Added %d SSDT table(s) into XSDT\n", ssdt_count);
DBG("Added %d SSDT table(s) into XSDT\n", ssdt_count);
}
// Correct the checksum of XSDT
*/
rsdp_mod->XsdtAddress=0xffffffffffffffffLL;
verbose("XSDT not found or incorrect\n");
DBG("XSDT not found or XSDT incorrect\n");
}
}
//verbose("Patched ACPI version %d DSDT\n", version+1);
if (version) {
/* XXX aserebln why uint32 cast if pointer is uint64 ? */
acpi20_p = (uint32_t)rsdp_mod;
acpi20_p = (uint64_t)(uint32_t)rsdp_mod;
addConfigurationTable(&gEfiAcpi20TableGuid, &acpi20_p, "ACPI_20");
} else {
/* XXX aserebln why uint32 cast if pointer is uint64 ? */
acpi10_p = (uint32_t)rsdp_mod;
acpi10_p = (uint64_t)(uint32_t)rsdp_mod;
addConfigurationTable(&gEfiAcpiTableGuid, &acpi10_p, "ACPI");
}
}
trunk/i386/libsaio/cpu.h
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#define MSR_CORE_THREAD_COUNT0x35// Undocumented
#define MSR_IA32_PLATFORM_ID0x17
#define K8_FIDVID_STATUS0xC0010042
#define K10_COFVID_STATUS0xC0010071
/*
* The CPUID_FEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 1:
*/
#define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */
#define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */
#define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */
#define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */
#define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */
#define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */
#define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */
#define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */
#define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */
#define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */
#define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */
#define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */
#define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */
#define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */
#define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */
#define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */
#define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */
#define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */
#define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */
#define CPUID_FEATURE_DS _Bit(21) /* Debug Store */
#define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */
#define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */
#define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */
#define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */
#define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */
#define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */
#define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */
#define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */
#define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */
#define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */
#define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ instruction */
#define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */
#define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */
#define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */
#define CPUID_FEATURE_VMX _HBit(5) /* VMX */
#define CPUID_FEATURE_SMX _HBit(6) /* SMX */
#define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */
#define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */
#define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */
#define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */
#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */
#define CPUID_FEATURE_FMA _HBit(12) /* Fused-Multiply-Add support */
#define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */
#define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */
#define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */
#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */
#define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */
#define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */
#define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */
#define CPUID_FEATURE_x2APIC _HBit(21) /* Extended APIC Mode */
#define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */
#define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */
#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */
#define CPUID_FEATURE_AES _HBit(25) /* AES instructions */
#define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */
#define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */
#define CPUID_FEATURE_AVX1_0_HBit(28) /* AVX 1.0 instructions */
#define CPUID_FEATURE_F16C_HBit(29) /* Float16 convert instructions */
#define CPUID_FEATURE_RDRAND_HBit(30) /* RDRAND instruction */
#define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */
/*
* Leaf 7, subleaf 0 additional features.
* Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
*/
#define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)/* FS/GS base read/write */
#define CPUID_LEAF7_FEATURE_TSCOFF _Bit(1)/* TSC thread offset */
#define CPUID_LEAF7_FEATURE_BMI1 _Bit(3)/* Bit Manipulation Instrs, set 1 */
#define CPUID_LEAF7_FEATURE_HLE _Bit(4)/* Hardware Lock Elision*/
#define CPUID_LEAF7_FEATURE_AVX2 _Bit(5)/* AVX2 Instructions */
#define CPUID_LEAF7_FEATURE_SMEP _Bit(7)/* Supervisor Mode Execute Protect */
#define CPUID_LEAF7_FEATURE_BMI2 _Bit(8)/* Bit Manipulation Instrs, set 2 */
#define CPUID_LEAF7_FEATURE_ENFSTRG _Bit(9)/* ENhanced Fast STRinG copy */
#define CPUID_LEAF7_FEATURE_INVPCID _Bit(10)/* INVPCID intruction, TDB */
#define CPUID_LEAF7_FEATURE_RTM _Bit(11)/* TBD */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
*/
#define CPUID_EXTFEATURE_SYSCALL _Bit(11)/* SYSCALL/sysret */
#define CPUID_EXTFEATURE_XD _Bit(20)/* eXecute Disable */
#define CPUID_EXTFEATURE_1GBPAGE _Bit(26)/* 1GB pages */
#define CPUID_EXTFEATURE_RDTSCP _Bit(27)/* RDTSCP */
#define CPUID_EXTFEATURE_EM64T _Bit(29)/* Extended Mem 64 Technology */
#define CPUID_EXTFEATURE_LAHF _HBit(0)/* LAFH/SAHF instructions */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
*/
#define CPUID_EXTFEATURE_TSCI _Bit(8)/* TSC Invariant */
#defineCPUID_CACHE_SIZE16/* Number of descriptor values */
#define CPUID_MWAIT_EXTENSION_Bit(0)/* enumeration of WMAIT extensions */
#define CPUID_MWAIT_BREAK_Bit(1)/* interrupts are break events */
//-- processor type -> p_type:
#define PT_OEM0x00// Intel Original OEM Processor;
#define PT_OD0x01 // Intel Over Drive Processor;
#define PT_DUAL0x02// Intel Dual Processor;
#define PT_RES0x03// Intel Reserved;
/* Known MSR registers */
#define MSR_IA32_PLATFORM_ID 0x0017
#define MSR_CORE_THREAD_COUNT 0x0035/* limited use - not for Penryn or older */
#define IA32_TSC_ADJUST 0x003B
#define MSR_IA32_BIOS_SIGN_ID 0x008B/* microcode version */
#define MSR_FSB_FREQ 0x00CD/* limited use - not for i7 */
#defineMSR_PLATFORM_INFO 0x00CE/* limited use - MinRatio for i7 but Max for Yonah*/
/* turbo for penryn */
#define MSR_PKG_CST_CONFIG_CONTROL 0x00E2/* sandy and ivy */
#define MSR_PMG_IO_CAPTURE_BASE 0x00E4
#define IA32_MPERF 0x00E7/* TSC in C0 only */
#define IA32_APERF 0x00E8/* actual clocks in C0 */
#define MSR_IA32_EXT_CONFIG 0x00EE/* limited use - not for i7 */
#define MSR_FLEX_RATIO 0x0194/* limited use - not for Penryn or older */
//see no value on most CPUs
#defineMSR_IA32_PERF_STATUS 0x0198
#define MSR_IA32_PERF_CONTROL 0x0199
#define MSR_IA32_CLOCK_MODULATION 0x019A
#define MSR_THERMAL_STATUS 0x019C
#define MSR_IA32_MISC_ENABLE 0x01A0
#define MSR_THERMAL_TARGET 0x01A2 /* TjMax limited use - not for Penryn or older*/
#define MSR_MISC_PWR_MGMT 0x01AA
#define MSR_TURBO_RATIO_LIMIT 0x01AD /* limited use - not for Penryn or older */
#define IA32_ENERGY_PERF_BIAS0x01B0
#define MSR_PACKAGE_THERM_STATUS0x01B1
#define IA32_PLATFORM_DCA_CAP0x01F8
#define MSR_POWER_CTL0x01FC // MSR 000001FC 0000-0000-0004-005F
// Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.
#define MSR_RAPL_POWER_UNIT0x606 /* R/O */
//MSR 00000606 0000-0000-000A-1003
#define MSR_PKGC3_IRTL 0x60A /* RW time limit to go C3 */
// bit 15 = 1 -- the value valid for C-state PM
#define MSR_PKGC6_IRTL 0x60B /* RW time limit to go C6 */
//MSR 0000060B 0000-0000-0000-8854
//Valid + 010=1024ns + 0x54=84mks
#define MSR_PKGC7_IRTL 0x60C /* RW time limit to go C7 */
//MSR 0000060C 0000-0000-0000-8854
#define MSR_PKG_C2_RESIDENCY 0x60D /* same as TSC but in C2 only */
#define MSR_PKG_RAPL_POWER_LIMIT0x610 //MSR 00000610 0000-A580-0000-8960
#define MSR_PKG_ENERGY_STATUS0x611 //MSR 00000611 0000-0000-3212-A857
#define MSR_PKG_POWER_INFO0x614 //MSR 00000614 0000-0000-01E0-02F8
//AMD
#define K8_FIDVID_STATUS 0xC0010042
#define K10_COFVID_LIMIT 0xC0010061
#define K10_PSTATE_STATUS 0xC0010064
#define K10_COFVID_STATUS 0xC0010071
#define MSR_AMD_MPERF 0x000000E7
#define MSR_AMD_APERF 0x000000E8
trunk/i386/libsaio/smbios.c
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//#define kDefaultMacBookProIvyBoardProduct"Mac-AFD8A9D944EA4843"
//#define kDefaultMacBookProIvyBIOSReleaseDate"10/02/2012"
// MacBookPro11,2 - Mac-3CBD00234E554E41 - MBP112.88Z.0138.B02.1310181745
// MacBookPro11,2 - Mac-3CBD00234E554E41 - MBP112.88Z.0138.B03.1310291227
// MacBookPro11,3 - Mac-2BD1B31983FE1663 - MBP112.88Z.0138.B02.1310181745
//=========== iMac ===========
//#define kDefaultiMacBoardAssetTagNumber"iMac-Aluminum"
#define kDefaultiMac"iMac8,1"
#define kDefaultiMacBIOSVersion" IM81.88Z.00C1.B00.0802091538"
#define kDefaultiMacBIOSVersion" IM81.88Z.00C1.B00.0903051113"
#define kDefaultiMacBIOSReleaseDate"02/09/08"
#define kDefaultiMacBoardProduct"Mac-F227BEC8"
// if (platformCPUFeature(CPU_FEATURE_MOBILE)) Bungo: doesn't recognise correctly
if (PlatformType == 2) // this method works
{
if (Platform.CPU.NoCores > 1)
{
if (Platform.CPU.NoCores > 1) {
defaultSystemInfo.productName = kDefaultMacBookPro;
defaultBIOSInfo.version = kDefaultMacBookProBIOSVersion;
defaultBIOSInfo.releaseDate = kDefaultMacBookProBIOSReleaseDate;
defaultBaseBoard.product = kDefaultMacBookProBoardProduct;
defaultBaseBoard.boardType = kSMBBaseBoardMotherboard;
defaultChassis.chassisType = kSMBchassisUnknown;
}
else
{
} else {
defaultSystemInfo.productName = kDefaultMacBook;
defaultBIOSInfo.version = kDefaultMacBookBIOSVersion;
defaultBIOSInfo.releaseDate = kDefaultMacBookBIOSReleaseDate;
defaultBaseBoard.boardType = kSMBBaseBoardMotherboard;
defaultChassis.chassisType = kSMBchassisUnknown;
}
}
else
{
} else {
switch (Platform.CPU.NoCores)
{
case 1:
if (getValueForKey(SMBSetters[idx].keyString, &string, &len, SMBPlist))
{
break;
}
else
{
} else {
if (structPtr->orig->type == kSMBTypeMemoryDevice)// MemoryDevice only
{
if (getSMBValueForKey(structPtr->orig, SMBSetters[idx].keyString, &string, NULL))
free(structPtr);
decodeSMBIOSTable(neweps);
DBG("SMBIOS orig was = %x\n", origeps);
DBG("SMBIOS new is = %x\n", neweps);
}
void *getSmbios(int which)
trunk/i386/libsaio/smbios_decode.c
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DBG("\tVersion: %s\n", SMBStringForField((SMBStructHeader *)structHeader, structHeader->version, neverMask));
DBG("\tSerial Number: %s\n", SMBStringForField((SMBStructHeader *)structHeader, structHeader->serialNumber, privateData));
if (minorVersion < 1 || structHeader->header.length < 25) {
if (minorVersion < 0x01 || structHeader->header.length < 0x19) {
return;
}
} else {
DBG("\tWake-up Type: %s\n", SMBWakeUpTypes[structHeader->wakeupReason]);
}
if (minorVersion < 4 || structHeader->header.length < 27) {
if (minorVersion < 0x04 || structHeader->header.length < 0x1B) {
return;
}
DBG("\tSerial Number: %s\n", SMBStringForField((SMBStructHeader *)structHeader, structHeader->serialNumber, privateData));
DBG("\tAsset Tag: %s\n", SMBStringForField((SMBStructHeader *)structHeader, structHeader->assetTag, neverMask));
DBG("\tPart Number: %s\n", SMBStringForField((SMBStructHeader *)structHeader, structHeader->partNumber, neverMask));
//DBG("\tCore Count: %d\n", structHeader->coreCount);
//DBG("\tCore Enabled: %d\n", structHeader->coreEnabled);
//DBG("\tThread Count: %d\n", structHeader->threadCount);
//DBG("\tProcessor Family 2: %d\n", structHeader->processorFamily2);
DBG("\n");
}
DBG("\tBank Locator: %s\n", SMBStringForField((SMBStructHeader *)structHeader, structHeader->bankLocator, neverMask));
DBG("\tMemory Type: %s\n", SMBMemoryDeviceTypes[structHeader->memoryType]);
if (minorVersion < 3 || structHeader->header.length < 27) {
if (minorVersion < 0x03 || structHeader->header.length < 0x1B) {
return;
}
DBG("\tSpeed: %d MHz\n", structHeader->memorySpeed);
trunk/i386/libsaio/smbios.h
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SMBString serialNumber;
SMBString assetTag;
SMBString partNumber;
// 2.5+ spec
// 2.5+ spec (38 bytes)
//SMBByte coreCount;
//SMBByte coreEnabled;
//SMBByte threadCount;
trunk/i386/libsaio/smbios_getters.c
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value->word = 0;
break;
default:
value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);
value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);
}
}
break;
default:
value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);
value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);
}
} else {
value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);
value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);
}
return true;
bool getProcessorInformationMaximumClock(returnType *value)
{
value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000);
value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);
return true;
}
qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);
qpimult &= 0x7F;
DBG("qpimult %d\n", qpimult);
qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));
qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));
// Rek: rounding decimals to match original mac profile info
if (qpibusspeed%100 != 0) {
qpibusspeed = ((qpibusspeed+50)/100)*100;

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Revision: 2349