Chameleon

Chameleon Commit Details

Date:2014-01-29 18:54:35 (10 years 2 months ago)
Author:Bungo
Commit:2360
Parents: 2359
Message:Merge some trunk r2359 changes
Changes:
M/branches/Bungo/i386/libsaio/cpu.c
M/branches/Bungo/i386/libsaio/fake_efi.c
M/branches/Bungo/i386/libsaio/platform.h
M/branches/Bungo/i386/libsaio/smbios_getters.c
M/branches/Bungo/package/OptionalSettings/Video.txt
M/branches/Bungo/i386/libsaio/nvidia.c
M/branches/Bungo/i386/libsaio/cpu.h
M/branches/Bungo/i386/libsaio/smbios.c
M/branches/Bungo/i386/libsaio/aml_generator.c
M/branches/Bungo/i386/libsaio/smbios_decode.c
M/branches/Bungo/package/OptionalSettings/General.txt
M/branches/Bungo/i386/libsaio/smbios.h
M/branches/Bungo/i386/libsaio/acpi_patcher.c
M/branches/Bungo/doc/BootHelp.txt

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branches/Bungo/i386/libsaio/acpi_patcher.c
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␊
␉␉␉␉verbose("Found ACPI CPU: %c%c%c%c\n", acpi_cpu_name[acpi_cpu_count][0], acpi_cpu_name[acpi_cpu_count][1], acpi_cpu_name[acpi_cpu_count][2], acpi_cpu_name[acpi_cpu_count][3]);␊
␊
␉␉␉␉if (++acpi_cpu_count == 32)␊
␉␉␉␉{␊
␉␉␉␉if (++acpi_cpu_count == 32) {␊
␉␉␉␉␉return;␊
␉␉␉␉}␊
␉␉␉}␊
␉␉aml_add_byte(pack, cstates_count);␊
␊
␉␉AML_CHUNK* tmpl = aml_add_package(pack);␊
␉␉if (cst_using_systemio)␊
␉␉{␊
␉␉if (cst_using_systemio) {␊
␉␉␉// C1␊
␉␉␉resource_template_register_fixedhw[8] = 0x00;␊
␉␉␉resource_template_register_fixedhw[9] = 0x00;␊
␉␉verbose ("SSDT with CPU C-States generated successfully\n");␊
␊
␉␉return ssdt;␊
␉}␊
␉else␊
␉{␊
␉} else {␊
␉␉verbose ("ACPI CPUs not found: C-States not generated !!!\n");␊
␉}␊
␊
␉␉␉␉␉␉␉DBG("P-States: Insane FID values!");␊
␉␉␉␉␉␉␉p_states_count = 0;␊
␉␉␉␉␉␉} else {␊
␉␉␉␉␉␉␉uint8_t vidstep;␊
␉␉␉␉␉␉␉uint8_t i = 0, u, invalid = 0;␊
␉␉␉␉␉␉␉// Finalize P-States␊
␉␉␉␉␉␉␉// Find how many P-States machine supports␊
␉␉␉␉␉␉␉p_states_count = maximum.CID - minimum.CID + 1;␊
␉␉␉␉␉␉␉p_states_count = (uint8_t)(maximum.CID - minimum.CID + 1);␊
␊
␉␉␉␉␉␉␉if (p_states_count > 32) {␊
␉␉␉␉␉␉␉␉p_states_count = 32;␊
␉␉␉␉␉␉␉}␊
␊
␉␉␉␉␉␉␉uint8_t vidstep;␊
␉␉␉␉␉␉␉uint8_t i = 0, u, invalid = 0;␊
␊
␉␉␉␉␉␉␉vidstep = ((maximum.VID << 2) - (minimum.VID << 2)) / (p_states_count - 1);␊
␊
␉␉␉␉␉␉␉for (u = 0; u < p_states_count; u++) {␊
␉␉␉␉␉␉␉␉i = u - invalid;␊
␊
␉␉␉␉␉␉␉␉p_states[i].CID = maximum.CID - u;␊
␉␉␉␉␉␉␉␉p_states[i].FID = (p_states[i].CID >> 1);␊
␉␉␉␉␉␉␉␉p_states[i].FID = (uint8_t)(p_states[i].CID >> 1);␊
␊
␉␉␉␉␉␉␉␉if (p_states[i].FID < 0x6) {␊
␉␉␉␉␉␉␉␉␉if (cpu_dynamic_fsb) {␊
␉␉␉␉␉␉␉␉if (i && p_states[i].FID == p_states[i-1].FID) {␊
␉␉␉␉␉␉␉␉␉invalid++;␊
␉␉␉␉␉␉␉␉}␊
␊
␉␉␉␉␉␉␉␉p_states[i].VID = ((maximum.VID << 2) - (vidstep * u)) >> 2;␊
␊
␉␉␉␉␉␉␉␉uint32_t multiplier = p_states[i].FID & 0x1f;␉␉// = 0x08␊
␉␉␉␉␉␉␉␉bool half = p_states[i].FID & 0x40;␉␉␉␉␉// = 0x01␊
␉␉␉␉␉␉␉␉bool dfsb = p_states[i].FID & 0x80;␉␉␉␉␉// = 0x00␊
␉␉␉␉␉␉␉␉uint32_t fsb = Platform.CPU.FSBFrequency / 1000000; // = 400␊
␉␉␉␉␉␉␉␉uint32_t fsb = (uint32_t)(Platform.CPU.FSBFrequency / 1000000); // = 400␊
␉␉␉␉␉␉␉␉uint32_t halffsb = (fsb + 1) >> 1;␉␉␉␉␉// = 200␊
␉␉␉␉␉␉␉␉uint32_t frequency = (multiplier * fsb);␉␉␉// = 3200␊
␊
␉␉␉␉␉␉␉␉p_states[i].Frequency = (frequency + (half * halffsb)) >> dfsb;␉// = 3200 + 200 = 3400␊
␉␉␉␉␉␉␉␉p_states[i].Frequency = (uint32_t)(frequency + (half * halffsb)) >> dfsb;␉// = 3200 + 200 = 3400␊
␉␉␉␉␉␉␉}␊
␊
␉␉␉␉␉␉␉p_states_count -= invalid;␊
␉␉␉␉␉case CPU_MODEL_HASWELL:␉//␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON: //␊
␉␉␉␉␉//case CPU_MODEL_HASWELL_H:␉//␊
␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␉//␊
␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␉//␊
␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉//␊
␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␉//␊
␊
␉␉␉␉␉{␊
␉␉␉␉␉if ((Platform.CPU.Model == CPU_MODEL_SANDYBRIDGE) || (Platform.CPU.Model == CPU_MODEL_JAKETOWN) ||␊
␉␉␉␉␉␉(Platform.CPU.Model == CPU_MODEL_IVYBRIDGE) || (Platform.CPU.Model == CPU_MODEL_HASWELL) ||␊
␉␉␉␉␉␉(Platform.CPU.Model == CPU_MODEL_IVYBRIDGE_XEON) || (Platform.CPU.Model == CPU_MODEL_HASWELL_MB) ||␊
␉␉␉␉␉␉(Platform.CPU.Model == CPU_MODEL_IVYBRIDGE_XEON) || (Platform.CPU.Model == CPU_MODEL_HASWELL_SVR) ||␊
␉␉␉␉␉␉(Platform.CPU.Model == CPU_MODEL_HASWELL_ULT) || (Platform.CPU.Model == CPU_MODEL_CRYSTALWELL))␊
␉␉␉␉␉{␊
␉␉␉␉␉␉maximum.Control = (rdmsr64(MSR_IA32_PERF_STATUS) >> 8) & 0xff;␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉}␊
␉␉␉␉␉default:␊
␉␉␉␉␉␉verbose ("Unsupported CPU: P-States not generated !!! Unknown CPU Type\n");␊
␉␉␉␉␉␉verbose ("Unsupported CPU (0x%X): P-States not generated !!!\n", Platform.CPU.Family);␊
␉␉␉␉␉␉break;␊
␉␉␉␉}␊
␉␉␉}␊
␊
␉␉␉AML_CHUNK* root = aml_create_node(NULL);␊
␉␉␉␉aml_add_buffer(root, ssdt_header, sizeof(ssdt_header)); // SSDT header␊
␊
␉␉␉␉␉AML_CHUNK* scop = aml_add_scope(root, "\\_PR_");␊
␉␉␉␉␉␉AML_CHUNK* name = aml_add_name(scop, "PSS_");␊
␉␉␉␉␉␉␉AML_CHUNK* pack = aml_add_package(name);␊
␊
␉␉␉ssdt->Length = root->Size;␊
␉␉␉ssdt->Checksum = 0;␊
␉␉␉ssdt->Checksum = 256 - checksum8(ssdt, ssdt->Length);␊
␉␉␉ssdt->Checksum = 256 - (uint8_t)(checksum8(ssdt, ssdt->Length));␊
␊
␉␉␉aml_destroy_node(root);␊
␊
{␊
␉extern void setupSystemType(); ␊
␊
␉struct acpi_2_fadt *fadt_mod;␊
␉struct acpi_2_fadt *fadt_mod = NULL;␊
␉bool fadt_rev2_needed = false;␊
␉bool fix_restart;␊
␉bool fix_restart_ps2;␊
//␉addConfigurationTable(&gEfiAcpiTableGuid, getAddressOfAcpiTable(), "ACPI");␊
//␉addConfigurationTable(&gEfiAcpi20TableGuid, getAddressOfAcpi20Table(), "ACPI_20");␊
␉/* XXX aserebln why uint32 cast if pointer is uint64 ? */␊
␉acpi10_p = (uint32_t)getAddressOfAcpiTable();␊
␉acpi20_p = (uint32_t)getAddressOfAcpi20Table();␊
␉acpi10_p = (uint64_t)(uint32_t)getAddressOfAcpiTable();␊
␉acpi20_p = (uint64_t)(uint32_t)getAddressOfAcpi20Table();␊
␉addConfigurationTable(&gEfiAcpiTableGuid, &acpi10_p, "ACPI");␊
␉if(acpi20_p) addConfigurationTable(&gEfiAcpi20TableGuid, &acpi20_p, "ACPI_20");␊
␉if(acpi20_p) {␊
␉␉addConfigurationTable(&gEfiAcpi20TableGuid, &acpi20_p, "ACPI_20");␊
␉}␊
␉return 1;␊
}␊
␊
␉␉␉␉␉␉␉xsdt_entries[i-dropoffset]=(uint32_t)new_dsdt;␊
␉␉␉␉␉␉}␊
␊
␉␉␉␉␉␉DBG("TABLE %c%c%c%c@%x,",table[0],table[1],table[2],table[3],xsdt_entries[i]);␊
␉␉␉␉␉␉DBG("TABLE %c%c%c%c@%x \n", table[0],table[1],table[2],table[3],xsdt_entries[i]);␊
␉␉␉␉␉␉␊
␉␉␉␉␉␉continue;␊
␉␉␉␉␉}␊
␉␉␉␉␉␉struct acpi_2_fadt *fadt, *fadt_mod;␊
␉␉␉␉␉␉fadt=(struct acpi_2_fadt *)(uint32_t)xsdt_entries[i];␊
␊
␉␉␉␉␉␉DBG("FADT found @%x,%x, Length %d\n",(uint32_t)(xsdt_entries[i]>>32),fadt, ␊
␉␉␉␉␉␉DBG("FADT found @%x%x, Length %d\n",(uint32_t)(xsdt_entries[i]>>32),fadt, ␊
␉␉␉␉␉␉␉fadt->Length);␊
␊
␉␉␉␉␉␉if (!fadt || (uint64_t)xsdt_entries[i] >= 0xffffffff || fadt->Length>0x10000) {␊
␉␉␉␉␉␉fadt_mod = patch_fadt(fadt, new_dsdt);␊
␉␉␉␉␉␉xsdt_entries[i-dropoffset]=(uint32_t)fadt_mod;␊
␊
␉␉␉␉␉␉DBG("TABLE %c%c%c%c@%x,",table[0],table[1],table[2],table[3],xsdt_entries[i]);␊
␉␉␉␉␉␉DBG("TABLE %c%c%c%c@%x \n", table[0],table[1],table[2],table[3],xsdt_entries[i]);␊
␊
␉␉␉␉␉␉// Generate _CST SSDT␊
␉␉␉␉␉␉if (generate_cstates && (new_ssdt[ssdt_count] = generate_cst_ssdt(fadt_mod))) {␊
␉␉␉␉␉␉continue;␊
␉␉␉␉␉}␊
␊
␉␉␉␉␉DBG("TABLE %c%c%c%c@%x,",table[0],table[1],table[2],table[3],xsdt_entries[i]);␊
␉␉␉␉␉DBG("TABLE %c%c%c%c@%x \n", table[0],table[1],table[2],table[3],xsdt_entries[i]);␊
␊
␉␉␉␉}␊
␊
␉␉␉␉ */␊
␊
␉␉␉␉rsdp_mod->XsdtAddress=0xffffffffffffffffLL;␊
␉␉␉␉verbose("XSDT not found or incorrect\n");␊
␉␉␉␉verbose("XSDT not found or XSDT incorrect\n");␊
␉␉␉}␊
␉␉}␊
␊
␉␉//verbose("Patched ACPI version %d DSDT\n", version+1);␊
␉␉if (version) {␊
␉␉␉/* XXX aserebln why uint32 cast if pointer is uint64 ? */␊
␉␉␉acpi20_p = (uint32_t)rsdp_mod;␊
␉␉␉acpi20_p = (uint64_t)(uint32_t)rsdp_mod;␊
␉␉␉addConfigurationTable(&gEfiAcpi20TableGuid, &acpi20_p, "ACPI_20");␊
␉␉} else {␊
␉␉␉/* XXX aserebln why uint32 cast if pointer is uint64 ? */␊
␉␉␉acpi10_p = (uint32_t)rsdp_mod;␊
␉␉␉acpi10_p = (uint64_t)(uint32_t)rsdp_mod;␊
␉␉␉addConfigurationTable(&gEfiAcpiTableGuid, &acpi10_p, "ACPI");␊
␉␉}␊
␉}␊
branches/Bungo/i386/libsaio/aml_generator.c
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␊
␉if (node) {␊
␉␉unsigned int offset = 0;␊
␉␉unsigned int len = strlen(StringBuf)+1;␊
␉␉unsigned int len = strlen(StringBuf);␊
␉␉node->Type = AML_CHUNK_BUFFER;␊
␉␉node->Length = (uint8_t)(len + 3);␊
␉␉node->Buffer = malloc (node->Length);␊
␉␉␉case AML_CHUNK_DEVICE:␊
␉␉␉␉offset = aml_write_byte(AML_CHUNK_OP, buffer, offset);␊
␉␉␉␉offset = aml_write_byte(node->Type, buffer, offset);␊
␉␉␉␉offset = aml_write_size(node->Size-3, buffer, offset);␊
␉␉␉␉offset = aml_write_size(node->Size-2, buffer, offset);␊
␉␉␉␉offset = aml_write_buffer(node->Buffer, node->Length, buffer, offset);␊
␉␉␉␉break;␊
␊
branches/Bungo/i386/libsaio/nvidia.c
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#define WRITE_LE_SHORT(data) (((data) << 8 & 0xff00) | ((data) >> 8 & 0x00ff ))␊
#define WRITE_LE_INT(data) (WRITE_LE_SHORT(data) << 16 | WRITE_LE_SHORT(data >> 16))␊
␊
static bool showGeneric = false;␊
char generic_name[128];␊
extern uint32_t devices_number;␊
␊
␉␉}␊
␉}␊
␊
␉//ErmaC added selector for Chameleon "old" style in System Profiler␊
␉if (getBoolForKey(kNvidiaGeneric, &showGeneric, &bootInfo->chameleonConfig)) {␊
␉␉verbose("\tNvidiaGeneric = Yes\n");␊
␊
␉␉for (i = 1; i < (sizeof(nvidia_card_generic) / sizeof(nvidia_card_generic[0])); i++) {␊
␉␉␉if (nvidia_card_generic[i].device == device_id) {␊
␉␉␉␉return nvidia_card_generic[i].name;␊
␉␉␉}␊
␉␉}␊
␉return nvidia_card_generic[0].name;␊
␉}␊
␊
␉// Then check the exceptions table␊
␉if (subsys_id) {␊
␉␉for (i = 0; i < (sizeof(nvidia_card_exceptions) / sizeof(nvidia_card_exceptions[0])); i++) {␊
␉␉␉if ((nvidia_card_exceptions[i].device == device_id) && (nvidia_card_exceptions[i].subdev == subsys_id)) {␊
␉␉␉if ((nvidia_card_exceptions[i].device == device_id) && (nvidia_card_exceptions[i].subdev == subsys_id))␉{␊
␉␉␉␉return nvidia_card_exceptions[i].name;␊
␉␉␉␉break;␊
␉␉␉}␊
␊
␉// At last try the generic names␊
␉for (i = 1; i < (sizeof(nvidia_card_generic) / sizeof(nvidia_card_generic[0])); i++) {␊
␉if (nvidia_card_generic[i].device == device_id) {␊
␉if (nvidia_card_generic[i].device == device_id) {␊
␉␉␉if (subsys_id) {␊
␉␉␉␉for (j = 0; j < (sizeof(nvidia_card_vendors) / sizeof(nvidia_card_vendors[0])); j++) {␊
␉␉␉␉␉if (nvidia_card_vendors[j].device == (subsys_id & 0xffff0000)) {␊
branches/Bungo/i386/libsaio/cpu.c
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␉␉pollCount = poll_PIT2_gate();␊
␉␉tscEnd = rdtsc64();␊
␉␉/* The poll loop must have run at least a few times for accuracy */␊
␉␉if (pollCount <= 1)␊
␉␉{␊
␉␉if (pollCount <= 1) {␊
␉␉␉continue;␊
␉␉}␊
␉␉/* The TSC must increment at LEAST once every millisecond.␊
␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
␉␉ * be >= 30. Anything less and the processor is way too slow.␊
␉␉ */␊
␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
␉␉{␊
␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC) {␊
␉␉␉continue;␊
␉␉}␊
␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
␉␉if ( (tscEnd - tscStart) < tscDelta )␊
␉␉{␊
␉␉if ( (tscEnd - tscStart) < tscDelta ) {␊
␉␉␉tscDelta = tscEnd - tscStart;␊
␉␉}␊
␉}␊
␉ * arithmetic headroom. For now, 32-bit should be enough.␊
␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
␉ */␊
␉if (tscDelta > (1ULL<<32))␊
␉{␊
␉if (tscDelta > (1ULL<<32)) {␊
␉␉retval = 0;␊
␉}␊
␉else␊
␉{␊
␉} else {␊
␉␉retval = tscDelta * 1000 / 30;␊
␉}␊
␉disable_PIT2();␊
␉␉pollCount = poll_PIT2_gate();␊
␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊
␉␉/* The poll loop must have run at least a few times for accuracy */␊
␉␉if (pollCount <= 1)␊
␉␉{␊
␉␉if (pollCount <= 1) {␊
␉␉␉continue;␊
␉␉}␊
␉␉/* The TSC must increment at LEAST once every millisecond.␊
␉␉ * We should have waited exactly 30 msec so the APERF delta should␊
␉␉ * be >= 30. Anything less and the processor is way too slow.␊
␉␉ */␊
␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊
␉␉{␊
␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC) {␊
␉␉␉continue;␊
␉␉}␊
␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊
␉␉{␊
␉␉if ( (aperfEnd - aperfStart) < aperfDelta ) {␊
␉␉␉aperfDelta = aperfEnd - aperfStart;␊
␉␉}␊
␉}␊
␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
␉ */␊
␉␊
␉if (aperfDelta > (1ULL<<32))␊
␉{␊
␉if (aperfDelta > (1ULL<<32)) {␊
␉␉retval = 0;␊
␉}␊
␉else␊
␉{␊
␉} else {␊
␉␉retval = aperfDelta * 1000 / 30;␊
␉}␊
␉disable_PIT2();␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE_XEON␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_MB ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_SVR ||␊
␉␉␉␉␉␉␉␉␉␉ //p->CPU.Model == CPU_MODEL_HASWELL_H ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_ULT ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_CRYSTALWELL ))␊
␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊
␉␉␉␉// EffFreq: effective frequency interface␊
␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊
␉␉␉␉{␊
␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1) {␊
␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊
␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊
␉␉␉␉␉cpuFrequency = aperf;␊
branches/Bungo/i386/libsaio/platform.h
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#define CPU_MODEL_IVYBRIDGE␉␉0x3A␉␉␉// Ivy Bridge␊
#define CPU_MODEL_HASWELL␉␉0x3C␉␉␉// Haswell DT␊
#define CPU_MODEL_IVYBRIDGE_XEON␉0x3E␉␉␉// Ivy Bridge Xeon␊
#define CPU_MODEL_HASWELL_MB␉␉0x3F␉␉␉// Haswell MB␊
#define CPU_MODEL_HASWELL_SVR␉␉0x3F␉␉␉// Haswell MB␊
//#define CPU_MODEL_HASWELL_H␉␉0x??␉␉␉// Haswell H␊
#define CPU_MODEL_HASWELL_ULT␉␉0x45␉␉␉// Haswell ULT␊
#define CPU_MODEL_CRYSTALWELL␉␉0x46␉␉␉// Haswell ULX␊
␉␉uint32_t␉␉Vendor;␉␉␉␉␉// Vendor␊
␉␉uint32_t␉␉Signature;␉␉␉␉// Processor Signature␊
␉␉uint32_t␉␉Stepping;␉␉␉␉// Stepping␊
␉␉//uint32_t␉␉Type;␉␉␉␉␉// Type␊
␉␉//uint16_t␉␉Type;␉␉␉␉␉// Type␊
␉␉uint32_t␉␉Model;␉␉␉␉␉// Model␊
␉␉uint32_t␉␉ExtModel;␉␉␉␉// Extended Model␊
␉␉uint32_t␉␉Family;␉␉␉␉␉// Family␊
␉␉uint32_t␉␉NoCores;␉␉␉␉// No Cores per Package␊
␉␉uint32_t␉␉NoThreads;␉␉␉␉// Threads per Package␊
␉␉uint8_t␉␉␉MaxCoef;␉␉␉␉// Max Multiplier␊
␉␉uint8_t␉␉␉MaxDiv;␊
␉␉uint8_t␉␉␉MaxDiv;␉␉␉␉␉// Min Multiplier␊
␉␉uint8_t␉␉␉CurrCoef;␉␉␉␉// Current Multiplier␊
␉␉uint8_t␉␉␉CurrDiv;␊
␉␉uint64_t␉␉TSCFrequency;␉␉␉// TSC Frequency Hz␊
␉␉uint64_t␉␉FSBFrequency;␉␉␉// FSB Frequency Hz␊
␉␉uint64_t␉␉CPUFrequency;␉␉␉// CPU Frequency Hz␊
␉␉uint64_t␉␉TSCFrequency;␉␉␉␉// TSC Frequency Hz␊
␉␉uint64_t␉␉FSBFrequency;␉␉␉␉// FSB Frequency Hz␊
␉␉uint64_t␉␉CPUFrequency;␉␉␉␉// CPU Frequency Hz␊
␉␉uint32_t␉␉MaxRatio;␉␉␉␉// Max Bus Ratio␊
␉␉uint32_t␉␉MinRatio;␉␉␉␉// Min Bus Ratio␊
␉␉char␉␉␉BrandString[48];␉␉// 48 Byte Branding String␊
␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊
␉␉char␉␉␉BrandString[48];␉␉␉// 48 Byte Branding String␊
␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉␉␉// CPUID 0..4, 80..81 Raw Values␊
␉} CPU;␊
␊
␉struct RAM {␊
branches/Bungo/i386/libsaio/cpu.h
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␊
#define CPU_STRING_UNKNOWN␉␉"Unknown CPU Type"␊
␊
#define␉MSR_IA32_PERF_STATUS␉0x00000198␊
#define MSR_IA32_PERF_CONTROL␉0x199␊
#define MSR_IA32_EXT_CONFIG␉␉0x00EE␊
#define MSR_FLEX_RATIO␉␉␉0x194␊
#define MSR_TURBO_RATIO_LIMIT␉0x1AD␊
#define␉MSR_PLATFORM_INFO␉␉0xCE␊
#define MSR_CORE_THREAD_COUNT␉0x35␉␉␉// Undocumented␊
#define MSR_IA32_PLATFORM_ID␉0x17␊
/*␊
* The CPUID_FEATURE_XXX values define 64-bit values␊
* returned in %ecx:%edx to a CPUID request with %eax of 1: ␊
*/␊
#define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */␊
#define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */␊
#define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */␊
#define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */␊
#define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */␊
#define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */␊
#define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */␊
#define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */␊
#define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */␊
#define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */␊
#define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */␊
#define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */␊
#define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */␊
#define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */␊
#define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */␊
#define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */␊
#define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */␊
#define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */␊
#define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */␊
#define CPUID_FEATURE_DS _Bit(21) /* Debug Store */␊
#define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */␊
#define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */␊
#define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */␊
#define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */␊
#define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */␊
#define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */␊
#define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */␊
#define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */␊
#define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */␊
␊
#define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */␊
#define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ instruction */␊
#define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */␊
#define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */␊
#define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */␊
#define CPUID_FEATURE_VMX _HBit(5) /* VMX */␊
#define CPUID_FEATURE_SMX _HBit(6) /* SMX */␊
#define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */␊
#define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */␊
#define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */␊
#define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */␊
#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */␊
#define CPUID_FEATURE_FMA _HBit(12) /* Fused-Multiply-Add support */␊
#define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */␊
#define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */␊
#define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */␊
␊
#define K8_FIDVID_STATUS␉␉0xC0010042␊
#define K10_COFVID_STATUS␉␉0xC0010071␊
#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */␊
#define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */␊
#define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */␊
#define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */␊
#define CPUID_FEATURE_x2APIC _HBit(21) /* Extended APIC Mode */␊
#define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */␊
#define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */␊
#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */␊
#define CPUID_FEATURE_AES _HBit(25) /* AES instructions */␊
#define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */␊
#define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */␊
#define CPUID_FEATURE_AVX1_0␉_HBit(28) /* AVX 1.0 instructions */␊
#define CPUID_FEATURE_F16C␉_HBit(29) /* Float16 convert instructions */␊
#define CPUID_FEATURE_RDRAND␉_HBit(30) /* RDRAND instruction */␊
#define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */␊
␊
/*␊
* Leaf 7, subleaf 0 additional features.␊
* Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:␊
*/␊
#define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)␉/* FS/GS base read/write */␊
#define CPUID_LEAF7_FEATURE_TSCOFF _Bit(1)␉/* TSC thread offset */␊
#define CPUID_LEAF7_FEATURE_BMI1 _Bit(3)␉/* Bit Manipulation Instrs, set 1 */␊
#define CPUID_LEAF7_FEATURE_HLE _Bit(4)␉/* Hardware Lock Elision*/␊
#define CPUID_LEAF7_FEATURE_AVX2 _Bit(5)␉/* AVX2 Instructions */␊
#define CPUID_LEAF7_FEATURE_SMEP _Bit(7)␉/* Supervisor Mode Execute Protect */␊
#define CPUID_LEAF7_FEATURE_BMI2 _Bit(8)␉/* Bit Manipulation Instrs, set 2 */␊
#define CPUID_LEAF7_FEATURE_ENFSTRG _Bit(9)␉/* ENhanced Fast STRinG copy */␊
#define CPUID_LEAF7_FEATURE_INVPCID _Bit(10)␉/* INVPCID intruction, TDB */␊
#define CPUID_LEAF7_FEATURE_RTM _Bit(11)␉/* TBD */␊
␊
/*␊
* The CPUID_EXTFEATURE_XXX values define 64-bit values␊
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000001: ␊
*/␊
#define CPUID_EXTFEATURE_SYSCALL _Bit(11)␉/* SYSCALL/sysret */␊
#define CPUID_EXTFEATURE_XD␉ _Bit(20)␉/* eXecute Disable */␊
␊
#define CPUID_EXTFEATURE_1GBPAGE _Bit(26)␉/* 1GB pages */␊
#define CPUID_EXTFEATURE_RDTSCP␉ _Bit(27)␉/* RDTSCP */␊
#define CPUID_EXTFEATURE_EM64T␉ _Bit(29)␉/* Extended Mem 64 Technology */␊
␊
#define CPUID_EXTFEATURE_LAHF␉ _HBit(0)␉/* LAFH/SAHF instructions */␊
␊
/*␊
* The CPUID_EXTFEATURE_XXX values define 64-bit values␊
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000007: ␊
*/␊
#define CPUID_EXTFEATURE_TSCI _Bit(8)␉/* TSC Invariant */␊
␊
#define␉CPUID_CACHE_SIZE␉16␉/* Number of descriptor values */␊
␊
#define CPUID_MWAIT_EXTENSION␉_Bit(0)␉/* enumeration of WMAIT extensions */␊
#define CPUID_MWAIT_BREAK␉_Bit(1)␉/* interrupts are break events␉ */␊
␊
//-- processor type -> p_type:␊
#define PT_OEM␉0x00␉// Intel Original OEM Processor;␊
#define PT_OD␉0x01 ␉// Intel Over Drive Processor;␊
#define PT_DUAL␉0x02␉// Intel Dual Processor;␊
#define PT_RES␉0x03␉// Intel Reserved;␊
␊
/* Known MSR registers */␊
#define MSR_IA32_PLATFORM_ID 0x0017␊
#define MSR_CORE_THREAD_COUNT 0x0035␉/* limited use - not for Penryn or older */␊
#define IA32_TSC_ADJUST 0x003B␊
#define MSR_IA32_BIOS_SIGN_ID 0x008B␉/* microcode version */␊
#define MSR_FSB_FREQ 0x00CD␉/* limited use - not for i7 */␊
#define␉MSR_PLATFORM_INFO 0x00CE␉/* limited use - MinRatio for i7 but Max for Yonah␉*/␊
/* turbo for penryn */␊
#define MSR_PKG_CST_CONFIG_CONTROL 0x00E2␉/* sandy and ivy */␊
#define MSR_PMG_IO_CAPTURE_BASE 0x00E4␊
#define IA32_MPERF 0x00E7␉/* TSC in C0 only */␊
#define IA32_APERF 0x00E8␉/* actual clocks in C0 */␊
#define MSR_IA32_EXT_CONFIG 0x00EE␉/* limited use - not for i7 */␊
#define MSR_FLEX_RATIO 0x0194␉/* limited use - not for Penryn or older */␊
␉␉␉␉␉␉//see no value on most CPUs␊
#define␉MSR_IA32_PERF_STATUS 0x0198␊
#define MSR_IA32_PERF_CONTROL 0x0199␊
#define MSR_IA32_CLOCK_MODULATION 0x019A␊
#define MSR_THERMAL_STATUS 0x019C␊
#define MSR_IA32_MISC_ENABLE 0x01A0␊
#define MSR_THERMAL_TARGET 0x01A2␉ /* TjMax limited use - not for Penryn or older␉*/␊
#define MSR_MISC_PWR_MGMT 0x01AA␊
#define MSR_TURBO_RATIO_LIMIT 0x01AD␉ /* limited use - not for Penryn or older */␊
␊
#define IA32_ENERGY_PERF_BIAS␉␉0x01B0␊
#define MSR_PACKAGE_THERM_STATUS␉0x01B1␊
#define IA32_PLATFORM_DCA_CAP␉␉0x01F8␊
#define MSR_POWER_CTL␉␉␉0x01FC // MSR 000001FC 0000-0000-0004-005F␊
␊
// Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.␊
#define MSR_RAPL_POWER_UNIT␉␉␉0x606 /* R/O */␊
//MSR 00000606 0000-0000-000A-1003␊
#define MSR_PKGC3_IRTL 0x60A /* RW time limit to go C3 */␊
// bit 15 = 1 -- the value valid for C-state PM␊
#define MSR_PKGC6_IRTL 0x60B /* RW time limit to go C6 */␊
//MSR 0000060B 0000-0000-0000-8854␊
//Valid + 010=1024ns + 0x54=84mks␊
#define MSR_PKGC7_IRTL 0x60C /* RW time limit to go C7 */␊
//MSR 0000060C 0000-0000-0000-8854␊
#define MSR_PKG_C2_RESIDENCY 0x60D /* same as TSC but in C2 only */␊
␊
#define MSR_PKG_RAPL_POWER_LIMIT␉0x610 //MSR 00000610 0000-A580-0000-8960␊
#define MSR_PKG_ENERGY_STATUS␉␉0x611 //MSR 00000611 0000-0000-3212-A857␊
#define MSR_PKG_POWER_INFO␉␉␉0x614 //MSR 00000614 0000-0000-01E0-02F8␊
␊
//AMD␊
#define K8_FIDVID_STATUS 0xC0010042␊
#define K10_COFVID_LIMIT 0xC0010061␊
#define K10_PSTATE_STATUS 0xC0010064␊
#define K10_COFVID_STATUS 0xC0010071␊
␊
#define MSR_AMD_MPERF 0x000000E7␊
#define MSR_AMD_APERF 0x000000E8␊
␊
#define CALIBRATE_TIME_MSEC␉30␉␉/* 30 msecs */␊
#define CALIBRATE_LATCH␉␉((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)␊
␊
// CPUID Values␊
/*␊
#define CPUID_MODEL_PRESCOTT␉␉3 // 0x03 Celeron D, Pentium 4 (90nm)␊
#define CPUID_MODEL_NOCONA␉␉4 // 0x04 Xeon Nocona, Irwindale (90nm)␊
#define CPUID_MODEL_PRESLER␉␉6 // 0x06 Pentium 4, Pentium D (65nm)␊
#define CPUID_MODEL_PENTIUM_M␉␉9 // 0x09␊
#define CPUID_MODEL_DOTHAN␉␉13 // 0x0D Dothan␊
#define CPUID_MODEL_YONAH␉␉14 // 0x0E Intel Mobile Core Solo, Duo␊
#define CPUID_MODEL_MEROM␉␉15 // 0x0F Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
#define CPUID_MODEL_CONROE␉␉15 // 0x0F␊
#define CPUID_MODEL_CELERON␉␉22 // 0x16␊
#define CPUID_MODEL_PENRYN␉␉23 // 0x17 Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
#define CPUID_MODEL_WOLFDALE␉␉23 // 0x17␊
#define CPUID_MODEL_NEHALEM␉␉26 // 0x1A Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
#define CPUID_MODEL_ATOM␉␉28 // 0x1C Intel Atom (45nm) Pineview, Silverthorne␊
#define CPUID_MODEL_XEON_MP␉␉29 // 0x1D MP 7400␊
#define CPUID_MODEL_FIELDS␉␉30 // 0x1E Intel Core i5, i7, Xeon X34xx LGA1156 (45nm),(Clarksfiled, Lynnfield, Jasper Forest)␊
#define CPUID_MODEL_DALES␉␉31 // 0x1F Havendale, Auburndale␊
#define CPUID_MODEL_DALES_32NM␉␉37 // 0x25 Intel Core i3, i5 LGA1156 (32nm), (Arrandale, Clarksdale)␊
#define CPUID_MODEL_ATOM_SAN␉␉38 // 0x26␊
#define CPUID_MODEL_LINCROFT␉␉39 // 0x27 Intel Atom (45nm) Z6xx (single core)␊
#define CPUID_MODEL_SANDYBRIDGE␉␉42 // 0x2A Intel Core i3, i5, i7 LGA1155 (32nm)␊
#define CPUID_MODEL_WESTMERE␉␉44 // 0x2C Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
#define CPUID_MODEL_JAKETOWN 45 // 0x2D Intel Xeon E5 LGA2011 (32nm), SandyBridge-E, SandyBridge-EN, SandyBridge-EP␊
#define CPUID_MODEL_NEHALEM_EX␉␉46 // 0x2E Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
#define CPUID_MODEL_WESTMERE_EX␉␉47 // 0x2F Intel Xeon E7␊
#define CPUID_MODEL_ATOM_2000␉␉54 // 0x36 Intel Atom (32nm) Cedarview␊
#define CPUID_MODEL_IVYBRIDGE␉␉58 // 0x3A Intel Core i5, i7 LGA1155 (22nm)␊
#define CPUID_MODEL_HASWELL␉␉60 // 0x3C Desktop version␊
#define CPUID_MODEL_IVYBRIDGE_XEON␉62 // 0x3E␊
#define CPUID_MODEL_HASWELL_MB␉␉63 // 0x3F Mobile/Laptop version␊
//#define CPUID_MODEL_HASWELL_H␉␉?? // 0x??␊
#define CPUID_MODEL_HASWELL_ULT␉␉69 // 0x45␊
#define CPUID_MODEL_CRYSTALWELL␉␉70 // 0x46␊
*/␊
/* HASWELL-DT HASWELL-MB HASWELL-H HASWELL-ULT HASWELL ULX*/␊
␊
//BROADWELL-ROCKWELL␊
␊
static inline uint64_t rdtsc64(void)␊
{␊
␉uint64_t ret;␊
branches/Bungo/i386/libsaio/smbios.c
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/* ============================␊
Processor Information (Type 4)␊
============================== */␊
// Bungo:␊
// Bungo␊
#define kSMBProcessorInformationSocketKey "SMcpusocket"␊
#define kSMBProcessorInformationManufacturerKey "SMcpumanufacturer"␊
#define kSMBProcessorInformationVersionKey "SMcpuversion"␊
//␊
#define kSMBProcessorInformationExternalClockKey␉"SMexternalclock"␊
#define kSMBProcessorInformationMaximalClockKey␉␉"SMmaximalclock"␊
// Bungo:␊
#define kSMBProcessorInformationMaximumClockKey␉␉"SMmaximalclock"␊
// Bungo␊
#define kSMBProcessorInformationCurrentClockKey "SMcurrentclock"␊
#define kSMBProcessorInformationUpgradeKey "SMcpuupgrade"␊
#define kSMBProcessorInformationSerialNumberKey "SMcpuserial"␊
␉uint8_t␉␉chassisType;␊
␉char␉␉*version;␊
␉char␉␉*serialNumber;␊
␉char␉␉*assetTag; // Bungo: renamed folowing convention␊
char *skuNumber;␊
␉char␉␉*assetTag;␊
} defaultChassis_t;␊
␊
defaultChassis_t defaultChassis;␊
typedef struct␊
{␊
␉uint8_t␉␉␉type;␊
␉SMBValueType␉valueType;␊
␉SMBValueType␉␉valueType;␊
␉uint8_t␉␉␉fieldOffset;␊
␉char␉␉␉*keyString;␊
␉bool␉␉␉(*getSMBValue)(returnType *);␊
{␊
␉/* =======================␊
␉ BIOS Information (Type 0)␊
␉ =========================*/␊
␉ ========================= */␊
␉{ kSMBTypeBIOSInformation, kSMBString, getFieldOffset(SMBBIOSInformation, vendor),␊
␉␉kSMBBIOSInformationVendorKey, NULL, &defaultBIOSInfo.vendor }, // SMbiosvendor - Apple Inc.␊
␊
␉␉kSMBProcessorInformationExternalClockKey, getProcessorInformationExternalClock,␉NULL}, // SMcpuexternalclock␊
␊
␉{kSMBTypeProcessorInformation,␉kSMBWord, getFieldOffset(SMBProcessorInformation, maximumClock),␊
␉␉kSMBProcessorInformationMaximalClockKey, getProcessorInformationMaximumClock,␉NULL}, // SMcpumaximumclock␊
␉␉kSMBProcessorInformationMaximumClockKey, getProcessorInformationMaximumClock,␉NULL}, // SMcpumaximumclock␊
␉// Bungo␊
␉{kSMBTypeProcessorInformation,␉kSMBWord,␉getFieldOffset(SMBProcessorInformation, currentClock),␊
␉␉kSMBProcessorInformationCurrentClockKey, NULL, NULL}, // SMcpucurrentspeed␊
␉␉kSMBProcessorInformationCurrentClockKey, NULL, NULL}, // SMcpucurrentclock␊
␊
␉{kSMBTypeProcessorInformation,␉kSMBByte,␉getFieldOffset(SMBProcessorInformation, processorUpgrade),␊
␉␉kSMBProcessorInformationUpgradeKey, NULL, NULL}, // SMcpuupgrade␊
static uint8_t stringIndex;␉// increament when a string is added and set the field value accordingly␊
static uint8_t stringsSize;␉// add string size␊
␊
static SMBWord tableLength = 0;␊
static SMBWord handle = 0;␊
static SMBWord tableLength␉= 0;␊
static SMBWord handle␉␉= 0;␊
static SMBWord maxStructSize␉= 0;␊
static SMBWord structureCount␉= 0;␊
␊
␊
// Bungo: suggest to not mixing data from different Mac models, use real Mac SMBIOS dumps␊
␊
#define kDefaultVendorManufacturer␉␉␉"Apple Inc."␊
//#define kDefaultBIOSReleaseDate␉␉␉"11/06/2009"␊
#define kDefaultSerialNumber␉␉␉␉"SOMESRLNMBR"␊
#define kDefaultVendorManufacturer "Apple Inc."␊
//#define kDefaultBIOSReleaseDate "11/06/2009"␊
#define kDefaultSerialNumber "SOMESRLNMBR"␊
//Bungo␊
#define kDefaultSkuNumber␉␉␉␉"Default SKU#"␊
#define kDefaultAssetTag␉␉␉␉"Default Asset Tag#"␊
//#define kDefaultBoardType␉␉␉␉"10" // 0xA␊
//#define kDefaultBoardProcessorType␉␉␉"11" // 0xB␊
#define kDefaultSystemVersion␉␉␉␉"1.0"␊
#define kDefaultBIOSRelease␉␉␉␉256 // 256 = 0x0100 -> swap bytes: 0x0001 -> Release: 0.1 (see SMBIOS spec. table Type 0)␊
//#define kDefaultLocatioInChassis␉␉␉"Part Component"␊
//#define KDefaultBoardSerialNumber␉␉␉"C02140302D5DMT31M" // new C07019501PLDCVHAD - C02032101R5DC771H␊
#define kDefaultSkuNumber "Default SKU#"␊
#define kDefaultAssetTag "Default Asset Tag#"␊
//#define kDefaultBoardType "10" // 0xA␊
//#define kDefaultBoardProcessorType "11" // 0xB␊
#define kDefaultSystemVersion "1.0"␊
#define kDefaultBIOSRelease 256 // 256 = 0x0100 -> swap bytes: 0x0001 -> Release: 0.1 (see SMBIOS spec. table Type 0)␊
//#define kDefaultLocatioInChassis "Part Component"␊
//#define KDefaultBoardSerialNumber "C02140302D5DMT31M" // new C07019501PLDCVHAD - C02032101R5DC771H␊
␊
//=========== Mac mini ===========␊
#define kDefaultMacMiniFamily␉␉␉␉"Mac mini"␊
//#define kDefaultMacMiniBoardAssetTagNumber␉␉"Mini-Aluminum"␊
#define kDefaultMacMiniFamily "Mac mini"␊
//#define kDefaultMacMiniBoardAssetTagNumber "Mini-Aluminum"␊
␊
#define kDefaultMacMini␉␉␉␉␉"Macmini2,1"␊
#define kDefaultMacMiniBIOSVersion␉␉␉" MM21.88Z.009A.B00.0706281359"␊
#define kDefaultMacMiniBIOSReleaseDate␉␉␉"06/28/07"␊
#define kDefaultMacMiniBoardProduct␉␉␉"Mac-F4208EAA"␊
#define kDefaultMacMini "Macmini2,1"␊
#define kDefaultMacMiniBIOSVersion " MM21.88Z.009A.B00.0706281359"␊
#define kDefaultMacMiniBIOSReleaseDate "06/28/07"␊
#define kDefaultMacMiniBoardProduct "Mac-F4208EAA"␊
␊
// MacMini5,1 Mac-8ED6AF5B48C039E1 - MM51.88Z.0077.B0F.1110201309␊
// MacMini5,2 Mac-4BC72D62AD45599E␊
//#define kDefaultMacMini62BIOSReleaseDate␉␉"10/14/2012"␊
␊
//=========== MacBook ===========␊
#define kDefaultMacBookFamily␉␉␉␉"MacBook"␊
#define kDefaultMacBookFamily "MacBook"␊
//#define kDefaultMacBookBoardAssetTagNumber␉␉"MacBook-Black"␊
␊
#define kDefaultMacBook␉␉␉␉␉"MacBook4,1"␊
#define kDefaultMacBookBIOSVersion␉␉␉" MB41.88Z.00C1.B00.0802091535"␊
#define kDefaultMacBookBIOSReleaseDate␉␉␉"02/09/08"␊
#define kDefaultMacBookBoardProduct␉␉␉"Mac-F22788A9"␊
#define kDefaultMacBook "MacBook4,1"␊
#define kDefaultMacBookBIOSVersion " MB41.88Z.00C1.B00.0802091535"␊
#define kDefaultMacBookBIOSReleaseDate "02/09/08"␊
#define kDefaultMacBookBoardProduct "Mac-F22788A9"␊
␊
//=========== MacBookAir ===========␊
#define kDefaultMacBookAirFamily␉␉␉"MacBook Air"␊
#define kDefaultMacBookAirFamily "MacBook Air"␊
␊
// MacBookAir4,1 - Mac-C08A6BB70A942AC2␊
// MacBookAir4,2 - Mac-742912EFDBEE19B3␊
#define kDefaultMacBookAir␉␉␉␉"MacBookAir5,2"␊
#define kDefaultMacBookAirBIOSVersion␉␉␉" MBA51.88Z.00EF.B00.1205221442"␊
#define kDefaultMacBookAirBIOSReleaseDate␉␉"05/10/12"␊
#define kDefaultMacBookBoardAirProduct␉␉␉"Mac-2E6FAB96566FE58C"␊
#define kDefaultMacBookAir "MacBookAir5,2"␊
#define kDefaultMacBookAirBIOSVersion " MBA51.88Z.00EF.B00.1205221442"␊
#define kDefaultMacBookAirBIOSReleaseDate "05/10/12"␊
#define kDefaultMacBookBoardAirProduct "Mac-2E6FAB96566FE58C"␊
␊
// MacBookAir6,1 - Mac-35C1E88140C3E6CF - MBA61.88Z.0099.B04.1309271229␊
// MacBookAir6,2 - Mac-7DF21CB3ED6977E5 - MBA62.88Z.00EF.B00.1205221442␊
␊
//=========== MacBookPro ===========␊
#define kDefaultMacBookProFamily␉␉␉"MacBook Pro"␊
#define kDefaultMacBookProFamily "MacBook Pro"␊
//#define kDefaultMacBookProBoardAssetTagNumber␉␉"MacBook-Aluminum"␊
␊
#define kDefaultMacBookPro␉␉␉␉"MacBookPro4,1"␊
#define kDefaultMacBookProBIOSVersion␉␉␉" MBP41.88Z.00C1.B03.0802271651"␊
#define kDefaultMacBookProBIOSReleaseDate␉␉"02/27/08"␊
#define kDefaultMacBookProBoardProduct␉␉␉"Mac-F42C89C8"␊
#define kDefaultMacBookPro "MacBookPro4,1"␊
#define kDefaultMacBookProBIOSVersion " MBP41.88Z.00C1.B03.0802271651"␊
#define kDefaultMacBookProBIOSReleaseDate "02/27/08"␊
#define kDefaultMacBookProBoardProduct "Mac-F42C89C8"␊
␊
//#define kDefaultMacBookPro␉␉␉␉"MacBookPro8,1"␊
//#define kDefaultMacBookProBIOSVersion␉␉␉" MBP81.88Z.0047.B24.1110141131"␊
//#define kDefaultMacBookProIvyBoardProduct␉␉"Mac-AFD8A9D944EA4843"␊
//#define kDefaultMacBookProIvyBIOSReleaseDate␉␉"10/02/2012"␊
␊
// MacBookPro11,2 - Mac-3CBD00234E554E41 - MBP112.88Z.0138.B02.1310181745␊
// MacBookPro11,2 - Mac-3CBD00234E554E41 - MBP112.88Z.0138.B03.1310291227␊
// MacBookPro11,3 - Mac-2BD1B31983FE1663 - MBP112.88Z.0138.B02.1310181745␊
␊
//=========== iMac ===========␊
#define kDefaultiMacFamily␉␉␉␉"iMac"␊
#define kDefaultiMacFamily "iMac"␊
//#define kDefaultiMacBoardAssetTagNumber␉␉"iMac-Aluminum"␊
␊
#define kDefaultiMac␉␉␉␉␉"iMac8,1"␊
#define kDefaultiMacBIOSVersion␉␉␉␉" IM81.88Z.00C1.B00.0802091538"␊
#define kDefaultiMacBIOSReleaseDate␉␉␉"02/09/08"␊
#define kDefaultiMacBoardProduct␉␉␉"Mac-F227BEC8"␊
#define kDefaultiMac "iMac8,1"␊
#define kDefaultiMacBIOSVersion " IM81.88Z.00C1.B00.0802091538"␊
#define kDefaultiMacBIOSReleaseDate "02/09/08"␊
#define kDefaultiMacBoardProduct "Mac-F227BEC8"␊
␊
// iMac10,1␊
// iMac11,1 core i3/i5/i7␊
#define kDefaultiMacNehalem␉␉␉␉"iMac11,1"␊
#define kDefaultiMacNehalemBIOSVersion␉␉␉" IM111.88Z.0034.B02.1003171314"␊
#define kDefaultiMacNehalemBIOSReleaseDate␉␉"03/30/10"␊
#define kDefaultiMacNehalemBoardProduct␉␉␉"Mac-F2268DAE"␊
#define kDefaultiMacNehalem "iMac11,1"␊
#define kDefaultiMacNehalemBIOSVersion " IM111.88Z.0034.B02.1003171314"␊
#define kDefaultiMacNehalemBIOSReleaseDate "03/30/10"␊
#define kDefaultiMacNehalemBoardProduct "Mac-F2268DAE"␊
// iMac11,2␊
// iMac11,3␊
␊
// iMac12,1␊
#define kDefaultiMacSandy␉␉␉␉"iMac12,1"␊
#define kDefaultiMacSandyBIOSVersion␉␉␉" IM121.88Z.0047.B00.1102091756"␊
#define kDefaultiMacSandyBIOSReleaseDate␉␉"01/02/08"␊
#define kDefaultiMacSandyBoardProduct␉␉␉"Mac-942B5BF58194151B"␊
#define kDefaultiMacSandy "iMac12,1"␊
#define kDefaultiMacSandyBIOSVersion " IM121.88Z.0047.B00.1102091756"␊
#define kDefaultiMacSandyBIOSReleaseDate "01/02/08"␊
#define kDefaultiMacSandyBoardProduct "Mac-942B5BF58194151B"␊
// iMac12,2 Mac-942B59F58194171B␊
//#define kDefaultiMacSandy␉␉␉␉"iMac12,2"␊
//#define kDefaultiMacSandyBIOSVersion␉␉␉" IM121.88Z.0047.B1D.1110171110"␊
//#define kDefaultiMacIvyBoardProduct␉␉␉"Mac-FC02E91DDD3FA6A4"␊
␊
//=========== MacPro ===========␊
#define kDefaultMacProFamily␉␉␉␉"Mac Pro"␊
#define kDefaultMacProFamily "Mac Pro"␊
//#define KDefauktMacProBoardAssetTagNumber␉␉"Pro-Enclosure"␊
//#define kDefaultMacProBoardType␉␉␉"0xB" // 11␊
␊
#define kDefaultMacPro␉␉␉␉␉"MacPro3,1"␊
#define kDefaultMacProBIOSVersion␉␉␉" MP31.88Z.006C.B02.0801021250"␊
#define kDefaultMacProBIOSReleaseDate␉␉␉"01/02/08"␊
#define kDefaultMacPro "MacPro3,1"␊
#define kDefaultMacProBIOSVersion " MP31.88Z.006C.B02.0801021250"␊
#define kDefaultMacProBIOSReleaseDate "01/02/08"␊
//#define kDefaultMacProSystemVersion␉␉␉"1.3"␊
#define kDefaultMacProBoardProduct␉␉␉"Mac-F42C88C8"␊
#define kDefaultMacProBoardProduct "Mac-F42C88C8"␊
//#define KDefaultMacProBoardSerialNumber␉␉"J593902RA4MFE"␊
␊
// Mac Pro 4,1 core i7/Xeon␊
#define kDefaultMacProNehalem␉␉␉␉"MacPro4,1"␊
#define kDefaultMacProNehalemBIOSVersion␉␉" MP41.88Z.0081.B07.0910130729"␊
#define kDefaultMacProNehalemBIOSReleaseDate␉␉"10/13/09"␊
#define kDefaultMacProNehalem "MacPro4,1"␊
#define kDefaultMacProNehalemBIOSVersion " MP41.88Z.0081.B07.0910130729"␊
#define kDefaultMacProNehalemBIOSReleaseDate "10/13/09"␊
//#define kDefaultMacProNehalemSystemVersion␉␉"1.4"␊
#define kDefaultMacProNehalemBoardProduct␉␉"Mac-F221BEC8"␊
//#define KDefaultMacProNehalemBoardSerialNumber␉"J593004RB1LUE"␊
␊
// Mac Pro 5,1 core i7/Xeon␊
#define kDefaultMacProWestmere␉␉␉␉"MacPro5,1"␊
#define kDefaultMacProWestmere "MacPro5,1"␊
#define kDefaultMacProWestmereBIOSVersion␉␉" MP51.88Z.007F.B03.1010071432"␊
#define kDefaultMacProWestmereBIOSReleaseDate␉␉"10/07/10"␊
#define kDefaultMacProWestmereBIOSReleaseDate␉"10/07/10"␊
//#define kDefaultMacProWestmereSystemVersion␉␉"1.2"␊
#define kDefaultMacProWestmereBoardProduct␉␉"Mac-F221BEC8"␊
//#define KDefaultMacProWestmereBoardSerialNumber␉"J522700H7BH8C"␊
␊
// Mac Pro 6,1␊
#define kDefaultMacProHaswell␉␉␉␉"MacPro6,1"␊
#define kDefaultMacProHaswell "MacPro6,1"␊
#define kDefaultMacProHaswellBIOSVersion␉␉" MP61.88Z.0116.B04.1312061508"␊
#define kDefaultMacProHaswellBIOSReleaseDate␉␉"12/06/2013"␊
#define kDefaultMacProHaswellBIOSReleaseDate␉"12/06/2013"␊
//#define kDefaultMacProHaswellSystemVersion␉␉"1.?"␊
#define kDefaultMacProHaswellBoardProduct␉␉"Mac-F60DEB81FF30ACF6"␊
//#define KDefaultMacProHaswellBoardSerialNumber␉"?????????????"␊
␉defaultChassis.manufacturer = kDefaultVendorManufacturer;␊
␉defaultChassis.serialNumber = kDefaultSerialNumber;␊
␉defaultChassis.assetTag = kDefaultAssetTag;␊
defaultChassis.skuNumber = kDefaultSkuNumber;␊
// defaultChassis.skuNumber = kDefaultSkuNumber;␊
␊
// if (platformCPUFeature(CPU_FEATURE_MOBILE)) Bungo: doesn't recognise correctly␊
␉if (PlatformType == 2) // this method works␊
// if (platformCPUFeature(CPU_FEATURE_MOBILE)) Bungo: doesn't recognise correctly, need fixing␊
␉if (PlatformType == 2) // this method works but it's a substitute␊
␉{␊
␉␉if (Platform.CPU.NoCores > 1)␊
␉␉{␊
␉␉␉defaultBaseBoard.product = kDefaultMacBookProBoardProduct;␊
␉␉␉defaultBaseBoard.boardType = kSMBBaseBoardMotherboard;␊
␉␉␉defaultChassis.chassisType = kSMBchassisUnknown;␊
␉␉}␊
␉␉else␊
␉␉{␊
␉␉} else {␊
␉␉␉defaultSystemInfo.productName = kDefaultMacBook;␊
␉␉␉defaultBIOSInfo.version = kDefaultMacBookBIOSVersion;␊
␉␉␉defaultBIOSInfo.releaseDate = kDefaultMacBookBIOSReleaseDate;␊
␉␉␉defaultBaseBoard.boardType = kSMBBaseBoardMotherboard;␊
␉␉␉defaultChassis.chassisType = kSMBchassisUnknown;␊
␉␉}␊
␉}␊
␉else␊
␉{␊
␉} else {␊
␉␉switch (Platform.CPU.NoCores)␊
␉␉{␊
␉␉␉case 1:␊
␊
␉strSize = strlen(string);␊
␊
/* What was this for?␊
/* Bungo: What was this for?␊
␉// remove any spaces found at the end␊
␉while ((strSize != 0) && (string[strSize - 1] == ' ')) {␊
␉␉strSize--;␊
␉␉␉␉if (getValueForKey(SMBSetters[idx].keyString, &string, &len, SMBPlist))␊
␉␉␉␉{␊
␉␉␉␉␉break;␊
␉␉␉␉}␊
␉␉␉␉else␊
␉␉␉␉{␊
␉␉␉␉} else {␊
␉␉␉␉␉if (structPtr->orig->type == kSMBTypeMemoryDevice)␉// MemoryDevice only␊
␉␉␉␉␉{␊
␉␉␉␉␉␉if (getSMBValueForKey(structPtr->orig, SMBSetters[idx].keyString, &string, NULL))␊
␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉case CPU_MODEL_HASWELL:␊
␉␉␉␉case CPU_MODEL_HASWELL_MB:␊
␉␉␉␉case CPU_MODEL_HASWELL_SVR:␊
␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊
␊
␉if (handle < structPtr->orig->handle) {␊
␉␉handle = structPtr->orig->handle;␊
␉}␊
// Bungo: fix unsuported tables lengths from original smbios: extend smaller or truncate bigger␊
// Bungo: fix unsuported tables lengths from original smbios: extend smaller or truncate bigger - we use SMBIOS rev. 2.4 like Apple uses␊
switch (structPtr->orig->type) {␊
case kSMBTypeBIOSInformation:␊
structSize = sizeof(SMBBIOSInformation);␊
structSize = sizeof(SMBMemoryDevice);␊
break;␊
default:␊
structSize = structPtr->orig->length; // don't change if not to patch␊
structSize = structPtr->orig->length; // don't change a length for unpatched␊
break;␊
}␊
␊
{␊
␉SMBStructPtrs *structPtr;␊
␉uint8_t *buffer;␊
␉// bool setSMB = true; Bungo␊
␉// bool setSMB = true; Bungo: now we use useSMBIOSdefaults␊
␊
␉if (!origeps) {␊
␉␉return;␊
␉free(structPtr);␊
␊
␉decodeSMBIOSTable(neweps);␊
␊
␉DBG("SMBIOS orig was = %x\n", origeps);␊
␉DBG("SMBIOS new is = %x\n", neweps);␊
}␊
␊
void *getSmbios(int which)␊
branches/Bungo/i386/libsaio/smbios_decode.c
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===*/␊
static const char *SMBWakeUpTypes[] = // Bungo: strings for wake-up type (Table Type 1 - System Information)␊
{␊
␉"Reserved", /* 00h */␊
␉"Other", /* 01h */␊
␉"Unknown", /* 02h */␊
␉"APM Timer", /* 03h */␊
␉"Modem Ring", /* 04h */␊
␉"LAN Remote", /* 05h */␊
␉"Power Switch", /* 06h */␊
␉"PCI PME#", /* 07h */␊
␉"AC Power Restored" /* 08h */␊
␉"Reserved", /* 00h */␊
␉"Other", /* 01h */␊
␉"Unknown", /* 02h */␊
␉"APM Timer", /* 03h */␊
␉"Modem Ring", /* 04h */␊
␉"LAN Remote", /* 05h */␊
␉"Power Switch", /* 06h */␊
␉"PCI PME#", /* 07h */␊
␉"AC Power Restored" /* 08h */␊
};␊
␊
/*====␊
===*/␊
static const char *SMBChassisTypes[] = // Bungo: strings for chassis type (Table Type 3 - Chassis Information)␊
{␊
␉"Other", /* 01h */␊
␉"Unknown", /* 02h */␊
␉"Desktop", /* 03h */␊
␉"Low Profile Desktop", /* 04h */␊
␉"Pizza Box", /* 05h */␊
␉"Mini Tower", /* 06h */␊
␉"Tower", /* 07h */␊
␉"Portable", /* 08h */␊
␉"Laptop", /* 09h */␊
␉"Notebook", /* 0Ah */␊
␉"Hand Held", /* 0Bh */␊
␉"Docking Station", /* 0Ch */␊
␉"All in One", /* 0Dh */␊
␉"Sub Notebook", /* 0Eh */␊
␉"Space-saving", /* 0Fh */␊
␉"Lunch Box",␉␉/* 10h */␊
␉"Main Server Chassis",␉/* 11h */␊
␉"Expansion Chassis",␉/* 12h */␊
␉"SubChassis",␉␉/* 13h */␊
␉"Bus Expansion Chassis",/* 14h */␊
␉"Peripheral Chassis",␉/* 15h */␊
␉"RAID Chassis",␉␉/* 16h */␊
␉"Rack Mount Chassis", /* 17h */␊
␉"Sealed-case PC",␉/* 18h */␊
␉"Multi-system Chassis", /* 19h */␊
␉"Compact PCI",␉␉/* 1Ah */␊
␉"Advanced TCA",␉␉/* 1Bh */␊
␉"Blade",␉␉/* 1Ch */ // An SMBIOS implementation for a Blade would contain a Type 3 Chassis structure␊
␉"Other", /* 01h */␊
␉"Unknown", /* 02h */␊
␉"Desktop", /* 03h */␊
␉"Low Profile Desktop", /* 04h */␊
␉"Pizza Box", /* 05h */␊
␉"Mini Tower", /* 06h */␊
␉"Tower", /* 07h */␊
␉"Portable", /* 08h */␊
␉"Laptop", /* 09h */␊
␉"Notebook", /* 0Ah */␊
␉"Hand Held", /* 0Bh */␊
␉"Docking Station", /* 0Ch */␊
␉"All in One", /* 0Dh */␊
␉"Sub Notebook", /* 0Eh */␊
␉"Space-saving", /* 0Fh */␊
␉"Lunch Box", /* 10h */␊
␉"Main Server Chassis", /* 11h */␊
␉"Expansion Chassis", /* 12h */␊
␉"SubChassis", /* 13h */␊
␉"Bus Expansion Chassis", /* 14h */␊
␉"Peripheral Chassis", /* 15h */␊
␉"RAID Chassis", /* 16h */␊
␉"Rack Mount Chassis", /* 17h */␊
␉"Sealed-case PC", /* 18h */␊
␉"Multi-system Chassis", /* 19h */␊
␉"Compact PCI", /* 1Ah */␊
␉"Advanced TCA", /* 1Bh */␊
␉"Blade", /* 1Ch */ // An SMBIOS implementation for a Blade would contain a Type 3 Chassis structure␊
␉"Blade Enclosing"␉/* 1Dh */ // A Blade Enclosure is a specialized chassis that contains a set of Blades.␊
};␊
␊
===*/␊
static const char *SMBProcessorTypes[] = // Bungo: strings for processor type (Table Type 4 - Processor Information)␊
{␊
␉"Other", /* 01h */␊
␉"Unknown", /* 02h */␊
␉"Central Processor", /* 03h */␊
␉"Math Processor", /* 04h */␊
␉"DSP Processor", /* 05h */␊
␉"Video Processor" /* 06h */␊
␉"Other", /* 01h */␊
␉"Unknown", /* 02h */␊
␉"Central Processor", /* 03h */␊
␉"Math Processor", /* 04h */␊
␉"DSP Processor", /* 05h */␊
␉"Video Processor" /* 06h */␊
};␊
␊
/*====␊
===*/␊
static const char *SMBProcessorUpgrades[] = // ErmaC: strings for processor upgrade (Table Type 4 - Processor Information)␊
{␊
␉"Other", // 01h␊
␉"Other", /* 01h */␊
"Unknown",␊
"Daughter Board",␊
"ZIF Socket",␊
"Socket FM1",␊
"Socket FM2",␊
"Socket LGA2011-3",␊
"Socket LGA1356-3" // 2Ch␊
"Socket LGA1356-3" /* 2Ch */␊
};␊
␊
/*=====␊
static const char *␊
SMBMemoryDeviceTypes[] =␊
{␊
␉"RAM", /* 00h Undefined */␊
␉"RAM", /* 01h Other */␊
␉"RAM", /* 02h Unknown */␊
␉"DRAM", /* 03h DRAM */␊
␉"EDRAM", /* 04h EDRAM */␊
␉"VRAM", /* 05h VRAM */␊
␉"SRAM", /* 06h SRAM */␊
␉"RAM", /* 07h RAM */␊
␉"ROM", /* 08h ROM */␊
␉"FLASH", /* 09h FLASH */␊
␉"EEPROM", /* 0Ah EEPROM */␊
␉"FEPROM", /* 0Bh FEPROM */␊
␉"EPROM", /* 0Ch EPROM */␊
␉"CDRAM", /* 0Dh CDRAM */␊
␉"3DRAM", /* 0Eh 3DRAM */␊
␉"SDRAM", /* 0Fh SDRAM */␊
␉"SGRAM", /* 10h SGRAM */␊
␉"RDRAM", /* 11h RDRAM */␊
␉"DDR SDRAM", /* 12h DDR */␊
␉"DDR2 SDRAM", /* 13h DDR2 */␊
␉"DDR2 FB-DIMM", /* 14h DDR2 FB-DIMM */␊
␉"RAM", /* 15h unused */␊
␉"RAM", /* 16h unused */␊
␉"RAM", /* 17h unused */␊
␉"DDR3", /* 18h DDR3, chosen in [5776134] */␊
␉"FBD2" /* 19h FBD2 */␊
␉"RAM", /* 00h Undefined */␊
␉"RAM", /* 01h Other */␊
␉"RAM", /* 02h Unknown */␊
␉"DRAM", /* 03h DRAM */␊
␉"EDRAM", /* 04h EDRAM */␊
␉"VRAM", /* 05h VRAM */␊
␉"SRAM", /* 06h SRAM */␊
␉"RAM", /* 07h RAM */␊
␉"ROM", /* 08h ROM */␊
␉"FLASH", /* 09h FLASH */␊
␉"EEPROM", /* 0Ah EEPROM */␊
␉"FEPROM", /* 0Bh FEPROM */␊
␉"EPROM", /* 0Ch EPROM */␊
␉"CDRAM", /* 0Dh CDRAM */␊
␉"3DRAM", /* 0Eh 3DRAM */␊
␉"SDRAM", /* 0Fh SDRAM */␊
␉"SGRAM", /* 10h SGRAM */␊
␉"RDRAM", /* 11h RDRAM */␊
␉"DDR SDRAM", /* 12h DDR */␊
␉"DDR2 SDRAM", /* 13h DDR2 */␊
␉"DDR2 FB-DIMM", /* 14h DDR2 FB-DIMM */␊
␉"RAM", /* 15h unused */␊
␉"RAM", /* 16h unused */␊
␉"RAM", /* 17h unused */␊
␉"DDR3", /* 18h DDR3, chosen in [5776134] */␊
␉"FBD2" /* 19h FBD2 */␊
};␊
␊
static const int kSMBMemoryDeviceTypeCount = sizeof(SMBMemoryDeviceTypes) /␊
char *stringPtr = (char *)structHeader + structHeader->length;␊
printHeader(structHeader);␊
␉DBG("OEM Strings:\n");␊
for (SMBByte i = 1; i <= ((SMBOEMStrings *)structHeader)->count; i++) {␊
SMBByte i;␊
for (i = 1; i <= ((SMBOEMStrings *)structHeader)->count; i++) {␊
DBG("\tString %d: %s\n", i, stringPtr);␊
stringPtr = stringPtr + strlen(stringPtr) + 1;␊
}␊
branches/Bungo/i386/libsaio/smbios.h
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␉SMBString serialNumber;␊
␉SMBString assetTag;␊
␉SMBString partNumber;␊
␉// 2.5+ spec␊
␉// 2.5+ spec (40 bytes)␊
//␉SMBByte coreCount;␊
//␉SMBByte coreEnabled;␊
//␉SMBByte threadCount;␊
//␉SMBWord processorCharacteristics;␊
␉// 2.6+ spec␊
//␉SMBWord processorFuncSupport;␊
␉// 2.6+ spec (42 bytes)␊
//␉SMBWord processorFamily2;␊
} __attribute__((packed)) SMBProcessorInformation;␊
␊
␉SMBByte slotCharacteristics1;␊
␉// 2.1+ spec (13 bytes)␊
␉SMBByte slotCharacteristics2;␊
␉// 2.6+ spec␊
␉// 2.6+ spec (17 bytes)␊
//␉SMBWord␉␉segmentGroupNumber;␊
//␉SMBByte␉␉busNumber;␊
//␉SMBByte␉␉devFuncNumber;␊
//␉SMBByte␉␉deviceFunctionNumber;␊
} __attribute__((packed)) SMBSystemSlot;␊
␊
/* ===================␊
␉SMBString serialNumber;␊
␉SMBString assetTag;␊
␉SMBString partNumber;␊
␉// 2.6+ spec␊
//␉SMBByte memoryAtributes;␊
␉// 2.6+ spec (28 bytes)␊
//␉SMBByte attributes;␊
␉// 2.7+ spec␊
//␉SMBDWord memoryExtSize;␊
//␉SMBWord confMemClkSpeed;␊
␉SMBWord ProcessorBusSpeed; // MT/s unit␊
} __attribute__((packed)) SMBOemProcessorBusSpeed;␊
␊
/* ==============================================␊
OEM Platform Feature (Apple Specific - Type 133)␊
================================================ */␊
struct SMBOemPlatformFeature␊
{␊
␉SMB_STRUCT_HEADER␊
␉SMBWord PlatformFeature;␊
} __attribute__((packed)) SMBOemPlatformFeature;␊
␊
//----------------------------------------------------------------------------------------------------------␊
␊
/* From Foundation/Efi/Guid/Smbios/SmBios.h */␊
branches/Bungo/i386/libsaio/fake_efi.c
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static const char SYSTEM_TYPE_PROP[] = "system-type";␊
static const char MODEL_PROP[] = "Model";␊
static const char BOARDID_PROP[] = "board-id";␊
␊
static const char DEV_PATH_SUP[] = "DevicePathsSupported";␊
static uint32_t DevPathSup = 1;␊
/*␊
* Get an smbios option string option to convert to EFI_CHAR16 string␊
*/␊
␉// too so we might as well create it so we have a pointer for it too.␊
␉node = DT__AddChild(node, "efi");␊
␊
␉if (archCpuType == CPU_TYPE_I386)␊
␉{␊
␉if (archCpuType == CPU_TYPE_I386) {␊
␉␉DT__AddProperty(node, FIRMWARE_ABI_PROP, sizeof(FIRMWARE_ABI_32_PROP_VALUE), (char*)FIRMWARE_ABI_32_PROP_VALUE);␊
␉}␊
␉else␊
␉{␊
␉} else {␊
␉␉DT__AddProperty(node, FIRMWARE_ABI_PROP, sizeof(FIRMWARE_ABI_64_PROP_VALUE), (char*)FIRMWARE_ABI_64_PROP_VALUE);␊
␉}␊
␊
␉// is set up. That is, name and table properties␊
␉Node *runtimeServicesNode = DT__AddChild(node, "runtime-services");␊
␊
␉if (archCpuType == CPU_TYPE_I386)␊
␉{␊
␉if (archCpuType == CPU_TYPE_I386) {␊
␉␉// The value of the table property is the 32-bit physical address for the RuntimeServices table.␊
␉␉// Since the EFI system table already has a pointer to it, we simply use the address of that pointer␊
␉␉// for the pointer to the property data. Warning.. DT finalization calls free on that but we're not␊
␉␉// the only thing to use a non-malloc'd pointer for something in the DT␊
␊
␉␉DT__AddProperty(runtimeServicesNode, "table", sizeof(uint64_t), &gST32->RuntimeServices);␊
␉}␊
␉else␊
␉{␊
␉} else {␊
␉␉DT__AddProperty(runtimeServicesNode, "table", sizeof(uint64_t), &gST64->RuntimeServices);␊
␉}␊
␊
␉// the value in the fsbFrequency global and not an malloc'd pointer␊
␉// because the DT_AddProperty function does not copy its args.␊
␊
␉if (Platform.CPU.FSBFrequency != 0)␊
␉{␊
␉if (Platform.CPU.FSBFrequency != 0) {␊
␉␉DT__AddProperty(efiPlatformNode, FSB_Frequency_prop, sizeof(uint64_t), &Platform.CPU.FSBFrequency);␊
␉}␊
␊
␉// Export TSC and CPU frequencies for use by the kernel or KEXTs␊
␉if (Platform.CPU.TSCFrequency != 0)␊
␉{␊
␉if (Platform.CPU.TSCFrequency != 0) {␊
␉␉DT__AddProperty(efiPlatformNode, TSC_Frequency_prop, sizeof(uint64_t), &Platform.CPU.TSCFrequency);␊
␉}␊
␊
␉if (Platform.CPU.CPUFrequency != 0)␊
␉{␊
␉if (Platform.CPU.CPUFrequency != 0) {␊
␉␉DT__AddProperty(efiPlatformNode, CPU_Frequency_prop, sizeof(uint64_t), &Platform.CPU.CPUFrequency);␊
␉}␊
␊
␉DT__AddProperty(efiPlatformNode,DEV_PATH_SUP, sizeof(uint32_t), &DevPathSup);␊
␊
␉// Bungo␊
␉/* Export system-id. Can be disabled with SystemId=No in com.apple.Boot.plist␊
␉if ((ret=getSystemID())) {␊
␉DT__AddProperty(efiPlatformNode, SYSTEM_ID_PROP, UUID_LEN, (EFI_UINT32 *)Platform.UUID);␊
␊
␉// Export SystemSerialNumber if present␊
␉if ((ret16=getSmbiosChar16("SMserial", &len)))␊
␉{␊
␉if ((ret16=getSmbiosChar16("SMserial", &len))) {␊
␉␉DT__AddProperty(efiPlatformNode, SYSTEM_SERIAL_PROP, len, ret16);␊
␉}␊
␊
␉// Export Model if present␊
␉if ((ret16=getSmbiosChar16("SMproductname", &len)))␊
␉{␊
␉if ((ret16=getSmbiosChar16("SMproductname", &len))) {␊
␉␉DT__AddProperty(efiPlatformNode, MODEL_PROP, len, ret16);␊
␉}␊
␊
branches/Bungo/i386/libsaio/smbios_getters.c
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␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
␉␉␉␉␉case CPU_MODEL_HASWELL:␊
␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␊
␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␊
␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊
␊
␉␉␉␉␉␉value->word = 0;␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉default:␊
␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);␊
␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
␉␉␉␉}␊
␉␉␉}␊
␉␉␉␉break;␊
␊
␉␉␉default:␊
␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);␊
␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
␉␉}␊
␉} else {␊
␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);␊
␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊
␉}␊
␊
␉return true;␊
␊
bool getProcessorInformationMaximumClock(returnType *value)␊
{␊
␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000);␊
␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊
␉return true;␊
}␊
␊
␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
␉␉␉␉␉␉qpimult &= 0x7F;␊
␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊
␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
␉␉␉␉␉␉if (qpibusspeed%100 != 0) {␊
␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
␊
␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// Xeon␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// Core i7␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// Lynnfiled Quad-Core Xeon␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// Core i7␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
␉␉␉␉␉␉␉value->word = 0x602;␉␉␉// Core i5␊
␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
␉␉␉␉␉␉␉value->word = 0x702;␉␉␉// Core i7␊
␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// Core i7␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
␉␉␉␉␉␉␉value->word = 0x602;␉␉␉// Core i5␊
␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
case CPU_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
case CPU_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
␉␉␉␉␉␉␉value->word = 0x501;␉␉// Xeon␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if(strstr(Platform.CPU.BrandString, "Core(TM) i5 CPU M 540")) {␊
␉␉␉␉␉␉␉value->word = 0x602;␉␉// Core i5␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
␉␉␉␉␉␉␉value->word = 0x701;␉␉// Core i7␊
␉␉␉␉␉␉␉value->word = 0x702;␉␉// Core i7␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
␉␉␉␉␉␉␉value->word = 0x602;␉␉// Core i5␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
␉␉␉␉␉␉␉value->word = 0x501;␉␉// Xeon␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
␉␉␉␉␉␉␉value->word = 0x701;␉␉// Core i7␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
␉␉␉␉␉␉␉value->word = 0x501;␉␉// Xeon␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
␉␉␉␉␉␉␉value->word = 0x903;␉␉// Core i3␊
␉␉␉␉␉␉␉value->word = 0x902;␉␉// Core i3␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
␉␉␉␉␉␉␉value->word = 0x603;␉␉// Core i5␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
␉␉␉␉␉␉␉value->word = 0x703;␉␉// Core i7␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
␉␉␉␉␉␉␉value->word = 0x603;␉␉// Core i5␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
␉␉␉␉␉␉␉value->word = 0xA01;␉␉// Xeon␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
␉␉␉␉␉␉␉value->word = 0x903;␉␉// Core i3 - Apple doesn't use it␊
␉␉␉␉␉␉␉value->word = 0x903;␉␉// Core i3 - Apple doesn't use it - but we yes:-)␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
␉␉␉␉␉␉␉value->word = 0x604;␉␉// Core i5␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
␉␉␉␉␉␉␉value->word = 0x704;␉␉// Core i7␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
␉␉␉␉␉␉␉value->word = 0x604;␉␉// Core i5␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␉␉␉// 0x3E - Mac Pro 6,1 - shouldn't be Sandy Bridge EP refering to intel spec.?␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊
␉␉␉␉␉␉value->word = 0xA01;␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_HASWELL:␉␉␉␉// 0x3C -␊
␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␉␉␉// 0x3F -␊
␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊
␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␉␉␉// 0x46␊
if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊
␉␉␉␉␉␉␉value->word = 0xA01;␉␉// Xeon␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊
␉␉␉␉␉␉␉value->word = 0x905;␉␉// Core i3 - Apple doesn't use it␊
␉␉␉␉␉␉␉value->word = 0x904;␉␉// Core i3 - Apple doesn't use it - but we yes:-)␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊
␉␉␉␉␉␉␉value->word = 0x605;␉␉// Core i5␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊
␉␉␉␉␉␉␉value->word = 0x705;␉␉// Core i7␊
return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊
␉␉␉␉␉␉␉value->word = 0x605;␉␉// Core i5␊
branches/Bungo/package/OptionalSettings/Video.txt
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Bool@SkipAtiGfx:SkipAtiGfx=Yes␊
Bool@EnableBacklight:EnableBacklight=Yes␊
Bool@EnableDualLink:EnableDualLink=Yes␊
Bool@NvidiaGeneric:NvidiaGeneric=Yes␊
branches/Bungo/package/OptionalSettings/General.txt
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Bool@UseMemDetect:UseMemDetect=No␊
Bool@UseKernelCache:UseKernelCache=Yes␊
Bool@Wake:Wake=Yes␊
Bool@PrivateData:PrivateData=No␊
branches/Bungo/doc/BootHelp.txt
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SkipNvidiaGfx=Yes|No Skip the Automatic device-properties generation for Nvidia cards.␊
SkipAtiGfx=Yes|No Skip the Automatic device-properties generation for Ati cards.␊
␊
NvidiaGeneric =Yes|No Use the classic Nvidia name for the SystemProfiler (disabled by default).␊
␊
AtiConfig=<cardcfg> Use a different card config, e.g. AtiConfig=Megalodon.␊
AtiPorts=<value> Specify the number of ports, e.g. AtiPorts=2.␊
UseAtiROM=Yes|No Use an alternate Ati ROM image␊
UseAtiROM=Yes|No Use an alternate Ati ROM image␊
(default path: /Extra/<vendorid>_<devid>_<subsysid>.rom)␊
UseNvidiaROM=Yes|No Use an alternate Nvidia ROM image␊
UseNvidiaROM=Yes|No Use an alternate Nvidia ROM image␊
(default path: /Extra/<vendorid>_<devid>.rom)␊
VBIOS=Yes|No Inject VBIOS to device-properties.␊
VBIOS=Yes|No Inject VBIOS to device-properties.␊
display_0=<value> Inject alternate value of display-cfg into NVDA,Display-A@0 (HEX).␊
display_1=<value> Inject alternate value of display-cfg into NVDA,Display-B@1 (HEX).␊
IntelCapriFB=<value> For Intel HD 4xxx, range 0-11.␊
IntelAzulFB=<value> For Intel HD 5xxx/IRIS, range 0-15.␊
InjectIntel-ig=<value> Inject alternate value into AAPL,ig-platform-id (HEX).␊
␊
EnableBacklight=Yes␉ Enable Back light option for NVIDIA and ATI␊
EnableDualLink=Yes␉ Enable DualLink option for NVIDIA and ATI␊
EnableHDMIAudio=Yes␉ Inject HDMI audio for NVIDIA and ATI.␊
EnableBacklight=Yes␉ Enable Back light option for NVIDIA and ATI␊
EnableDualLink=Yes␉ Enable DualLink option for NVIDIA and ATI␊
EnableHDMIAudio=Yes␉ Inject HDMI audio for NVIDIA and ATI.␊
␊
EthernetBuiltIn=Yes|No Automatic "built-in"=YES device-properties generation␊
for ethernet interfaces.␊
EnableC3State=Yes Enable specific Processor power state, C3.␊
EnableC4State=Yes Enable specific Processor power state, C4.␊
␊
PrivateData=No Show masked data (serial number) in bdmesg log (enbaled by default).␊
␊
ForceFullMemInfo=Yes Force SMBIOS Table 17 to be 27 bytes long (disabled by default).␊
␊
SMBIOS=<file> Use an alternate SMBIOS.plist file␊

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Revision: 2360