Chameleon

Chameleon Commit Details

Date:2010-07-25 05:05:01 (13 years 9 months ago)
Author:mozo
Commit:238
Parents: 237
Message:Merged Rekursor's changes
Changes:
A/branches/mozodojo/GPL_V2_LICENSE
A/branches/mozodojo/README
A/branches/mozodojo/MEMTEST86_LICENSE
A/branches/mozodojo/i386/libsaio/dram_controllers.c
A/branches/mozodojo/i386/libsaio/dram_controllers.h
M/branches/mozodojo/i386/libsaio/acpi_patcher.c
M/branches/mozodojo/Chameleon.xcodeproj/project.pbxproj
M/branches/mozodojo/i386/libsaio/memvendors.h
M/branches/mozodojo/i386/libsaio/platform.c
M/branches/mozodojo/i386/libsaio/spd.c
M/branches/mozodojo/i386/libsaio/fake_efi.c
M/branches/mozodojo/i386/libsaio/platform.h
M/branches/mozodojo/i386/libsaio/pci_setup.c
M/branches/mozodojo/i386/libsaio/Makefile

File differences

branches/mozodojo/Chameleon.xcodeproj/project.pbxproj
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␉objects = {␊
␊
/* Begin PBXFileReference section */␊
␉␉B0056CD611F3868000754B65 /* boot */ = {isa = PBXFileReference; lastKnownFileType = file; path = boot; sourceTree = "<group>"; };␊
␉␉0172D0DC11FB66820030222E /* dram_controllers.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = dram_controllers.h; sourceTree = "<group>"; };␊
␉␉0172D0DD11FB66820030222E /* dram_controllers.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = dram_controllers.c; sourceTree = "<group>"; };␊
␉␉019DFBAF11FB94090013E8CC /* MEMTEST86_LICENSE */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = MEMTEST86_LICENSE; sourceTree = "<group>"; };␊
␉␉B0056CD611F3868000754B65 /* boot */ = {isa = PBXFileReference; lastKnownFileType = text; path = boot; sourceTree = "<group>"; };␊
␉␉B0056CD711F3868000754B65 /* boot.sys */ = {isa = PBXFileReference; lastKnownFileType = "compiled.mach-o.preload"; path = boot.sys; sourceTree = "<group>"; };␊
␉␉B0056CD811F3868000754B65 /* boot0 */ = {isa = PBXFileReference; lastKnownFileType = file; path = boot0; sourceTree = "<group>"; };␊
␉␉B0056CD911F3868000754B65 /* boot0hfs */ = {isa = PBXFileReference; lastKnownFileType = file; path = boot0hfs; sourceTree = "<group>"; };␊
␉␉B0056CDA11F3868000754B65 /* boot1f32 */ = {isa = PBXFileReference; lastKnownFileType = file; path = boot1f32; sourceTree = "<group>"; };␊
␉␉B0056CDB11F3868000754B65 /* boot1h */ = {isa = PBXFileReference; lastKnownFileType = file; path = boot1h; sourceTree = "<group>"; };␊
␉␉B0056CDC11F3868000754B65 /* boot1he */ = {isa = PBXFileReference; lastKnownFileType = file; path = boot1he; sourceTree = "<group>"; };␊
␉␉B0056CDD11F3868000754B65 /* boot1hp */ = {isa = PBXFileReference; lastKnownFileType = file; path = boot1hp; sourceTree = "<group>"; };␊
␉␉B0056CDE11F3868000754B65 /* cdboot */ = {isa = PBXFileReference; lastKnownFileType = file; path = cdboot; sourceTree = "<group>"; };␊
␉␉B0056CDF11F3868000754B65 /* chain0 */ = {isa = PBXFileReference; lastKnownFileType = file; path = chain0; sourceTree = "<group>"; };␊
␉␉B0056CD811F3868000754B65 /* boot0 */ = {isa = PBXFileReference; lastKnownFileType = text; path = boot0; sourceTree = "<group>"; };␊
␉␉B0056CD911F3868000754B65 /* boot0hfs */ = {isa = PBXFileReference; lastKnownFileType = text; path = boot0hfs; sourceTree = "<group>"; };␊
␉␉B0056CDA11F3868000754B65 /* boot1f32 */ = {isa = PBXFileReference; lastKnownFileType = text; path = boot1f32; sourceTree = "<group>"; };␊
␉␉B0056CDB11F3868000754B65 /* boot1h */ = {isa = PBXFileReference; lastKnownFileType = text; path = boot1h; sourceTree = "<group>"; };␊
␉␉B0056CDC11F3868000754B65 /* boot1he */ = {isa = PBXFileReference; lastKnownFileType = text; path = boot1he; sourceTree = "<group>"; };␊
␉␉B0056CDD11F3868000754B65 /* boot1hp */ = {isa = PBXFileReference; lastKnownFileType = text; path = boot1hp; sourceTree = "<group>"; };␊
␉␉B0056CDE11F3868000754B65 /* cdboot */ = {isa = PBXFileReference; lastKnownFileType = text; path = cdboot; sourceTree = "<group>"; };␊
␉␉B0056CDF11F3868000754B65 /* chain0 */ = {isa = PBXFileReference; lastKnownFileType = text; path = chain0; sourceTree = "<group>"; };␊
␉␉B0056CE011F3868000754B65 /* embedded.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = embedded.h; sourceTree = "<group>"; };␊
␉␉B0056CE111F3868000754B65 /* libsa.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; path = libsa.a; sourceTree = "<group>"; };␊
␉␉B0056CE211F3868000754B65 /* libsaio.a */ = {isa = PBXFileReference; lastKnownFileType = archive.ar; path = libsaio.a; sourceTree = "<group>"; };␊
␉␉B0056E1A11F3868000754B65 /* Users_Guide0.5.pdf */ = {isa = PBXFileReference; lastKnownFileType = image.pdf; path = Users_Guide0.5.pdf; sourceTree = "<group>"; };␊
␉␉B00F494911F6089500B1D7C5 /* aml_generator.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = aml_generator.h; sourceTree = "<group>"; };␊
␉␉B00F494A11F6089500B1D7C5 /* aml_generator.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = aml_generator.c; sourceTree = "<group>"; };␊
␉␉B04870CC11FBD948005EBBAD /* README */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = README; sourceTree = "<group>"; };␊
␉␉B04870D511FBD9AA005EBBAD /* GPL_V2_LICENSE */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; path = GPL_V2_LICENSE; sourceTree = "<group>"; };␊
/* End PBXFileReference section */␊
␊
/* Begin PBXGroup section */␊
␉␉␉␉B0056CE511F3868000754B65 /* i386 */,␊
␉␉␉␉B0056D8311F3868000754B65 /* package */,␊
␉␉␉␉B0056CD411F3868000754B65 /* sym */,␊
␉␉␉␉B04870CC11FBD948005EBBAD /* README */,␊
␉␉␉␉B0056D7C11F3868000754B65 /* TODO */,␊
␉␉␉␉B0056D7D11F3868000754B65 /* Makefile */,␊
␉␉␉␉B0056D7F11F3868000754B65 /* CREDITS */,␊
␉␉␉␉B0056D8011F3868000754B65 /* coding_standards.txt */,␊
␉␉␉␉B0056D8111F3868000754B65 /* CHANGES */,␊
␉␉␉␉B0056D8211F3868000754B65 /* APPLE_LICENSE */,␊
␉␉␉␉019DFBAF11FB94090013E8CC /* MEMTEST86_LICENSE */,␊
␉␉␉␉B04870D511FBD9AA005EBBAD /* GPL_V2_LICENSE */,␊
␉␉␉);␊
␉␉␉name = Chameleon;␊
␉␉␉sourceTree = "<group>";␊
␉␉␉␉B0056D3911F3868000754B65 /* device_tree.c */,␊
␉␉␉␉B0056D3A11F3868000754B65 /* device_tree.h */,␊
␉␉␉␉B0056D3B11F3868000754B65 /* disk.c */,␊
␉␉␉␉0172D0DD11FB66820030222E /* dram_controllers.c */,␊
␉␉␉␉0172D0DC11FB66820030222E /* dram_controllers.h */,␊
␉␉␉␉B0056D3C11F3868000754B65 /* efi.h */,␊
␉␉␉␉B0056D3D11F3868000754B65 /* ext2fs.c */,␊
␉␉␉␉B0056D3E11F3868000754B65 /* ext2fs.h */,␊
branches/mozodojo/i386/libsaio/acpi_patcher.c
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␉␉␊
␉␉␉␉␉␉struct aml_chunk* tmpl = aml_add_package(pack);␊
␉␉␉␉␉␉␉cstate_resource_template[11] = 0x00; // C1␊
␉␉␉␉␉␉␉cstate_resource_template[10] = 0x00; // C1␊
␉␉␉␉␉␉␉aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template));␊
␉␉␉␉␉␉␉aml_add_byte(tmpl, 0x01); // C1␊
␉␉␉␉␉␉␉aml_add_byte(tmpl, 0x01); // Latency␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉tmpl = aml_add_package(pack);␊
␉␉␉␉␉␉␉␉cstate_resource_template[11] = 0x10; // C2␊
␉␉␉␉␉␉␉␉cstate_resource_template[10] = 0x01; // C2␊
␉␉␉␉␉␉␉␉aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template));␊
␉␉␉␉␉␉␉␉aml_add_byte(tmpl, 0x02); // C2␊
␉␉␉␉␉␉␉␉aml_add_byte(tmpl, fadt->C2_Latency);␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉tmpl = aml_add_package(pack);␊
␉␉␉␉␉␉␉cstate_resource_template[11] = 0x30; // C4␊
␉␉␉␉␉␉␉cstate_resource_template[10] = 0x03; // C4␊
␉␉␉␉␉␉␉aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template));␊
␉␉␉␉␉␉␉aml_add_byte(tmpl, 0x04); // C4␊
␉␉␉␉␉␉␉aml_add_word(tmpl, fadt->C3_Latency); // TODO: right latency for C4␊
␉␉␉␉␉␉␉aml_add_word(tmpl, fadt->C3_Latency / 2); // TODO: right latency for C4␊
␉␉␉␉␉␉␉aml_add_byte(tmpl, 0xfa); // Power␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉else␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉tmpl = aml_add_package(pack);␊
␉␉␉␉␉␉␉cstate_resource_template[11] = 0x20; // C3␊
␉␉␉␉␉␉␉cstate_resource_template[10] = 0x02; // C3␊
␉␉␉␉␉␉␉aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template));␊
␉␉␉␉␉␉␉aml_add_byte(tmpl, 0x03); // C3␊
␉␉␉␉␉␉␉aml_add_word(tmpl, fadt->C3_Latency);␊
branches/mozodojo/i386/libsaio/spd.c
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uint8_t bank = 0;␊
uint8_t code = 0;␊
int i = 0;␊
char * spd = slot->spd;␊
uint8_t * spd = (uint8_t *) slot->spd;␊
␊
if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { // DDR3␊
bank = spd[SPD_DDR3_MEMORY_BANK];␊
bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1␊
code = spd[SPD_DDR3_MEMORY_CODE];␊
for (i=0; i < VEN_MAP_SIZE; i++)␊
if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
␊
// determine spd speed␊
speed = getDDRspeedMhz(slot->spd);␊
if (slot->Frequency<speed) slot->Frequency = speed; // should test the mem controller to get potential overclocking info ? ␊
if (slot->Frequency<speed) slot->Frequency = speed;␊
␉␉␉␊
␉␉␉// pci memory controller if available, is more reliable␊
␉␉␉if (Platform.RAM.Frequency > 0) {␊
␉␉␉␉uint32_t freq = (uint32_t)Platform.RAM.Frequency / 500000;␊
␉␉␉␉// now round off special cases␊
␉␉␉␉uint32_t fmod100 = freq %100;␊
␉␉␉␉switch(fmod100) {␊
␉␉␉␉␉case 32:␉freq++;␉break;␊
␉␉␉␉␉case 65:␉freq++; break;␊
␉␉␉␉␉case 98:␉freq+=2;break;␊
␉␉␉␉␉case 99:␉freq++; break;␊
␉␉␉␉}␊
␉␉␉␉slot->Frequency = freq;␊
␉␉␉}␊
␉␉␉␊
␉␉␉printf("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n", ␊
i, ␊
(int)slot->Type,␊
␊
void scan_spd(PlatformInfo_t *p)␊
{␊
␉printf("\n--> Start of mem detect:\n");␊
find_and_read_smbus_controller(root_pci_dev);␊
␉printf("\n<-- End of mem detect.\n");␊
}␊
branches/mozodojo/i386/libsaio/Makefile
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␉smbios_patcher.o fake_efi.o ext2fs.o \␊
␉hpet.o spd.o usb.o pci_setup.o \␊
␉device_inject.o nvidia.o ati.o pci_root.o \␊
␉convert.o mem.o aml_generator.o␊
␉convert.o mem.o aml_generator.o dram_controllers.o␊
␊
␊
SAIO_EXTERN_OBJS = console.o␊
branches/mozodojo/i386/libsaio/memvendors.h
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} VenIdName;␊
␊
VenIdName vendorMap[] = {␊
{ 0, 0x01, "AMD"},␊
{ 0, 0x01, "AMD"},␊
␉␉{ 0, 0x02, "AMI"},␊
␉␉{ 0, 0x83, "Fairchild"},␊
␉␉{ 0, 0x04, "Fujitsu"},␊
␉␉{ 4, 0xfd, "Focus Enhancements"},␊
␉␉{ 4, 0xfe, "Xyratex"},␊
␉␉{ 5, 0x01, "Specular Networks"},␊
␉␉{ 5, 0x02, "Patriot Memory (PDP Systems)"},␊
␉␉{ 5, 0x02, "PDP Systems"},␊
␉␉{ 5, 0x83, "U-Chip Technology Corp."},␊
␉␉{ 5, 0x04, "Silicon Optix"},␊
␉␉{ 5, 0x85, "Greenfield Networks"},␊
branches/mozodojo/i386/libsaio/dram_controllers.c
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/*␊
* dram controller access and scan from the pci host controller␊
* Integrated and adapted for chameleon 2.0 RC5 by Rekursor from original :␊
*␊
* memtest86␊
*␊
* Released under version 2 of the Gnu Public License.␊
* By Chris Brady, cbrady@sgi.com␊
* ----------------------------------------------------␊
* MemTest86+ V4.00 Specific code (GPL V2.0)␊
* By Samuel DEMEULEMEESTER, sdemeule@memtest.org␊
* http://www.canardpc.com - http://www.memtest.org␊
*/␊
␊
#include "libsaio.h"␊
#include "bootstruct.h"␊
#include "pci.h"␊
#include "platform.h"␊
#include "dram_controllers.h"␊
␊
#ifndef DEBUG_DRAM␊
#define DEBUG_DRAM 0␊
#endif␊
␊
#if DEBUG_DRAM␊
#define DBG(x...) printf(x)␊
#else␊
#define DBG(x...)␊
#endif␊
␊
/*␊
* Initialise memory controller functions␊
*/␊
␊
// Setup P35 Memory Controller␊
static void setup_p35(pci_dt_t *dram_dev)␊
{␊
␉uint32_t dev0;␊
␉␊
␉// Activate MMR I/O␊
␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
␉if (!(dev0 & 0x1))␊
␉␉pci_config_write8(dram_dev->dev.addr, 0x48, (dev0 | 1));␊
}␊
␊
int nhm_bus = 0x3F;␊
␊
// Setup Nehalem Integrated Memory Controller␊
static void setup_nhm(pci_dt_t *dram_dev)␊
{␊
␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
␉unsigned long did, vid;␊
␉int i;␊
␉␊
␉// Nehalem supports Scrubbing␊
␉// First, locate the PCI bus where the MCH is located␊
␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊
␉{␊
␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
␉␉vid &= 0xFFFF;␊
␉␉did &= 0xFF00;␊
␉␉␊
␉␉if(vid == 0x8086 && did >= 0x2C00)␊
␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
␉}␊
}␊
␊
/*␊
* Retrieve memory controller fsb functions␊
*/␊
␊
␊
// Get i965 Memory Speed␊
static void get_fsb_i965(pci_dt_t *dram_dev)␊
{␊
␉uint32_t dev0, mch_ratio, mch_cfg, mch_fsb;␊
␊
␉long *ptr;␊
␉␊
␉// Find Ratio␊
␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
␉dev0 &= 0xFFFFC000;␊
␉ptr = (long*)(dev0 + 0xC00);␊
␉mch_cfg = *ptr & 0xFFFF;␊
␉␊
␉mch_ratio = 100000;␊
␉␊
␉switch (mch_cfg & 7)␊
␉{␊
␉␉case 0: mch_fsb = 1066; break;␊
␉␉case 1: mch_fsb = 533; break;␊
␉ default: ␊
␉␉case 2: mch_fsb = 800; break;␊
␉␉case 3: mch_fsb = 667; break;␉␉␊
␉␉case 4: mch_fsb = 1333; break;␊
␉␉case 6: mch_fsb = 1600; break;␉␉␉␉␉␊
␉}␊
␉␊
␉DBG("mch_fsb %d\n", mch_fsb);␊
␉␊
␉switch (mch_fsb)␊
␉{␊
␉␉case 533:␊
␉␉␉switch ((mch_cfg >> 4) & 7)␊
␉␉{␊
␉␉␉case 1:␉mch_ratio = 200000; break;␊
␉␉␉case 2:␉mch_ratio = 250000; break;␊
␉␉␉case 3:␉mch_ratio = 300000; break;␊
␉␉}␊
␉␉␉break;␊
␉␉␉␊
␉␉default:␊
␉␉case 800:␊
␉␉␉switch ((mch_cfg >> 4) & 7)␊
␉␉{␊
␉␉␉case 0:␉mch_ratio = 100000; break;␊
␉␉␉case 1:␉mch_ratio = 125000; break;␊
␉␉␉case 2:␉mch_ratio = 166667; break; // 1.666666667␊
␉␉␉case 3:␉mch_ratio = 200000; break;␊
␉␉␉case 4:␉mch_ratio = 266667; break; // 2.666666667␊
␉␉␉case 5:␉mch_ratio = 133553; break; // 1.333333333␊
␉␉}␊
␉␉␉break;␊
␉␉␉␊
␉␉case 1066:␊
␉␉␉switch ((mch_cfg >> 4) & 7)␊
␉␉{␊
␉␉␉case 1:␉mch_ratio = 100000; break;␊
␉␉␉case 2:␉mch_ratio = 125000; break;␊
␉␉␉case 3:␉mch_ratio = 150000; break;␊
␉␉␉case 4:␉mch_ratio = 200000; break;␊
␉␉␉case 5:␉mch_ratio = 250000; break;␊
␉␉}␊
␉␉␉break;␊
␉␉␉␊
␉␉case 1333:␊
␉␉␉switch ((mch_cfg >> 4) & 7)␊
␉␉{␊
␉␉␉case 2:␉mch_ratio = 100000; break;␊
␉␉␉case 3:␉mch_ratio = 120000; break;␊
␉␉␉case 4:␉mch_ratio = 160000; break;␊
␉␉␉case 5:␉mch_ratio = 200000; break;␊
␉␉}␊
␉␉␉break;␊
␉␉␉␊
␉␉case 1600:␊
␉␉␉switch ((mch_cfg >> 4) & 7)␊
␉␉{␊
␉␉␉case 3:␉mch_ratio = 100000; break;␊
␉␉␉case 4:␉mch_ratio = 133333; break; // 1.333333333␊
␉␉␉case 5:␉mch_ratio = 150000; break;␊
␉␉␉case 6:␉mch_ratio = 200000; break;␊
␉␉}␊
␉␉␉break;␊
␉}␊
␉␊
␉DBG("mch_ratio %d\n", mch_ratio);␊
␊
␉// Compute RAM Frequency␊
␉Platform.RAM.Frequency = (Platform.CPU.FSBFrequency * mch_ratio) / 100000;␊
␉␊
␉DBG("ram_fsb %d\n", Platform.RAM.Frequency);␊
␊
}␊
␊
// Get i965m Memory Speed␊
static void get_fsb_im965(pci_dt_t *dram_dev)␊
{␊
␉uint32_t dev0, mch_ratio, mch_cfg, mch_fsb;␊
␊
␉long *ptr;␊
␉␊
␉// Find Ratio␊
␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
␉dev0 &= 0xFFFFC000;␊
␉ptr = (long*)(dev0 + 0xC00);␊
␉mch_cfg = *ptr & 0xFFFF;␊
␉␊
␉mch_ratio = 100000;␊
␉␊
␉switch (mch_cfg & 7)␊
␉{␊
␉␉case 1: mch_fsb = 533; break;␊
␉␉default: ␊
␉␉case 2:␉mch_fsb = 800; break;␊
␉␉case 3:␉mch_fsb = 667; break;␉␉␉␉␊
␉}␊
␉␊
␉switch (mch_fsb)␊
␉{␊
␉␉case 533:␊
␉␉␉switch ((mch_cfg >> 4) & 7)␊
␉␉␉{␊
␉␉␉␉case 1:␉mch_ratio = 125000; break;␊
␉␉␉␉case 2:␉mch_ratio = 150000; break;␊
␉␉␉␉case 3:␉mch_ratio = 200000; break;␊
␉␉␉}␊
␉␉␉break;␊
␉␉␉␊
␉␉case 667:␊
␉␉␉switch ((mch_cfg >> 4)& 7)␊
␉␉␉{␊
␉␉␉␉case 1:␉mch_ratio = 100000; break;␊
␉␉␉␉case 2:␉mch_ratio = 120000; break;␊
␉␉␉␉case 3:␉mch_ratio = 160000; break;␊
␉␉␉␉case 4:␉mch_ratio = 200000; break;␊
␉␉␉␉case 5:␉mch_ratio = 240000; break;␊
␉␉␉}␊
␉␉␉break;␊
␉␉␉␊
␉␉default:␊
␉␉case 800:␊
␉␉␉switch ((mch_cfg >> 4) & 7)␊
␉␉␉{␊
␉␉␉␉case 1:␉mch_ratio = 83000; break; // 0.833333333␊
␉␉␉␉case 2:␉mch_ratio = 100000; break;␊
␉␉␉␉case 3:␉mch_ratio = 133333; break; // 1.333333333␊
␉␉␉␉case 4:␉mch_ratio = 166667; break; // 1.666666667␊
␉␉␉␉case 5:␉mch_ratio = 200000; break;␊
␉␉␉}␊
␉␉␉break;␊
␉␉␉␊
␉}␊
␉␊
␉// Compute RAM Frequency␊
␉Platform.RAM.Frequency = (Platform.CPU.FSBFrequency * mch_ratio) / 100000;␊
}␊
␊
␊
// Get iCore7 Memory Speed␊
static void get_fsb_nhm(pci_dt_t *dram_dev)␊
{␊
␉uint32_t mch_ratio, mc_dimm_clk_ratio;␊
␉␊
␉// Get the clock ratio␊
␉mc_dimm_clk_ratio = pci_config_read16(PCIADDR(nhm_bus, 3, 4), 0x54 );␊
␉mch_ratio = (mc_dimm_clk_ratio & 0x1F);␊
␉␊
␉// Compute RAM Frequency␊
␉Platform.RAM.Frequency = Platform.CPU.FSBFrequency * mch_ratio / 2;␊
}␊
␊
/*␊
* Retrieve memory controller info functions␊
*/␊
␊
// Get i965 Memory Timings␊
static void get_timings_i965(pci_dt_t *dram_dev)␊
{ ␊
␉// Thanks for CDH optis␊
␉uint32_t dev0, c0ckectrl, c1ckectrl, offset;␊
␉uint32_t ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;␊
␊
␉long *ptr;␊
␉␊
␉// Read MMR Base Address␊
␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
␉dev0 &= 0xFFFFC000;␊
␉␊
␉ptr = (long*)(dev0 + 0x260);␊
␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊
␉␊
␉ptr = (long*)(dev0 + 0x660);␊
␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
␉␊
␉// If DIMM 0 not populated, check DIMM 1␊
␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);␊
␉␊
␉ptr = (long*)(dev0 + offset + 0x29C);␊
␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
␉␊
␉ptr = (long*)(dev0 + offset + 0x250);␉␊
␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
␉␊
␉ptr = (long*)(dev0 + offset + 0x252);␊
␉ACT_Register = *ptr & 0xFFFFFFFF;␊
␉␊
␉ptr = (long*)(dev0 + offset + 0x258);␊
␉Read_Register = *ptr & 0xFFFFFFFF;␊
␉␊
␉ptr = (long*)(dev0 + offset + 0x244);␊
␉Misc_Register = *ptr & 0xFFFFFFFF;␊
␉␊
␉// 965 Series only support DDR2␊
␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊
␉␊
␉// CAS Latency (tCAS)␊
␉Platform.RAM.CAS = ((ODT_Control_Register >> 17) & 7) + 3;␊
␉␊
␉// RAS-To-CAS (tRCD)␊
␉Platform.RAM.TRC = (Read_Register >> 16) & 0xF;␊
␉␊
␉// RAS Precharge (tRP)␊
␉Platform.RAM.TRP = (ACT_Register >> 13) & 0xF;␊
␉␊
␉// RAS Active to precharge (tRAS)␊
␉Platform.RAM.RAS = (Precharge_Register >> 11) & 0x1F;␊
␉␊
␉if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF))␊
␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
␉else␊
␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
}␊
␊
// Get im965 Memory Timings␊
static void get_timings_im965(pci_dt_t *dram_dev)␊
{␊
␉// Thanks for CDH optis␊
␉uint32_t dev0, c0ckectrl, c1ckectrl, offset, ODT_Control_Register, Precharge_Register;␊
␉long *ptr;␊
␉␊
␉// Read MMR Base Address␊
␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
␉dev0 &= 0xFFFFC000;␊
␉␊
␉ptr = (long*)(dev0 + 0x1200);␊
␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊
␉␊
␉ptr = (long*)(dev0 + 0x1300);␊
␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
␉␊
␉// If DIMM 0 not populated, check DIMM 1␊
␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x100);␊
␉␊
␉ptr = (long*)(dev0 + offset + 0x121C);␊
␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
␉␊
␉ptr = (long*)(dev0 + offset + 0x1214);␉␊
␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
␉␊
␉// Series only support DDR2␊
␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊
␉␊
␉// CAS Latency (tCAS)␊
␉Platform.RAM.CAS = ((ODT_Control_Register >> 23) & 7) + 3;␊
␉␊
␉// RAS-To-CAS (tRCD)␊
␉Platform.RAM.TRC = ((Precharge_Register >> 5) & 7) + 2;␊
␉␊
␉// RAS Precharge (tRP)␊
␉Platform.RAM.TRP= (Precharge_Register & 7) + 2;␊
␉␊
␉// RAS Active to precharge (tRAS)␊
␉Platform.RAM.RAS = (Precharge_Register >> 21) & 0x1F;␊
␉␊
␉if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) ␊
␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
␉else␊
␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
}␊
␊
// Get P35 Memory Timings␊
static void get_timings_p35(pci_dt_t *dram_dev)␊
{ ␊
␉// Thanks for CDH optis␊
␉unsigned long dev0, Memory_Check, c0ckectrl, c1ckectrl, offset;␊
␉unsigned long ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;␊
␉long *ptr;␊
␉␊
␉//Device_ID = pci_config_read16(dram_dev->dev.addr, 0x02);␊
␉//Device_ID &= 0xFFFF;␊
␉␊
␉// Now, read MMR Base Address␊
␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
␉dev0 &= 0xFFFFC000;␊
␉␊
␉ptr = (long*)(dev0 + 0x260);␊
␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊
␉␊
␉ptr = (long*)(dev0 + 0x660);␊
␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
␉␊
␉// If DIMM 0 not populated, check DIMM 1␊
␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);␊
␉␊
␉ptr = (long*)(dev0 + offset + 0x265);␊
␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
␉␊
␉ptr = (long*)(dev0 + offset + 0x25D);␉␊
␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
␉␊
␉ptr = (long*)(dev0 + offset + 0x252);␊
␉ACT_Register = *ptr & 0xFFFFFFFF;␊
␉␊
␉ptr = (long*)(dev0 + offset + 0x258);␊
␉Read_Register = *ptr & 0xFFFFFFFF;␊
␉␊
␉ptr = (long*)(dev0 + offset + 0x244);␊
␉Misc_Register = *ptr & 0xFFFFFFFF;␊
␉␊
␉ptr = (long*)(dev0 + offset + 0x1E8);␊
␉Memory_Check = *ptr & 0xFFFFFFFF;␉␊
␉␊
␉// On P45, check 1A8␊
␉if(dram_dev->device_id > 0x2E00) {␊
␉␉ptr = (long*)(dev0 + offset + 0x1A8);␊
␉␉Memory_Check = *ptr & 0xFFFFFFFF;␉␊
␉␉Memory_Check >>= 2;␊
␉␉Memory_Check &= 1;␊
␉␉Memory_Check = !Memory_Check;␊
␉} else {␊
␉␉ptr = (long*)(dev0 + offset + 0x1E8);␊
␉␉Memory_Check = *ptr & 0xFFFFFFFF;␉␉␊
␉}␊
␉␊
␉// Determine DDR-II or DDR-III␊
␉if (Memory_Check & 1)␊
␉␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊
␉else␊
␉␉Platform.RAM.Type = SMB_MEM_TYPE_DDR3;␊
␉␊
␉// CAS Latency (tCAS)␊
␉if(dram_dev->device_id > 0x2E00)␊
␉␉Platform.RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 6;␊
␉else␊
␉␉Platform.RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 9;␊
␉␊
␉// RAS-To-CAS (tRCD)␊
␉Platform.RAM.TRC = (Read_Register >> 17) & 0xF;␊
␉␊
␉// RAS Precharge (tRP)␊
␉Platform.RAM.TRP = (ACT_Register >> 13) & 0xF;␊
␉␊
␉// RAS Active to precharge (tRAS)␊
␉Platform.RAM.RAS = Precharge_Register & 0x3F;␊
␉␊
␉// Channel configuration␊
␉if (((c0ckectrl >> 20) & 0xF) && ((c1ckectrl >> 20) & 0xF)) ␊
␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
␉else␊
␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
}␊
␊
// Get Nehalem Memory Timings␊
static void get_timings_nhm(pci_dt_t *dram_dev)␊
{␊
␉unsigned long mc_channel_bank_timing, mc_control, mc_channel_mrs_value;␊
␉int fvc_bn = 4;␊
␉␊
␉// Find which channels are populated␊
␉mc_control = pci_config_read16(PCIADDR(nhm_bus, 3, 0), 0x48);␊
␉mc_control = (mc_control >> 8) & 0x7;␊
␉␊
␉// DDR-III␊
␉Platform.RAM.Type = SMB_MEM_TYPE_DDR3;␊
␉␊
␉// Get the first valid channel␊
␉if(mc_control & 1)␊
␉␉fvc_bn = 4; ␊
␉else if(mc_control & 2)␊
␉␉fvc_bn = 5; ␊
␉else if(mc_control & 7) ␊
␉␉fvc_bn = 6; ␊
␉␊
␉// Now, detect timings␊
␉mc_channel_bank_timing = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x88);␊
␉mc_channel_mrs_value = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x70);␊
␉␊
␉// CAS Latency (tCAS)␊
␉Platform.RAM.CAS = ((mc_channel_mrs_value >> 4) & 0xF ) + 4;␊
␉␊
␉// RAS-To-CAS (tRCD)␊
␉Platform.RAM.TRC = (mc_channel_bank_timing >> 9) & 0xF; ␊
␉␊
␉// RAS Precharge (tRP)␊
␉Platform.RAM.CAS = (mc_channel_bank_timing >> 4) & 0x1F; ␊
␉␊
␉// RAS Active to precharge (tRAS)␊
␉Platform.RAM.TRP = mc_channel_bank_timing & 0xF;␊
␉␊
␉// Single , Dual or Triple Channels␊
␉if (mc_control == 1 || mc_control == 2 || mc_control == 4 )␊
␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
␉else if (mc_control == 7)␊
␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_TRIPLE;␊
␉else␊
␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
}␊
␊
static struct mem_controller_t dram_controllers[] = {␊
␊
␉// Default unknown chipset␊
␉{ 0, 0, "",␉NULL, NULL, NULL },␊
␊
␉// Intel␊
␉{ 0x8086, 0x7190, "VMWare",␉NULL, NULL, NULL },␊
␊
␉{ 0x8086, 0x1A30, "i845",␉NULL, NULL, NULL },␊
␉␊
␉{ 0x8086, 0x2970, "i946PL/GZ",␉␉setup_p35, get_fsb_i965, get_timings_i965 },␊
␉{ 0x8086, 0x2990, "Q963/Q965",␉␉setup_p35, get_fsb_i965, get_timings_i965 },␊
␉{ 0x8086, 0x29A0, "P965/G965",␉␉setup_p35, get_fsb_i965, get_timings_i965 },␊
␊
␉{ 0x8086, 0x2A00, "GM965/GL960",␉setup_p35, get_fsb_im965, get_timings_im965 },␊
␉{ 0x8086, 0x2A10, "GME965/GLE960",␉setup_p35, get_fsb_im965, get_timings_im965 },␊
␉{ 0x8086, 0x2A40, "PM/GM45/47",␉␉setup_p35, get_fsb_im965, get_timings_im965 },␉␊
␊
␉{ 0x8086, 0x29B0, "Q35",␉␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
␉{ 0x8086, 0x29C0, "P35/G33",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
␉{ 0x8086, 0x29D0, "Q33",␉␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
␉{ 0x8086, 0x29E0, "X38/X48",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␉␉␊
␉{ 0x8086, 0x2E00, "Eaglelake",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␊
␉{ 0x8086, 0x2E10, "Q45/Q43",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
␉{ 0x8086, 0x2E20, "P45/G45",␉␉setup_p35, get_fsb_i965, get_timings_p35 },␉␊
␉{ 0x8086, 0x2E30, "G41",␉␉␉setup_p35, get_fsb_i965, get_timings_p35 },␊
␉␊
␉{ 0x8086, 0xD131, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
␉{ 0x8086, 0xD132, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
␉{ 0x8086, 0x3400, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉ get_timings_nhm },␊
␉{ 0x8086, 0x3401, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
␉{ 0x8086, 0x3402, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
␉{ 0x8086, 0x3403, "NHM IMC",␉␉setup_nhm, get_fsb_nhm, get_timings_nhm },␊
␉␊
};␊
␊
static const char *memory_channel_types[] =␊
{␊
␉"Unknown", "Single", "Dual", "Triple"␊
};␉␉␉␊
␊
void scan_dram_controller(pci_dt_t *dram_dev)␊
{␊
␉int i;␊
␉for(i = 1; i < sizeof(dram_controllers) / sizeof(dram_controllers[0]); i++)␊
␉if ((dram_controllers[i].vendor == dram_dev->vendor_id) ␊
␉␉␉␉&& (dram_controllers[i].device == dram_dev->device_id))␊
␉␉{␊
␉␉␉verbose("%s%s DRAM Controller [%4x:%4x] at %02x:%02x.%x\n", ␊
␉␉␉␉␉␉(dram_dev->vendor_id == 0x8086) ? "Intel " : "" ,␊
␉␉␉␉␉␉dram_controllers[i].name, dram_dev->vendor_id, dram_dev->device_id,␊
␉␉␉␉␉␉dram_dev->dev.bits.bus, dram_dev->dev.bits.dev, dram_dev->dev.bits.func);␊
␉␉␉␊
␉␉␉if (dram_controllers[i].initialise != NULL)␊
␉␉␉␉dram_controllers[i].initialise(dram_dev);␊
␉␉␉␉␉␉␉␊
␉␉␉if (dram_controllers[i].poll_timings != NULL)␊
␉␉␉␉dram_controllers[i].poll_timings(dram_dev);␊
␉␉␉␉␉␉␉␉␊
␉␉␉if (dram_controllers[i].poll_speed != NULL)␊
␉␉␉␉dram_controllers[i].poll_speed(dram_dev);␊
␊
␉␉␉verbose("Frequency detected: %d MHz (%d) %s Channel %d-%d-%d-%d\n", ␊
␉␉␉␉␉␉(uint32_t)Platform.RAM.Frequency / 1000000,␊
␉␉␉␉␉␉(uint32_t)Platform.RAM.Frequency / 500000,␊
␉␉␉␉␉␉memory_channel_types[Platform.RAM.Channels],␊
␉␉␉␉␉␉Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS␊
␉␉␉␉ );␊
␉␉␉␊
␉␉}␉␊
}␉␊
branches/mozodojo/i386/libsaio/dram_controllers.h
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/*␊
* dram controller access and scan from the pci host controller␊
* Adapted for chameleon 2.0 RC5 by Rekursor from original :␊
*␊
* memtest86␊
*␊
* Released under version 2 of the Gnu Public License.␊
* By Chris Brady, cbrady@sgi.com␊
* ----------------------------------------------------␊
* MemTest86+ V4.00 Specific code (GPL V2.0)␊
* By Samuel DEMEULEMEESTER, sdemeule@memtest.org␊
* http://www.canardpc.com - http://www.memtest.org␊
*/␊
␊
#ifndef __LIBSAIO_DRAM_CONTROLLERS_H␊
#define __LIBSAIO_DRAM_CONTROLLERS_H␊
␊
#include "libsaio.h"␊
␊
struct mem_controller_t {␊
␉uint16_t vendor;␊
␉uint16_t device;␊
␉char *name;␊
␉void (*initialise)(pci_dt_t *dram_dev);␊
␉void (*poll_speed)(pci_dt_t *dram_dev);␊
␉void (*poll_timings)(pci_dt_t *dram_dev);␊
};␊
␊
void scan_dram_controller(pci_dt_t *dram_dev);␊
␊
#endif /* !__LIBSAIO_DRAM_CONTROLLERS_H */␊
branches/mozodojo/i386/libsaio/platform.c
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#include "cpu.h"␊
#include "mem.h"␊
#include "spd.h"␊
#include "dram_controllers.h"␊
␊
#ifndef DEBUG_PLATFORM␊
#define DEBUG_PLATFORM 0␊
#endif␊
␊
PlatformInfo_t Platform;␊
pci_dt_t * dram_controller_dev = NULL;␊
␊
/** Return if a CPU feature specified by feature is activated (true) or not (false) */␊
bool platformCPUFeature(uint32_t feature)␊
getBoolForKey(kUseMemDetect, &useAutodetection, &bootInfo->bootConfig);␊
␊
if (useAutodetection) {␊
␉␉if (dram_controller_dev!=NULL) {␊
␉␉␉scan_dram_controller(dram_controller_dev); // Rek: pci dev ram controller direct and fully informative scan ...␊
␉␉}␊
scan_memory(&Platform); // unfortunately still necesary for some comp where spd cant read correct speed␊
scan_spd(&Platform);␊
␉␉//getc();␊
}␊
␉done = true;␊
}␊
␉memset(&Platform, 0, sizeof(Platform));␊
␉build_pci_dt();␊
␉scan_cpu(&Platform);␊
␉// It's working after some changes in strdup␊
␉scan_mem();␊
␉//scan_mem(); Rek: called after pci devs init in fake_efi now ...␊
}␊
branches/mozodojo/i386/libsaio/platform.h
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␉} CPU;␊
␊
␉struct RAM {␊
␉␉uint64_t␉␉Frequency;␉␉␉␉// Ram Frequency␊
␉␉uint32_t␉␉Divider;␉␉␉␉// Memory divider␊
␉␉uint8_t␉␉␉CAS;␉␉␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊
␉␉uint8_t␉␉␉TRC;␉␉␉␉␉␊
␉␉uint8_t␉␉␉TRP;␊
␉␉uint8_t␉␉␉RAS;␊
␉␉uint8_t␉␉␉Channels;␉␉␉␉// Channel Configuration Single,Dual or Triple␊
␉␉uint8_t␉␉␉NoSlots;␉␉␉␉// Maximum no of slots available␊
␉␉uint8_t␉␉␉Type;␉␉␉␉␉// Standard SMBIOS v2.5 Memory Type␊
␉␉RamSlotInfo_t␉␉DIMM[MAX_RAM_SLOTS];␉// Information about each slot␊
␉} RAM;␊
␊
branches/mozodojo/i386/libsaio/pci_setup.c
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extern void notify_usb_dev(pci_dt_t *pci_dev);␊
extern void force_enable_hpet(pci_dt_t *lpc_dev);␊
␊
extern pci_dt_t *dram_controller_dev;␊
␊
void setup_pci_devs(pci_dt_t *pci_dt)␊
{␊
␉char *devicepath;␊
␊
␉␉switch (current->class_id)␊
␉␉{␊
␉␉␉case PCI_CLASS_BRIDGE_HOST:␊
␉␉␉␉␉dram_controller_dev = current;␊
␉␉␉␉break;␊
␉␉␉␉␊
␉␉␉case PCI_CLASS_NETWORK_ETHERNET: ␊
␉␉␉␉if (do_eth_devprop)␊
␉␉␉␉␉set_eth_builtin(current);␊
branches/mozodojo/i386/libsaio/fake_efi.c
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fixupEfiSystemTableCRC32(gST);␊
}␊
␊
static void setupEfiDevices(setup)␊
{␊
␉setup_pci_devs(root_pci_dev);␊
}␊
␊
/* Entrypoint from boot.c */␊
void setupFakeEfi(void)␊
{␊
␉// Generate efi device strings ␊
␉setup_pci_devs(root_pci_dev);␊
␉␊
␉// load smbios.plist file if any␊
␉setupSmbiosConfigFile();␊
␉␊
␉// Generate efi device strings ␊
␉setupEfiDevices();␊
␉␊
␉// Initialize the base table␊
␉setupEfiTables();␊
␉␊
branches/mozodojo/GPL_V2_LICENSE
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GNU GENERAL PUBLIC LICENSE␊
Version 2, June 1991␊
␊
Copyright (C) 1989, 1991 Free Software Foundation, Inc.,␊
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA␊
Everyone is permitted to copy and distribute verbatim copies␊
of this license document, but changing it is not allowed.␊
␊
Preamble␊
␊
The licenses for most software are designed to take away your␊
freedom to share and change it. By contrast, the GNU General Public␊
License is intended to guarantee your freedom to share and change free␊
software--to make sure the software is free for all its users. This␊
General Public License applies to most of the Free Software␊
Foundation's software and to any other program whose authors commit to␊
using it. (Some other Free Software Foundation software is covered by␊
the GNU Lesser General Public License instead.) You can apply it to␊
your programs, too.␊
␊
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price. Our General Public Licenses are designed to make sure that you␊
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GNU GENERAL PUBLIC LICENSE␊
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION␊
␊
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a) Accompany it with the complete corresponding machine-readable␊
source code, which must be distributed under the terms of Sections␊
1 and 2 above on a medium customarily used for software interchange; or,␊
␊
b) Accompany it with a written offer, valid for at least three␊
years, to give any third party, for a charge no more than your␊
cost of physically performing source distribution, a complete␊
machine-readable copy of the corresponding source code, to be␊
distributed under the terms of Sections 1 and 2 above on a medium␊
customarily used for software interchange; or,␊
␊
c) Accompany it with the information you received as to the offer␊
to distribute corresponding source code. (This alternative is␊
allowed only for noncommercial distribution and only if you␊
received the program in object code or executable form with such␊
an offer, in accord with Subsection b above.)␊
␊
The source code for a work means the preferred form of the work for␊
making modifications to it. For an executable work, complete source␊
code means all the source code for all modules it contains, plus any␊
associated interface definition files, plus the scripts used to␊
control compilation and installation of the executable. However, as a␊
special exception, the source code distributed need not include␊
anything that is normally distributed (in either source or binary␊
form) with the major components (compiler, kernel, and so on) of the␊
operating system on which the executable runs, unless that component␊
itself accompanies the executable.␊
␊
If distribution of executable or object code is made by offering␊
access to copy from a designated place, then offering equivalent␊
access to copy the source code from the same place counts as␊
distribution of the source code, even though third parties are not␊
compelled to copy the source along with the object code.␊
␊
4. You may not copy, modify, sublicense, or distribute the Program␊
except as expressly provided under this License. Any attempt␊
otherwise to copy, modify, sublicense or distribute the Program is␊
void, and will automatically terminate your rights under this License.␊
However, parties who have received copies, or rights, from you under␊
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parties remain in full compliance.␊
␊
5. You are not required to accept this License, since you have not␊
signed it. However, nothing else grants you permission to modify or␊
distribute the Program or its derivative works. These actions are␊
prohibited by law if you do not accept this License. Therefore, by␊
modifying or distributing the Program (or any work based on the␊
Program), you indicate your acceptance of this License to do so, and␊
all its terms and conditions for copying, distributing or modifying␊
the Program or works based on it.␊
␊
6. Each time you redistribute the Program (or any work based on the␊
Program), the recipient automatically receives a license from the␊
original licensor to copy, distribute or modify the Program subject to␊
these terms and conditions. You may not impose any further␊
restrictions on the recipients' exercise of the rights granted herein.␊
You are not responsible for enforcing compliance by third parties to␊
this License.␊
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7. If, as a consequence of a court judgment or allegation of patent␊
infringement or for any other reason (not limited to patent issues),␊
conditions are imposed on you (whether by court order, agreement or␊
otherwise) that contradict the conditions of this License, they do not␊
excuse you from the conditions of this License. If you cannot␊
distribute so as to satisfy simultaneously your obligations under this␊
License and any other pertinent obligations, then as a consequence you␊
may not distribute the Program at all. For example, if a patent␊
license would not permit royalty-free redistribution of the Program by␊
all those who receive copies directly or indirectly through you, then␊
the only way you could satisfy both it and this License would be to␊
refrain entirely from distribution of the Program.␊
␊
If any portion of this section is held invalid or unenforceable under␊
any particular circumstance, the balance of the section is intended to␊
apply and the section as a whole is intended to apply in other␊
circumstances.␊
␊
It is not the purpose of this section to induce you to infringe any␊
patents or other property right claims or to contest validity of any␊
such claims; this section has the sole purpose of protecting the␊
integrity of the free software distribution system, which is␊
implemented by public license practices. Many people have made␊
generous contributions to the wide range of software distributed␊
through that system in reliance on consistent application of that␊
system; it is up to the author/donor to decide if he or she is willing␊
to distribute software through any other system and a licensee cannot␊
impose that choice.␊
␊
This section is intended to make thoroughly clear what is believed to␊
be a consequence of the rest of this License.␊
␊
8. If the distribution and/or use of the Program is restricted in␊
certain countries either by patents or by copyrighted interfaces, the␊
original copyright holder who places the Program under this License␊
may add an explicit geographical distribution limitation excluding␊
those countries, so that distribution is permitted only in or among␊
countries not thus excluded. In such case, this License incorporates␊
the limitation as if written in the body of this License.␊
␊
9. The Free Software Foundation may publish revised and/or new versions␊
of the General Public License from time to time. Such new versions will␊
be similar in spirit to the present version, but may differ in detail to␊
address new problems or concerns.␊
␊
Each version is given a distinguishing version number. If the Program␊
specifies a version number of this License which applies to it and "any␊
later version", you have the option of following the terms and conditions␊
either of that version or of any later version published by the Free␊
Software Foundation. If the Program does not specify a version number of␊
this License, you may choose any version ever published by the Free Software␊
Foundation.␊
␊
10. If you wish to incorporate parts of the Program into other free␊
programs whose distribution conditions are different, write to the author␊
to ask for permission. For software which is copyrighted by the Free␊
Software Foundation, write to the Free Software Foundation; we sometimes␊
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of preserving the free status of all derivatives of our free software and␊
of promoting the sharing and reuse of software generally.␊
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NO WARRANTY␊
␊
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY␊
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN␊
OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES␊
PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED␊
OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF␊
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS␊
TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE␊
PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,␊
REPAIR OR CORRECTION.␊
␊
12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING␊
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR␊
REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,␊
INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING␊
OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED␊
TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY␊
YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER␊
PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE␊
POSSIBILITY OF SUCH DAMAGES.␊
␊
END OF TERMS AND CONDITIONS␊
␊
How to Apply These Terms to Your New Programs␊
␊
If you develop a new program, and you want it to be of the greatest␊
possible use to the public, the best way to achieve this is to make it␊
free software which everyone can redistribute and change under these terms.␊
␊
To do so, attach the following notices to the program. It is safest␊
to attach them to the start of each source file to most effectively␊
convey the exclusion of warranty; and each file should have at least␊
the "copyright" line and a pointer to where the full notice is found.␊
␊
<one line to give the program's name and a brief idea of what it does.>␊
Copyright (C) <year> <name of author>␊
␊
This program is free software; you can redistribute it and/or modify␊
it under the terms of the GNU General Public License as published by␊
the Free Software Foundation; either version 2 of the License, or␊
(at your option) any later version.␊
␊
This program is distributed in the hope that it will be useful,␊
but WITHOUT ANY WARRANTY; without even the implied warranty of␊
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
GNU General Public License for more details.␊
␊
You should have received a copy of the GNU General Public License along␊
with this program; if not, write to the Free Software Foundation, Inc.,␊
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.␊
␊
Also add information on how to contact you by electronic and paper mail.␊
␊
If the program is interactive, make it output a short notice like this␊
when it starts in an interactive mode:␊
␊
Gnomovision version 69, Copyright (C) year name of author␊
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.␊
This is free software, and you are welcome to redistribute it␊
under certain conditions; type `show c' for details.␊
␊
The hypothetical commands `show w' and `show c' should show the appropriate␊
parts of the General Public License. Of course, the commands you use may␊
be called something other than `show w' and `show c'; they could even be␊
mouse-clicks or menu items--whatever suits your program.␊
␊
You should also get your employer (if you work as a programmer) or your␊
school, if any, to sign a "copyright disclaimer" for the program, if␊
necessary. Here is a sample; alter the names:␊
␊
Yoyodyne, Inc., hereby disclaims all copyright interest in the program␊
`Gnomovision' (which makes passes at compilers) written by James Hacker.␊
␊
<signature of Ty Coon>, 1 April 1989␊
Ty Coon, President of Vice␊
␊
This General Public License does not permit incorporating your program into␊
proprietary programs. If your program is a subroutine library, you may␊
consider it more useful to permit linking proprietary applications with the␊
library. If this is what you want to do, use the GNU Lesser General␊
Public License instead of this License.
branches/mozodojo/README
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Chameleon is a Darwin/XNU boot loader based on Apple's boot-132.␊
␊
Because Chameleon now uses part of GPL V2 licensed code in 2 files,␊
it *must* conform to the most restrictive license that it uses that is the:␊
GPL Version 2 LICENSE␊
␊
Chameleon can thus be (and has to be) freely distributed under the term of the GPL V2 license which prevails, as it is the most restrictive license.␊
branches/mozodojo/MEMTEST86_LICENSE
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dram_controllers.c/h that scans from the pci host controller USES␊
an adaptation for chameleon 2.0 RC5 from original :␊
␊
========================␊
memtest86 license notice␊
========================␊
␊
Released under version 2 of the Gnu Public License.␊
By Chris Brady, cbrady@sgi.com␊
----------------------------------------------------␊
MemTest86+ V4.00 Specific code (GPL V2.0)␊
By Samuel DEMEULEMEESTER, sdemeule@memtest.org␊
http://www.canardpc.com - http://www.memtest.org␊
␊
␊
============================␊
GPL version 2 license notice␊
============================␊
␊
This program is free software; you can redistribute it and/or␊
modify it under the terms of the GNU General Public License␊
as published by the Free Software Foundation; either version 2␊
of the License, or (at your option) any later version.␊
␊
This program is distributed in the hope that it will be useful,␊
but WITHOUT ANY WARRANTY; without even the implied warranty of␊
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
GNU General Public License for more details.␊
␊
You should have received a copy of the GNU General Public License␊
along with this program; if not, write to the Free Software␊
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.␊

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