| */␊ |
| void scan_cpu(PlatformInfo_t *p)␊ |
| {␊ |
| ␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊ |
| ␉uint64_t␉msr, flex_ratio;␊ |
| ␉uint8_t␉␉maxcoef, maxdiv, currcoef, bus_ratio_max, currdiv;␊ |
| ␉uint64_t␉tscFrequency = 0;␊ |
| ␉uint64_t␉fsbFrequency = 0;␊ |
| ␉uint64_t␉cpuFrequency = 0;␊ |
| ␉uint64_t␉msr = 0;␊ |
| ␉uint64_t␉flex_ratio = 0;␊ |
| ␉uint32_t␉max_ratio = 0;␊ |
| ␉uint32_t␉min_ratio = 0;␊ |
| ␉uint8_t␉␉bus_ratio_max = 0;␊ |
| ␉uint8_t␉␉currdiv = 0;␊ |
| ␉uint8_t␉␉currcoef = 0;␊ |
| ␉uint8_t␉␉maxdiv = 0;␊ |
| ␉uint8_t␉␉maxcoef = 0;␊ |
| ␉const char␉*newratio;␊ |
| ␉int␉␉␉len, myfsb;␊ |
| ␉uint8_t␉␉bus_ratio_min;␊ |
| ␉uint32_t␉max_ratio, min_ratio;␊ |
| ␉int␉␉len = 0;␊ |
| ␉int␉␉myfsb = 0;␊ |
| ␉uint8_t␉␉bus_ratio_min = 0;␊ |
| ␉uint32_t␉reg[4];␊ |
| ␉char␉␉str[128];␊ |
| ␊ |
| ␉max_ratio = min_ratio = myfsb = bus_ratio_min = 0;␊ |
| ␉maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;␊ |
| ␊ |
| ␉/* get cpuid values */␊ |
| ␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊ |
| ␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊ |
|
| ␊ |
| ␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊ |
| ␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊ |
| ␉// stepping = cpu_feat_eax & 0xF;␊ |
| ␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊ |
| ␉// model = (cpu_feat_eax >> 4) & 0xF;␊ |
| ␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊ |
| ␉// family = (cpu_feat_eax >> 8) & 0xF;␊ |
| ␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊ |
| ␉// type = (cpu_feat_eax >> 12) & 0x3;␊ |
| ␉//p->CPU.Type␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␊ |
| ␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊ |
| ␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊ |
| ␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊ |
| ␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊ |
| ␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0); // stepping = cpu_feat_eax & 0xF;␊ |
| ␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4); // model = (cpu_feat_eax >> 4) & 0xF;␊ |
| ␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8); // family = (cpu_feat_eax >> 8) & 0xF;␊ |
| ␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊ |
| ␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16); // ext_model = (cpu_feat_eax >> 16) & 0xF;␊ |
| ␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊ |
| ␊ |
| ␉p->CPU.Model += (p->CPU.ExtModel << 4);␊ |
| ␊ |
| ␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&␊ |
| ␉␉p->CPU.Family == 0x06 &&␊ |
| ␉␉p->CPU.Model >= CPU_MODEL_NEHALEM &&␊ |
| ␉␉p->CPU.Model != CPU_MODEL_ATOM␉␉// MSR is *NOT* available on the Intel Atom CPU␊ |
| ␉␉) {␊ |
| ␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊ |
| ␉␉p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉// Using undocumented MSR to get actual values␊ |
| ␉␉p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉// Using undocumented MSR to get actual values␊ |
| ␉} else if (p->CPU.Vendor == CPUID_VENDOR_AMD) {␊ |
| ␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
| ␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊ |
| ␉} else {␊ |
| ␉␉// Use previous method for Cores and Threads␊ |
| ␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
| ␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊ |
| ␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL)␊ |
| ␉{␊ |
| ␉␉/*␊ |
| ␉␉ * Find the number of enabled cores and threads␊ |
| ␉␉ * (which determines whether SMT/Hyperthreading is active).␊ |
| ␉␉ */␊ |
| ␉␉switch (p->CPU.Model)␊ |
| ␉␉{␊ |
| ␉␉␉case CPU_MODEL_NEHALEM:␊ |
| ␉␉␉case CPU_MODEL_FIELDS:␊ |
| ␉␉␉case CPU_MODEL_DALES:␊ |
| ␉␉␉case CPU_MODEL_NEHALEM_EX:␊ |
| ␉␉␉case CPU_MODEL_JAKETOWN:␊ |
| ␉␉␉case CPU_MODEL_SANDYBRIDGE:␊ |
| ␉␉␉case CPU_MODEL_IVYBRIDGE:␊ |
| ␉␉␉case CPU_MODEL_HASWELL:␊ |
| ␉␉␉case CPU_MODEL_HASWELL_SVR:␊ |
| ␉␉␉//case CPU_MODEL_HASWELL_H:␊ |
| ␉␉␉case CPU_MODEL_HASWELL_ULT:␊ |
| ␉␉␉case CPU_MODEL_CRYSTALWELL:␊ |
| ␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊ |
| ␉␉␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield((uint32_t)msr, 31, 16);␊ |
| ␉␉␉␉p->CPU.NoThreads␉= (uint8_t)bitfield((uint32_t)msr, 15, 0);␊ |
| ␉␉␉␉break;␊ |
| ␊ |
| ␉␉␉case CPU_MODEL_DALES_32NM:␊ |
| ␉␉␉case CPU_MODEL_WESTMERE:␊ |
| ␉␉␉case CPU_MODEL_WESTMERE_EX:␊ |
| ␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊ |
| ␉␉␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield((uint32_t)msr, 19, 16);␊ |
| ␉␉␉␉p->CPU.NoThreads␉= (uint8_t)bitfield((uint32_t)msr, 15, 0);␊ |
| ␉␉␉␉break;␊ |
| ␊ |
| ␉␉␉default:␊ |
| ␉␉␉␉p->CPU.NoCores = 0;␊ |
| ␉␉␉␉break;␊ |
| ␉␉} // end switch␊ |
| ␉}␊ |
| ␊ |
| ␉if (p->CPU.NoCores == 0) {␊ |
| ␉␉p->CPU.NoCores␉␉= (uint8_t)(p->CPU.CoresPerPackage & 0xff);␊ |
| ␉␉p->CPU.NoThreads␉= (uint8_t)(p->CPU.LogicalPerPackage & 0xff);␊ |
| ␉}␊ |
| ␊ |
| ␉/* get BrandString (if supported) */␊ |
| ␉/* Copyright: from Apple's XNU cpuid.c */␊ |
| ␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊ |
| ␉␉uint32_t␉reg[4];␊ |
| ␉␉char␉␉str[128], *s;␊ |
| ␉␉char␉ *s;␊ |
| ␉␉bzero(str, 128);␊ |
| ␉␉/*␊ |
| ␉␉ * The BrandString 48 bytes (max), guaranteed to␊ |
| ␉␉ * be NULL terminated.␊ |
| ␉␉ */␊ |
| ␉␉do_cpuid(0x80000002, reg);␊ |
| ␉␉bcopy((char *)reg, &str[0], 16);␊ |
| ␉␉memcpy(&str[0], (char *)reg, 16);␊ |
| ␉␉do_cpuid(0x80000003, reg);␊ |
| ␉␉bcopy((char *)reg, &str[16], 16);␊ |
| ␉␉memcpy(&str[16], (char *)reg, 16);␊ |
| ␉␉do_cpuid(0x80000004, reg);␊ |
| ␉␉bcopy((char *)reg, &str[32], 16);␊ |
| ␉␉memcpy(&str[32], (char *)reg, 16);␊ |
| ␉␉for (s = str; *s != '\0'; s++) {␊ |
| ␉␉␉if (*s != ' ') {␊ |
| ␉␉␉␉break;␊ |
| ␉␉␉}␊ |
| ␉␉␉if (*s != ' ') { break; }␊ |
| ␉␉}␊ |
| ␉␉␊ |
| ␉␉strlcpy(p->CPU.BrandString, s, sizeof(p->CPU.BrandString));␊ |
| ␉␉␊ |
| ␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊ |
| ␉␉strlcpy(p->CPU.BrandString, s, 48);␊ |
| ␊ |
| ␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN,␊ |
| MIN(sizeof(p->CPU.BrandString),␊ |
| strlen(CPU_STRING_UNKNOWN) + 1))) {␊ |
| ␉␉␉/*␊ |
| ␉␉␉ * This string means we have a firmware-programmable brand string,␊ |
| ␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊ |
| ␉␉␉ */␊ |
| ␉␉␉p->CPU.BrandString[0] = '\0';␊ |
| ␉␉}␊ |
| ␉␉p->CPU.BrandString[47] = '\0';␊ |
| //␉␉DBG("Brandstring = %s\n", p->CPU.BrandString);␊ |
| ␉}␊ |
| ␊ |
| ␉//workaround for N270. I don't know why it detected wrong␊ |
| ␉// MSR is *NOT* available on the Intel Atom CPU␊ |
| ␉if ((p->CPU.Model == CPU_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270"))) {␊ |
| ␉␉p->CPU.NoCores␉␉= 1;␊ |
| ␉␉p->CPU.NoThreads␉= 2;␊ |
| ␉}␊ |
| ␊ |
| ␉if (p->CPU.Vendor == CPUID_VENDOR_AMD) {␊ |
| ␉␉p->CPU.NoThreads␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
| ␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊ |
| ␉}␊ |
| ␊ |
| ␉/* setup features */␊ |
| ␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
| ␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊ |
|
| ␉}␊ |
| ␊ |
| ␉tscFrequency = measure_tsc_frequency();␊ |
| ␉DBG("cpu freq classic = 0x%016llx\n", tscFrequency);␊ |
| ␉/* if usual method failed */␊ |
| ␉if ( tscFrequency < 1000 ) { //TEST␊ |
| ␉␉tscFrequency = timeRDTSC() * 20;␊ |
| ␉␉tscFrequency = timeRDTSC() * 20;//measure_tsc_frequency();␊ |
| ␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊ |
| ␉} else {␊ |
| ␉␉// DBG("cpu freq timeRDTSC = 0x%016llxn", timeRDTSC() * 20);␊ |
| ␉}␊ |
| ␉fsbFrequency = 0;␊ |
| ␉cpuFrequency = 0;␊ |
| ␊ |
| ␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊ |
| ␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))) {␊ |
| ␉␉int intelCPU = p->CPU.Model;␊ |
| ␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␉{␊ |
| ␉␉if (p->CPU.Family == 0x06) {␊ |
| ␉␉␉/* Nehalem CPU model */␊ |
| ␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM␉␉||␊ |
| ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_FIELDS␉||␊ |
| ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES␉||␊ |
| ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES_32NM␉||␊ |
| ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE␉||␊ |
| ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_NEHALEM_EX␉||␊ |
| ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊ |
| ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDYBRIDGE ||␊ |
| ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_JAKETOWN ||␊ |
| ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE_XEON␉||␊ |
| ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE ||␊ |
| ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL ||␊ |
| ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_SVR ||␊ |
| ␉␉␉␉␉␉␉␉␉␉ //p->CPU.Model == CPU_MODEL_HASWELL_H ||␊ |
| ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_ULT ||␊ |
| ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_CRYSTALWELL ))␊ |
| ␉␉␉{␊ |
| ␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊ |
| ␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
| ␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊ |
| ␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊ |
| ␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
| ␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
| ␉␉␉␉if (bitfield(msr, 16, 16)) {␊ |
| ␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊ |
| ␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊ |
| ␉␉␉␉␉ where the cpu multipler can't be changed to␊ |
| ␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊ |
| ␉␉␉␉␉ contents.␉These contents cause mach_kernel to␊ |
| ␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊ |
| ␉␉␉␉␉ causing the system to crash since tscGranularity␊ |
| ␉␉␉␉␉ is inadvertently set to 0.␊ |
| ␉␉␉␉␉ */␊ |
| ␉␉␉␉␉if (flex_ratio == 0) {␊ |
| ␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊ |
| ␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊ |
| ␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
| ␉␉␉␉␉␉verbose("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊ |
| ␉␉␉␉␉} else {␊ |
| ␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊ |
| ␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊ |
| ␉␉␉switch (p->CPU.Model) {␊ |
| ␉␉␉␉case CPU_MODEL_NEHALEM:␊ |
| ␉␉␉␉case CPU_MODEL_FIELDS:␊ |
| ␉␉␉␉case CPU_MODEL_DALES:␊ |
| ␉␉␉␉case CPU_MODEL_DALES_32NM:␊ |
| ␉␉␉␉case CPU_MODEL_WESTMERE:␊ |
| ␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊ |
| ␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊ |
| /* --------------------------------------------------------- */␊ |
| ␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊ |
| ␉␉␉␉case CPU_MODEL_JAKETOWN:␊ |
| ␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊ |
| ␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊ |
| ␉␉␉␉case CPU_MODEL_HASWELL:␊ |
| ␉␉␉␉case CPU_MODEL_HASWELL_SVR:␊ |
| ␊ |
| ␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊ |
| ␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊ |
| /* --------------------------------------------------------- */␊ |
| ␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊ |
| ␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
| ␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊ |
| ␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊ |
| ␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
| ␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
| ␉␉␉␉␉if (bitfield(msr, 16, 16)) {␊ |
| ␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊ |
| ␉␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊ |
| ␉␉␉␉␉␉ where the cpu multipler can't be changed to␊ |
| ␉␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊ |
| ␉␉␉␉␉␉ contents.␉These contents cause mach_kernel to␊ |
| ␉␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊ |
| ␉␉␉␉␉␉ causing the system to crash since tscGranularity␊ |
| ␉␉␉␉␉␉ is inadvertently set to 0.␊ |
| ␉␉␉␉␉␉ */␊ |
| ␉␉␉␉␉␉if (flex_ratio == 0) {␊ |
| ␉␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊ |
| ␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊ |
| ␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
| ␉␉␉␉␉␉␉DBG("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊ |
| ␉␉␉␉␉␉} else {␊ |
| ␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊ |
| ␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊ |
| ␉␉␉␉␉␉␉}␊ |
| ␉␉␉␉␉␉}␊ |
| ␉␉␉␉␉}␊ |
| ␉␉␉␉}␊ |
| ␊ |
| ␉␉␉␉if (bus_ratio_max) {␊ |
| ␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
| ␉␉␉␉}␊ |
| ␉␉␉␉//valv: Turbo Ratio Limit␊ |
| ␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f)) {␊ |
| ␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊ |
| ␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊ |
| ␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
| ␉␉␉␉} else {␊ |
| ␉␉␉␉␉cpuFrequency = tscFrequency;␊ |
| ␉␉␉␉}␊ |
| ␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4)) {␊ |
| ␉␉␉␉␉max_ratio = atoi(newratio);␊ |
| ␉␉␉␉␉max_ratio = (max_ratio * 10);␊ |
| ␉␉␉␉␉if (len >= 3) {␊ |
| ␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊ |
| ␉␉␉␉␉if (bus_ratio_max) {␊ |
| ␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
| ␉␉␉␉␉}␊ |
| ␉␉␉␉␉//valv: Turbo Ratio Limit␊ |
| ␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f)) {␊ |
| ␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊ |
| ␊ |
| ␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊ |
| ␉␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊ |
| ␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
| ␉␉␉␉␉} else {␊ |
| ␉␉␉␉␉␉cpuFrequency = tscFrequency;␊ |
| ␉␉␉␉␉}␊ |
| ␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4)) {␊ |
| ␉␉␉␉␉␉max_ratio = atoi(newratio);␊ |
| ␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊ |
| ␉␉␉␉␉␉if (len >= 3) {␊ |
| ␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊ |
| ␉␉␉␉␉␉}␊ |
| ␊ |
| ␉␉␉␉␉// extreme overclockers may love 320 ;)␊ |
| ␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320)) {␊ |
| ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊ |
| ␉␉␉␉␉␉if (len >= 3) {␊ |
| ␉␉␉␉␉␉␉maxdiv = 1;␊ |
| ␉␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊ |
| ␊ |
| ␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊ |
| ␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320)) {␊ |
| ␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊ |
| ␉␉␉␉␉␉␉if (len >= 3) {␊ |
| ␉␉␉␉␉␉␉␉maxdiv = 1;␊ |
| ␉␉␉␉␉␉␉} else {␊ |
| ␉␉␉␉␉␉␉␉maxdiv = 0;␊ |
| ␉␉␉␉␉␉␉}␊ |
| ␉␉␉␉␉␉} else {␊ |
| ␉␉␉␉␉␉␉maxdiv = 0;␊ |
| ␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊ |
| ␉␉␉␉␉␉}␊ |
| ␉␉␉␉␉} else {␊ |
| ␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊ |
| ␉␉␉␉␉}␊ |
| ␉␉␉␉}␊ |
| ␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊ |
| ␉␉␉␉/*if (bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊ |
| ␉␉␉␉p->CPU.MaxRatio = max_ratio;␊ |
| ␉␉␉␉p->CPU.MinRatio = min_ratio;␊ |
| ␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊ |
| ␉␉␉␉␉/*if (bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊ |
| ␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊ |
| ␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊ |
| ␊ |
| ␉␉␉␉myfsb = fsbFrequency / 1000000;␊ |
| ␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊ |
| ␉␉␉␉currcoef = bus_ratio_max;␊ |
| ␉␉␉} else {␊ |
| ␊ |
| ␉␉␉␉break;␊ |
| ␊ |
| ␉␉␉default:␊ |
| ␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
| ␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
| ␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊ |
|
| ␉␉␉␉␉}␊ |
| ␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊ |
| ␉␉␉␉}␊ |
| ␉␉␉␉break;␊ |
| ␉␉␉}␊ |
| ␉␉}␊ |
| ␉␉/* Mobile CPU */␊ |
|
| ␉␉cpuFrequency = tscFrequency;␊ |
| ␉␉DBG("0 ! using the default value for FSB !\n");␊ |
| ␉}␊ |
| ␊ |
| ␉DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊ |
| ␊ |
| #endif␊ |
| ␊ |
| ␉p->CPU.MaxCoef = maxcoef;␊ |
|
| ␉p->CPU.CPUFrequency = cpuFrequency;␊ |
| ␊ |
| ␉// keep formatted with spaces instead of tabs␊ |
| ␉DBG("CPU: Brand String: %s\n", p->CPU.BrandString);␊ |
| ␉DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊ |
| ␉DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊ |
| ␉DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);␊ |
| ␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);␊ |
| ␉DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊ |
| ␉DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊ |
| ␉DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊ |
| ␉DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊ |
| ␉DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊ |
| ␉DBG("\n---------------------------------------------\n");␊ |
| ␉DBG("--------------- CPU INFO ---------------\n");␊ |
| ␉DBG("---------------------------------------------\n");␊ |
| ␉DBG("Brand String: %s\n", p->CPU.BrandString); // Processor name (BIOS)␊ |
| ␉DBG("Vendor: 0x%x\n", p->CPU.Vendor); // Vendor ex: GenuineIntel␊ |
| ␉DBG("Family: 0x%x\n", p->CPU.Family); // Family ex: 6 (06h)␊ |
| ␉DBG("ExtFamily: 0x%x\n", p->CPU.ExtFamily);␊ |
| ␉DBG("Signature: %x\n", p->CPU.Signature); // CPUID signature␊ |
| ␉DBG("Model: 0x%x\n", p->CPU.Model); // Model ex: 37 (025h)␊ |
| ␉DBG("ExtModel: 0x%x\n", p->CPU.ExtModel);␊ |
| ␉DBG("Stepping: 0x%x\n", p->CPU.Stepping); // Stepping ex: 5 (05h)␊ |
| ␉DBG("MaxCoef: 0x%x\n", p->CPU.MaxCoef);␊ |
| ␉DBG("CurrCoef: 0x%x\n", p->CPU.CurrCoef);␊ |
| ␉DBG("MaxDiv: 0x%x\n", p->CPU.MaxDiv);␊ |
| ␉DBG("CurrDiv: 0x%x\n", p->CPU.CurrDiv);␊ |
| ␉DBG("TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊ |
| ␉DBG("FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊ |
| ␉DBG("CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊ |
| ␉DBG("Cores: %d\n", p->CPU.NoCores); // Cores␊ |
| ␉DBG("Logical processor: %d\n", p->CPU.NoThreads); // Logical procesor␊ |
| ␉DBG("Features: 0x%08x\n", p->CPU.Features);␊ |
| ␊ |
| ␉DBG("\n---------------------------------------------\n");␊ |
| #if DEBUG_CPU␊ |
| ␉pause();␊ |
| #endif␊ |
