Chameleon

Chameleon Commit Details

Date:2014-11-15 04:11:44 (9 years 5 months ago)
Author:ErmaC
Commit:2483
Parents: 2482
Message:Rename CPU_MODEL_xxx into CPUID_MODEL_xxx follow Apple source name
Changes:
M/trunk/i386/libsaio/acpi_patcher.c
M/trunk/i386/libsaio/cpu.c
M/trunk/i386/libsaio/platform.h
M/trunk/i386/libsaio/smbios_getters.c
M/trunk/i386/modules/AcpiCodec/acpi_codec.c
M/trunk/CHANGES
M/trunk/i386/libsaio/smbios.c
M/trunk/i386/boot2/options.c

File differences

trunk/i386/libsaio/acpi_patcher.c
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␉␉␉{␊
␉␉␉␉switch (Platform.CPU.Model) ␊
␉␉␉␉{␊
␉␉␉␉␉case CPU_MODEL_DOTHAN:␉// Intel Pentium M␊
␉␉␉␉␉case CPU_MODEL_YONAH:␉// Intel Mobile Core Solo, Duo␊
␉␉␉␉␉case CPU_MODEL_MEROM:␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
␉␉␉␉␉case CPU_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
␉␉␉␉␉case CPU_MODEL_ATOM:␉// Intel Atom (45nm)␊
␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉// Intel Pentium M␊
␉␉␉␉␉case CPUID_MODEL_YONAH:␉// Intel Mobile Core Solo, Duo␊
␉␉␉␉␉case CPUID_MODEL_MEROM:␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
␉␉␉␉␉case CPUID_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
␉␉␉␉␉case CPUID_MODEL_ATOM:␉// Intel Atom (45nm)␊
␉␉␉␉␉{␊
␉␉␉␉␉␉bool cpu_dynamic_fsb = false;␊
␊
␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉}␊
␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
␉␉␉␉␉case CPU_MODEL_DALES:␉␉␊
␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx␊
␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉␉case CPU_MODEL_HASWELL:␉␉//␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON: //␊
␉␉␉␉␉//case CPU_MODEL_HASWELL_H:␉//␊
␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␉//␊
␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉//␊
␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␉//␊
␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␊
␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx␊
␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉␉case CPUID_MODEL_HASWELL:␉␉//␊
␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON: //␊
␉␉␉␉␉//case CPUID_MODEL_HASWELL_H:␉//␊
␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␉//␊
␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉//␊
␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␉//␊
␊
␉␉␉␉␉{␊
␉␉␉␉␉if ((Platform.CPU.Model == CPU_MODEL_SANDYBRIDGE) || (Platform.CPU.Model == CPU_MODEL_JAKETOWN) ||␊
␉␉␉␉␉␉(Platform.CPU.Model == CPU_MODEL_IVYBRIDGE) || (Platform.CPU.Model == CPU_MODEL_HASWELL) ||␊
␉␉␉␉␉␉(Platform.CPU.Model == CPU_MODEL_IVYBRIDGE_XEON) || (Platform.CPU.Model == CPU_MODEL_HASWELL_SVR) ||␊
␉␉␉␉␉␉(Platform.CPU.Model == CPU_MODEL_HASWELL_ULT) || (Platform.CPU.Model == CPU_MODEL_CRYSTALWELL))␊
␉␉␉␉␉if ((Platform.CPU.Model == CPUID_MODEL_SANDYBRIDGE) || (Platform.CPU.Model == CPUID_MODEL_JAKETOWN) ||␊
␉␉␉␉␉␉(Platform.CPU.Model == CPUID_MODEL_IVYBRIDGE) || (Platform.CPU.Model == CPUID_MODEL_HASWELL) ||␊
␉␉␉␉␉␉(Platform.CPU.Model == CPUID_MODEL_IVYBRIDGE_XEON) || (Platform.CPU.Model == CPUID_MODEL_HASWELL_SVR) ||␊
␉␉␉␉␉␉(Platform.CPU.Model == CPUID_MODEL_HASWELL_ULT) || (Platform.CPU.Model == CPUID_MODEL_CRYSTALWELL))␊
␉␉␉␉␉{␊
␉␉␉␉␉␉maximum.Control = (rdmsr64(MSR_IA32_PERF_STATUS) >> 8) & 0xff;␊
␉␉␉␉␉}␊
trunk/i386/libsaio/cpu.c
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␉␉ */␊
␉␉switch (p->CPU.Model)␊
␉␉{␊
␉␉␉case CPU_MODEL_NEHALEM:␊
␉␉␉case CPU_MODEL_FIELDS:␊
␉␉␉case CPU_MODEL_DALES:␊
␉␉␉case CPU_MODEL_NEHALEM_EX:␊
␉␉␉case CPU_MODEL_JAKETOWN:␊
␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
␉␉␉case CPU_MODEL_IVYBRIDGE:␊
␉␉␉case CPU_MODEL_HASWELL:␊
␉␉␉case CPU_MODEL_HASWELL_SVR:␊
␉␉␉//case CPU_MODEL_HASWELL_H:␊
␉␉␉case CPU_MODEL_HASWELL_ULT:␊
␉␉␉case CPU_MODEL_CRYSTALWELL:␊
␉␉␉case CPUID_MODEL_NEHALEM:␊
␉␉␉case CPUID_MODEL_FIELDS:␊
␉␉␉case CPUID_MODEL_DALES:␊
␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
␉␉␉case CPUID_MODEL_JAKETOWN:␊
␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
␉␉␉case CPUID_MODEL_HASWELL:␊
␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
␉␉␉//case CPUID_MODEL_HASWELL_H:␊
␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
␉␉␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield((uint32_t)msr, 31, 16);␊
␉␉␉␉p->CPU.NoThreads␉= (uint8_t)bitfield((uint32_t)msr, 15, 0);␊
␉␉␉␉break;␊
␊
␉␉␉case CPU_MODEL_DALES_32NM:␊
␉␉␉case CPU_MODEL_WESTMERE:␊
␉␉␉case CPU_MODEL_WESTMERE_EX:␊
␉␉␉case CPUID_MODEL_DALES_32NM:␊
␉␉␉case CPUID_MODEL_WESTMERE:␊
␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
␉␉␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield((uint32_t)msr, 19, 16);␊
␉␉␉␉p->CPU.NoThreads␉= (uint8_t)bitfield((uint32_t)msr, 15, 0);␊
␊
␉//workaround for N270. I don't know why it detected wrong␊
␉// MSR is *NOT* available on the Intel Atom CPU␊
␉if ((p->CPU.Model == CPU_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊
␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊
␉{␊
␉␉p->CPU.NoCores␉␉= 1;␊
␉␉p->CPU.NoThreads␉= 2;␊
␉␉if (p->CPU.Family == 0x06) {␊
␉␉␉/* Nehalem CPU model */␊
␉␉␉switch (p->CPU.Model) {␊
␉␉␉␉case CPU_MODEL_NEHALEM:␊
␉␉␉␉case CPU_MODEL_FIELDS:␊
␉␉␉␉case CPU_MODEL_DALES:␊
␉␉␉␉case CPU_MODEL_DALES_32NM:␊
␉␉␉␉case CPU_MODEL_WESTMERE:␊
␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊
␉␉␉␉case CPUID_MODEL_NEHALEM:␊
␉␉␉␉case CPUID_MODEL_FIELDS:␊
␉␉␉␉case CPUID_MODEL_DALES:␊
␉␉␉␉case CPUID_MODEL_DALES_32NM:␊
␉␉␉␉case CPUID_MODEL_WESTMERE:␊
␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
/* --------------------------------------------------------- */␊
␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
␉␉␉␉case CPU_MODEL_JAKETOWN:␊
␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
␉␉␉␉case CPU_MODEL_HASWELL:␊
␉␉␉␉case CPU_MODEL_HASWELL_SVR:␊
␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
␉␉␉␉case CPUID_MODEL_HASWELL:␊
␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
␊
␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊
␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
/* --------------------------------------------------------- */␊
␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
trunk/i386/libsaio/platform.h
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#define CPUID_88␉␉␉9␊
#define CPUID_MAX␉␉␉10␊
␊
#define CPU_MODEL_ANY␉␉␉0x00␊
#define CPU_MODEL_UNKNOWN␉␉0x01␊
#define CPU_MODEL_PRESCOTT␉␉0x03␉␉␉// Celeron D, Pentium 4 (90nm)␊
#define CPU_MODEL_NOCONA␉␉0x04␉␉␉// Xeon Nocona/Paxville, Irwindale (90nm)␊
#define CPU_MODEL_PRESLER␉␉0x06␉␉␉// Pentium 4, Pentium D (65nm)␊
#define CPU_MODEL_PENTIUM_M␉␉0x09␉␉␉// Banias Pentium M (130nm)␊
#define CPU_MODEL_DOTHAN␉␉0x0D␉␉␉// Dothan Pentium M, Celeron M (90nm)␊
#define CPU_MODEL_YONAH␉␉␉0x0E␉␉␉// Sossaman, Yonah␊
#define CPU_MODEL_MEROM␉␉␉0x0F␉␉␉// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom␊
#define CPU_MODEL_CONROE␉␉0x0F␉␉␉// ␊
#define CPU_MODEL_CELERON␉␉0x16␉␉␉// Merom, Conroe (65nm)␊
#define CPU_MODEL_PENRYN␉␉0x17␉␉␉// Wolfdale, Yorkfield, Harpertown, Penryn␊
#define CPU_MODEL_WOLFDALE␉␉0x17␉␉␉// ␊
#define CPU_MODEL_NEHALEM␉␉0x1A␉␉␉// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown␊
#define CPU_MODEL_ATOM␉␉␉0x1C␉␉␉// Pineview, Bonnell␊
#define CPU_MODEL_XEON_MP␉␉0x1D␉␉␉// MP 7400␊
#define CPU_MODEL_FIELDS␉␉0x1E␉␉␉// Lynnfield, Clarksfield, Jasper Forest␊
#define CPU_MODEL_DALES␉␉␉0x1F␉␉␉// Havendale, Auburndale␊
#define CPU_MODEL_DALES_32NM␉␉0x25␉␉␉// Clarkdale, Arrandale␊
#define CPU_MODEL_ATOM_SAN␉␉0x26␉␉␉// Lincroft␊
#define CPU_MODEL_LINCROFT␉␉0x27␉␉␉// Bonnell␊
#define CPU_MODEL_SANDYBRIDGE␉␉0x2A␉␉␉// Sandy Bridge␊
#define CPU_MODEL_WESTMERE␉␉0x2C␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊
#define CPU_MODEL_JAKETOWN␉␉0x2D␉␉␉// Sandy Bridge-E, Sandy Bridge-EP␊
#define CPU_MODEL_NEHALEM_EX␉␉0x2E␉␉␉// Beckton␊
#define CPU_MODEL_WESTMERE_EX␉␉0x2F␉␉␉// Westmere-EX␊
//#define CPU_MODEL_BONNELL_ATOM␉0x35␉␉␉// Bonnell␊
#define CPU_MODEL_ATOM_2000␉␉0x36␉␉␉// Cedarview / Saltwell␊
#define CPU_MODEL_SILVERMONT␉␉0x37␉␉␉// Atom Silvermont␊
#define CPU_MODEL_IVYBRIDGE␉␉0x3A␉␉␉// Ivy Bridge␊
#define CPU_MODEL_HASWELL␉␉0x3C␉␉␉// Haswell DT␊
#define CPU_MODEL_BROADWELL␉␉0x3D␉␉␉// Core M, Broadwell / Core-AVX2␊
#define CPU_MODEL_IVYBRIDGE_XEON␉0x3E␉␉␉// Ivy Bridge Xeon␊
#define CPU_MODEL_HASWELL_SVR␉␉0x3F␉␉␉// Haswell Server␊
//#define CPU_MODEL_HASWELL_H␉␉0x??␉␉␉// Haswell H␊
#define CPU_MODEL_HASWELL_ULT␉␉0x45␉␉␉// Haswell ULT␊
#define CPU_MODEL_CRYSTALWELL␉␉0x46␉␉␉// Crystal Well␊
// 4A silvermont / atom␊
#define CPU_MODEL_AVOTON␉␉0x4D␉␉␉// Silvermont/Avoton Atom C2000␊
// 4E Core???␊
#define CPU_MODEL_BRODWELL_SVR␉␉0x4F␉␉␉// Broadwell Server␊
#define CPU_MODEL_BRODWELL_MSVR␉␉0x56␉␉␉// Broadwell Micro Server␊
// 5A silvermont / atom␊
// 5D silvermont / atom␊
#define CPUID_MODEL_ANY␉␉␉0x00␊
#define CPUID_MODEL_UNKNOWN␉␉0x01␊
#define CPUID_MODEL_PRESCOTT␉␉0x03␉␉␉// Celeron D, Pentium 4 (90nm)␊
#define CPUID_MODEL_NOCONA␉␉0x04␉␉␉// Xeon Nocona/Paxville, Irwindale (90nm)␊
#define CPUID_MODEL_PRESLER␉␉0x06␉␉␉// Pentium 4, Pentium D (65nm)␊
#define CPUID_MODEL_PENTIUM_M␉␉0x09␉␉␉// Banias Pentium M (130nm)␊
#define CPUID_MODEL_DOTHAN␉␉0x0D␉␉␉// Dothan Pentium M, Celeron M (90nm)␊
#define CPUID_MODEL_YONAH␉␉0x0E␉␉␉// Sossaman, Yonah␊
#define CPUID_MODEL_MEROM␉␉0x0F␉␉␉// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom␊
#define CPUID_MODEL_CONROE␉␉0x0F␉␉␉// ␊
#define CPUID_MODEL_CELERON␉␉0x16␉␉␉// Merom, Conroe (65nm), Celeron (45nm)␊
#define CPUID_MODEL_PENRYN␉␉0x17␉␉␉// Wolfdale, Yorkfield, Harpertown, Penryn␊
#define CPUID_MODEL_WOLFDALE␉␉0x17␉␉␉// Xeon 31xx, 33xx, 52xx, 54xx, Core 2 Quad 8xxx and 9xxx␊
#define CPUID_MODEL_NEHALEM␉␉0x1A␉␉␉// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown␊
#define CPUID_MODEL_ATOM␉␉0x1C␉␉␉// Pineview, Bonnell␊
#define CPUID_MODEL_XEON_MP␉␉0x1D␉␉␉// MP 7400␊
#define CPUID_MODEL_FIELDS␉␉0x1E␉␉␉// Lynnfield, Clarksfield, Jasper Forest␊
#define CPUID_MODEL_DALES␉␉0x1F␉␉␉// Havendale, Auburndale␊
#define CPUID_MODEL_DALES_32NM␉␉0x25␉␉␉// Clarkdale, Arrandale␊
#define CPUID_MODEL_ATOM_SAN␉␉0x26␉␉␉// Lincroft␊
#define CPUID_MODEL_LINCROFT␉␉0x27␉␉␉// Bonnell␊
#define CPUID_MODEL_SANDYBRIDGE␉␉0x2A␉␉␉// Sandy Bridge␊
#define CPUID_MODEL_WESTMERE␉␉0x2C␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊
#define CPUID_MODEL_JAKETOWN␉␉0x2D␉␉␉// Sandy Bridge-E, Sandy Bridge-EP␊
#define CPUID_MODEL_NEHALEM_EX␉␉0x2E␉␉␉// Beckton␊
#define CPUID_MODEL_WESTMERE_EX␉␉0x2F␉␉␉// Westmere-EX␊
//#define CPUID_MODEL_BONNELL_ATOM␉0x35␉␉␉// Atom Family Bonnell␊
#define CPUID_MODEL_ATOM_2000␉␉0x36␉␉␉// Cedarview / Saltwell␊
#define CPUID_MODEL_SILVERMONT␉␉0x37␉␉␉// Atom E3000, Z3000 Atom Silvermont␊
#define CPUID_MODEL_IVYBRIDGE␉␉0x3A␉␉␉// Ivy Bridge␊
#define CPUID_MODEL_HASWELL␉␉0x3C␉␉␉// Haswell DT␊
#define CPUID_MODEL_BROADWELL␉␉0x3D␉␉␉// Core M, Broadwell / Core-AVX2␊
#define CPUID_MODEL_IVYBRIDGE_XEON␉0x3E␉␉␉// Ivy Bridge Xeon␊
#define CPUID_MODEL_HASWELL_SVR␉␉0x3F␉␉␉// Haswell Server, Xeon E5-2600/1600 v3 (Haswell-E)␊
//#define CPUID_MODEL_HASWELL_H␉␉0x??␉␉␉// Haswell H␊
#define CPUID_MODEL_HASWELL_ULT␉␉0x45␉␉␉// Haswell ULT, 4th gen Core, Xeon E3-12xx v3␊
#define CPUID_MODEL_CRYSTALWELL␉␉0x46␉␉␉// Crystal Well, 4th gen Core, Xeon E3-12xx v3␊
//#define CPUID_MODEL_␉␉␉0x4A␉␉␉// Future Atom E3000, Z3000 silvermont / atom␊
#define CPUID_MODEL_AVOTON␉␉0x4D␉␉␉// Silvermont/Avoton Atom C2000␊
//#define CPUID_MODEL_␉␉␉0x4E␉␉␉// Future Core␊
#define CPUID_MODEL_BRODWELL_SVR␉0x4F␉␉␉// Broadwell Server␊
#define CPUID_MODEL_BRODWELL_MSVR␉0x56␉␉␉// Broadwell Micro Server, Future Xeon␊
//#define CPUID_MODEL_␉␉␉0x5A␉␉␉// Silvermont, Future Atom E3000, Z3000␊
//#define CPUID_MODEL_␉␉␉0x5D␉␉␉// Silvermont, Future Atom E3000, Z3000␊
␊
/* CPU Features */␊
#define CPU_FEATURE_MMX␉␉␉0x00000001␉␉// MMX Instruction Set␊
␉␉uint32_t␉␉MinRatio;␉␉␉␉// Min Bus Ratio␊
␉␉char␉␉␉BrandString[48];␉␉␉// 48 Byte Branding String␊
␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉␉␉// CPUID 0..4, 80..81 Raw Values␊
␊
␉} CPU;␊
␊
␉struct RAM {␊
trunk/i386/libsaio/smbios.c
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␉␉␉␉␉{␊
␉␉␉␉␉␉switch (Platform.CPU.Model)␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
␉␉␉␉␉␉␉case CPU_MODEL_DALES:␊
␉␉␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
␉␉␉␉␉␉␉case CPUID_MODEL_DALES:␊
␉␉␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉␉␉␉␉defaultBIOSInfo.version␉␉␉= kDefaultiMacNehalemBIOSVersion;␊
␉␉␉␉␉␉␉␉defaultBIOSInfo.releaseDate␉␉= kDefaultiMacNehalemBIOSReleaseDate;␊
␉␉␉␉␉␉␉␉defaultSystemInfo.productName␉= kDefaultiMacNehalem;␊
␉␉␉␉␉␉␉␉defaultChassis.chassisType = kSMBchassisAllInOne;␊
␉␉␉␉␉␉␉␉break;␊
␊
␉␉␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉␉␉␉␉defaultBIOSInfo.version = kDefaultiMacSandyBIOSVersion;␊
␉␉␉␉␉␉␉␉defaultBIOSInfo.releaseDate = kDefaultiMacSandyBIOSReleaseDate;␊
␉␉␉␉␉␉␉␉defaultSystemInfo.productName␉= kDefaultiMacSandy;␊
␉␉␉␉␉␉␉␉defaultChassis.chassisType = kSMBchassisAllInOne;␊
␉␉␉␉␉␉␉␉break;␊
␊
␉␉␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
␉␉␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
␉␉␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
␉␉␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
␉␉␉␉␉␉␉␉defaultBIOSInfo.version␉␉= kDefaultMacProNehalemBIOSVersion;␊
␉␉␉␉␉␉␉␉defaultBIOSInfo.releaseDate␉= kDefaultMacProNehalemBIOSReleaseDate;␊
␉␉␉␉␉␉␉␉defaultSystemInfo.productName␉= kDefaultMacProNehalem;␊
␉␉␉␉␉␉␉␉defaultChassis.chassisType = kSMBchassisTower;␊
␉␉␉␉␉␉␉␉break;␊
␊
␉␉␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉// Intel Xeon E7␊
␉␉␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␉␉// Intel Core i7, Xeon E5 v2 LGA2011 (22nm)␊
␉␉␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉// Intel Xeon E7␊
␉␉␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␉// Intel Core i7, Xeon E5 v2 LGA2011 (22nm)␊
␉␉␉␉␉␉␉␉defaultBIOSInfo.version␉␉= kDefaultMacProWestmereBIOSVersion;␊
␉␉␉␉␉␉␉␉defaultBIOSInfo.releaseDate␉= kDefaultMacProWestmereBIOSReleaseDate;␊
␉␉␉␉␉␉␉␉defaultSystemInfo.productName␉= kDefaultMacProWestmere;␊
␉␉␉switch (Platform.CPU.Model)␊
␉␉␉{␊
␉␉␉␉case 0x19:␉␉␉// Intel Core i5 650 @3.20 Ghz␊
␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
␉␉␉␉case CPU_MODEL_DALES:␊
␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉case CPU_MODEL_HASWELL:␊
␉␉␉␉case CPU_MODEL_HASWELL_SVR:␊
␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊
␉␉␉␉case CPUID_MODEL_FIELDS:␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
␉␉␉␉case CPUID_MODEL_DALES:␊
␉␉␉␉case CPUID_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉case CPUID_MODEL_NEHALEM:␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
␉␉␉␉case CPUID_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉case CPUID_MODEL_HASWELL:␊
␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
␊
␉␉␉␉␉break;␊
␊
trunk/i386/libsaio/smbios_getters.c
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␉␉␉␉{␊
␉␉␉␉␉␉// set external clock to 0 for SANDY␊
␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
␉␉␉␉␉case CPU_MODEL_JAKETOWN:␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
␉␉␉␉␉case CPU_MODEL_HASWELL:␊
␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␊
␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊
␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
␉␉␉␉␉case CPUID_MODEL_HASWELL:␊
␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊
␊
␉␉␉␉␉␉value->word = 0;␊
␉␉␉␉␉␉break;␊
␉␉␉{␊
␉␉␉␉switch (Platform.CPU.Model)␊
␉␉␉␉{␊
␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊
␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊
␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉␉// Intel Pentium M␊
␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉␉// Intel Mobile Core Solo, Duo␊
␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉␉// Intel Atom (45nm)␊
␉␉␉␉␉␉return false;␊
␊
␉␉␉␉␉case 0x19:␊
␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
␉␉␉␉␉case CPU_MODEL_DALES:␊
␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
␉␉␉␉␉case CPU_MODEL_HASWELL:␊
␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
␉␉␉␉␉case CPUID_MODEL_DALES:␊
␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉// Intel Xeon E7␊
␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
␉␉␉␉␉case CPUID_MODEL_HASWELL:␊
␉␉␉␉␉{␊
␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
␉␉␉␉␉␉int nhm_bus = 0x3F;␊
␉␉␉{␊
␉␉␉␉switch (Platform.CPU.Model)␊
␉␉␉␉{␊
␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊
␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// 0x0D - Intel Pentium M model D␊
␉␉␉␉␉case CPU_MODEL_PRESCOTT:␊
␉␉␉␉␉case CPU_MODEL_NOCONA:␊
␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊
␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉␉␉␉// 0x0D - Intel Pentium M model D␊
␉␉␉␉␉case CPUID_MODEL_PRESCOTT:␊
␉␉␉␉␉case CPUID_MODEL_NOCONA:␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_PRESLER:␊
␉␉␉␉␉case CPU_MODEL_CELERON:␊
␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
␉␉␉␉␉case CPUID_MODEL_PRESLER:␊
␉␉␉␉␉case CPUID_MODEL_CELERON:␊
␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
␉␉␉␉␉case CPU_MODEL_XEON_MP:␉␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
␉␉␉␉␉case CPUID_MODEL_XEON_MP:␉␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
␉␉␉␉␉case CPUID_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// 1281 - Lynnfiled Quad-Core Xeon␊
␉␉␉␉␉␉␉return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
␉␉␉␉␉␉␉return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊
␉␉␉␉␉␉␉return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
␉␉␉␉␉␉␉return true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊
␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊
␉␉␉␉␉␉value->word = 0xA01;␉␉␉// 2561 - Xeon␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_HASWELL:␉␉␉␉// 0x3C -␊
␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊
␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␉␉␉// 0x46␊
␉␉␉␉␉case CPUID_MODEL_HASWELL:␉␉␉␉// 0x3C -␊
␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊
␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␉␉␉// 0x46␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊
␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊
␉␉␉␉␉␉␉return true;␊
trunk/i386/boot2/options.c
12451245
12461246
12471247
1248
12481249
12491250
12501251
␉␉{␊
␉␉␉if( YOSEMITE ) // is 10.10␊
␉␉␉{␊
␊
␉␉␉␉strlcpy( bootInfo->bootFile, kOSXKernel, sizeof(bootInfo->bootFile) );␊
␉␉␉␉//printf(HEADER "/System/Library/Kernels/%s\n", bootInfo->bootFile);␊
␉␉␉}␊
trunk/i386/modules/AcpiCodec/acpi_codec.c
775775
776776
777777
778
778
779779
780780
781781
782782
783
783
784784
785785
786786
......
10711071
10721072
10731073
1074
1075
1076
1077
1078
1074
1075
1076
1077
1078
10791079
10801080
10811081
10821082
10831083
1084
1084
10851085
10861086
10871087
......
11211121
11221122
11231123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1124
1125
1126
1127
1128
1129
1130
1131
1132
11331133
11341134
11351135
......
13321332
13331333
13341334
1335
1336
1337
1338
1339
1335
1336
1337
1338
1339
13401340
13411341
13421342
......
14551455
14561456
14571457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1458
1459
1460
1461
1462
1463
1464
1465
1466
14671467
14681468
14691469
␊
static bool is_sandybridge(void)␊
{␊
return Platform.CPU.Model == CPU_MODEL_SANDYBRIDGE;␊
return Platform.CPU.Model == CPUID_MODEL_SANDYBRIDGE;␊
}␊
␊
static bool is_jaketown(void)␊
{␊
return Platform.CPU.Model == CPU_MODEL_JAKETOWN;␊
return Platform.CPU.Model == CPUID_MODEL_JAKETOWN;␊
}␊
␊
static U32 get_bclk(void)␊
␉␉{␊
␉␉␉switch (Platform.CPU.Model) ␊
␉␉␉{␊
␉␉␉␉case CPU_MODEL_DOTHAN: ␊
␉␉␉␉case CPU_MODEL_YONAH: // Yonah␊
␉␉␉␉case CPU_MODEL_MEROM: // Merom␊
␉␉␉␉case CPU_MODEL_PENRYN: // Penryn␊
␉␉␉␉case CPU_MODEL_ATOM: // Intel Atom (45nm)␊
␉␉␉␉case CPUID_MODEL_DOTHAN: ␊
␉␉␉␉case CPUID_MODEL_YONAH: // Yonah␊
␉␉␉␉case CPUID_MODEL_MEROM: // Merom␊
␉␉␉␉case CPUID_MODEL_PENRYN: // Penryn␊
␉␉␉␉case CPUID_MODEL_ATOM: // Intel Atom (45nm)␊
␉␉␉␉{␊
␉␉␉␉␉␊
␉␉␉␉␉cpu->core_c1_supported = ((sub_Cstates >> 4) & 0xf) ? 1 : 0;␊
␉␉␉␉␉cpu->core_c4_supported = ((sub_Cstates >> 16) & 0xf) ? 1 : 0;␊
␉␉␉␉␉␊
␉␉␉␉␉if (Platform.CPU.Model == CPU_MODEL_ATOM)␊
␉␉␉␉␉if (Platform.CPU.Model == CPUID_MODEL_ATOM)␊
␉␉␉␉␉{␊
␉␉␉␉␉␉cpu->core_c2_supported = cpu->core_c3_supported = ((sub_Cstates >> 8) & 0xf) ? 1 : 0;␊
␉␉␉␉␉␉cpu->core_c6_supported = ((sub_Cstates >> 12) & 0xf) ? 1 : 0;␊
␉␉␉␉␉␊
␉␉␉␉␉break;␊
␉␉␉␉} ␊
␉␉␉␉case CPU_MODEL_FIELDS:␊
␉␉␉␉case CPU_MODEL_DALES:␊
␉␉␉␉case CPU_MODEL_DALES_32NM:␊
␉␉␉␉case CPU_MODEL_NEHALEM: ␊
␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
␉␉␉␉case CPU_MODEL_WESTMERE:␊
␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊
␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
␉␉␉␉case CPU_MODEL_JAKETOWN:␊
␉␉␉␉case CPUID_MODEL_FIELDS:␊
␉␉␉␉case CPUID_MODEL_DALES:␊
␉␉␉␉case CPUID_MODEL_DALES_32NM:␊
␉␉␉␉case CPUID_MODEL_NEHALEM: ␊
␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
␉␉␉␉case CPUID_MODEL_WESTMERE:␊
␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
␉␉␉␉{␉␉␊
␉␉␉␉␉␊
␉␉␉␉␉cpu->core_c1_supported = ((sub_Cstates >> 4) & 0xf) ? 1 : 0;␊
␉␉␉{␊
␉␉␉␉switch (Platform.CPU.Model) ␊
␉␉␉␉{␊
␉␉␉␉␉case CPU_MODEL_DOTHAN: ␊
␉␉␉␉␉case CPU_MODEL_YONAH: // Yonah␊
␉␉␉␉␉case CPU_MODEL_MEROM: // Merom␊
␉␉␉␉␉case CPU_MODEL_PENRYN: // Penryn␊
␉␉␉␉␉case CPU_MODEL_ATOM: // Intel Atom (45nm)␊
␉␉␉␉␉case CPUID_MODEL_DOTHAN: ␊
␉␉␉␉␉case CPUID_MODEL_YONAH: // Yonah␊
␉␉␉␉␉case CPUID_MODEL_MEROM: // Merom␊
␉␉␉␉␉case CPUID_MODEL_PENRYN: // Penryn␊
␉␉␉␉␉case CPUID_MODEL_ATOM: // Intel Atom (45nm)␊
␉␉␉␉␉{␊
␉␉␉␉␉␉bool cpu_dynamic_fsb = false;␊
␉␉␉␉␉␉␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉} ␊
␉␉␉␉␉case CPU_MODEL_FIELDS:␊
␉␉␉␉␉case CPU_MODEL_DALES:␊
␉␉␉␉␉case CPU_MODEL_DALES_32NM:␊
␉␉␉␉␉case CPU_MODEL_NEHALEM: ␊
␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
␉␉␉␉␉case CPU_MODEL_WESTMERE:␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
␉␉␉␉␉case CPU_MODEL_JAKETOWN:␊
␉␉␉␉␉case CPUID_MODEL_FIELDS:␊
␉␉␉␉␉case CPUID_MODEL_DALES:␊
␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␊
␉␉␉␉␉case CPUID_MODEL_NEHALEM: ␊
␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
␉␉␉␉␉case CPUID_MODEL_WESTMERE:␊
␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
␉␉␉␉␉{␉␉␊
␉␉␉␉␉␉␊
␉␉␉␉␉␉maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; // Seems it always contains maximum multiplier value (with turbo, that's we need)...␊
trunk/CHANGES
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- meklort : Update laoder.h to latest, declare gMI global, Load modules passed in via the multiboot header / first bootloader,␊
␉␉Fix mboot.h include, Add ?log command to print out bdmesg without needing Wait=y, Add slightly more debugging for modules.␊
- ErmaC : Rename CPU_MODEL_xxx into CPUID_MODEL_xxx follow Apple source name␊
- ErmaC : Rename decompress_lzvn function to lzvn_decode follow Apple source name.␊
- bitshoveler : Fix "sed: RE error: illegal byte sequence", which turns out to be from feeding sed a TIFF file (buildpkg.sh)␊
- bitshoveler : CacheInit(), CacheRead() prototypes: use u_int32_t instead of long where appropriate (saio_internal.h)␊

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Revision: 2483