Chameleon

Chameleon Commit Details

Date:2015-01-24 17:18:49 (4 years 9 months ago)
Author:ErmaC
Commit:2547
Parents: 2546
Message:Update cpu define (Bungo)
Changes:
M/trunk/i386/libsaio/cpu.c
M/trunk/i386/libsaio/cpu.h

File differences

trunk/i386/libsaio/cpu.c
236236
237237
238238
239
240
241
242
243
239
240
241
242
243
244244
245
246
245
246
247247
248248
249
250
251
252
253
254
249
250
251
252
253
254
255255
256256
257257
*/
void scan_cpu(PlatformInfo_t *p)
{
uint64_ttscFrequency = 0;
uint64_tfsbFrequency = 0;
uint64_tcpuFrequency = 0;
uint64_tmsr = 0;
uint64_tflex_ratio = 0;
uint64_ttscFrequency= 0;
uint64_tfsbFrequency= 0;
uint64_tcpuFrequency= 0;
uint64_tmsr= 0;
uint64_tflex_ratio= 0;
uint32_tmax_ratio = 0;
uint32_tmin_ratio = 0;
uint32_tmax_ratio= 0;
uint32_tmin_ratio= 0;
uint32_treg[4];
uint8_tbus_ratio_max = 0;
uint8_tbus_ratio_min = 0;
uint8_tcurrdiv = 0;
uint8_tcurrcoef = 0;
uint8_tmaxdiv = 0;
uint8_tmaxcoef = 0;
uint8_tbus_ratio_max= 0;
uint8_tbus_ratio_min= 0;
uint8_tcurrdiv= 0;
uint8_tcurrcoef= 0;
uint8_tmaxdiv= 0;
uint8_tmaxcoef= 0;
const char*newratio;
charstr[128];
trunk/i386/libsaio/cpu.h
1010
1111
1212
13
14
15
16
1713
1814
15
16
17
18
19
20
21
22
23
24
25
1926
2027
2128
2229
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
6959
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
8576
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
8693
8794
8895
8996
90
91
92
93
94
95
96
97
98
99
97
98
99
100
101
102
103
104
105
106
100107
101108
102109
103110
104111
105
106
112
113
107114
108
109
110
115
116
117
111118
112
113119
120
121
122
114123
115124
116125
117126
118
127
119128
120
129
121130
122
123
131
132
124133
125134
126
127
128
129
135
136
137
138
130139
131140
132
133
134
135
136
137
141
142
143
144
145
146
147
138148
139
140
141
142
143
144
149
150
151
152
153
154
145155
146
147
148
149
150
151
152
153
156
157
158
159
160
161
162
163
154164
155165
156166
157167
158
168
159169
160170
161
171
162172
163
173
164174
165
175
166176
167177
168
178
169179
170
180
171181
172
173
174
182
183
184
175185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
176212
177
178
179
180
213
214
215
216
217
181218
182
183
219
220
184221
185
222
186223
187224
188
225
189226
190227
191228
......
215252
216253
217254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
218270
219271
220
221
222
223
224
225
272
273
274
275
276
277
278
279
226280
227281
228282
229283
230
231
232
233
234
235
284
285
286
287
288
289
290
291
236292
237293
238294
extern void scan_cpu(PlatformInfo_t *);
#define bit(n)(1ULL << (n))
#define bitmask(h,l)((bit(h) | (bit(h)-1)) & ~(bit(l)-1))
#define bitfield(x,h,l)(((x) & bitmask(h,l)) >> l)
#define CPU_STRING_UNKNOWN"Unknown CPU Type"
//definitions from Apple XNU
/* CPU defines */
#define bit(n)(1ULL << (n))
#define bitmask(h,l)((bit(h) | (bit(h)-1)) & ~(bit(l)-1))
#define bitfield(x,h,l)(((x) & bitmask(h,l)) >> l)
#define hbit(n)(1ULL << ((n)+32))
#define min(a,b)((a) < (b) ? (a) : (b))
#define quad32(hi,lo)((((uint32_t)(hi)) << 16) | (((uint32_t)(lo)) & 0xFFFF))
#define quad64(hi,lo)((((uint64_t)(hi)) << 32) | (((uint64_t)(lo)) & 0xFFFFFFFFUL))
/*
* The CPUID_FEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 1:
*/
#define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */
#define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */
#define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */
#define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */
#define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */
#define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */
#define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */
#define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */
#define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */
#define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */
#define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */
#define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */
#define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */
#define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */
#define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */
#define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */
#define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */
#define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */
#define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */
#define CPUID_FEATURE_DS _Bit(21) /* Debug Store */
#define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */
#define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */
#define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */
#define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */
#define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */
#define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */
#define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */
#define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */
#define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */
#define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */
#define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ instruction */
#define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */
#define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */
#define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */
#define CPUID_FEATURE_VMX _HBit(5) /* VMX */
#define CPUID_FEATURE_SMX _HBit(6) /* SMX */
#define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */
#define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */
#define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */
#define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */
#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */
#define CPUID_FEATURE_FMA _HBit(12) /* Fused-Multiply-Add support */
#define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */
#define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */
#define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */
#define CPUID_FEATURE_FPUbit(0) /* Floating point unit on-chip */
#define CPUID_FEATURE_VMEbit(1) /* Virtual Mode Extension */
#define CPUID_FEATURE_DEbit(2) /* Debugging Extension */
#define CPUID_FEATURE_PSEbit(3) /* Page Size Extension */
#define CPUID_FEATURE_TSCbit(4) /* Time Stamp Counter */
#define CPUID_FEATURE_MSRbit(5) /* Model Specific Registers */
#define CPUID_FEATURE_PAEbit(6) /* Physical Address Extension */
#define CPUID_FEATURE_MCEbit(7) /* Machine Check Exception */
#define CPUID_FEATURE_CX8bit(8) /* CMPXCHG8B */
#define CPUID_FEATURE_APICbit(9) /* On-chip APIC */
#define CPUID_FEATURE_SEPbit(11) /* Fast System Call */
#define CPUID_FEATURE_MTRRbit(12) /* Memory Type Range Register */
#define CPUID_FEATURE_PGEbit(13) /* Page Global Enable */
#define CPUID_FEATURE_MCAbit(14) /* Machine Check Architecture */
#define CPUID_FEATURE_CMOVbit(15) /* Conditional Move Instruction */
#define CPUID_FEATURE_PATbit(16) /* Page Attribute Table */
#define CPUID_FEATURE_PSE36bit(17) /* 36-bit Page Size Extension */
#define CPUID_FEATURE_PSNbit(18) /* Processor Serial Number */
#define CPUID_FEATURE_CLFSHbit(19) /* CLFLUSH Instruction supported */
#define CPUID_FEATURE_DSbit(21) /* Debug Store */
#define CPUID_FEATURE_ACPIbit(22) /* Thermal monitor and Clock Ctrl */
#define CPUID_FEATURE_MMXbit(23) /* MMX supported */
#define CPUID_FEATURE_FXSRbit(24) /* Fast floating pt save/restore */
#define CPUID_FEATURE_SSEbit(25) /* Streaming SIMD extensions */
#define CPUID_FEATURE_SSE2bit(26) /* Streaming SIMD extensions 2 */
#define CPUID_FEATURE_SSbit(27) /* Self-Snoop */
#define CPUID_FEATURE_HTTbit(28) /* Hyper-Threading Technology */
#define CPUID_FEATURE_TMbit(29) /* Thermal Monitor (TM1) */
#define CPUID_FEATURE_PBEbit(31) /* Pend Break Enable */
#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */
#define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */
#define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */
#define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */
#define CPUID_FEATURE_x2APIC _HBit(21) /* Extended APIC Mode */
#define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */
#define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */
#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */
#define CPUID_FEATURE_AES _HBit(25) /* AES instructions */
#define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */
#define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */
#define CPUID_FEATURE_AVX1_0_HBit(28) /* AVX 1.0 instructions */
#define CPUID_FEATURE_F16C_HBit(29) /* Float16 convert instructions */
#define CPUID_FEATURE_RDRAND_HBit(30) /* RDRAND instruction */
#define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */
#define CPUID_FEATURE_SSE3hbit(0) /* Streaming SIMD extensions 3 */
#define CPUID_FEATURE_PCLMULQDQhbit(1) /* PCLMULQDQ Instruction */
#define CPUID_FEATURE_DTES64hbit(2) /* 64-bit DS layout */
#define CPUID_FEATURE_MONITORhbit(3) /* Monitor/mwait */
#define CPUID_FEATURE_DSCPLhbit(4) /* Debug Store CPL */
#define CPUID_FEATURE_VMXhbit(5) /* VMX */
#define CPUID_FEATURE_SMXhbit(6) /* SMX */
#define CPUID_FEATURE_ESThbit(7) /* Enhanced SpeedsTep (GV3) */
#define CPUID_FEATURE_TM2hbit(8) /* Thermal Monitor 2 */
#define CPUID_FEATURE_SSSE3hbit(9) /* Supplemental SSE3 instructions */
#define CPUID_FEATURE_CIDhbit(10) /* L1 Context ID */
#define CPUID_FEATURE_SEGLIM64hbit(11) /* 64-bit segment limit checking */
#define CPUID_FEATURE_FMAhbit(12) /* Fused-Multiply-Add support */
#define CPUID_FEATURE_CX16hbit(13) /* CmpXchg16b instruction */
#define CPUID_FEATURE_xTPRhbit(14) /* Send Task PRiority msgs */
#define CPUID_FEATURE_PDCMhbit(15) /* Perf/Debug Capability MSR */
#define CPUID_FEATURE_PCIDhbit(17) /* ASID-PCID support */
#define CPUID_FEATURE_DCAhbit(18) /* Direct Cache Access */
#define CPUID_FEATURE_SSE4_1hbit(19) /* Streaming SIMD extensions 4.1 */
#define CPUID_FEATURE_SSE4_2hbit(20) /* Streaming SIMD extensions 4.2 */
#define CPUID_FEATURE_x2APIChbit(21) /* Extended APIC Mode */
#define CPUID_FEATURE_MOVBEhbit(22) /* MOVBE instruction */
#define CPUID_FEATURE_POPCNThbit(23) /* POPCNT instruction */
#define CPUID_FEATURE_TSCTMRhbit(24) /* TSC deadline timer */
#define CPUID_FEATURE_AEShbit(25) /* AES instructions */
#define CPUID_FEATURE_XSAVEhbit(26) /* XSAVE instructions */
#define CPUID_FEATURE_OSXSAVEhbit(27) /* XGETBV/XSETBV instructions */
#define CPUID_FEATURE_AVX1_0hbit(28) /* AVX 1.0 instructions */
#define CPUID_FEATURE_F16Chbit(29) /* Float16 convert instructions */
#define CPUID_FEATURE_RDRANDhbit(30) /* RDRAND instruction */
#define CPUID_FEATURE_VMMhbit(31) /* VMM (Hypervisor) present */
/*
* Leaf 7, subleaf 0 additional features.
* Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
*/
#define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)/* FS/GS base read/write */
#define CPUID_LEAF7_FEATURE_TSCOFF _Bit(1)/* TSC thread offset */
#define CPUID_LEAF7_FEATURE_BMI1 _Bit(3)/* Bit Manipulation Instrs, set 1 */
#define CPUID_LEAF7_FEATURE_HLE _Bit(4)/* Hardware Lock Elision*/
#define CPUID_LEAF7_FEATURE_AVX2 _Bit(5)/* AVX2 Instructions */
#define CPUID_LEAF7_FEATURE_SMEP _Bit(7)/* Supervisor Mode Execute Protect */
#define CPUID_LEAF7_FEATURE_BMI2 _Bit(8)/* Bit Manipulation Instrs, set 2 */
#define CPUID_LEAF7_FEATURE_ENFSTRG _Bit(9)/* ENhanced Fast STRinG copy */
#define CPUID_LEAF7_FEATURE_INVPCID _Bit(10)/* INVPCID intruction, TDB */
#define CPUID_LEAF7_FEATURE_RTM _Bit(11)/* TBD */
#define CPUID_LEAF7_FEATURE_RDWRFSGSbit(0)/* FS/GS base read/write */
#define CPUID_LEAF7_FEATURE_TSCOFFbit(1)/* TSC thread offset */
#define CPUID_LEAF7_FEATURE_BMI1bit(3)/* Bit Manipulation Instrs, set 1 */
#define CPUID_LEAF7_FEATURE_HLEbit(4)/* Hardware Lock Elision*/
#define CPUID_LEAF7_FEATURE_AVX2bit(5)/* AVX2 Instructions */
#define CPUID_LEAF7_FEATURE_SMEPbit(7)/* Supervisor Mode Execute Protect */
#define CPUID_LEAF7_FEATURE_BMI2bit(8)/* Bit Manipulation Instrs, set 2 */
#define CPUID_LEAF7_FEATURE_ENFSTRGbit(9)/* ENhanced Fast STRinG copy */
#define CPUID_LEAF7_FEATURE_INVPCIDbit(10)/* INVPCID intruction, TDB */
#define CPUID_LEAF7_FEATURE_RTMbit(11)/* TBD */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
*/
#define CPUID_EXTFEATURE_SYSCALL _Bit(11)/* SYSCALL/sysret */
#define CPUID_EXTFEATURE_XD _Bit(20)/* eXecute Disable */
#define CPUID_EXTFEATURE_SYSCALLbit(11)/* SYSCALL/sysret */
#define CPUID_EXTFEATURE_XDbit(20)/* eXecute Disable */
#define CPUID_EXTFEATURE_1GBPAGE _Bit(26)/* 1GB pages */
#define CPUID_EXTFEATURE_RDTSCP _Bit(27)/* RDTSCP */
#define CPUID_EXTFEATURE_EM64T _Bit(29)/* Extended Mem 64 Technology */
#define CPUID_EXTFEATURE_1GBPAGEbit(26)/* 1GB pages support */
#define CPUID_EXTFEATURE_RDTSCPbit(27)/* RDTSCP */
#define CPUID_EXTFEATURE_EM64Tbit(29)/* Extended Mem 64 Technology */
#define CPUID_EXTFEATURE_LAHF _HBit(0)/* LAFH/SAHF instructions */
#define CPUID_EXTFEATURE_LAHFhbit(0)/* LAFH/SAHF instructions */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
*/
#define CPUID_EXTFEATURE_TSCI _Bit(8)/* TSC Invariant */
#define CPUID_EXTFEATURE_TSCIbit(8)/* TSC Invariant */
#defineCPUID_CACHE_SIZE16/* Number of descriptor values */
#defineCPUID_CACHE_SIZE16/* Number of descriptor values */
#define CPUID_MWAIT_EXTENSION_Bit(0)/* enumeration of WMAIT extensions */
#define CPUID_MWAIT_BREAK_Bit(1)/* interrupts are break events */
#define CPUID_MWAIT_EXTENSIONbit(0)/* enumeration of WMAIT extensions */
#define CPUID_MWAIT_BREAKbit(1)/* interrupts are break events */
//-- processor type -> p_type:
#define PT_OEM0x00// Intel Original OEM Processor;
#define PT_OD0x01 // Intel Over Drive Processor;
#define PT_DUAL0x02// Intel Dual Processor;
#define PT_RES0x03// Intel Reserved;
#define PT_OEM0x00// Intel Original OEM Processor;
#define PT_OD0x01 // Intel Over Drive Processor;
#define PT_DUAL0x02// Intel Dual Processor;
#define PT_RES0x03// Intel Reserved;
/* Known MSR registers */
#define MSR_IA32_PLATFORM_ID 0x0017
#define MSR_CORE_THREAD_COUNT 0x0035/* limited use - not for Penryn or older */
#define IA32_TSC_ADJUST 0x003B
#define MSR_IA32_BIOS_SIGN_ID 0x008B/* microcode version */
#define MSR_FSB_FREQ 0x00CD/* limited use - not for i7 */
#defineMSR_PLATFORM_INFO 0x00CE/* limited use - MinRatio for i7 but Max for Yonah*/
#define MSR_IA32_PLATFORM_ID0x0017
#define IA32_APIC_BASE0x001B /* used also for AMD */
#define MSR_CORE_THREAD_COUNT0x0035/* limited use - not for Penryn or older */
#define IA32_TSC_ADJUST0x003B
#define MSR_IA32_BIOS_SIGN_ID0x008B/* microcode version */
#define MSR_FSB_FREQ0x00CD/* limited use - not for i7 */
#defineMSR_PLATFORM_INFO0x00CE/* limited use - MinRatio for i7 but Max for Yonah*/
/* turbo for penryn */
#define MSR_PKG_CST_CONFIG_CONTROL 0x00E2/* sandy and ivy */
#define MSR_PMG_IO_CAPTURE_BASE 0x00E4
#define IA32_MPERF 0x00E7/* TSC in C0 only */
#define IA32_APERF 0x00E8/* actual clocks in C0 */
#define MSR_IA32_EXT_CONFIG 0x00EE/* limited use - not for i7 */
#define MSR_FLEX_RATIO 0x0194/* limited use - not for Penryn or older */
#define MSR_PKG_CST_CONFIG_CONTROL0x00E2// sandy and ivy
#define MSR_PMG_IO_CAPTURE_BASE0x00E4
#define IA32_MPERF0x00E7// TSC in C0 only
#define IA32_APERF0x00E8// actual clocks in C0
#define MSR_IA32_EXT_CONFIG0x00EE// limited use - not for i7
#define MSR_FLEX_RATIO0x0194// limited use - not for Penryn or older
//see no value on most CPUs
#defineMSR_IA32_PERF_STATUS 0x0198
#define MSR_IA32_PERF_CONTROL 0x0199
#define MSR_IA32_CLOCK_MODULATION 0x019A
#define MSR_THERMAL_STATUS 0x019C
#define MSR_IA32_MISC_ENABLE 0x01A0
#define MSR_THERMAL_TARGET 0x01A2 /* TjMax limited use - not for Penryn or older*/
#define MSR_MISC_PWR_MGMT 0x01AA
#define MSR_TURBO_RATIO_LIMIT 0x01AD /* limited use - not for Penryn or older */
#defineMSR_IA32_PERF_STATUS0x0198
#define MSR_IA32_PERF_CONTROL0x0199
#define MSR_IA32_CLOCK_MODULATION0x019A
#define MSR_THERMAL_STATUS0x019C
#define MSR_IA32_MISC_ENABLE0x01A0
#define MSR_THERMAL_TARGET0x01A2// TjMax limited use - not for Penryn or older
#define MSR_MISC_PWR_MGMT0x01AA
#define MSR_TURBO_RATIO_LIMIT0x01AD// limited use - not for Penryn or older
#define IA32_ENERGY_PERF_BIAS0x01B0
#define MSR_PACKAGE_THERM_STATUS0x01B1
#define IA32_PLATFORM_DCA_CAP0x01F8
#define MSR_POWER_CTL0x01FC // MSR 000001FC 0000-0000-0004-005F
#define MSR_POWER_CTL0x01FC// MSR 000001FC 0000-0000-0004-005F
// Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.
#define MSR_RAPL_POWER_UNIT0x606 /* R/O */
#define MSR_RAPL_POWER_UNIT0x606// R/O
//MSR 00000606 0000-0000-000A-1003
#define MSR_PKGC3_IRTL 0x60A /* RW time limit to go C3 */
#define MSR_PKGC3_IRTL0x60A// RW time limit to go C3
// bit 15 = 1 -- the value valid for C-state PM
#define MSR_PKGC6_IRTL 0x60B /* RW time limit to go C6 */
#define MSR_PKGC6_IRTL0x60B// RW time limit to go C6
//MSR 0000060B 0000-0000-0000-8854
//Valid + 010=1024ns + 0x54=84mks
#define MSR_PKGC7_IRTL 0x60C /* RW time limit to go C7 */
#define MSR_PKGC7_IRTL0x60C// RW time limit to go C7
//MSR 0000060C 0000-0000-0000-8854
#define MSR_PKG_C2_RESIDENCY 0x60D /* same as TSC but in C2 only */
#define MSR_PKG_C2_RESIDENCY0x60D// same as TSC but in C2 only
#define MSR_PKG_RAPL_POWER_LIMIT0x610 //MSR 00000610 0000-A580-0000-8960
#define MSR_PKG_ENERGY_STATUS0x611 //MSR 00000611 0000-0000-3212-A857
#define MSR_PKG_POWER_INFO0x614 //MSR 00000614 0000-0000-01E0-02F8
#define MSR_PKG_RAPL_POWER_LIMIT0x610//MSR 00000610 0000-A580-0000-8960
#define MSR_PKG_ENERGY_STATUS0x611//MSR 00000611 0000-0000-3212-A857
#define MSR_PKG_POWER_INFO0x614//MSR 00000614 0000-0000-01E0-02F8
// Sandy Bridge IA (Core) domain MSR's.
#define MSR_PP0_POWER_LIMIT0x638
#define MSR_PP0_ENERGY_STATUS0x639
#define MSR_PP0_POLICY0x63A
#define MSR_PP0_PERF_STATUS0x63B
// Sandy Bridge Uncore (IGPU) domain MSR's (Not on JakeTown).
#define MSR_PP1_POWER_LIMIT0x640
#define MSR_PP1_ENERGY_STATUS 0x641
//MSR 00000641 0000-0000-0000-0000
#define MSR_PP1_POLICY0x642
// JakeTown only Memory MSR's.
#define MSR_PKG_PERF_STATUS0x613
#define MSR_DRAM_POWER_LIMIT 0x618
#define MSR_DRAM_ENERGY_STATUS0x619
#define MSR_DRAM_PERF_STATUS0x61B
#define MSR_DRAM_POWER_INFO0x61C
//IVY_BRIDGE
#define MSR_CONFIG_TDP_NOMINAL0x648
#define MSR_CONFIG_TDP_LEVEL10x649
#define MSR_CONFIG_TDP_LEVEL20x64A
#define MSR_CONFIG_TDP_CONTROL0x64B// write once to lock
#define MSR_TURBO_ACTIVATION_RATIO0x64C
//AMD
#define K8_FIDVID_STATUS 0xC0010042
#define K10_COFVID_LIMIT 0xC0010061
#define K10_PSTATE_STATUS 0xC0010064
#define K10_COFVID_STATUS 0xC0010071
#define K8_FIDVID_STATUS0xC0010042
#define K10_COFVID_LIMIT0xC0010061// max enabled p-state (msr >> 4) & 7
#define K10_COFVID_CONTROL0xC0010062// switch to p-state
#define K10_PSTATE_STATUS0xC0010064
#define K10_COFVID_STATUS0xC0010071// current p-state (msr >> 16) & 7
#define MSR_AMD_MPERF 0x000000E7
#define MSR_AMD_APERF 0x000000E8
#define MSR_AMD_MPERF0x000000E7
#define MSR_AMD_APERF0x000000E8
#define DEFAULT_FSB100000 /* for now, hardcoding 100MHz for old CPUs */
#define DEFAULT_FSB100000 /* for now, hardcoding 100MHz for old CPUs */
// DFE: This constant comes from older xnu:
#define CLKNUM1193182/* formerly 1193167 */
#define CLKNUM1193182/* formerly 1193167 */
// DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM
#define CALIBRATE_TIME_MSEC30/* 30 msecs */
while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; }
}
/* From Apple's cpuid.h */
typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
static inline void cpuid(uint32_t *data)
{
asm(
"cpuid" : "=a" (data[eax]),
"=b" (data[ebx]),
"=c" (data[ecx]),
"=d" (data[edx]) : "a" (data[eax]),
"b" (data[ebx]),
"c" (data[ecx]),
"d" (data[edx]));
}
static inline void do_cpuid(uint32_t selector, uint32_t *data)
{
asm volatile ("cpuid"
: "=a" (data[0]),
"=b" (data[1]),
"=c" (data[2]),
"=d" (data[3])
: "a" (selector));
asm(
"cpuid" : "=a" (data[eax]),
"=b" (data[ebx]),
"=c" (data[ecx]),
"=d" (data[edx]) : "a"(selector),
"b" (0),
"c" (0),
"d" (0));
}
static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data)
{
asm volatile ("cpuid"
: "=a" (data[0]),
"=b" (data[1]),
"=c" (data[2]),
"=d" (data[3])
: "a" (selector), "c" (selector2));
asm volatile (
"cpuid" : "=a" (data[eax]),
"=b" (data[ebx]),
"=c" (data[ecx]),
"=d" (data[edx]) : "a" (selector),
"b" (0),
"c" (selector2),
"d" (0));
}
// DFE: enable_PIT2 and disable_PIT2 come from older xnu

Archive Download the corresponding diff file

Revision: 2547