Chameleon

Chameleon Commit Details

Date:2015-01-24 17:23:08 (4 years 9 months ago)
Author:ErmaC
Commit:2548
Parents: 2547
Message:Move define stuff from cpu.h to platform.h
Changes:
M/trunk/i386/libsaio/platform.h
M/trunk/i386/libsaio/cpu.h

File differences

trunk/i386/libsaio/platform.h
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extern void scan_platform(void);
extern void dumpPhysAddr(const char * title, void * a, int len);
/* CPUID Vendor */
#define CPUID_VENDOR_INTEL 0x756E6547
#define CPUID_VENDOR_AMD 0x68747541
/* CPUID index into cpuid_raw */
#define CPUID_00
#define CPUID_11
//#define CPUID_MODEL_0x5A// Silvermont, Future Atom E3000, Z3000
//#define CPUID_MODEL_0x5D// Silvermont, Future Atom E3000, Z3000
/* CPUID Vendor */
#defineCPUID_VID_INTEL"GenuineIntel"
#defineCPUID_VID_AMD"AuthenticAMD"
#define CPUID_VENDOR_INTEL0x756E6547
#define CPUID_VENDOR_AMD0x68747541
/* Unknown CPU */
#define CPU_STRING_UNKNOWN"Unknown CPU Type"
//definitions from Apple XNU
/* CPU defines */
#define bit(n)(1ULL << (n))
#define bitmask(h,l)((bit(h) | (bit(h)-1)) & ~(bit(l)-1))
#define bitfield(x,h,l)(((x) & bitmask(h,l)) >> l)
#define hbit(n)(1ULL << ((n)+32))
#define min(a,b)((a) < (b) ? (a) : (b))
#define quad32(hi,lo)((((uint32_t)(hi)) << 16) | (((uint32_t)(lo)) & 0xFFFF))
#define quad64(hi,lo)((((uint64_t)(hi)) << 32) | (((uint64_t)(lo)) & 0xFFFFFFFFUL))
/*
* The CPUID_FEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 1:
*/
#define CPUID_FEATURE_FPUbit(0) /* Floating point unit on-chip */
#define CPUID_FEATURE_VMEbit(1) /* Virtual Mode Extension */
#define CPUID_FEATURE_DEbit(2) /* Debugging Extension */
#define CPUID_FEATURE_PSEbit(3) /* Page Size Extension */
#define CPUID_FEATURE_TSCbit(4) /* Time Stamp Counter */
#define CPUID_FEATURE_MSRbit(5) /* Model Specific Registers */
#define CPUID_FEATURE_PAEbit(6) /* Physical Address Extension */
#define CPUID_FEATURE_MCEbit(7) /* Machine Check Exception */
#define CPUID_FEATURE_CX8bit(8) /* CMPXCHG8B */
#define CPUID_FEATURE_APICbit(9) /* On-chip APIC */
#define CPUID_FEATURE_SEPbit(11) /* Fast System Call */
#define CPUID_FEATURE_MTRRbit(12) /* Memory Type Range Register */
#define CPUID_FEATURE_PGEbit(13) /* Page Global Enable */
#define CPUID_FEATURE_MCAbit(14) /* Machine Check Architecture */
#define CPUID_FEATURE_CMOVbit(15) /* Conditional Move Instruction */
#define CPUID_FEATURE_PATbit(16) /* Page Attribute Table */
#define CPUID_FEATURE_PSE36bit(17) /* 36-bit Page Size Extension */
#define CPUID_FEATURE_PSNbit(18) /* Processor Serial Number */
#define CPUID_FEATURE_CLFSHbit(19) /* CLFLUSH Instruction supported */
#define CPUID_FEATURE_DSbit(21) /* Debug Store */
#define CPUID_FEATURE_ACPIbit(22) /* Thermal monitor and Clock Ctrl */
#define CPUID_FEATURE_MMXbit(23) /* MMX supported */
#define CPUID_FEATURE_FXSRbit(24) /* Fast floating pt save/restore */
#define CPUID_FEATURE_SSEbit(25) /* Streaming SIMD extensions */
#define CPUID_FEATURE_SSE2bit(26) /* Streaming SIMD extensions 2 */
#define CPUID_FEATURE_SSbit(27) /* Self-Snoop */
#define CPUID_FEATURE_HTTbit(28) /* Hyper-Threading Technology */
#define CPUID_FEATURE_TMbit(29) /* Thermal Monitor (TM1) */
#define CPUID_FEATURE_PBEbit(31) /* Pend Break Enable */
#define CPUID_FEATURE_SSE3hbit(0) /* Streaming SIMD extensions 3 */
#define CPUID_FEATURE_PCLMULQDQhbit(1) /* PCLMULQDQ Instruction */
#define CPUID_FEATURE_DTES64hbit(2) /* 64-bit DS layout */
#define CPUID_FEATURE_MONITORhbit(3) /* Monitor/mwait */
#define CPUID_FEATURE_DSCPLhbit(4) /* Debug Store CPL */
#define CPUID_FEATURE_VMXhbit(5) /* VMX */
#define CPUID_FEATURE_SMXhbit(6) /* SMX */
#define CPUID_FEATURE_ESThbit(7) /* Enhanced SpeedsTep (GV3) */
#define CPUID_FEATURE_TM2hbit(8) /* Thermal Monitor 2 */
#define CPUID_FEATURE_SSSE3hbit(9) /* Supplemental SSE3 instructions */
#define CPUID_FEATURE_CIDhbit(10) /* L1 Context ID */
#define CPUID_FEATURE_SEGLIM64hbit(11) /* 64-bit segment limit checking */
#define CPUID_FEATURE_FMAhbit(12) /* Fused-Multiply-Add support */
#define CPUID_FEATURE_CX16hbit(13) /* CmpXchg16b instruction */
#define CPUID_FEATURE_xTPRhbit(14) /* Send Task PRiority msgs */
#define CPUID_FEATURE_PDCMhbit(15) /* Perf/Debug Capability MSR */
#define CPUID_FEATURE_PCIDhbit(17) /* ASID-PCID support */
#define CPUID_FEATURE_DCAhbit(18) /* Direct Cache Access */
#define CPUID_FEATURE_SSE4_1hbit(19) /* Streaming SIMD extensions 4.1 */
#define CPUID_FEATURE_SSE4_2hbit(20) /* Streaming SIMD extensions 4.2 */
#define CPUID_FEATURE_x2APIChbit(21) /* Extended APIC Mode */
#define CPUID_FEATURE_MOVBEhbit(22) /* MOVBE instruction */
#define CPUID_FEATURE_POPCNThbit(23) /* POPCNT instruction */
#define CPUID_FEATURE_TSCTMRhbit(24) /* TSC deadline timer */
#define CPUID_FEATURE_AEShbit(25) /* AES instructions */
#define CPUID_FEATURE_XSAVEhbit(26) /* XSAVE instructions */
#define CPUID_FEATURE_OSXSAVEhbit(27) /* XGETBV/XSETBV instructions */
#define CPUID_FEATURE_AVX1_0hbit(28) /* AVX 1.0 instructions */
#define CPUID_FEATURE_F16Chbit(29) /* Float16 convert instructions */
#define CPUID_FEATURE_RDRANDhbit(30) /* RDRAND instruction */
#define CPUID_FEATURE_VMMhbit(31) /* VMM (Hypervisor) present */
/*
* Leaf 7, subleaf 0 additional features.
* Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
*/
#define CPUID_LEAF7_FEATURE_RDWRFSGSbit(0)/* FS/GS base read/write */
#define CPUID_LEAF7_FEATURE_TSCOFFbit(1)/* TSC thread offset */
#define CPUID_LEAF7_FEATURE_BMI1bit(3)/* Bit Manipulation Instrs, set 1 */
#define CPUID_LEAF7_FEATURE_HLEbit(4)/* Hardware Lock Elision*/
#define CPUID_LEAF7_FEATURE_AVX2bit(5)/* AVX2 Instructions */
#define CPUID_LEAF7_FEATURE_SMEPbit(7)/* Supervisor Mode Execute Protect */
#define CPUID_LEAF7_FEATURE_BMI2bit(8)/* Bit Manipulation Instrs, set 2 */
#define CPUID_LEAF7_FEATURE_ENFSTRGbit(9)/* ENhanced Fast STRinG copy */
#define CPUID_LEAF7_FEATURE_INVPCIDbit(10)/* INVPCID intruction, TDB */
#define CPUID_LEAF7_FEATURE_RTMbit(11)/* TBD */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
*/
#define CPUID_EXTFEATURE_SYSCALLbit(11)/* SYSCALL/sysret */
#define CPUID_EXTFEATURE_XDbit(20)/* eXecute Disable */
#define CPUID_EXTFEATURE_1GBPAGEbit(26)/* 1GB pages support */
#define CPUID_EXTFEATURE_RDTSCPbit(27)/* RDTSCP */
#define CPUID_EXTFEATURE_EM64Tbit(29)/* Extended Mem 64 Technology */
#define CPUID_EXTFEATURE_LAHFhbit(0)/* LAFH/SAHF instructions */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
*/
#define CPUID_EXTFEATURE_TSCIbit(8)/* TSC Invariant */
#defineCPUID_CACHE_SIZE16/* Number of descriptor values */
#define CPUID_MWAIT_EXTENSIONbit(0)/* enumeration of WMAIT extensions */
#define CPUID_MWAIT_BREAKbit(1)/* interrupts are break events */
//-- processor type -> p_type:
#define PT_OEM0x00// Intel Original OEM Processor;
#define PT_OD0x01 // Intel Over Drive Processor;
#define PT_DUAL0x02// Intel Dual Processor;
#define PT_RES0x03// Intel Reserved;
/* Known MSR registers */
#define MSR_IA32_PLATFORM_ID0x0017
#define IA32_APIC_BASE0x001B /* used also for AMD */
#define MSR_CORE_THREAD_COUNT0x0035/* limited use - not for Penryn or older */
#define IA32_TSC_ADJUST0x003B
#define MSR_IA32_BIOS_SIGN_ID0x008B/* microcode version */
#define MSR_FSB_FREQ0x00CD/* limited use - not for i7 */
#defineMSR_PLATFORM_INFO0x00CE/* limited use - MinRatio for i7 but Max for Yonah*/
/* turbo for penryn */
#define MSR_PKG_CST_CONFIG_CONTROL0x00E2// sandy and ivy
#define MSR_PMG_IO_CAPTURE_BASE0x00E4
#define IA32_MPERF0x00E7// TSC in C0 only
#define IA32_APERF0x00E8// actual clocks in C0
#define MSR_IA32_EXT_CONFIG0x00EE// limited use - not for i7
#define MSR_FLEX_RATIO0x0194// limited use - not for Penryn or older
//see no value on most CPUs
#defineMSR_IA32_PERF_STATUS0x0198
#define MSR_IA32_PERF_CONTROL0x0199
#define MSR_IA32_CLOCK_MODULATION0x019A
#define MSR_THERMAL_STATUS0x019C
#define MSR_IA32_MISC_ENABLE0x01A0
#define MSR_THERMAL_TARGET0x01A2// TjMax limited use - not for Penryn or older
#define MSR_MISC_PWR_MGMT0x01AA
#define MSR_TURBO_RATIO_LIMIT0x01AD// limited use - not for Penryn or older
#define IA32_ENERGY_PERF_BIAS0x01B0
#define MSR_PACKAGE_THERM_STATUS0x01B1
#define IA32_PLATFORM_DCA_CAP0x01F8
#define MSR_POWER_CTL0x01FC// MSR 000001FC 0000-0000-0004-005F
// Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.
#define MSR_RAPL_POWER_UNIT0x606// R/O
//MSR 00000606 0000-0000-000A-1003
#define MSR_PKGC3_IRTL0x60A// RW time limit to go C3
// bit 15 = 1 -- the value valid for C-state PM
#define MSR_PKGC6_IRTL0x60B// RW time limit to go C6
//MSR 0000060B 0000-0000-0000-8854
//Valid + 010=1024ns + 0x54=84mks
#define MSR_PKGC7_IRTL0x60C// RW time limit to go C7
//MSR 0000060C 0000-0000-0000-8854
#define MSR_PKG_C2_RESIDENCY0x60D// same as TSC but in C2 only
#define MSR_PKG_RAPL_POWER_LIMIT0x610//MSR 00000610 0000-A580-0000-8960
#define MSR_PKG_ENERGY_STATUS0x611//MSR 00000611 0000-0000-3212-A857
#define MSR_PKG_POWER_INFO0x614//MSR 00000614 0000-0000-01E0-02F8
// Sandy Bridge IA (Core) domain MSR's.
#define MSR_PP0_POWER_LIMIT0x638
#define MSR_PP0_ENERGY_STATUS0x639
#define MSR_PP0_POLICY0x63A
#define MSR_PP0_PERF_STATUS0x63B
// Sandy Bridge Uncore (IGPU) domain MSR's (Not on JakeTown).
#define MSR_PP1_POWER_LIMIT0x640
#define MSR_PP1_ENERGY_STATUS 0x641
//MSR 00000641 0000-0000-0000-0000
#define MSR_PP1_POLICY0x642
// JakeTown only Memory MSR's.
#define MSR_PKG_PERF_STATUS0x613
#define MSR_DRAM_POWER_LIMIT 0x618
#define MSR_DRAM_ENERGY_STATUS0x619
#define MSR_DRAM_PERF_STATUS0x61B
#define MSR_DRAM_POWER_INFO0x61C
//IVY_BRIDGE
#define MSR_CONFIG_TDP_NOMINAL0x648
#define MSR_CONFIG_TDP_LEVEL10x649
#define MSR_CONFIG_TDP_LEVEL20x64A
#define MSR_CONFIG_TDP_CONTROL0x64B// write once to lock
#define MSR_TURBO_ACTIVATION_RATIO0x64C
//AMD
#define K8_FIDVID_STATUS0xC0010042
#define K10_COFVID_LIMIT0xC0010061// max enabled p-state (msr >> 4) & 7
#define K10_COFVID_CONTROL0xC0010062// switch to p-state
#define K10_PSTATE_STATUS0xC0010064
#define K10_COFVID_STATUS0xC0010071// current p-state (msr >> 16) & 7
#define MSR_AMD_MPERF0x000000E7
#define MSR_AMD_APERF0x000000E8
#define DEFAULT_FSB100000 /* for now, hardcoding 100MHz for old CPUs */
// DFE: This constant comes from older xnu:
#define CLKNUM1193182/* formerly 1193167 */
/* CPU Features */
#define CPU_FEATURE_MMX0x00000001// MMX Instruction Set
#define CPU_FEATURE_SSE0x00000002// SSE Instruction Set
trunk/i386/libsaio/cpu.h
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extern void scan_cpu(PlatformInfo_t *);
#define CPU_STRING_UNKNOWN"Unknown CPU Type"
//definitions from Apple XNU
/* CPU defines */
#define bit(n)(1ULL << (n))
#define bitmask(h,l)((bit(h) | (bit(h)-1)) & ~(bit(l)-1))
#define bitfield(x,h,l)(((x) & bitmask(h,l)) >> l)
#define hbit(n)(1ULL << ((n)+32))
#define min(a,b)((a) < (b) ? (a) : (b))
#define quad32(hi,lo)((((uint32_t)(hi)) << 16) | (((uint32_t)(lo)) & 0xFFFF))
#define quad64(hi,lo)((((uint64_t)(hi)) << 32) | (((uint64_t)(lo)) & 0xFFFFFFFFUL))
/*
* The CPUID_FEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 1:
*/
#define CPUID_FEATURE_FPUbit(0) /* Floating point unit on-chip */
#define CPUID_FEATURE_VMEbit(1) /* Virtual Mode Extension */
#define CPUID_FEATURE_DEbit(2) /* Debugging Extension */
#define CPUID_FEATURE_PSEbit(3) /* Page Size Extension */
#define CPUID_FEATURE_TSCbit(4) /* Time Stamp Counter */
#define CPUID_FEATURE_MSRbit(5) /* Model Specific Registers */
#define CPUID_FEATURE_PAEbit(6) /* Physical Address Extension */
#define CPUID_FEATURE_MCEbit(7) /* Machine Check Exception */
#define CPUID_FEATURE_CX8bit(8) /* CMPXCHG8B */
#define CPUID_FEATURE_APICbit(9) /* On-chip APIC */
#define CPUID_FEATURE_SEPbit(11) /* Fast System Call */
#define CPUID_FEATURE_MTRRbit(12) /* Memory Type Range Register */
#define CPUID_FEATURE_PGEbit(13) /* Page Global Enable */
#define CPUID_FEATURE_MCAbit(14) /* Machine Check Architecture */
#define CPUID_FEATURE_CMOVbit(15) /* Conditional Move Instruction */
#define CPUID_FEATURE_PATbit(16) /* Page Attribute Table */
#define CPUID_FEATURE_PSE36bit(17) /* 36-bit Page Size Extension */
#define CPUID_FEATURE_PSNbit(18) /* Processor Serial Number */
#define CPUID_FEATURE_CLFSHbit(19) /* CLFLUSH Instruction supported */
#define CPUID_FEATURE_DSbit(21) /* Debug Store */
#define CPUID_FEATURE_ACPIbit(22) /* Thermal monitor and Clock Ctrl */
#define CPUID_FEATURE_MMXbit(23) /* MMX supported */
#define CPUID_FEATURE_FXSRbit(24) /* Fast floating pt save/restore */
#define CPUID_FEATURE_SSEbit(25) /* Streaming SIMD extensions */
#define CPUID_FEATURE_SSE2bit(26) /* Streaming SIMD extensions 2 */
#define CPUID_FEATURE_SSbit(27) /* Self-Snoop */
#define CPUID_FEATURE_HTTbit(28) /* Hyper-Threading Technology */
#define CPUID_FEATURE_TMbit(29) /* Thermal Monitor (TM1) */
#define CPUID_FEATURE_PBEbit(31) /* Pend Break Enable */
#define CPUID_FEATURE_SSE3hbit(0) /* Streaming SIMD extensions 3 */
#define CPUID_FEATURE_PCLMULQDQhbit(1) /* PCLMULQDQ Instruction */
#define CPUID_FEATURE_DTES64hbit(2) /* 64-bit DS layout */
#define CPUID_FEATURE_MONITORhbit(3) /* Monitor/mwait */
#define CPUID_FEATURE_DSCPLhbit(4) /* Debug Store CPL */
#define CPUID_FEATURE_VMXhbit(5) /* VMX */
#define CPUID_FEATURE_SMXhbit(6) /* SMX */
#define CPUID_FEATURE_ESThbit(7) /* Enhanced SpeedsTep (GV3) */
#define CPUID_FEATURE_TM2hbit(8) /* Thermal Monitor 2 */
#define CPUID_FEATURE_SSSE3hbit(9) /* Supplemental SSE3 instructions */
#define CPUID_FEATURE_CIDhbit(10) /* L1 Context ID */
#define CPUID_FEATURE_SEGLIM64hbit(11) /* 64-bit segment limit checking */
#define CPUID_FEATURE_FMAhbit(12) /* Fused-Multiply-Add support */
#define CPUID_FEATURE_CX16hbit(13) /* CmpXchg16b instruction */
#define CPUID_FEATURE_xTPRhbit(14) /* Send Task PRiority msgs */
#define CPUID_FEATURE_PDCMhbit(15) /* Perf/Debug Capability MSR */
#define CPUID_FEATURE_PCIDhbit(17) /* ASID-PCID support */
#define CPUID_FEATURE_DCAhbit(18) /* Direct Cache Access */
#define CPUID_FEATURE_SSE4_1hbit(19) /* Streaming SIMD extensions 4.1 */
#define CPUID_FEATURE_SSE4_2hbit(20) /* Streaming SIMD extensions 4.2 */
#define CPUID_FEATURE_x2APIChbit(21) /* Extended APIC Mode */
#define CPUID_FEATURE_MOVBEhbit(22) /* MOVBE instruction */
#define CPUID_FEATURE_POPCNThbit(23) /* POPCNT instruction */
#define CPUID_FEATURE_TSCTMRhbit(24) /* TSC deadline timer */
#define CPUID_FEATURE_AEShbit(25) /* AES instructions */
#define CPUID_FEATURE_XSAVEhbit(26) /* XSAVE instructions */
#define CPUID_FEATURE_OSXSAVEhbit(27) /* XGETBV/XSETBV instructions */
#define CPUID_FEATURE_AVX1_0hbit(28) /* AVX 1.0 instructions */
#define CPUID_FEATURE_F16Chbit(29) /* Float16 convert instructions */
#define CPUID_FEATURE_RDRANDhbit(30) /* RDRAND instruction */
#define CPUID_FEATURE_VMMhbit(31) /* VMM (Hypervisor) present */
/*
* Leaf 7, subleaf 0 additional features.
* Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
*/
#define CPUID_LEAF7_FEATURE_RDWRFSGSbit(0)/* FS/GS base read/write */
#define CPUID_LEAF7_FEATURE_TSCOFFbit(1)/* TSC thread offset */
#define CPUID_LEAF7_FEATURE_BMI1bit(3)/* Bit Manipulation Instrs, set 1 */
#define CPUID_LEAF7_FEATURE_HLEbit(4)/* Hardware Lock Elision*/
#define CPUID_LEAF7_FEATURE_AVX2bit(5)/* AVX2 Instructions */
#define CPUID_LEAF7_FEATURE_SMEPbit(7)/* Supervisor Mode Execute Protect */
#define CPUID_LEAF7_FEATURE_BMI2bit(8)/* Bit Manipulation Instrs, set 2 */
#define CPUID_LEAF7_FEATURE_ENFSTRGbit(9)/* ENhanced Fast STRinG copy */
#define CPUID_LEAF7_FEATURE_INVPCIDbit(10)/* INVPCID intruction, TDB */
#define CPUID_LEAF7_FEATURE_RTMbit(11)/* TBD */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
*/
#define CPUID_EXTFEATURE_SYSCALLbit(11)/* SYSCALL/sysret */
#define CPUID_EXTFEATURE_XDbit(20)/* eXecute Disable */
#define CPUID_EXTFEATURE_1GBPAGEbit(26)/* 1GB pages support */
#define CPUID_EXTFEATURE_RDTSCPbit(27)/* RDTSCP */
#define CPUID_EXTFEATURE_EM64Tbit(29)/* Extended Mem 64 Technology */
#define CPUID_EXTFEATURE_LAHFhbit(0)/* LAFH/SAHF instructions */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
*/
#define CPUID_EXTFEATURE_TSCIbit(8)/* TSC Invariant */
#defineCPUID_CACHE_SIZE16/* Number of descriptor values */
#define CPUID_MWAIT_EXTENSIONbit(0)/* enumeration of WMAIT extensions */
#define CPUID_MWAIT_BREAKbit(1)/* interrupts are break events */
//-- processor type -> p_type:
#define PT_OEM0x00// Intel Original OEM Processor;
#define PT_OD0x01 // Intel Over Drive Processor;
#define PT_DUAL0x02// Intel Dual Processor;
#define PT_RES0x03// Intel Reserved;
/* Known MSR registers */
#define MSR_IA32_PLATFORM_ID0x0017
#define IA32_APIC_BASE0x001B /* used also for AMD */
#define MSR_CORE_THREAD_COUNT0x0035/* limited use - not for Penryn or older */
#define IA32_TSC_ADJUST0x003B
#define MSR_IA32_BIOS_SIGN_ID0x008B/* microcode version */
#define MSR_FSB_FREQ0x00CD/* limited use - not for i7 */
#defineMSR_PLATFORM_INFO0x00CE/* limited use - MinRatio for i7 but Max for Yonah*/
/* turbo for penryn */
#define MSR_PKG_CST_CONFIG_CONTROL0x00E2// sandy and ivy
#define MSR_PMG_IO_CAPTURE_BASE0x00E4
#define IA32_MPERF0x00E7// TSC in C0 only
#define IA32_APERF0x00E8// actual clocks in C0
#define MSR_IA32_EXT_CONFIG0x00EE// limited use - not for i7
#define MSR_FLEX_RATIO0x0194// limited use - not for Penryn or older
//see no value on most CPUs
#defineMSR_IA32_PERF_STATUS0x0198
#define MSR_IA32_PERF_CONTROL0x0199
#define MSR_IA32_CLOCK_MODULATION0x019A
#define MSR_THERMAL_STATUS0x019C
#define MSR_IA32_MISC_ENABLE0x01A0
#define MSR_THERMAL_TARGET0x01A2// TjMax limited use - not for Penryn or older
#define MSR_MISC_PWR_MGMT0x01AA
#define MSR_TURBO_RATIO_LIMIT0x01AD// limited use - not for Penryn or older
#define IA32_ENERGY_PERF_BIAS0x01B0
#define MSR_PACKAGE_THERM_STATUS0x01B1
#define IA32_PLATFORM_DCA_CAP0x01F8
#define MSR_POWER_CTL0x01FC// MSR 000001FC 0000-0000-0004-005F
// Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.
#define MSR_RAPL_POWER_UNIT0x606// R/O
//MSR 00000606 0000-0000-000A-1003
#define MSR_PKGC3_IRTL0x60A// RW time limit to go C3
// bit 15 = 1 -- the value valid for C-state PM
#define MSR_PKGC6_IRTL0x60B// RW time limit to go C6
//MSR 0000060B 0000-0000-0000-8854
//Valid + 010=1024ns + 0x54=84mks
#define MSR_PKGC7_IRTL0x60C// RW time limit to go C7
//MSR 0000060C 0000-0000-0000-8854
#define MSR_PKG_C2_RESIDENCY0x60D// same as TSC but in C2 only
#define MSR_PKG_RAPL_POWER_LIMIT0x610//MSR 00000610 0000-A580-0000-8960
#define MSR_PKG_ENERGY_STATUS0x611//MSR 00000611 0000-0000-3212-A857
#define MSR_PKG_POWER_INFO0x614//MSR 00000614 0000-0000-01E0-02F8
// Sandy Bridge IA (Core) domain MSR's.
#define MSR_PP0_POWER_LIMIT0x638
#define MSR_PP0_ENERGY_STATUS0x639
#define MSR_PP0_POLICY0x63A
#define MSR_PP0_PERF_STATUS0x63B
// Sandy Bridge Uncore (IGPU) domain MSR's (Not on JakeTown).
#define MSR_PP1_POWER_LIMIT0x640
#define MSR_PP1_ENERGY_STATUS 0x641
//MSR 00000641 0000-0000-0000-0000
#define MSR_PP1_POLICY0x642
// JakeTown only Memory MSR's.
#define MSR_PKG_PERF_STATUS0x613
#define MSR_DRAM_POWER_LIMIT 0x618
#define MSR_DRAM_ENERGY_STATUS0x619
#define MSR_DRAM_PERF_STATUS0x61B
#define MSR_DRAM_POWER_INFO0x61C
//IVY_BRIDGE
#define MSR_CONFIG_TDP_NOMINAL0x648
#define MSR_CONFIG_TDP_LEVEL10x649
#define MSR_CONFIG_TDP_LEVEL20x64A
#define MSR_CONFIG_TDP_CONTROL0x64B// write once to lock
#define MSR_TURBO_ACTIVATION_RATIO0x64C
//AMD
#define K8_FIDVID_STATUS0xC0010042
#define K10_COFVID_LIMIT0xC0010061// max enabled p-state (msr >> 4) & 7
#define K10_COFVID_CONTROL0xC0010062// switch to p-state
#define K10_PSTATE_STATUS0xC0010064
#define K10_COFVID_STATUS0xC0010071// current p-state (msr >> 16) & 7
#define MSR_AMD_MPERF0x000000E7
#define MSR_AMD_APERF0x000000E8
#define DEFAULT_FSB100000 /* for now, hardcoding 100MHz for old CPUs */
// DFE: This constant comes from older xnu:
#define CLKNUM1193182/* formerly 1193167 */
// DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM
#define CALIBRATE_TIME_MSEC30/* 30 msecs */
#define CALIBRATE_LATCH((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)

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