Chameleon

Chameleon Commit Details

Date:2015-01-24 17:35:00 (4 years 5 months ago)
Author:ErmaC
Commit:2549
Parents: 2548
Message:Sync with trunk(r.2548)
Changes:
M/branches/ErmaC/Enoch/CHANGES
M/branches/ErmaC/Enoch/i386/libsaio/cpu.h
M/branches/ErmaC/Enoch/i386/libsaio/saio_internal.h
M/branches/ErmaC/Enoch/i386/libsaio/stringTable.c
M/branches/ErmaC/Enoch/i386/libsaio/pci.h
M/branches/ErmaC/Enoch/i386/libsaio/console.c
M/branches/ErmaC/Enoch/i386/libsaio/gma.c
M/branches/ErmaC/Enoch/i386/libsaio/spd.c
M/branches/ErmaC/Enoch/i386/libsaio/cpu.c
M/branches/ErmaC/Enoch/i386/libsaio/platform.h
M/branches/ErmaC/Enoch/i386/libsaio/disk.c
M/branches/ErmaC/Enoch/i386/boot2/boot.h

File differences

branches/ErmaC/Enoch/i386/libsaio/console.c
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bzero(msgbuf, BOOTER_LOG_SIZE);
cursor = msgbuf;
msglog("%s\n", "Enoch (r" I386BOOT_CHAMELEONREVISION ")" " [" I386BOOT_BUILDDATE "]");
getRTCdatetime();
verbose("Logging started: %04d/%02d/%02d, %02d:%02d:%02d\n", datetime.year, datetime.mon, datetime.day, datetime.hour, datetime.mins, datetime.secs);
}
void msglog(const char * fmt, ...)
int msglog(const char * fmt, ...)
{
va_list ap;
struct putc_info pi;
if (!msgbuf)
{
return;
return 0;
}
if (((cursor - msgbuf) > (BOOTER_LOG_SIZE - SAFE_LOG_SIZE)))
{
return;
return 0;
}
va_start(ap, fmt);
prf(fmt, ap, sputc, &pi);
va_end(ap);
cursor += strlen((char *)cursor);
return 0;
}
void setupBooterLog(void)
{
vprf(fmt, ap);
}
/*
{
// Kabyl: BooterLog
struct putc_info pi;
prf(fmt, ap, sputc, &pi);
cursor += strlen((char *)cursor);
}
*/
va_end(ap);
return 0;
}
branches/ErmaC/Enoch/i386/libsaio/spd.c
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if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3
{
bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1
code = spd[SPD_DDR3_MEMORY_CODE];
for (i=0; i < VEN_MAP_SIZE; i++)
/* Get Default Memory Module Speed (no overclocking handled) */
int getDDRspeedMhz(const char * spd)
{
if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3)
if ((spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2) || (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR))
{
switch(spd[12])
{
case 0x0f:
return 1066;
case 0x0c:
return 1333;
case 0x0a:
return 1600;
case 0x14:
default:
return 800;
}
}
else if ((spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR2) || (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR))
{
switch(spd[9])
{
case 0x50:
return 1066;
}
}
else if (spd[SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3)
{
switch(spd[12])
{
case 0x0f:
return 1066;
case 0x0c:
return 1333;
case 0x0a:
return 1600;
case 0x14:
default:
return 800;
}
}
return 800; // default freq for unknown types
}
branches/ErmaC/Enoch/i386/libsaio/gma.c
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{ 0x00,0x00,0x26,0x04 },// 5 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 3, Ports: 3, FBMem: 3 - mobile GT3
{ 0x00,0x00,0x26,0x0a },// 6 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 3, Ports: 3, FBMem: 3 - ULT mobile GT3
{ 0x00,0x00,0x26,0x0c },// 7 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 3, Ports: 3, FBMem: 3 - SDV mobile GT3
{ 0x00,0x00,0x26,0x0d }, // 8 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 3, Ports: 3, FBMem: 3 - CRW mobile GT3
{ 0x00,0x00,0x26,0x0d },// 8 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 3, Ports: 3, FBMem: 3 - CRW mobile GT3
{ 0x02,0x00,0x16,0x04 },// 9 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 1, Ports: 1, FBMem: 1 - mobile GT2
{ 0x03,0x00,0x22,0x0d }, // 10 "AAPL,ig-platform-id" //FB: 0MB, Pipes: 0, Ports: 0, FBMem: 0 - CRW Desktop GT3
{ 0x03,0x00,0x22,0x0d },// 10 "AAPL,ig-platform-id" //FB: 0MB, Pipes: 0, Ports: 0, FBMem: 0 - CRW Desktop GT3
//{ 0x04,0x00,0x12,0x04 },// ?? "AAPL,ig-platform-id" //FB: 32MB, Pipes: 3, Ports: 3, FBMem: 3 - ULT mobile GT3
{ 0x05,0x00,0x26,0x0a },// 11 "AAPL,ig-platform-id" //FB: 32MB, Pipes: 3, Ports: 3, FBMem: 3 - ULT mobile GT3
{ 0x06,0x00,0x26,0x0a },// 12 "AAPL,ig-platform-id" //FB: 32MB, Pipes: 3, Ports: 3, FBMem: 3 - ULT mobile GT3
{ 0x07,0x00,0x26,0x0d }, // 13 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 3, Ports: 4, FBMem: 3 - CRW mobile GT3
{ 0x07,0x00,0x26,0x0d },// 13 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 3, Ports: 4, FBMem: 3 - CRW mobile GT3
{ 0x08,0x00,0x26,0x0a },// 14 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 3, Ports: 3, FBMem: 3 - ULT mobile GT3
{ 0x08,0x00,0x2e,0x0a },// 15 "AAPL,ig-platform-id" //FB: 64MB, Pipes: 3, Ports: 3, FBMem: 3 - ULT reserved GT3
};
//devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
break;
/* Haswell */
/* HD Graphics 5000, HD Graphics 5000 Mobile, HD Graphics P5000, HD Graphics 4600, HD Graphics 4600 Mobile */
//case 0x80860090:
//case 0x80860091:
//case 0x80860092:
case GMA_HASWELL_M_GT2: // 0416
device_id = 0x0412;// Inject a valid desktop GPU device id (0x0412) instead of patching kexts
devprop_add_value(device, "vendor-id",(uint8_t *)INTEL_VENDORID, 4);
devprop_add_value(device, "device-id",(uint8_t *)&device_id, sizeof(device_id));
devprop_add_value(device, "compatible",(uint8_t *)"pci8086,0412", 13); // GT2 Desktop
case GMA_HASWELL_D_GT1: // 0402
case GMA_HASWELL_M_GT1: // 0406
case GMA_HASWELL_S_GT1: // 040a
case GMA_HASWELL_D_GT2: // 0412
case GMA_HASWELL_S_GT2: // 041a
case GMA_HASWELL_E_GT1: // 040e
/* Haswell */
/* HD Graphics 5000, HD Graphics 5000 Mobile, HD Graphics P5000, HD Graphics 4600, HD Graphics 4600 Mobile */
//case 0x80860090:
//case 0x80860091:
//case 0x80860092:
case GMA_HASWELL_M_GT2: // 0416
case GMA_HASWELL_E_GT2: // 041e
case GMA_HASWELL_E_GT3: // 042e
case GMA_HASWELL_D_GT3: // 0422
case GMA_HASWELL_M_GT3: // 0426
case GMA_HASWELL_S_GT3: // 042a
case GMA_HASWELL_ULT_M_GT1: // 0a06
case GMA_HASWELL_ULT_E_GT1: // 0a0e
case GMA_HASWELL_ULT_M_GT2: // 0a16
case GMA_HASWELL_ULT_E_GT2: // 0a1e
case GMA_HASWELL_ULT_D_GT3: // 0a22
case GMA_HASWELL_ULT_M_GT3: // 0a26
case GMA_HASWELL_ULT_S_GT3: // 0a2a
case GMA_HASWELL_ULT_E_GT3: // 0a2e
case GMA_HASWELL_SDV_D_GT1_IG: // 0c02
case GMA_HASWELL_SDV_M_GT1_IG: // 0c06
case GMA_HASWELL_SDV_D_GT2_IG: // 0c12
case GMA_HASWELL_SDV_M_GT2_IG: // 0c16
case GMA_HASWELL_SDV_D_GT2_PLUS_IG: // 0c22
case GMA_HASWELL_SDV_M_GT2_PLUS_IG: // 0c26
case GMA_HASWELL_CRW_D_GT1: // 0d02
case GMA_HASWELL_CRW_D_GT2: // 0d12
case GMA_HASWELL_CRW_D_GT3: // 0d22
case GMA_HASWELL_CRW_M_GT1: // 0d06
case GMA_HASWELL_CRW_M_GT2: // 0d16
case GMA_HASWELL_CRW_M_GT3: // 0d26
case GMA_HASWELL_CRW_S_GT1: // 0d0a
case GMA_HASWELL_CRW_S_GT2: // 0d1a
case GMA_HASWELL_CRW_S_GT3: // 0d2a
case GMA_HASWELL_CRW_B_GT1: // 0d0b
case GMA_HASWELL_CRW_B_GT2: // 0d1b
case GMA_HASWELL_CRW_B_GT3: // 0d2b
case GMA_HASWELL_CRW_E_GT1: // 0d0e
case GMA_HASWELL_CRW_E_GT2: // 0d1e
case GMA_HASWELL_CRW_E_GT3: // 0d2e
case GMA_HASWELL_CRW_M_GT2_PLUS_IG: // 0d36
verbose(" Inject a valid desktop GPU device id (0x0412) instead of patching kexts");
device_id = 0x0412;// Inject a valid desktop GPU device id (0x0412) instead of patching kexts
devprop_add_value(device, "vendor-id",(uint8_t *)INTEL_VENDORID, 4);
devprop_add_value(device, "device-id",(uint8_t *)&device_id, sizeof(device_id));
devprop_add_value(device, "compatible",(uint8_t *)"pci8086,0412", 13); // GT2 Desktop
if (getValueForKey(kAAPLCustomIG, &value, &len, &bootInfo->chameleonConfig) && len == AAPL_LEN_HSW * 2)
{
uint8_t new_aapl0[AAPL_LEN_HSW];
if (hex2bin(value, new_aapl0, AAPL_LEN_HSW) == 0)
{
memcpy(default_aapl_haswell, new_aapl0, AAPL_LEN_HSW);
verbose("Using user supplied AAPL,ig-platform-id\n");
verbose("AAPL,ig-platform-id: %02x%02x%02x%02x\n",
default_aapl_haswell[0], default_aapl_haswell[1], default_aapl_haswell[2], default_aapl_haswell[3]);
}
devprop_add_value(device, "AAPL,ig-platform-id", default_aapl_haswell, AAPL_LEN_HSW);
}
else if (getIntForKey(kIntelAzulFB, &n_igs, &bootInfo->chameleonConfig))
{
if ((n_igs >= 0) || (n_igs <= 15))
{
verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with value %d\n", n_igs);
devprop_add_value(device, "AAPL,ig-platform-id", haswell_ig_vals[n_igs], 4);
}
else
{
verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with bad value please choose a number between 0 and 15.\n");
}
}
else
{
uint32_t ig_platform_id = 0x0000260c; // set the default platform ig
devprop_add_value(device, "AAPL,ig-platform-id", (uint8_t *)&ig_platform_id, 4);
}
case GMA_HASWELL_D_GT1: // 0402
case GMA_HASWELL_M_GT1: // 0406
case GMA_HASWELL_S_GT1: // 040a
case GMA_HASWELL_D_GT2: // 0412
case GMA_HASWELL_S_GT2: // 041a
case GMA_HASWELL_E_GT1: // 040e
case GMA_HASWELL_E_GT3: // 042e
case GMA_HASWELL_D_GT3: // 0422
case GMA_HASWELL_M_GT3: // 0426
case GMA_HASWELL_S_GT3: // 042a
case GMA_HASWELL_ULT_M_GT1: // 0a06
case GMA_HASWELL_ULT_E_GT1: // 0a0e
case GMA_HASWELL_ULT_D_GT3: // 0a22
case GMA_HASWELL_ULT_M_GT3: // 0a26
case GMA_HASWELL_ULT_S_GT3: // 0a2a
case GMA_HASWELL_ULT_E_GT3: // 0a2e
case GMA_HASWELL_SDV_D_GT1_IG: // 0c02
case GMA_HASWELL_SDV_M_GT1_IG: // 0c06
case GMA_HASWELL_SDV_D_GT2_IG: // 0c12
case GMA_HASWELL_SDV_M_GT2_IG: // 0c16
case GMA_HASWELL_SDV_D_GT2_PLUS_IG: // 0c22
case GMA_HASWELL_SDV_M_GT2_PLUS_IG: // 0c26
case GMA_HASWELL_CRW_D_GT1: // 0d02
case GMA_HASWELL_CRW_D_GT2: // 0d12
case GMA_HASWELL_CRW_D_GT3: // 0d22
case GMA_HASWELL_CRW_M_GT1: // 0d06
case GMA_HASWELL_CRW_M_GT2: // 0d16
case GMA_HASWELL_CRW_M_GT3: // 0d26
case GMA_HASWELL_CRW_S_GT1: // 0d0a
case GMA_HASWELL_CRW_S_GT2: // 0d1a
case GMA_HASWELL_CRW_S_GT3: // 0d2a
case GMA_HASWELL_CRW_B_GT1: // 0d0b
case GMA_HASWELL_CRW_B_GT2: // 0d1b
case GMA_HASWELL_CRW_B_GT3: // 0d2b
case GMA_HASWELL_CRW_E_GT1: // 0d0e
case GMA_HASWELL_CRW_E_GT2: // 0d1e
case GMA_HASWELL_CRW_E_GT3: // 0d2e
case GMA_HASWELL_CRW_M_GT2_PLUS_IG: // 0d36
devprop_add_value(device, "AAPL00,DualLink", HD4000_vals[10], 4);
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
//devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
break;
if (getValueForKey(kAAPLCustomIG, &value, &len, &bootInfo->chameleonConfig) && len == AAPL_LEN_HSW * 2)
{
uint8_t new_aapl0[AAPL_LEN_HSW];
default:
break;
if (hex2bin(value, new_aapl0, AAPL_LEN_HSW) == 0)
{
memcpy(default_aapl_haswell, new_aapl0, AAPL_LEN_HSW);
verbose("Using user supplied AAPL,ig-platform-id\n");
verbose("AAPL,ig-platform-id: %02x%02x%02x%02x\n",
default_aapl_haswell[0], default_aapl_haswell[1], default_aapl_haswell[2], default_aapl_haswell[3]);
}
devprop_add_value(device, "AAPL,ig-platform-id", default_aapl_haswell, AAPL_LEN_HSW);
}
else if (getIntForKey(kIntelAzulFB, &n_igs, &bootInfo->chameleonConfig))
{
if ((n_igs >= 0) || (n_igs <= 15))
{
verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with value %d\n", n_igs);
devprop_add_value(device, "AAPL,ig-platform-id", haswell_ig_vals[n_igs], 4);
}
else
{
verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with bad value please choose a number between 0 and 15.\n");
}
}
else
{
uint32_t ig_platform_id = 0x0000260c; // set the default platform ig
devprop_add_value(device, "AAPL,ig-platform-id", (uint8_t *)&ig_platform_id, 4);
}
devprop_add_value(device, "AAPL00,DualLink", HD4000_vals[10], 4);
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
//devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
break;
default:
break;
}
stringdata = malloc(sizeof(uint8_t) * string->length);
branches/ErmaC/Enoch/i386/libsaio/cpu.c
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*/
void scan_cpu(PlatformInfo_t *p)
{
uint64_ttscFrequency = 0;
uint64_tfsbFrequency = 0;
uint64_tcpuFrequency = 0;
uint64_tmsr = 0;
uint64_tflex_ratio = 0;
uint64_ttscFrequency= 0;
uint64_tfsbFrequency= 0;
uint64_tcpuFrequency= 0;
uint64_tmsr= 0;
uint64_tflex_ratio= 0;
uint32_tmax_ratio = 0;
uint32_tmin_ratio = 0;
uint8_tbus_ratio_max = 0;
uint8_tbus_ratio_min = 0;
uint8_tcurrdiv = 0;
uint8_tcurrcoef = 0;
uint8_tmaxdiv = 0;
uint8_tmaxcoef = 0;
uint32_tmax_ratio= 0;
uint32_tmin_ratio= 0;
uint8_tbus_ratio_max= 0;
uint8_tbus_ratio_min= 0;
uint8_tcurrdiv= 0;
uint8_tcurrcoef= 0;
uint8_tmaxdiv= 0;
uint8_tmaxcoef= 0;
const char*newratio;
intlen = 0;
intmyfsb = 0;
p->CPU.MCodeVersion= (uint32_t)(rdmsr64(MSR_IA32_BIOS_SIGN_ID) >> 32);
p->CPU.Vendor= p->CPU.CPUID[CPUID_0][1];
p->CPU.Signature= p->CPU.CPUID[CPUID_1][0];
p->CPU.Stepping= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0); // stepping = cpu_feat_eax & 0xF;
p->CPU.Model= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4); // model = (cpu_feat_eax >> 4) & 0xF;
p->CPU.Family= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8); // family = (cpu_feat_eax >> 8) & 0xF;
//p->CPU.Type= bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);// type = (cpu_feat_eax >> 12) & 0x3;
p->CPU.ExtModel= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16); // ext_model = (cpu_feat_eax >> 16) & 0xF;
p->CPU.ExtFamily= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);// ext_family = (cpu_feat_eax >> 20) & 0xFF;
p->CPU.Stepping= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);// stepping = cpu_feat_eax & 0xF;
p->CPU.Model= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);// model = (cpu_feat_eax >> 4) & 0xF;
p->CPU.Family= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);// family = (cpu_feat_eax >> 8) & 0xF;
//p->CPU.Type= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);// type = (cpu_feat_eax >> 12) & 0x3;
p->CPU.ExtModel= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);// ext_model = (cpu_feat_eax >> 16) & 0xF;
p->CPU.ExtFamily= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);// ext_family = (cpu_feat_eax >> 20) & 0xFF;
p->CPU.Model += (p->CPU.ExtModel << 4);
}
else if (p->CPU.Vendor == CPUID_VENDOR_AMD)
{
p->CPU.NoThreads= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);
p->CPU.NoCores= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;
p->CPU.NoThreads= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);
p->CPU.NoCores= (uint8_t)bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;
}
else
{
// Use previous method for Cores and Threads
p->CPU.NoThreads= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);
p->CPU.NoCores= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;
p->CPU.NoThreads= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);
p->CPU.NoCores= (uint8_t)bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;
}
/* get BrandString (if supported) */
}
}
if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1)))
if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))
{
/*
* This string means we have a firmware-programmable brand string,
break;
}
}
/* Mobile CPU */
// Mobile CPU
if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))
{
p->CPU.Features |= CPU_FEATURE_MOBILE;
{
switch(p->CPU.ExtFamily)
{
case 0x00: /* K8 */
case 0x00: //* K8 *//
msr = rdmsr64(K8_FIDVID_STATUS);
maxcoef = bitfield(msr, 21, 16) / 2 + 4;
currcoef = bitfield(msr, 5, 0) / 2 + 4;
break;
case 0x01: /* K10 */
case 0x01: //* K10 *//
msr = rdmsr64(K10_COFVID_STATUS);
do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);
// EffFreq: effective frequency interface
break;
case 0x05: /* K14 */
case 0x05: //* K14 *//
msr = rdmsr64(K10_COFVID_STATUS);
currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;
currdiv = (bitfield(msr, 8, 4) + 1) << 2;
break;
case 0x02: /* K11 */
case 0x02: //* K11 *//
// not implimented
break;
}
DBG("\n---------------------------------------------\n");
DBG("------------------ CPU INFO -----------------\n");
DBG("---------------------------------------------\n");
DBG("Brand String: %s\n",p->CPU.BrandString); // Processor name (BIOS)
DBG("Vendor: 0x%x\n",p->CPU.Vendor); // Vendor ex: GenuineIntel
DBG("Family: 0x%x\n",p->CPU.Family); // Family ex: 6 (06h)
DBG("Brand String: %s\n",p->CPU.BrandString);// Processor name (BIOS)
DBG("Vendor: 0x%x\n",p->CPU.Vendor);// Vendor ex: GenuineIntel
DBG("Family: 0x%x\n",p->CPU.Family);// Family ex: 6 (06h)
DBG("ExtFamily: 0x%x\n",p->CPU.ExtFamily);
DBG("Signature: %x\n",p->CPU.Signature); // CPUID signature
DBG("Signature: %x\n",p->CPU.Signature);// CPUID signature
/*switch (p->CPU.Type) {
case PT_OEM:
DBG("Processor type: Intel Original OEM Processor\n");
default:
break;
}*/
DBG("Model: 0x%x\n",p->CPU.Model); // Model ex: 37 (025h)
DBG("Model: 0x%x\n",p->CPU.Model);// Model ex: 37 (025h)
DBG("ExtModel: 0x%x\n",p->CPU.ExtModel);
DBG("Stepping: 0x%x\n",p->CPU.Stepping); // Stepping ex: 5 (05h)
DBG("Stepping: 0x%x\n",p->CPU.Stepping);// Stepping ex: 5 (05h)
DBG("MaxCoef: 0x%x\n",p->CPU.MaxCoef);
DBG("CurrCoef: 0x%x\n",p->CPU.CurrCoef);
DBG("MaxDiv: 0x%x\n",p->CPU.MaxDiv);
DBG("TSCFreq: %dMHz\n",p->CPU.TSCFrequency / 1000000);
DBG("FSBFreq: %dMHz\n",(p->CPU.FSBFrequency + 500000) / 1000000);
DBG("CPUFreq: %dMHz\n",p->CPU.CPUFrequency / 1000000);
DBG("Cores: %d\n",p->CPU.NoCores); // Cores
DBG("Logical processor: %d\n",p->CPU.NoThreads); // Logical procesor
DBG("Cores: %d\n",p->CPU.NoCores);// Cores
DBG("Logical processor: %d\n",p->CPU.NoThreads);// Logical procesor
DBG("Features: 0x%08x\n",p->CPU.Features);
DBG("Microcode version: %d\n",p->CPU.MCodeVersion); // CPU microcode version
DBG("Microcode version: %d\n",p->CPU.MCodeVersion);// CPU microcode version
DBG("\n---------------------------------------------\n");
#if DEBUG_CPU
pause();
branches/ErmaC/Enoch/i386/libsaio/platform.h
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extern void scan_platform(void);
extern void dumpPhysAddr(const char * title, void * a, int len);
/* CPUID Vendor */
#define CPUID_VENDOR_INTEL 0x756E6547
#define CPUID_VENDOR_AMD 0x68747541
/* CPUID index into cpuid_raw */
#define CPUID_00
#define CPUID_11
//#define CPUID_MODEL_0x5A// Silvermont, Future Atom E3000, Z3000
//#define CPUID_MODEL_0x5D// Silvermont, Future Atom E3000, Z3000
/* CPUID Vendor */
#defineCPUID_VID_INTEL"GenuineIntel"
#defineCPUID_VID_AMD"AuthenticAMD"
#define CPUID_VENDOR_INTEL0x756E6547
#define CPUID_VENDOR_AMD0x68747541
/* Unknown CPU */
#define CPU_STRING_UNKNOWN"Unknown CPU Type"
#define bit(n)(1ULL << (n))
#define bitmask(h,l)((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
#define bitfield(x,h,l)(((x) & bitmask(h,l)) >> l)
#define CPU_STRING_UNKNOWN"Unknown CPU Type"
//definitions from Apple XNU
/* CPU defines */
#define bit(n)(1ULL << (n))
#define bitmask(h,l)((bit(h) | (bit(h)-1)) & ~(bit(l)-1))
#define bitfield(x,h,l)(((x) & bitmask(h,l)) >> l)
#define hbit(n)(1ULL << ((n)+32))
#define min(a,b)((a) < (b) ? (a) : (b))
#define quad32(hi,lo)((((uint32_t)(hi)) << 16) | (((uint32_t)(lo)) & 0xFFFF))
#define quad64(hi,lo)((((uint64_t)(hi)) << 32) | (((uint64_t)(lo)) & 0xFFFFFFFFUL))
/*
* The CPUID_FEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 1:
*/
#define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */
#define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */
#define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */
#define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */
#define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */
#define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */
#define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */
#define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */
#define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */
#define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */
#define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */
#define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */
#define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */
#define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */
#define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */
#define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */
#define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */
#define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */
#define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */
#define CPUID_FEATURE_DS _Bit(21) /* Debug Store */
#define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */
#define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */
#define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */
#define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */
#define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */
#define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */
#define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */
#define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */
#define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */
#define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */
#define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ instruction */
#define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */
#define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */
#define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */
#define CPUID_FEATURE_VMX _HBit(5) /* VMX */
#define CPUID_FEATURE_SMX _HBit(6) /* SMX */
#define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */
#define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */
#define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */
#define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */
#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */
#define CPUID_FEATURE_FMA _HBit(12) /* Fused-Multiply-Add support */
#define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */
#define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */
#define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */
#define CPUID_FEATURE_FPUbit(0) /* Floating point unit on-chip */
#define CPUID_FEATURE_VMEbit(1) /* Virtual Mode Extension */
#define CPUID_FEATURE_DEbit(2) /* Debugging Extension */
#define CPUID_FEATURE_PSEbit(3) /* Page Size Extension */
#define CPUID_FEATURE_TSCbit(4) /* Time Stamp Counter */
#define CPUID_FEATURE_MSRbit(5) /* Model Specific Registers */
#define CPUID_FEATURE_PAEbit(6) /* Physical Address Extension */
#define CPUID_FEATURE_MCEbit(7) /* Machine Check Exception */
#define CPUID_FEATURE_CX8bit(8) /* CMPXCHG8B */
#define CPUID_FEATURE_APICbit(9) /* On-chip APIC */
#define CPUID_FEATURE_SEPbit(11) /* Fast System Call */
#define CPUID_FEATURE_MTRRbit(12) /* Memory Type Range Register */
#define CPUID_FEATURE_PGEbit(13) /* Page Global Enable */
#define CPUID_FEATURE_MCAbit(14) /* Machine Check Architecture */
#define CPUID_FEATURE_CMOVbit(15) /* Conditional Move Instruction */
#define CPUID_FEATURE_PATbit(16) /* Page Attribute Table */
#define CPUID_FEATURE_PSE36bit(17) /* 36-bit Page Size Extension */
#define CPUID_FEATURE_PSNbit(18) /* Processor Serial Number */
#define CPUID_FEATURE_CLFSHbit(19) /* CLFLUSH Instruction supported */
#define CPUID_FEATURE_DSbit(21) /* Debug Store */
#define CPUID_FEATURE_ACPIbit(22) /* Thermal monitor and Clock Ctrl */
#define CPUID_FEATURE_MMXbit(23) /* MMX supported */
#define CPUID_FEATURE_FXSRbit(24) /* Fast floating pt save/restore */
#define CPUID_FEATURE_SSEbit(25) /* Streaming SIMD extensions */
#define CPUID_FEATURE_SSE2bit(26) /* Streaming SIMD extensions 2 */
#define CPUID_FEATURE_SSbit(27) /* Self-Snoop */
#define CPUID_FEATURE_HTTbit(28) /* Hyper-Threading Technology */
#define CPUID_FEATURE_TMbit(29) /* Thermal Monitor (TM1) */
#define CPUID_FEATURE_PBEbit(31) /* Pend Break Enable */
#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */
#define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */
#define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */
#define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */
#define CPUID_FEATURE_x2APIC _HBit(21) /* Extended APIC Mode */
#define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */
#define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */
#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */
#define CPUID_FEATURE_AES _HBit(25) /* AES instructions */
#define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */
#define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */
#define CPUID_FEATURE_AVX1_0_HBit(28) /* AVX 1.0 instructions */
#define CPUID_FEATURE_F16C_HBit(29) /* Float16 convert instructions */
#define CPUID_FEATURE_RDRAND_HBit(30) /* RDRAND instruction */
#define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */
#define CPUID_FEATURE_SSE3hbit(0) /* Streaming SIMD extensions 3 */
#define CPUID_FEATURE_PCLMULQDQhbit(1) /* PCLMULQDQ Instruction */
#define CPUID_FEATURE_DTES64hbit(2) /* 64-bit DS layout */
#define CPUID_FEATURE_MONITORhbit(3) /* Monitor/mwait */
#define CPUID_FEATURE_DSCPLhbit(4) /* Debug Store CPL */
#define CPUID_FEATURE_VMXhbit(5) /* VMX */
#define CPUID_FEATURE_SMXhbit(6) /* SMX */
#define CPUID_FEATURE_ESThbit(7) /* Enhanced SpeedsTep (GV3) */
#define CPUID_FEATURE_TM2hbit(8) /* Thermal Monitor 2 */
#define CPUID_FEATURE_SSSE3hbit(9) /* Supplemental SSE3 instructions */
#define CPUID_FEATURE_CIDhbit(10) /* L1 Context ID */
#define CPUID_FEATURE_SEGLIM64hbit(11) /* 64-bit segment limit checking */
#define CPUID_FEATURE_FMAhbit(12) /* Fused-Multiply-Add support */
#define CPUID_FEATURE_CX16hbit(13) /* CmpXchg16b instruction */
#define CPUID_FEATURE_xTPRhbit(14) /* Send Task PRiority msgs */
#define CPUID_FEATURE_PDCMhbit(15) /* Perf/Debug Capability MSR */
#define CPUID_FEATURE_PCIDhbit(17) /* ASID-PCID support */
#define CPUID_FEATURE_DCAhbit(18) /* Direct Cache Access */
#define CPUID_FEATURE_SSE4_1hbit(19) /* Streaming SIMD extensions 4.1 */
#define CPUID_FEATURE_SSE4_2hbit(20) /* Streaming SIMD extensions 4.2 */
#define CPUID_FEATURE_x2APIChbit(21) /* Extended APIC Mode */
#define CPUID_FEATURE_MOVBEhbit(22) /* MOVBE instruction */
#define CPUID_FEATURE_POPCNThbit(23) /* POPCNT instruction */
#define CPUID_FEATURE_TSCTMRhbit(24) /* TSC deadline timer */
#define CPUID_FEATURE_AEShbit(25) /* AES instructions */
#define CPUID_FEATURE_XSAVEhbit(26) /* XSAVE instructions */
#define CPUID_FEATURE_OSXSAVEhbit(27) /* XGETBV/XSETBV instructions */
#define CPUID_FEATURE_AVX1_0hbit(28) /* AVX 1.0 instructions */
#define CPUID_FEATURE_F16Chbit(29) /* Float16 convert instructions */
#define CPUID_FEATURE_RDRANDhbit(30) /* RDRAND instruction */
#define CPUID_FEATURE_VMMhbit(31) /* VMM (Hypervisor) present */
/*
* Leaf 7, subleaf 0 additional features.
* Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
*/
#define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)/* FS/GS base read/write */
#define CPUID_LEAF7_FEATURE_TSCOFF _Bit(1)/* TSC thread offset */
#define CPUID_LEAF7_FEATURE_BMI1 _Bit(3)/* Bit Manipulation Instrs, set 1 */
#define CPUID_LEAF7_FEATURE_HLE _Bit(4)/* Hardware Lock Elision*/
#define CPUID_LEAF7_FEATURE_AVX2 _Bit(5)/* AVX2 Instructions */
#define CPUID_LEAF7_FEATURE_SMEP _Bit(7)/* Supervisor Mode Execute Protect */
#define CPUID_LEAF7_FEATURE_BMI2 _Bit(8)/* Bit Manipulation Instrs, set 2 */
#define CPUID_LEAF7_FEATURE_ENFSTRG _Bit(9)/* ENhanced Fast STRinG copy */
#define CPUID_LEAF7_FEATURE_INVPCID _Bit(10)/* INVPCID intruction, TDB */
#define CPUID_LEAF7_FEATURE_RTM _Bit(11)/* TBD */
#define CPUID_LEAF7_FEATURE_RDWRFSGSbit(0)/* FS/GS base read/write */
#define CPUID_LEAF7_FEATURE_TSCOFFbit(1)/* TSC thread offset */
#define CPUID_LEAF7_FEATURE_BMI1bit(3)/* Bit Manipulation Instrs, set 1 */
#define CPUID_LEAF7_FEATURE_HLEbit(4)/* Hardware Lock Elision*/
#define CPUID_LEAF7_FEATURE_AVX2bit(5)/* AVX2 Instructions */
#define CPUID_LEAF7_FEATURE_SMEPbit(7)/* Supervisor Mode Execute Protect */
#define CPUID_LEAF7_FEATURE_BMI2bit(8)/* Bit Manipulation Instrs, set 2 */
#define CPUID_LEAF7_FEATURE_ENFSTRGbit(9)/* ENhanced Fast STRinG copy */
#define CPUID_LEAF7_FEATURE_INVPCIDbit(10)/* INVPCID intruction, TDB */
#define CPUID_LEAF7_FEATURE_RTMbit(11)/* TBD */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
*/
#define CPUID_EXTFEATURE_SYSCALL _Bit(11)/* SYSCALL/sysret */
#define CPUID_EXTFEATURE_XD _Bit(20)/* eXecute Disable */
#define CPUID_EXTFEATURE_SYSCALLbit(11)/* SYSCALL/sysret */
#define CPUID_EXTFEATURE_XDbit(20)/* eXecute Disable */
#define CPUID_EXTFEATURE_1GBPAGE _Bit(26)/* 1GB pages */
#define CPUID_EXTFEATURE_RDTSCP _Bit(27)/* RDTSCP */
#define CPUID_EXTFEATURE_EM64T _Bit(29)/* Extended Mem 64 Technology */
#define CPUID_EXTFEATURE_1GBPAGEbit(26)/* 1GB pages support */
#define CPUID_EXTFEATURE_RDTSCPbit(27)/* RDTSCP */
#define CPUID_EXTFEATURE_EM64Tbit(29)/* Extended Mem 64 Technology */
#define CPUID_EXTFEATURE_LAHF _HBit(0)/* LAFH/SAHF instructions */
#define CPUID_EXTFEATURE_LAHFhbit(0)/* LAFH/SAHF instructions */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
*/
#define CPUID_EXTFEATURE_TSCI _Bit(8)/* TSC Invariant */
#define CPUID_EXTFEATURE_TSCIbit(8)/* TSC Invariant */
#defineCPUID_CACHE_SIZE16/* Number of descriptor values */
#defineCPUID_CACHE_SIZE16/* Number of descriptor values */
#define CPUID_MWAIT_EXTENSION_Bit(0)/* enumeration of WMAIT extensions */
#define CPUID_MWAIT_BREAK_Bit(1)/* interrupts are break events */
#define CPUID_MWAIT_EXTENSIONbit(0)/* enumeration of WMAIT extensions */
#define CPUID_MWAIT_BREAKbit(1)/* interrupts are break events */
//-- processor type -> p_type:
#define PT_OEM0x00// Intel Original OEM Processor;
#define PT_OD0x01 // Intel Over Drive Processor;
#define PT_DUAL0x02// Intel Dual Processor;
#define PT_RES0x03// Intel Reserved;
#define PT_OEM0x00// Intel Original OEM Processor;
#define PT_OD0x01 // Intel Over Drive Processor;
#define PT_DUAL0x02// Intel Dual Processor;
#define PT_RES0x03// Intel Reserved;
/* Known MSR registers */
#define MSR_IA32_PLATFORM_ID 0x0017
#define MSR_CORE_THREAD_COUNT 0x0035/* limited use - not for Penryn or older */
#define IA32_TSC_ADJUST 0x003B
#define MSR_IA32_BIOS_SIGN_ID 0x008B/* microcode version */
#define MSR_FSB_FREQ 0x00CD/* limited use - not for i7 */
#defineMSR_PLATFORM_INFO 0x00CE/* limited use - MinRatio for i7 but Max for Yonah*/
#define MSR_IA32_PLATFORM_ID0x0017
#define IA32_APIC_BASE0x001B /* used also for AMD */
#define MSR_CORE_THREAD_COUNT0x0035/* limited use - not for Penryn or older */
#define IA32_TSC_ADJUST0x003B
#define MSR_IA32_BIOS_SIGN_ID0x008B/* microcode version */
#define MSR_FSB_FREQ0x00CD/* limited use - not for i7 */
#defineMSR_PLATFORM_INFO0x00CE/* limited use - MinRatio for i7 but Max for Yonah*/
/* turbo for penryn */
#define MSR_PKG_CST_CONFIG_CONTROL 0x00E2/* sandy and ivy */
#define MSR_PMG_IO_CAPTURE_BASE 0x00E4
#define IA32_MPERF 0x00E7/* TSC in C0 only */
#define IA32_APERF 0x00E8/* actual clocks in C0 */
#define MSR_IA32_EXT_CONFIG 0x00EE/* limited use - not for i7 */
#define MSR_FLEX_RATIO 0x0194/* limited use - not for Penryn or older */
#define MSR_PKG_CST_CONFIG_CONTROL0x00E2// sandy and ivy
#define MSR_PMG_IO_CAPTURE_BASE0x00E4
#define IA32_MPERF0x00E7// TSC in C0 only
#define IA32_APERF0x00E8// actual clocks in C0
#define MSR_IA32_EXT_CONFIG0x00EE// limited use - not for i7
#define MSR_FLEX_RATIO0x0194// limited use - not for Penryn or older
//see no value on most CPUs
#defineMSR_IA32_PERF_STATUS 0x0198
#define MSR_IA32_PERF_CONTROL 0x0199
#define MSR_IA32_CLOCK_MODULATION 0x019A
#define MSR_THERMAL_STATUS 0x019C
#define MSR_IA32_MISC_ENABLE 0x01A0
#define MSR_THERMAL_TARGET 0x01A2 /* TjMax limited use - not for Penryn or older*/
#define MSR_MISC_PWR_MGMT 0x01AA
#define MSR_TURBO_RATIO_LIMIT 0x01AD /* limited use - not for Penryn or older */
#defineMSR_IA32_PERF_STATUS0x0198
#define MSR_IA32_PERF_CONTROL0x0199
#define MSR_IA32_CLOCK_MODULATION0x019A
#define MSR_THERMAL_STATUS0x019C
#define MSR_IA32_MISC_ENABLE0x01A0
#define MSR_THERMAL_TARGET0x01A2// TjMax limited use - not for Penryn or older
#define MSR_MISC_PWR_MGMT0x01AA
#define MSR_TURBO_RATIO_LIMIT0x01AD// limited use - not for Penryn or older
#define IA32_ENERGY_PERF_BIAS0x01B0
#define MSR_PACKAGE_THERM_STATUS0x01B1
#define IA32_PLATFORM_DCA_CAP0x01F8
#define MSR_POWER_CTL0x01FC // MSR 000001FC 0000-0000-0004-005F
#define MSR_POWER_CTL0x01FC// MSR 000001FC 0000-0000-0004-005F
// Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.
#define MSR_RAPL_POWER_UNIT0x606 /* R/O */
#define MSR_RAPL_POWER_UNIT0x606// R/O
//MSR 00000606 0000-0000-000A-1003
#define MSR_PKGC3_IRTL 0x60A /* RW time limit to go C3 */
#define MSR_PKGC3_IRTL0x60A// RW time limit to go C3
// bit 15 = 1 -- the value valid for C-state PM
#define MSR_PKGC6_IRTL 0x60B /* RW time limit to go C6 */
#define MSR_PKGC6_IRTL0x60B// RW time limit to go C6
//MSR 0000060B 0000-0000-0000-8854
//Valid + 010=1024ns + 0x54=84mks
#define MSR_PKGC7_IRTL 0x60C /* RW time limit to go C7 */
#define MSR_PKGC7_IRTL0x60C// RW time limit to go C7
//MSR 0000060C 0000-0000-0000-8854
#define MSR_PKG_C2_RESIDENCY 0x60D /* same as TSC but in C2 only */
#define MSR_PKG_C2_RESIDENCY0x60D// same as TSC but in C2 only
#define MSR_PKG_RAPL_POWER_LIMIT0x610 //MSR 00000610 0000-A580-0000-8960
#define MSR_PKG_ENERGY_STATUS0x611 //MSR 00000611 0000-0000-3212-A857
#define MSR_PKG_POWER_INFO0x614 //MSR 00000614 0000-0000-01E0-02F8
#define MSR_PKG_RAPL_POWER_LIMIT0x610//MSR 00000610 0000-A580-0000-8960
#define MSR_PKG_ENERGY_STATUS0x611//MSR 00000611 0000-0000-3212-A857
#define MSR_PKG_POWER_INFO0x614//MSR 00000614 0000-0000-01E0-02F8
// Sandy Bridge IA (Core) domain MSR's.
#define MSR_PP0_POWER_LIMIT0x638
#define MSR_PP0_ENERGY_STATUS0x639
#define MSR_PP0_POLICY0x63A
#define MSR_PP0_PERF_STATUS0x63B
// Sandy Bridge Uncore (IGPU) domain MSR's (Not on JakeTown).
#define MSR_PP1_POWER_LIMIT0x640
#define MSR_PP1_ENERGY_STATUS 0x641
//MSR 00000641 0000-0000-0000-0000
#define MSR_PP1_POLICY0x642
// JakeTown only Memory MSR's.
#define MSR_PKG_PERF_STATUS0x613
#define MSR_DRAM_POWER_LIMIT 0x618
#define MSR_DRAM_ENERGY_STATUS0x619
#define MSR_DRAM_PERF_STATUS0x61B
#define MSR_DRAM_POWER_INFO0x61C
//IVY_BRIDGE
#define MSR_CONFIG_TDP_NOMINAL0x648
#define MSR_CONFIG_TDP_LEVEL10x649
#define MSR_CONFIG_TDP_LEVEL20x64A
#define MSR_CONFIG_TDP_CONTROL0x64B// write once to lock
#define MSR_TURBO_ACTIVATION_RATIO0x64C
//AMD
#define K8_FIDVID_STATUS 0xC0010042
#define K10_COFVID_LIMIT 0xC0010061
#define K10_PSTATE_STATUS 0xC0010064
#define K10_COFVID_STATUS 0xC0010071
#define K8_FIDVID_STATUS0xC0010042
#define K10_COFVID_LIMIT0xC0010061// max enabled p-state (msr >> 4) & 7
#define K10_COFVID_CONTROL0xC0010062// switch to p-state
#define K10_PSTATE_STATUS0xC0010064
#define K10_COFVID_STATUS0xC0010071// current p-state (msr >> 16) & 7
#define MSR_AMD_MPERF 0x000000E7
#define MSR_AMD_APERF 0x000000E8
#define MSR_AMD_MPERF0x000000E7
#define MSR_AMD_APERF0x000000E8
#define DEFAULT_FSB100000 /* for now, hardcoding 100MHz for old CPUs */
#define DEFAULT_FSB100000 /* for now, hardcoding 100MHz for old CPUs */
// DFE: This constant comes from older xnu:
#define CLKNUM1193182/* formerly 1193167 */
#define CLKNUM1193182/* formerly 1193167 */
/* CPU Features */
#define CPU_FEATURE_MMX0x00000001// MMX Instruction Set
#define CPU_FEATURE_MSR0x00000200// MSR Support
/* SMBIOS Memory Types */
#define SMB_MEM_TYPE_UNDEFINED0
#define SMB_MEM_TYPE_UNDEFINED0
#define SMB_MEM_TYPE_OTHER1
#define SMB_MEM_TYPE_UNKNOWN2
#define SMB_MEM_TYPE_UNKNOWN2
#define SMB_MEM_TYPE_DRAM3
#define SMB_MEM_TYPE_EDRAM4
#define SMB_MEM_TYPE_VRAM5
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if (bvr->flags & kBVFlagBooter)
{
sprintf(dirSpec, "hd(%d,%d)/System/Library/CoreServices/", BIOS_DEV_UNIT(bvr), bvr->part_no);
sprintf(fileSpec, "%s", ".disk_label.contentDetails");
strcpy(fileSpec, ".disk_label.contentDetails");
ret = GetFileInfo(dirSpec, fileSpec, &flags, &time);
if (!ret)
{
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while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; }
}
/* From Apple's cpuid.h */
typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
static inline void cpuid(uint32_t *data)
{
asm(
"cpuid" : "=a" (data[eax]),
"=b" (data[ebx]),
"=c" (data[ecx]),
"=d" (data[edx]) : "a" (data[eax]),
"b" (data[ebx]),
"c" (data[ecx]),
"d" (data[edx]));
}
static inline void do_cpuid(uint32_t selector, uint32_t *data)
{
asm volatile ("cpuid"
: "=a" (data[0]),
"=b" (data[1]),
"=c" (data[2]),
"=d" (data[3])
: "a" (selector));
asm(
"cpuid" : "=a" (data[eax]),
"=b" (data[ebx]),
"=c" (data[ecx]),
"=d" (data[edx]) : "a"(selector),
"b" (0),
"c" (0),
"d" (0));
}
static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data)
{
asm volatile ("cpuid"
: "=a" (data[0]),
"=b" (data[1]),
"=c" (data[2]),
"=d" (data[3])
: "a" (selector), "c" (selector2));
asm volatile (
"cpuid" : "=a" (data[eax]),
"=b" (data[ebx]),
"=c" (data[ecx]),
"=d" (data[edx]) : "a" (selector),
"b" (0),
"c" (selector2),
"d" (0));
}
// DFE: enable_PIT2 and disable_PIT2 come from older xnu
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char *dirspec[] = {
"/Mac OS X Install Data/com.apple.Boot.plist",// OS X Installer (Lion 10.7)
"/OS X Install Data/com.apple.Boot.plist",// OS X Installer (10.8+)
"/.IABootFiles/com.apple.Boot.plist",// OS X Installer
//"/.IABootFiles/com.apple.Boot.plist",// OS X Installer
"/Library/Preferences/SystemConfiguration/com.apple.Boot.plist",// com.apple.Boot.plist
"/com.apple.recovery.boot/com.apple.Boot.plist"// OS X Recovery
};
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/* Option ROM header */
typedef struct {
uint16_tsignature; // 0xAA55
uint8_trom_size; //in 512 bytes blocks
uint8_tjump; //0xE9 for ATI and Intel, 0xEB for NVidia
uint32_tentry_point;
uint8_treserved[16];
uint16_tpci_header_offset; //@0x18
uint16_texpansion_header_offset;
uint16_tsignature;// 0xAA55
uint8_trom_size;//in 512 bytes blocks
uint8_tjump;//0xE9 for ATI and Intel, 0xEB for NVidia
uint32_tentry_point;
uint8_treserved[16];
uint16_tpci_header_offset;//@0x18
uint16_texpansion_header_offset;
} option_rom_header_t;
/* Option ROM PCI Data Structure */
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extern bool gVerboseMode;
extern bool gErrors;
extern void initBooterLog(void);
extern void msglog(const char * format, ...);
extern int msglog(const char * format, ...);
extern void setupBooterLog(void);
extern int putchar(int ch);
extern int getchar(void);
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#define kUseIntelHDMI"UseIntelHDMI"/* ati.c && nvidia.c && gma.c */
/* Signal64: added this key */
#define kLegacyOff"USBLegacyOff"/* usb.c */
#define kLegacyOff"USBLegacyOff"/* usb.c */
/* Lebidou: added this key */
/* cparm: added these keys */
//#define kRebootOnPanic"RebootOnPanic"
//#define kEnableHiDPI"EnableHiDPI"/* enable High resolution display (aka Retina) */
//#define kEnableHiDPI"EnableHiDPI"/* enable High resolution display (aka Retina) */
/* ErmaC: added these keys */
#define kEnableDualLink"EnableDualLink"/* ati.c && nvidia.c && gma.c*/
#define kNvidiaGeneric"NvidiaGeneric"/* nvidia.c */
#define kEnableDualLink"EnableDualLink"/* ati.c && nvidia.c && gma.c*/
#define kNvidiaGeneric"NvidiaGeneric"/* nvidia.c */
#define kSkipIntelGfx"SkipIntelGfx"/* pci_setup.c */
#define kSkipNvidiaGfx"SkipNvidiaGfx"/* pci_setup.c */
#define kSkipAtiGfx"SkipAtiGfx"/* pci_setup.c */
#define kSkipNvidiaGfx"SkipNvidiaGfx"/* pci_setup.c */
#define kSkipAtiGfx"SkipAtiGfx"/* pci_setup.c */
//#define kUsbInject"USBInject"/* usb.c */
#define kIntelCapriFB"IntelCapriFB"/* gma.c was HD4K-ig */
#define kIntelAzulFB"IntelAzulFB"/* gma.c was HD5K-ig */
#define kAAPLCustomIG"InjectIntel-ig"/* gma.c */
#define kHDAEnabler"HDAEnabler"/* pci_setup.c */
#define kHDEFLayoutID"HDEFLayoutID"/* hda.c */
#define kHDAULayoutID"HDAULayoutID"/* hda.c */
#define kBGRT"BGRT"/* acpi_patcher.c */
#define kDropBGRT"DropBGRT"/* acpi_patcher.c */
#define kDropMCFG"DropMCFG"/* acpi_patcher.c */
#define kDropAPIC"DropAPIC"/* acpi_patcher.c */
#define kIntelCapriFB"IntelCapriFB"/* gma.c was HD4K-ig */
#define kIntelAzulFB"IntelAzulFB"/* gma.c was HD5K-ig */
#define kAAPLCustomIG"InjectIntel-ig"/* gma.c */
#define kHDAEnabler"HDAEnabler"/* pci_setup.c */
#define kHDEFLayoutID"HDEFLayoutID"/* hda.c */
#define kHDAULayoutID"HDAULayoutID"/* hda.c */
#define kBGRT"BGRT"/* acpi_patcher.c */
#define kDropBGRT"DropBGRT"/* acpi_patcher.c */
#define kDropMCFG"DropMCFG"/* acpi_patcher.c */
#define kDropAPIC"DropAPIC"/* acpi_patcher.c */
/* Karas: added these keys */
#define kMemFullInfo"ForceFullMemInfo"/* smbios.c */
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- Bungo : Added getRTCdatetime() Int 1Ah function 02h - RTC service
- Zenith432 : Use caching with ExFat filesystem
- Zenith432 : Add turning off USB legacy for XHCI (XHCILegacyOff)
- Bungo : Added Logging start time.
- Bungo : Added getRTCdatetime() Int 1Ah function 02h - RTC service.
- Zenith432 : Use caching with ExFat filesystem.
- Zenith432 : Add turning off USB legacy for XHCI (XHCILegacyOff).
- Zenith432 : saio_types.h, biosfn.c - minor typo in bios-defined data structure that isn't actually used.
fake_efi.c - eliminate redundant scan of bt(0,0) in setupSmbiosConfigFile. loadConfigFile already does a fall-back scan of bt(0,0), so another scan isn't needed.
sys.c - While scanning a volume, getOSVersion looks for 5 files and switches back-n-forth between hd(X,Y)/....SystemVersion.plist on the newly scanned volume and bt(0,0)/hd(X,Y)/...SystemVersion.plist - which is an invalid path - should always return an error.

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Revision: 2549