| extern void scan_platform(void);␊ |
| extern void dumpPhysAddr(const char * title, void * a, int len);␊ |
| ␊ |
| /* CPUID Vendor */␊ |
| #define CPUID_VENDOR_INTEL 0x756E6547␊ |
| #define CPUID_VENDOR_AMD 0x68747541␊ |
| ␊ |
| /* CPUID index into cpuid_raw */␊ |
| #define CPUID_0␉␉␉␉0␊ |
| #define CPUID_1␉␉␉␉1␊ |
|
| //#define CPUID_MODEL_␉␉␉0x5A␉␉␉// Silvermont, Future Atom E3000, Z3000␊ |
| //#define CPUID_MODEL_␉␉␉0x5D␉␉␉// Silvermont, Future Atom E3000, Z3000␊ |
| ␊ |
| /* CPUID Vendor */␊ |
| #define␉CPUID_VID_INTEL␉␉␉"GenuineIntel"␊ |
| #define␉CPUID_VID_AMD␉␉␉"AuthenticAMD"␊ |
| ␊ |
| #define CPUID_VENDOR_INTEL␉␉0x756E6547␊ |
| #define CPUID_VENDOR_AMD␉␉0x68747541␊ |
| /* Unknown CPU */␊ |
| #define CPU_STRING_UNKNOWN␉"Unknown CPU Type"␊ |
| #define bit(n)␉␉␉(1ULL << (n))␊ |
| #define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊ |
| #define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊ |
| #define CPU_STRING_UNKNOWN␉␉"Unknown CPU Type"␊ |
| ␊ |
| //definitions from Apple XNU␊ |
| ␊ |
| /* CPU defines */␊ |
| #define bit(n)␉␉␉␉(1ULL << (n))␊ |
| #define bitmask(h,l)␉␉␉((bit(h) | (bit(h)-1)) & ~(bit(l)-1))␊ |
| #define bitfield(x,h,l)␉␉␉(((x) & bitmask(h,l)) >> l)␊ |
| #define hbit(n)␉␉␉␉(1ULL << ((n)+32))␊ |
| #define min(a,b)␉␉␉((a) < (b) ? (a) : (b))␊ |
| #define quad32(hi,lo)␉␉␉((((uint32_t)(hi)) << 16) | (((uint32_t)(lo)) & 0xFFFF))␊ |
| #define quad64(hi,lo)␉␉␉((((uint64_t)(hi)) << 32) | (((uint64_t)(lo)) & 0xFFFFFFFFUL))␊ |
| ␊ |
| /*␊ |
| * The CPUID_FEATURE_XXX values define 64-bit values␊ |
| * returned in %ecx:%edx to a CPUID request with %eax of 1: ␊ |
| */␊ |
| #define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */␊ |
| #define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */␊ |
| #define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */␊ |
| #define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */␊ |
| #define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */␊ |
| #define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */␊ |
| #define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */␊ |
| #define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */␊ |
| #define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */␊ |
| #define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */␊ |
| #define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */␊ |
| #define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */␊ |
| #define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */␊ |
| #define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */␊ |
| #define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */␊ |
| #define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */␊ |
| #define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */␊ |
| #define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */␊ |
| #define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */␊ |
| #define CPUID_FEATURE_DS _Bit(21) /* Debug Store */␊ |
| #define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */␊ |
| #define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */␊ |
| #define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */␊ |
| #define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */␊ |
| #define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */␊ |
| #define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */␊ |
| #define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */␊ |
| #define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */␊ |
| #define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */␊ |
| ␊ |
| #define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */␊ |
| #define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ instruction */␊ |
| #define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */␊ |
| #define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */␊ |
| #define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */␊ |
| #define CPUID_FEATURE_VMX _HBit(5) /* VMX */␊ |
| #define CPUID_FEATURE_SMX _HBit(6) /* SMX */␊ |
| #define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */␊ |
| #define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */␊ |
| #define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */␊ |
| #define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */␊ |
| #define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */␊ |
| #define CPUID_FEATURE_FMA _HBit(12) /* Fused-Multiply-Add support */␊ |
| #define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */␊ |
| #define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */␊ |
| #define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */␊ |
| #define CPUID_FEATURE_FPU␉␉bit(0) /* Floating point unit on-chip */␊ |
| #define CPUID_FEATURE_VME␉␉bit(1) /* Virtual Mode Extension */␊ |
| #define CPUID_FEATURE_DE␉␉bit(2) /* Debugging Extension */␊ |
| #define CPUID_FEATURE_PSE␉␉bit(3) /* Page Size Extension */␊ |
| #define CPUID_FEATURE_TSC␉␉bit(4) /* Time Stamp Counter */␊ |
| #define CPUID_FEATURE_MSR␉␉bit(5) /* Model Specific Registers */␊ |
| #define CPUID_FEATURE_PAE␉␉bit(6) /* Physical Address Extension */␊ |
| #define CPUID_FEATURE_MCE␉␉bit(7) /* Machine Check Exception */␊ |
| #define CPUID_FEATURE_CX8␉␉bit(8) /* CMPXCHG8B */␊ |
| #define CPUID_FEATURE_APIC␉␉bit(9) /* On-chip APIC */␊ |
| #define CPUID_FEATURE_SEP␉␉bit(11) /* Fast System Call */␊ |
| #define CPUID_FEATURE_MTRR␉␉bit(12) /* Memory Type Range Register */␊ |
| #define CPUID_FEATURE_PGE␉␉bit(13) /* Page Global Enable */␊ |
| #define CPUID_FEATURE_MCA␉␉bit(14) /* Machine Check Architecture */␊ |
| #define CPUID_FEATURE_CMOV␉␉bit(15) /* Conditional Move Instruction */␊ |
| #define CPUID_FEATURE_PAT␉␉bit(16) /* Page Attribute Table */␊ |
| #define CPUID_FEATURE_PSE36␉␉bit(17) /* 36-bit Page Size Extension */␊ |
| #define CPUID_FEATURE_PSN␉␉bit(18) /* Processor Serial Number */␊ |
| #define CPUID_FEATURE_CLFSH␉␉bit(19) /* CLFLUSH Instruction supported */␊ |
| #define CPUID_FEATURE_DS␉␉bit(21) /* Debug Store */␊ |
| #define CPUID_FEATURE_ACPI␉␉bit(22) /* Thermal monitor and Clock Ctrl */␊ |
| #define CPUID_FEATURE_MMX␉␉bit(23) /* MMX supported */␊ |
| #define CPUID_FEATURE_FXSR␉␉bit(24) /* Fast floating pt save/restore */␊ |
| #define CPUID_FEATURE_SSE␉␉bit(25) /* Streaming SIMD extensions */␊ |
| #define CPUID_FEATURE_SSE2␉␉bit(26) /* Streaming SIMD extensions 2 */␊ |
| #define CPUID_FEATURE_SS␉␉bit(27) /* Self-Snoop */␊ |
| #define CPUID_FEATURE_HTT␉␉bit(28) /* Hyper-Threading Technology */␊ |
| #define CPUID_FEATURE_TM␉␉bit(29) /* Thermal Monitor (TM1) */␊ |
| #define CPUID_FEATURE_PBE␉␉bit(31) /* Pend Break Enable */␊ |
| ␊ |
| #define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */␊ |
| #define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */␊ |
| #define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */␊ |
| #define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */␊ |
| #define CPUID_FEATURE_x2APIC _HBit(21) /* Extended APIC Mode */␊ |
| #define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */␊ |
| #define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */␊ |
| #define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */␊ |
| #define CPUID_FEATURE_AES _HBit(25) /* AES instructions */␊ |
| #define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */␊ |
| #define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */␊ |
| #define CPUID_FEATURE_AVX1_0␉_HBit(28) /* AVX 1.0 instructions */␊ |
| #define CPUID_FEATURE_F16C␉_HBit(29) /* Float16 convert instructions */␊ |
| #define CPUID_FEATURE_RDRAND␉_HBit(30) /* RDRAND instruction */␊ |
| #define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */␊ |
| #define CPUID_FEATURE_SSE3␉␉hbit(0) /* Streaming SIMD extensions 3 */␊ |
| #define CPUID_FEATURE_PCLMULQDQ␉␉hbit(1) /* PCLMULQDQ Instruction */␊ |
| #define CPUID_FEATURE_DTES64␉␉hbit(2) /* 64-bit DS layout */␊ |
| #define CPUID_FEATURE_MONITOR␉␉hbit(3) /* Monitor/mwait */␊ |
| #define CPUID_FEATURE_DSCPL␉␉hbit(4) /* Debug Store CPL */␊ |
| #define CPUID_FEATURE_VMX␉␉hbit(5) /* VMX */␊ |
| #define CPUID_FEATURE_SMX␉␉hbit(6) /* SMX */␊ |
| #define CPUID_FEATURE_EST␉␉hbit(7) /* Enhanced SpeedsTep (GV3) */␊ |
| #define CPUID_FEATURE_TM2␉␉hbit(8) /* Thermal Monitor 2 */␊ |
| #define CPUID_FEATURE_SSSE3␉␉hbit(9) /* Supplemental SSE3 instructions */␊ |
| #define CPUID_FEATURE_CID␉␉hbit(10) /* L1 Context ID */␊ |
| #define CPUID_FEATURE_SEGLIM64␉␉hbit(11) /* 64-bit segment limit checking */␊ |
| #define CPUID_FEATURE_FMA␉␉hbit(12) /* Fused-Multiply-Add support */␊ |
| #define CPUID_FEATURE_CX16␉␉hbit(13) /* CmpXchg16b instruction */␊ |
| #define CPUID_FEATURE_xTPR␉␉hbit(14) /* Send Task PRiority msgs */␊ |
| #define CPUID_FEATURE_PDCM␉␉hbit(15) /* Perf/Debug Capability MSR */␊ |
| ␊ |
| #define CPUID_FEATURE_PCID␉␉hbit(17) /* ASID-PCID support */␊ |
| #define CPUID_FEATURE_DCA␉␉hbit(18) /* Direct Cache Access */␊ |
| #define CPUID_FEATURE_SSE4_1␉␉hbit(19) /* Streaming SIMD extensions 4.1 */␊ |
| #define CPUID_FEATURE_SSE4_2␉␉hbit(20) /* Streaming SIMD extensions 4.2 */␊ |
| #define CPUID_FEATURE_x2APIC␉␉hbit(21) /* Extended APIC Mode */␊ |
| #define CPUID_FEATURE_MOVBE␉␉hbit(22) /* MOVBE instruction */␊ |
| #define CPUID_FEATURE_POPCNT␉␉hbit(23) /* POPCNT instruction */␊ |
| #define CPUID_FEATURE_TSCTMR␉␉hbit(24) /* TSC deadline timer */␊ |
| #define CPUID_FEATURE_AES␉␉hbit(25) /* AES instructions */␊ |
| #define CPUID_FEATURE_XSAVE␉␉hbit(26) /* XSAVE instructions */␊ |
| #define CPUID_FEATURE_OSXSAVE␉␉hbit(27) /* XGETBV/XSETBV instructions */␊ |
| #define CPUID_FEATURE_AVX1_0␉␉hbit(28) /* AVX 1.0 instructions */␊ |
| #define CPUID_FEATURE_F16C␉␉hbit(29) /* Float16 convert instructions */␊ |
| #define CPUID_FEATURE_RDRAND␉␉hbit(30) /* RDRAND instruction */␊ |
| #define CPUID_FEATURE_VMM␉␉hbit(31) /* VMM (Hypervisor) present */␊ |
| ␊ |
| /*␊ |
| * Leaf 7, subleaf 0 additional features.␊ |
| * Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:␊ |
| */␊ |
| #define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)␉/* FS/GS base read/write */␊ |
| #define CPUID_LEAF7_FEATURE_TSCOFF _Bit(1)␉/* TSC thread offset */␊ |
| #define CPUID_LEAF7_FEATURE_BMI1 _Bit(3)␉/* Bit Manipulation Instrs, set 1 */␊ |
| #define CPUID_LEAF7_FEATURE_HLE _Bit(4)␉/* Hardware Lock Elision*/␊ |
| #define CPUID_LEAF7_FEATURE_AVX2 _Bit(5)␉/* AVX2 Instructions */␊ |
| #define CPUID_LEAF7_FEATURE_SMEP _Bit(7)␉/* Supervisor Mode Execute Protect */␊ |
| #define CPUID_LEAF7_FEATURE_BMI2 _Bit(8)␉/* Bit Manipulation Instrs, set 2 */␊ |
| #define CPUID_LEAF7_FEATURE_ENFSTRG _Bit(9)␉/* ENhanced Fast STRinG copy */␊ |
| #define CPUID_LEAF7_FEATURE_INVPCID _Bit(10)␉/* INVPCID intruction, TDB */␊ |
| #define CPUID_LEAF7_FEATURE_RTM _Bit(11)␉/* TBD */␊ |
| #define CPUID_LEAF7_FEATURE_RDWRFSGS␉bit(0)␉/* FS/GS base read/write */␊ |
| #define CPUID_LEAF7_FEATURE_TSCOFF␉bit(1)␉/* TSC thread offset */␊ |
| #define CPUID_LEAF7_FEATURE_BMI1␉bit(3)␉/* Bit Manipulation Instrs, set 1 */␊ |
| #define CPUID_LEAF7_FEATURE_HLE␉␉bit(4)␉/* Hardware Lock Elision*/␊ |
| #define CPUID_LEAF7_FEATURE_AVX2␉bit(5)␉/* AVX2 Instructions */␊ |
| #define CPUID_LEAF7_FEATURE_SMEP␉bit(7)␉/* Supervisor Mode Execute Protect */␊ |
| #define CPUID_LEAF7_FEATURE_BMI2␉bit(8)␉/* Bit Manipulation Instrs, set 2 */␊ |
| #define CPUID_LEAF7_FEATURE_ENFSTRG␉bit(9)␉/* ENhanced Fast STRinG copy */␊ |
| #define CPUID_LEAF7_FEATURE_INVPCID␉bit(10)␉/* INVPCID intruction, TDB */␊ |
| #define CPUID_LEAF7_FEATURE_RTM␉␉bit(11)␉/* TBD */␊ |
| ␊ |
| /*␊ |
| * The CPUID_EXTFEATURE_XXX values define 64-bit values␊ |
| * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001: ␊ |
| */␊ |
| #define CPUID_EXTFEATURE_SYSCALL _Bit(11)␉/* SYSCALL/sysret */␊ |
| #define CPUID_EXTFEATURE_XD␉ _Bit(20)␉/* eXecute Disable */␊ |
| #define CPUID_EXTFEATURE_SYSCALL␉bit(11)␉/* SYSCALL/sysret */␊ |
| #define CPUID_EXTFEATURE_XD␉␉bit(20)␉/* eXecute Disable */␊ |
| ␊ |
| #define CPUID_EXTFEATURE_1GBPAGE _Bit(26)␉/* 1GB pages */␊ |
| #define CPUID_EXTFEATURE_RDTSCP␉ _Bit(27)␉/* RDTSCP */␊ |
| #define CPUID_EXTFEATURE_EM64T␉ _Bit(29)␉/* Extended Mem 64 Technology */␊ |
| #define CPUID_EXTFEATURE_1GBPAGE␉bit(26)␉/* 1GB pages support */␊ |
| #define CPUID_EXTFEATURE_RDTSCP␉␉bit(27)␉/* RDTSCP */␊ |
| #define CPUID_EXTFEATURE_EM64T␉␉bit(29)␉/* Extended Mem 64 Technology */␊ |
| ␊ |
| #define CPUID_EXTFEATURE_LAHF␉ _HBit(0)␉/* LAFH/SAHF instructions */␊ |
| ␊ |
| ␊ |
| #define CPUID_EXTFEATURE_LAHF␉␉hbit(0)␉/* LAFH/SAHF instructions */␊ |
| ␊ |
| /*␊ |
| * The CPUID_EXTFEATURE_XXX values define 64-bit values␊ |
| * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007: ␊ |
| */␊ |
| #define CPUID_EXTFEATURE_TSCI _Bit(8)␉/* TSC Invariant */␊ |
| #define CPUID_EXTFEATURE_TSCI␉␉bit(8)␉/* TSC Invariant */␊ |
| ␊ |
| #define␉CPUID_CACHE_SIZE␉16␉/* Number of descriptor values */␊ |
| #define␉CPUID_CACHE_SIZE␉␉16␉/* Number of descriptor values */␊ |
| ␊ |
| #define CPUID_MWAIT_EXTENSION␉_Bit(0)␉/* enumeration of WMAIT extensions */␊ |
| #define CPUID_MWAIT_BREAK␉_Bit(1)␉/* interrupts are break events␉ */␊ |
| #define CPUID_MWAIT_EXTENSION␉␉bit(0)␉/* enumeration of WMAIT extensions */␊ |
| #define CPUID_MWAIT_BREAK␉␉bit(1)␉/* interrupts are break events␉ */␊ |
| ␊ |
| //-- processor type -> p_type:␊ |
| #define PT_OEM␉0x00␉// Intel Original OEM Processor;␊ |
| #define PT_OD␉0x01 ␉// Intel Over Drive Processor;␊ |
| #define PT_DUAL␉0x02␉// Intel Dual Processor;␊ |
| #define PT_RES␉0x03␉// Intel Reserved;␊ |
| #define PT_OEM␉␉␉␉0x00␉// Intel Original OEM Processor;␊ |
| #define PT_OD␉␉␉␉0x01 ␉// Intel Over Drive Processor;␊ |
| #define PT_DUAL␉␉␉␉0x02␉// Intel Dual Processor;␊ |
| #define PT_RES␉␉␉␉0x03␉// Intel Reserved;␊ |
| ␊ |
| /* Known MSR registers */␊ |
| #define MSR_IA32_PLATFORM_ID 0x0017␊ |
| #define MSR_CORE_THREAD_COUNT 0x0035␉/* limited use - not for Penryn or older */␊ |
| #define IA32_TSC_ADJUST 0x003B␊ |
| #define MSR_IA32_BIOS_SIGN_ID 0x008B␉/* microcode version */␊ |
| #define MSR_FSB_FREQ 0x00CD␉/* limited use - not for i7 */␊ |
| #define␉MSR_PLATFORM_INFO 0x00CE␉/* limited use - MinRatio for i7 but Max for Yonah␉*/␊ |
| #define MSR_IA32_PLATFORM_ID␉␉0x0017␊ |
| #define IA32_APIC_BASE␉␉␉0x001B /* used also for AMD */␊ |
| #define MSR_CORE_THREAD_COUNT␉␉0x0035␉/* limited use - not for Penryn or older */␊ |
| #define IA32_TSC_ADJUST␉␉␉0x003B␊ |
| #define MSR_IA32_BIOS_SIGN_ID␉␉0x008B␉/* microcode version */␊ |
| #define MSR_FSB_FREQ␉␉␉0x00CD␉/* limited use - not for i7 */␊ |
| #define␉MSR_PLATFORM_INFO␉␉0x00CE␉/* limited use - MinRatio for i7 but Max for Yonah␉*/␊ |
| /* turbo for penryn */␊ |
| #define MSR_PKG_CST_CONFIG_CONTROL 0x00E2␉/* sandy and ivy */␊ |
| #define MSR_PMG_IO_CAPTURE_BASE 0x00E4␊ |
| #define IA32_MPERF 0x00E7␉/* TSC in C0 only */␊ |
| #define IA32_APERF 0x00E8␉/* actual clocks in C0 */␊ |
| #define MSR_IA32_EXT_CONFIG 0x00EE␉/* limited use - not for i7 */␊ |
| #define MSR_FLEX_RATIO 0x0194␉/* limited use - not for Penryn or older */␊ |
| #define MSR_PKG_CST_CONFIG_CONTROL␉0x00E2␉␉// sandy and ivy␊ |
| #define MSR_PMG_IO_CAPTURE_BASE␉␉0x00E4␊ |
| #define IA32_MPERF␉␉␉0x00E7␉␉// TSC in C0 only␊ |
| #define IA32_APERF␉␉␉0x00E8␉␉// actual clocks in C0␊ |
| #define MSR_IA32_EXT_CONFIG␉␉0x00EE␉␉// limited use - not for i7␊ |
| #define MSR_FLEX_RATIO␉␉␉0x0194␉␉// limited use - not for Penryn or older␊ |
| ␉␉␉␉␉␉//see no value on most CPUs␊ |
| #define␉MSR_IA32_PERF_STATUS 0x0198␊ |
| #define MSR_IA32_PERF_CONTROL 0x0199␊ |
| #define MSR_IA32_CLOCK_MODULATION 0x019A␊ |
| #define MSR_THERMAL_STATUS 0x019C␊ |
| #define MSR_IA32_MISC_ENABLE 0x01A0␊ |
| #define MSR_THERMAL_TARGET 0x01A2␉ /* TjMax limited use - not for Penryn or older␉*/␊ |
| #define MSR_MISC_PWR_MGMT 0x01AA␊ |
| #define MSR_TURBO_RATIO_LIMIT 0x01AD␉ /* limited use - not for Penryn or older */␊ |
| #define␉MSR_IA32_PERF_STATUS␉␉0x0198␊ |
| #define MSR_IA32_PERF_CONTROL␉␉0x0199␊ |
| #define MSR_IA32_CLOCK_MODULATION␉0x019A␊ |
| #define MSR_THERMAL_STATUS␉␉0x019C␊ |
| #define MSR_IA32_MISC_ENABLE␉␉0x01A0␊ |
| #define MSR_THERMAL_TARGET␉␉0x01A2␉␉// TjMax limited use - not for Penryn or older␊ |
| #define MSR_MISC_PWR_MGMT␉␉0x01AA␊ |
| #define MSR_TURBO_RATIO_LIMIT␉␉0x01AD␉␉// limited use - not for Penryn or older␊ |
| ␊ |
| #define IA32_ENERGY_PERF_BIAS␉␉0x01B0␊ |
| #define MSR_PACKAGE_THERM_STATUS␉0x01B1␊ |
| #define IA32_PLATFORM_DCA_CAP␉␉0x01F8␊ |
| #define MSR_POWER_CTL␉␉␉0x01FC // MSR 000001FC 0000-0000-0004-005F␊ |
| #define MSR_POWER_CTL␉␉␉0x01FC␉␉// MSR 000001FC 0000-0000-0004-005F␊ |
| ␊ |
| // Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.␊ |
| #define MSR_RAPL_POWER_UNIT␉␉␉0x606 /* R/O */␊ |
| #define MSR_RAPL_POWER_UNIT␉␉0x606␉␉// R/O␊ |
| //MSR 00000606 0000-0000-000A-1003␊ |
| #define MSR_PKGC3_IRTL 0x60A /* RW time limit to go C3 */␊ |
| #define MSR_PKGC3_IRTL␉␉␉0x60A␉␉// RW time limit to go C3␊ |
| // bit 15 = 1 -- the value valid for C-state PM␊ |
| #define MSR_PKGC6_IRTL 0x60B /* RW time limit to go C6 */␊ |
| #define MSR_PKGC6_IRTL␉␉␉0x60B␉␉// RW time limit to go C6␊ |
| //MSR 0000060B 0000-0000-0000-8854␊ |
| //Valid + 010=1024ns + 0x54=84mks␊ |
| #define MSR_PKGC7_IRTL 0x60C /* RW time limit to go C7 */␊ |
| #define MSR_PKGC7_IRTL␉␉␉0x60C␉␉// RW time limit to go C7␊ |
| //MSR 0000060C 0000-0000-0000-8854␊ |
| #define MSR_PKG_C2_RESIDENCY 0x60D /* same as TSC but in C2 only */␊ |
| #define MSR_PKG_C2_RESIDENCY␉␉0x60D␉␉// same as TSC but in C2 only␊ |
| ␊ |
| #define MSR_PKG_RAPL_POWER_LIMIT␉0x610 //MSR 00000610 0000-A580-0000-8960␊ |
| #define MSR_PKG_ENERGY_STATUS␉␉0x611 //MSR 00000611 0000-0000-3212-A857␊ |
| #define MSR_PKG_POWER_INFO␉␉␉0x614 //MSR 00000614 0000-0000-01E0-02F8␊ |
| #define MSR_PKG_RAPL_POWER_LIMIT␉0x610␉␉//MSR 00000610 0000-A580-0000-8960␊ |
| #define MSR_PKG_ENERGY_STATUS␉␉0x611␉␉//MSR 00000611 0000-0000-3212-A857␊ |
| #define MSR_PKG_POWER_INFO␉␉0x614␉␉//MSR 00000614 0000-0000-01E0-02F8␊ |
| ␊ |
| // Sandy Bridge IA (Core) domain MSR's.␊ |
| #define MSR_PP0_POWER_LIMIT␉␉0x638␊ |
| #define MSR_PP0_ENERGY_STATUS␉␉0x639␊ |
| #define MSR_PP0_POLICY␉␉␉0x63A␊ |
| #define MSR_PP0_PERF_STATUS␉␉0x63B␊ |
| ␊ |
| // Sandy Bridge Uncore (IGPU) domain MSR's (Not on JakeTown).␊ |
| #define MSR_PP1_POWER_LIMIT␉␉0x640␊ |
| #define MSR_PP1_ENERGY_STATUS␉ ␉0x641␊ |
| //MSR 00000641 0000-0000-0000-0000␊ |
| #define MSR_PP1_POLICY␉␉␉0x642␊ |
| ␊ |
| // JakeTown only Memory MSR's.␊ |
| #define MSR_PKG_PERF_STATUS␉␉0x613 ␊ |
| #define MSR_DRAM_POWER_LIMIT␉ ␉0x618␊ |
| #define MSR_DRAM_ENERGY_STATUS␉␉0x619␊ |
| #define MSR_DRAM_PERF_STATUS␉␉0x61B␊ |
| #define MSR_DRAM_POWER_INFO␉␉0x61C␊ |
| ␊ |
| //IVY_BRIDGE␊ |
| #define MSR_CONFIG_TDP_NOMINAL␉␉0x648␊ |
| #define MSR_CONFIG_TDP_LEVEL1␉␉0x649␊ |
| #define MSR_CONFIG_TDP_LEVEL2␉␉0x64A␊ |
| #define MSR_CONFIG_TDP_CONTROL␉␉0x64B␉␉// write once to lock␊ |
| #define MSR_TURBO_ACTIVATION_RATIO␉0x64C␊ |
| ␊ |
| //AMD␊ |
| #define K8_FIDVID_STATUS 0xC0010042␊ |
| #define K10_COFVID_LIMIT 0xC0010061␊ |
| #define K10_PSTATE_STATUS 0xC0010064␊ |
| #define K10_COFVID_STATUS 0xC0010071␊ |
| #define K8_FIDVID_STATUS␉␉0xC0010042␊ |
| #define K10_COFVID_LIMIT␉␉0xC0010061␉// max enabled p-state (msr >> 4) & 7␊ |
| #define K10_COFVID_CONTROL␉␉0xC0010062␉// switch to p-state␊ |
| #define K10_PSTATE_STATUS␉␉0xC0010064␊ |
| #define K10_COFVID_STATUS␉␉0xC0010071␉// current p-state (msr >> 16) & 7␊ |
| ␊ |
| #define MSR_AMD_MPERF 0x000000E7␊ |
| #define MSR_AMD_APERF 0x000000E8␊ |
| #define MSR_AMD_MPERF␉␉␉0x000000E7␊ |
| #define MSR_AMD_APERF␉␉␉0x000000E8␊ |
| ␊ |
| #define DEFAULT_FSB␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊ |
| #define DEFAULT_FSB␉␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊ |
| ␊ |
| // DFE: This constant comes from older xnu:␊ |
| #define CLKNUM␉␉␉1193182␉␉/* formerly 1193167 */␊ |
| #define CLKNUM␉␉␉␉1193182␉␉/* formerly 1193167 */␊ |
| ␊ |
| /* CPU Features */␊ |
| #define CPU_FEATURE_MMX␉␉␉0x00000001␉␉// MMX Instruction Set␊ |
|
| #define CPU_FEATURE_MSR␉␉␉0x00000200␉␉// MSR Support␊ |
| ␊ |
| /* SMBIOS Memory Types */ ␊ |
| #define SMB_MEM_TYPE_UNDEFINED␉0␊ |
| #define SMB_MEM_TYPE_UNDEFINED␉␉0␊ |
| #define SMB_MEM_TYPE_OTHER␉␉1␊ |
| #define SMB_MEM_TYPE_UNKNOWN␉2␊ |
| #define SMB_MEM_TYPE_UNKNOWN␉␉2␊ |
| #define SMB_MEM_TYPE_DRAM␉␉3␊ |
| #define SMB_MEM_TYPE_EDRAM␉␉4␊ |
| #define SMB_MEM_TYPE_VRAM␉␉5␊ |
