Chameleon

Chameleon Commit Details

Date:2015-01-26 00:25:00 (9 years 2 months ago)
Author:ErmaC
Commit:2550
Parents: 2549
Message:Typo
Changes:
M/branches/ErmaC/Enoch/i386/libsaio/convert.c
M/branches/ErmaC/Enoch/i386/libsaio/pci.h
M/branches/ErmaC/Enoch/i386/libsaio/smbios.h
M/branches/ErmaC/Enoch/i386/libsa/memory.h
M/branches/ErmaC/Enoch/i386/boot2/boot.c
M/branches/ErmaC/Enoch/i386/libsaio/spd.c
M/branches/ErmaC/Enoch/i386/libsaio/platform.h

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branches/ErmaC/Enoch/i386/libsaio/spd.c
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␊
static const char *spd_memory_types[] =␊
{␊
␉"RAM", /* 00h Undefined */␊
␉"FPM", /* 01h FPM */␊
␉"EDO", /* 02h EDO */␊
␉"",␉␉/* 03h PIPELINE NIBBLE */␊
␉"SDRAM", /* 04h SDRAM */␊
␉"",␉␉/* 05h MULTIPLEXED ROM */␊
␉"DDR SGRAM",␉/* 06h SGRAM DDR */␊
␉"DDR SDRAM",␉/* 07h SDRAM DDR */␊
␉"DDR2 SDRAM", /* 08h SDRAM DDR 2 */␊
␉"",␉␉/* 09h Undefined */␊
␉"",␉␉/* 0Ah Undefined */␊
␉"DDR3 SDRAM"␉/* 0Bh SDRAM DDR 3 */␊
␉"RAM",␉␉␉␉/* 00h Undefined */␊
␉"STD FPM DRAM",␉␉␉/* 01h FPM */␊
␉"EDO",␉␉␉␉/* 02h EDO */␊
␉"PIPE NIBBLE",␉␉␉/* 03h PIPELINE NIBBLE */␊
␉"SDRAM",␉␉␉/* 04h SDRAM */␊
␉"ROM",␉␉␉␉/* 05h MULTIPLEXED ROM */␊
␉"DDR SGRAM"␉␉␉/* 06h SGRAM DDR */␊
␉"DDR SDRAM",␉␉␉/* 07h SDRAM DDR */␊
␉"DDR2 SDRAM",␉␉␉/* 08h SDRAM DDR 2 */␊
␉"DDR2 SDRAM FB-DIMM",␉␉/* 09h Undefined */␊
␉"DDR2 SDRAM FB-DIMM Probe",␉/* 0Ah Undefined */␊
␉"DDR3 SDRAM",␉␉␉/* 0Bh SDRAM DDR 3 */␊
␉"DDR4 SDRAM"␉␉␉/* 0Ch SDRAM DDR 4 */␊
};␊
␊
#define UNKNOWN_MEM_TYPE 2␊
␊
␉rdtsc(l1, h1);␊
␊
␉while (!( inb(base + SMBHSTSTS) & 0x02))␉// wait til command finished␊
␉while (!( inb(base + SMBHSTSTS) & 0x02))␉// wait till command finished␊
␉{␊
␉␉rdtsc(l2, h2);␊
␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
branches/ErmaC/Enoch/i386/libsaio/platform.h
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␊
/* Maximum number of ram slots */␊
#define MAX_RAM_SLOTS␉␉␉8␊
␊
#define RAM_SLOT_ENUMERATOR␉␉{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}␊
␊
/* Maximum number of SPD bytes */␊
␊
typedef struct _RamSlotInfo_t␊
{␊
␉uint32_t␉␉ModuleSize;␉␉␉␉␉// Size of Module in MB␊
␉uint32_t␉␉Frequency;␉␉␉␉␉// in Mhz␊
␉uint32_t␉␉ModuleSize;␉␉␉// Size of Module in MB␊
␉uint32_t␉␉Frequency;␉␉␉// in Mhz␊
␉const char*␉␉Vendor;␊
␉const char*␉␉PartNo;␊
␉const char*␉␉SerialNo;␊
␉char*␉␉␉spd;␉␉␉␉␉␉// SPD Dump␊
␉char*␉␉␉spd;␉␉␉␉// SPD Dump␊
␉bool␉␉␉InUse;␊
␉uint8_t␉␉␉Type;␊
␉uint8_t␉␉␉BankConnections;␉␉␉// table type 6, see (3.3.7)␊
␉uint8_t␉␉␉BankConnections;␉␉// table type 6, see (3.3.7)␊
␉uint8_t␉␉␉BankConnCnt;␊
} RamSlotInfo_t;␊
␊
typedef struct _PlatformInfo_t␊
{␊
␉struct CPU {␊
␉␉uint32_t␉␉Vendor;␉␉␉␉␉// Vendor - char Vendor[16];␊
␉␉char␉␉␉BrandString[48];␉␉␉// 48 Byte Branding String␊
␉␉//uint16_t␉␉Type;␉␉␉␉␉// Type␊
␉␉uint8_t␉␉␉Family;␉␉␉␉␉// Family␊
␉␉uint8_t␉␉␉Model;␉␉␉␉␉// Model␊
␉␉uint8_t␉␉␉ExtModel;␉␉␉␉// Extended Model␊
␉␉uint8_t␉␉␉ExtFamily;␉␉␉␉// Extended Family␊
␉␉uint8_t␉␉␉Stepping;␉␉␉␉// Stepping␊
␉␉uint64_t␉␉Features;␉␉␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊
␉␉uint32_t␉␉Vendor;␉␉␉// Vendor - char Vendor[16];␊
␉␉char␉␉␉BrandString[48];␉// 48 Byte Branding String␊
␉␉//uint16_t␉␉Type;␉␉␉// Type␊
␉␉uint8_t␉␉␉Family;␉␉␉// Family␊
␉␉uint8_t␉␉␉Model;␉␉␉// Model␊
␉␉uint8_t␉␉␉ExtModel;␉␉// Extended Model␊
␉␉uint8_t␉␉␉ExtFamily;␉␉// Extended Family␊
␉␉uint8_t␉␉␉Stepping;␉␉// Stepping␊
␉␉uint64_t␉␉Features;␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊
␉␉uint64_t␉␉ExtFeatures;␊
␉␉uint32_t␉␉CoresPerPackage;␊
␉␉uint32_t␉␉LogicalPerPackage;␊
␉␉uint32_t␉␉Signature;␉␉␉␉// Processor Signature␊
␉␉uint32_t␉␉Signature;␉␉// Processor Signature␊
␉␉//uint8_t␉␉Brand;␊
␉␉//uint8_t␉␉ProcessorFlag;␊
␊
␉␉uint32_t␉␉NoCores;␉␉␉␉// No Cores per Package␊
␉␉uint32_t␉␉NoThreads;␉␉␉␉// Threads per Package␊
␉␉uint32_t␉␉NoCores;␉␉// No Cores per Package␊
␉␉uint32_t␉␉NoThreads;␉␉// Threads per Package␊
␊
␉␉//uint32_t␉␉CacheSize[LCACHE_MAX];␊
␉␉//uint32_t␉␉CacheLineSize;␊
␊
␉␉//uint8_t␉␉cache_info[64];␉␉␉␉// list of cache descriptors␊
␉␉//uint8_t␉␉cache_info[64];␉␉// list of cache descriptors␊
␊
␉␉uint8_t␉␉␉MaxCoef;␉␉␉␉// Max Multiplier␊
␉␉uint8_t␉␉␉MaxDiv;␉␉␉␉␉// Min Multiplier␊
␉␉uint8_t␉␉␉CurrCoef;␉␉␉␉// Current Multiplier␊
␉␉uint8_t␉␉␉MaxCoef;␉␉// Max Multiplier␊
␉␉uint8_t␉␉␉MaxDiv;␉␉␉// Min Multiplier␊
␉␉uint8_t␉␉␉CurrCoef;␉␉// Current Multiplier␊
␉␉uint8_t␉␉␉CurrDiv;␊
␉␉uint64_t␉␉TSCFrequency;␉␉␉␉// TSC Frequency Hz␊
␉␉uint64_t␉␉FSBFrequency;␉␉␉␉// FSB Frequency Hz␊
␉␉uint64_t␉␉CPUFrequency;␉␉␉␉// CPU Frequency Hz␊
␉␉uint32_t␉␉MaxRatio;␉␉␉␉// Max Bus Ratio␊
␉␉uint32_t␉␉MinRatio;␉␉␉␉// Min Bus Ratio␊
␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉␉␉// CPUID 0..4, 80..81 Raw Values␊
␉␉uint64_t␉␉TSCFrequency;␉␉// TSC Frequency Hz␊
␉␉uint64_t␉␉FSBFrequency;␉␉// FSB Frequency Hz␊
␉␉uint64_t␉␉CPUFrequency;␉␉// CPU Frequency Hz␊
␉␉uint32_t␉␉MaxRatio;␉␉// Max Bus Ratio␊
␉␉uint32_t␉␉MinRatio;␉␉// Min Bus Ratio␊
␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊
␊
␉␉uint32_t␉␉MCodeVersion;␉␉␉␉// CPU Microcode version␊
␉␉uint32_t␉␉MCodeVersion;␉␉// CPU Microcode version␊
␉} CPU;␊
␊
␉struct RAM {␊
␉␉uint64_t␉␉Frequency;␉␉␉␉// Ram Frequency␊
␉␉uint32_t␉␉Divider;␉␉␉␉// Memory divider␊
␉␉uint8_t␉␉␉CAS;␉␉␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊
␉␉uint8_t␉␉␉TRC;␉␉␉␉␉␊
␉␉uint64_t␉␉Frequency;␉␉// Ram Frequency␊
␉␉uint32_t␉␉Divider;␉␉// Memory divider␊
␉␉uint8_t␉␉␉CAS;␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊
␉␉uint8_t␉␉␉TRC;␉␊
␉␉uint8_t␉␉␉TRP;␊
␉␉uint8_t␉␉␉RAS;␊
␉␉uint8_t␉␉␉Channels;␉␉␉␉// Channel Configuration Single,Dual or Triple␊
␉␉uint8_t␉␉␉NoSlots;␉␉␉␉// Maximum no of slots available␊
␉␉uint8_t␉␉␉Type;␉␉␉␉␉// Standard SMBIOS v2.5 Memory Type␊
␉␉RamSlotInfo_t␉DIMM[MAX_RAM_SLOTS];␉// Information about each slot␊
␉␉uint8_t␉␉␉Channels;␉␉// Channel Configuration Single,Dual or Triple␊
␉␉uint8_t␉␉␉NoSlots;␉␉// Maximum no of slots available␊
␉␉uint8_t␉␉␉Type;␉␉␉// Standard SMBIOS v2.5 Memory Type␊
␉␉RamSlotInfo_t␉DIMM[MAX_RAM_SLOTS];␉␉// Information about each slot␊
␉} RAM;␊
␊
␉struct DMI {␊
␉␉int␉␉␉DIMM[MAX_RAM_SLOTS];␉// Information and SPD mapping for each slot␊
␉} DMI;␊
␊
␉uint8_t␉␉␉␉Type;␉␉␉// System Type: 1=Desktop, 2=Portable, 3=Workstation... according ACPI2.0 (FACP: PM_Profile)␊
␉uint8_t␉␉␉␉*UUID;␊
␉uint8_t␉␉␉␉Type;␉␉␉// system-type: 1=Desktop, 2=Portable, 3=Workstation... according ACPI2.0 (FACP: PM_Profile)␊
␉uint8_t␉␉␉␉*UUID;␉␉␉// system-id (SMBIOS Table 1: system uuid)␊
␊
} PlatformInfo_t;␊
␊
extern PlatformInfo_t Platform;␊
branches/ErmaC/Enoch/i386/libsaio/smbios.h
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␉SMBString serialNumber;␊
␉SMBString assetTag;␊
␉SMBString partNumber;␊
␉// 2.5+ spec (40 bytes)␊
␉// 2.5+ spec (40 bytes) Apple still uses 2.4 spec␊
␉SMBByte coreCount;␊
␉SMBByte coreEnabled;␊
␉SMBByte threadCount;␊
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/** Parse an UUID string into an (EFI_CHAR8*) buffer */␊
EFI_CHAR8* getUUIDFromString(const char *source)␊
{␊
␉if (!source) return 0;␊
␉if (!source)␊
␉{␊
␉␉return 0;␊
␉}␊
␊
␉char␉*p = (char *)source;␊
␉int␉i;␊
branches/ErmaC/Enoch/i386/libsaio/pci.h
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/* Option ROM header */␊
typedef struct {␊
␉uint16_t␉␉signature;␉␉// 0xAA55␊
␉uint8_t␉␉␉rom_size;␉␉//in 512 bytes blocks␊
␉uint8_t␉␉␉jump;␉␉␉//0xE9 for ATI and Intel, 0xEB for NVidia␊
␉uint32_t␉␉entry_point;␊
␉uint8_t␉␉␉rom_size;␉␉// in 512 bytes blocks␊
␉uint8_t␉␉␉jump;␉␉␉// 0xE9 for ATI and Intel, 0xEB for NVidia␊
␉uint8_t␉␉␉entry_point[4];␉␉// offset to␊
␉uint8_t␉␉␉reserved[16];␊
␉uint16_t␉␉pci_header_offset;␉//@0x18␊
␉uint16_t␉␉pci_header_offset;␉// @0x18␊
␉uint16_t␉␉expansion_header_offset;␊
} option_rom_header_t;␊
␊
#define PCI_CLASS_SIGNAL_OTHER␉␉␉␉␉0x1180␊
␊
// values for the class_sub field for class_base = 0xff (Device does not fit any defined class)␊
#define PCI_CLASS_OTHERS 0xff␊
#define PCI_CLASS_OTHERS␉␉␉␉␉0xff␊
␊
/* Several ID's we need in the library */␊
#define PCI_VENDOR_ID_LOGITECH␉␉␉␉␉0x046d␊
branches/ErmaC/Enoch/i386/boot2/boot.c
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␉␉}␊
␉␉else␊
␉␉{␊
␉␉␉DBG("Kernel Cache using disabled by user.");␊
␉␉␉DBG("Kernel Cache using disabled by user.\n");␊
␉␉}␊
␊
␉␉do␊
branches/ErmaC/Enoch/i386/libsa/memory.h
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#define KERNEL_LEN 0x08000000␊
␊
#define ZALLOC_ADDR 0x08100000 // 256M zalloc area␊
#define ZALLOC_LEN 0x14000000␊
␊
#define ZALLOC_LEN 0x14000000 // Pike R. Alpha: was 0x10000000␊
␊
#define LOAD_ADDR 0x18100000 // 64M File load buffer␊
#define LOAD_LEN 0x04000000␊
␊

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Revision: 2550