Chameleon

Chameleon Commit Details

Date:2015-01-26 00:25:00 (4 years 5 months ago)
Author:ErmaC
Commit:2550
Parents: 2549
Message:Typo
Changes:
M/branches/ErmaC/Enoch/i386/libsaio/convert.c
M/branches/ErmaC/Enoch/i386/libsaio/pci.h
M/branches/ErmaC/Enoch/i386/libsaio/smbios.h
M/branches/ErmaC/Enoch/i386/libsa/memory.h
M/branches/ErmaC/Enoch/i386/boot2/boot.c
M/branches/ErmaC/Enoch/i386/libsaio/spd.c
M/branches/ErmaC/Enoch/i386/libsaio/platform.h

File differences

branches/ErmaC/Enoch/i386/libsaio/spd.c
2727
2828
2929
30
31
32
33
34
35
36
37
38
39
40
41
30
31
32
33
34
35
36
37
38
39
40
41
42
4243
4344
4445
......
109110
110111
111112
112
113
113114
114115
115116
static const char *spd_memory_types[] =
{
"RAM", /* 00h Undefined */
"FPM", /* 01h FPM */
"EDO", /* 02h EDO */
"",/* 03h PIPELINE NIBBLE */
"SDRAM", /* 04h SDRAM */
"",/* 05h MULTIPLEXED ROM */
"DDR SGRAM",/* 06h SGRAM DDR */
"DDR SDRAM",/* 07h SDRAM DDR */
"DDR2 SDRAM", /* 08h SDRAM DDR 2 */
"",/* 09h Undefined */
"",/* 0Ah Undefined */
"DDR3 SDRAM"/* 0Bh SDRAM DDR 3 */
"RAM",/* 00h Undefined */
"STD FPM DRAM",/* 01h FPM */
"EDO",/* 02h EDO */
"PIPE NIBBLE",/* 03h PIPELINE NIBBLE */
"SDRAM",/* 04h SDRAM */
"ROM",/* 05h MULTIPLEXED ROM */
"DDR SGRAM"/* 06h SGRAM DDR */
"DDR SDRAM",/* 07h SDRAM DDR */
"DDR2 SDRAM",/* 08h SDRAM DDR 2 */
"DDR2 SDRAM FB-DIMM",/* 09h Undefined */
"DDR2 SDRAM FB-DIMM Probe",/* 0Ah Undefined */
"DDR3 SDRAM",/* 0Bh SDRAM DDR 3 */
"DDR4 SDRAM"/* 0Ch SDRAM DDR 4 */
};
#define UNKNOWN_MEM_TYPE 2
rdtsc(l1, h1);
while (!( inb(base + SMBHSTSTS) & 0x02))// wait til command finished
while (!( inb(base + SMBHSTSTS) & 0x02))// wait till command finished
{
rdtsc(l2, h2);
t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);
branches/ErmaC/Enoch/i386/libsaio/platform.h
337337
338338
339339
340
340341
341342
342343
......
347348
348349
349350
350
351
351
352
352353
353354
354355
355
356
356357
357358
358
359
359360
360361
361362
......
364365
365366
366367
367
368
369
370
371
372
373
374
375
368
369
370
371
372
373
374
375
376
376377
377378
378379
379
380
380381
381382
382383
383
384
384
385
385386
386387
387388
388389
389
390
390391
391
392
393
392
393
394
394395
395
396
397
398
399
400
396
397
398
399
400
401
401402
402
403
403404
404405
405406
406
407
408
409
407
408
409
410
410411
411412
412
413
414
415
413
414
415
416
416417
417418
418419
......
422423
423424
424425
425
426
426
427
428
427429
428430
429431
/* Maximum number of ram slots */
#define MAX_RAM_SLOTS8
#define RAM_SLOT_ENUMERATOR{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}
/* Maximum number of SPD bytes */
typedef struct _RamSlotInfo_t
{
uint32_tModuleSize;// Size of Module in MB
uint32_tFrequency;// in Mhz
uint32_tModuleSize;// Size of Module in MB
uint32_tFrequency;// in Mhz
const char*Vendor;
const char*PartNo;
const char*SerialNo;
char*spd;// SPD Dump
char*spd;// SPD Dump
boolInUse;
uint8_tType;
uint8_tBankConnections;// table type 6, see (3.3.7)
uint8_tBankConnections;// table type 6, see (3.3.7)
uint8_tBankConnCnt;
} RamSlotInfo_t;
typedef struct _PlatformInfo_t
{
struct CPU {
uint32_tVendor;// Vendor - char Vendor[16];
charBrandString[48];// 48 Byte Branding String
//uint16_tType;// Type
uint8_tFamily;// Family
uint8_tModel;// Model
uint8_tExtModel;// Extended Model
uint8_tExtFamily;// Extended Family
uint8_tStepping;// Stepping
uint64_tFeatures;// CPU Features like MMX, SSE2, VT, MobileCPU
uint32_tVendor;// Vendor - char Vendor[16];
charBrandString[48];// 48 Byte Branding String
//uint16_tType;// Type
uint8_tFamily;// Family
uint8_tModel;// Model
uint8_tExtModel;// Extended Model
uint8_tExtFamily;// Extended Family
uint8_tStepping;// Stepping
uint64_tFeatures;// CPU Features like MMX, SSE2, VT, MobileCPU
uint64_tExtFeatures;
uint32_tCoresPerPackage;
uint32_tLogicalPerPackage;
uint32_tSignature;// Processor Signature
uint32_tSignature;// Processor Signature
//uint8_tBrand;
//uint8_tProcessorFlag;
uint32_tNoCores;// No Cores per Package
uint32_tNoThreads;// Threads per Package
uint32_tNoCores;// No Cores per Package
uint32_tNoThreads;// Threads per Package
//uint32_tCacheSize[LCACHE_MAX];
//uint32_tCacheLineSize;
//uint8_tcache_info[64];// list of cache descriptors
//uint8_tcache_info[64];// list of cache descriptors
uint8_tMaxCoef;// Max Multiplier
uint8_tMaxDiv;// Min Multiplier
uint8_tCurrCoef;// Current Multiplier
uint8_tMaxCoef;// Max Multiplier
uint8_tMaxDiv;// Min Multiplier
uint8_tCurrCoef;// Current Multiplier
uint8_tCurrDiv;
uint64_tTSCFrequency;// TSC Frequency Hz
uint64_tFSBFrequency;// FSB Frequency Hz
uint64_tCPUFrequency;// CPU Frequency Hz
uint32_tMaxRatio;// Max Bus Ratio
uint32_tMinRatio;// Min Bus Ratio
uint32_tCPUID[CPUID_MAX][4];// CPUID 0..4, 80..81 Raw Values
uint64_tTSCFrequency;// TSC Frequency Hz
uint64_tFSBFrequency;// FSB Frequency Hz
uint64_tCPUFrequency;// CPU Frequency Hz
uint32_tMaxRatio;// Max Bus Ratio
uint32_tMinRatio;// Min Bus Ratio
uint32_tCPUID[CPUID_MAX][4];// CPUID 0..4, 80..81 Raw Values
uint32_tMCodeVersion;// CPU Microcode version
uint32_tMCodeVersion;// CPU Microcode version
} CPU;
struct RAM {
uint64_tFrequency;// Ram Frequency
uint32_tDivider;// Memory divider
uint8_tCAS;// CAS 1/2/2.5/3/4/5/6/7
uint8_tTRC;
uint64_tFrequency;// Ram Frequency
uint32_tDivider;// Memory divider
uint8_tCAS;// CAS 1/2/2.5/3/4/5/6/7
uint8_tTRC;
uint8_tTRP;
uint8_tRAS;
uint8_tChannels;// Channel Configuration Single,Dual or Triple
uint8_tNoSlots;// Maximum no of slots available
uint8_tType;// Standard SMBIOS v2.5 Memory Type
RamSlotInfo_tDIMM[MAX_RAM_SLOTS];// Information about each slot
uint8_tChannels;// Channel Configuration Single,Dual or Triple
uint8_tNoSlots;// Maximum no of slots available
uint8_tType;// Standard SMBIOS v2.5 Memory Type
RamSlotInfo_tDIMM[MAX_RAM_SLOTS];// Information about each slot
} RAM;
struct DMI {
intDIMM[MAX_RAM_SLOTS];// Information and SPD mapping for each slot
} DMI;
uint8_tType;// System Type: 1=Desktop, 2=Portable, 3=Workstation... according ACPI2.0 (FACP: PM_Profile)
uint8_t*UUID;
uint8_tType;// system-type: 1=Desktop, 2=Portable, 3=Workstation... according ACPI2.0 (FACP: PM_Profile)
uint8_t*UUID;// system-id (SMBIOS Table 1: system uuid)
} PlatformInfo_t;
extern PlatformInfo_t Platform;
branches/ErmaC/Enoch/i386/libsaio/smbios.h
566566
567567
568568
569
569
570570
571571
572572
SMBString serialNumber;
SMBString assetTag;
SMBString partNumber;
// 2.5+ spec (40 bytes)
// 2.5+ spec (40 bytes) Apple still uses 2.4 spec
SMBByte coreCount;
SMBByte coreEnabled;
SMBByte threadCount;
branches/ErmaC/Enoch/i386/libsaio/convert.c
2424
2525
2626
27
27
28
29
30
2831
2932
3033
/** Parse an UUID string into an (EFI_CHAR8*) buffer */
EFI_CHAR8* getUUIDFromString(const char *source)
{
if (!source) return 0;
if (!source)
{
return 0;
}
char*p = (char *)source;
inti;
branches/ErmaC/Enoch/i386/libsaio/pci.h
8181
8282
8383
84
85
86
84
85
86
8787
88
88
8989
9090
9191
......
937937
938938
939939
940
940
941941
942942
943943
/* Option ROM header */
typedef struct {
uint16_tsignature;// 0xAA55
uint8_trom_size;//in 512 bytes blocks
uint8_tjump;//0xE9 for ATI and Intel, 0xEB for NVidia
uint32_tentry_point;
uint8_trom_size;// in 512 bytes blocks
uint8_tjump;// 0xE9 for ATI and Intel, 0xEB for NVidia
uint8_tentry_point[4];// offset to
uint8_treserved[16];
uint16_tpci_header_offset;//@0x18
uint16_tpci_header_offset;// @0x18
uint16_texpansion_header_offset;
} option_rom_header_t;
#define PCI_CLASS_SIGNAL_OTHER0x1180
// values for the class_sub field for class_base = 0xff (Device does not fit any defined class)
#define PCI_CLASS_OTHERS 0xff
#define PCI_CLASS_OTHERS0xff
/* Several ID's we need in the library */
#define PCI_VENDOR_ID_LOGITECH0x046d
branches/ErmaC/Enoch/i386/boot2/boot.c
721721
722722
723723
724
724
725725
726726
727727
}
else
{
DBG("Kernel Cache using disabled by user.");
DBG("Kernel Cache using disabled by user.\n");
}
do
branches/ErmaC/Enoch/i386/libsa/memory.h
9090
9191
9292
93
9493
94
95
9596
9697
9798
#define KERNEL_LEN 0x08000000
#define ZALLOC_ADDR 0x08100000 // 256M zalloc area
#define ZALLOC_LEN 0x14000000
#define ZALLOC_LEN 0x14000000 // Pike R. Alpha: was 0x10000000
#define LOAD_ADDR 0x18100000 // 64M File load buffer
#define LOAD_LEN 0x04000000

Archive Download the corresponding diff file

Revision: 2550