Chameleon

Chameleon Commit Details

Date:2015-01-26 00:45:09 (9 years 2 months ago)
Author:ErmaC
Commit:2554
Parents: 2553
Message:Typo.
Changes:
M/trunk/i386/libsaio/hda.h
M/trunk/i386/libsaio/smbios.h
M/trunk/i386/boot2/graphics.c
M/trunk/i386/libsaio/gma.c
M/trunk/i386/libsa/memory.h
M/trunk/i386/boot2/boot.c
M/trunk/i386/libsaio/spd.c
M/trunk/i386/libsaio/fake_efi.c
M/trunk/i386/libsaio/gma.h
M/trunk/i386/libsaio/platform.h
M/trunk/i386/libsaio/hda.c
M/trunk/i386/libsaio/smbios.c
M/trunk/i386/libsaio/sys.c
M/trunk/i386/libsaio/pci.h

File differences

trunk/i386/libsaio/spd.c
2727
2828
2929
30
31
32
33
34
35
36
37
38
39
40
41
30
31
32
33
34
35
36
37
38
39
40
41
42
4243
4344
4445
......
109110
110111
111112
112
113
113114
114115
115116
......
172173
173174
174175
176
175177
176178
177179
......
294296
295297
296298
297
299
298300
299301
300302
301303
304
302305
306
303307
304308
305309
␊
static const char *spd_memory_types[] =␊
{␊
␉"RAM", /* 00h Undefined */␊
␉"FPM", /* 01h FPM */␊
␉"EDO", /* 02h EDO */␊
␉"",␉␉/* 03h PIPELINE NIBBLE */␊
␉"SDRAM", /* 04h SDRAM */␊
␉"",␉␉/* 05h MULTIPLEXED ROM */␊
␉"DDR SGRAM",␉/* 06h SGRAM DDR */␊
␉"DDR SDRAM",␉/* 07h SDRAM DDR */␊
␉"DDR2 SDRAM", /* 08h SDRAM DDR 2 */␊
␉"",␉␉/* 09h Undefined */␊
␉"",␉␉/* 0Ah Undefined */␊
␉"DDR3 SDRAM"␉/* 0Bh SDRAM DDR 3 */␊
␉"RAM",␉␉␉␉/* 00h Undefined */␊
␉"STD FPM DRAM",␉␉␉/* 01h FPM */␊
␉"EDO",␉␉␉␉/* 02h EDO */␊
␉"PIPE NIBBLE",␉␉␉/* 03h PIPELINE NIBBLE */␊
␉"SDRAM",␉␉␉/* 04h SDRAM */␊
␉"ROM",␉␉␉␉/* 05h MULTIPLEXED ROM */␊
␉"DDR SGRAM"␉␉␉/* 06h SGRAM DDR */␊
␉"DDR SDRAM",␉␉␉/* 07h SDRAM DDR */␊
␉"DDR2 SDRAM",␉␉␉/* 08h SDRAM DDR 2 */␊
␉"DDR2 SDRAM FB-DIMM",␉␉/* 09h Undefined */␊
␉"DDR2 SDRAM FB-DIMM Probe",␉/* 0Ah Undefined */␊
␉"DDR3 SDRAM",␉␉␉/* 0Bh SDRAM DDR 3 */␊
␉"DDR4 SDRAM"␉␉␉/* 0Ch SDRAM DDR 4 */␊
};␊
␊
#define UNKNOWN_MEM_TYPE 2␊
␊
␉rdtsc(l1, h1);␊
␊
␉while (!( inb(base + SMBHSTSTS) & 0x02))␉// wait til command finished␊
␉while (!( inb(base + SMBHSTSTS) & 0x02))␉// wait till command finished␊
␉{␊
␉␉rdtsc(l2, h2);␊
␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
␉␉␉code = spd[64];␊
␉␉␉bank = 0;␊
␉␉}␊
␊
␉␉for (i=0; i < VEN_MAP_SIZE; i++)␊
␉␉{␊
␉␉␉if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
␉int␉␉i, speed;␊
␉uint8_t␉␉spd_size, spd_type;␊
␉uint32_t␉base, mmio, hostc;␊
␉uint16_t␉cmd;␊
␉uint16_t␉cmd;␉␉// Command␊
//␉bool␉␉dump = false;␊
␉RamSlotInfo_t␉*slot;␊
␊
␉cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);␊
␊
␉DBG("SMBus CmdReg: 0x%x\n", cmd);␊
␊
␉pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);␊
␊
␉mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;␊
trunk/i386/libsaio/gma.c
213213
214214
215215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262262
263
264
265
263
264
265
266266
267267
268268
269269
270
271
272
270
271
272
273273
274
275
276
277
278
279
280
281
282
283
274
275
276
277
278
279
280
281
282
283
284284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306306
307307
308
309
310
311
308
309
310
311
312312
313
314
313
314
315315
316
317
316
317
318318
319319
320
320
321321
322
323
324
325
326
327
322
323
324
325
326
327
328328
329
330
331
332
333
334
329
330
331
332
333
334
335335
336
337
336
337
338338
339
340
339
340
341341
342
342
343343
344344
345345
......
390390
391391
392392
393
393
394
394395
395396
396397
397398
398
399
400
399401
400402
401403
......
415417
416418
417419
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
436438
437
438
439
440
441
442
443
444
439
440
441
442
443
444
445
446
445447
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
477479
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
499501
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
523525
524
525
526
527
528
529
530
531
532
533
534
526
527
528
529
530
531
532
533
534
535
536
535537
536
537
538
539
540
541
542
543
544
545
546
547
538
539
540
541
542
543
544
545
546
547
548
549
548550
549
550
551
552
553
554
555
556
557
558
559
551
552
553
554
555
556
557
558
559
560
561
560562
561
562
563
564
565
563
566564
567
565
568566
569
570
571
567
568
569
570
571
572
573
574
575
572576
573
574
575
576
577
577
578578
579
580
579
580
581
582
583
584
585
586
587
581588
582589
583590
584
585
586
587
588
589
590
591
592
593
594
595
591
592
593
594
595
596
597
596598
597
598
599
599
600
601
600602
601
602
603
603
604
605
604606
605
606
607
608
609
610
607
608
609
610
611
612
613
614
611615
612
613
614616
615
616
617
618
619
617
618
619
620
621
620622
621
622
623
624
625
626
627
628
629
630
631
632
633
634
623
624
625
626
627
628
629
630
631
632
633
634
635
636
635637
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
674676
675
676
677
678
679
677
680678
681
679
682680
683
684
685
681
682
683
684
685
686
687
688
689
686690
687
688
689
690
691
691
692692
693
694
693
694
695
696
697
698
699
700
701
695702
696703
697704
698
705
706
699707
700
701
702
703
704
705
706708
707
708
709
710
711
709
710
711
712
713
712714
713
714
715
716
715717
716718
717719
/* http://cgit.freedesktop.org/xorg/driver/xf86-video-intel/tree/src/intel_module.c */␊
␊
static intel_gfx_info_t intel_gfx_chipsets[] = {␊
␉{GMA_I810, "i810"},␊
␉{GMA_I810_DC100, "i810-dc100"},␊
␉{GMA_I810_E, "i810e"},␊
␉{GMA_I815, "i815"},␊
␉{GMA_I830_M, "i830M"},␊
␉{GMA_845_G, "845G"},␊
␉{GMA_I854, "854"},␊
␉{GMA_I855_GM, "852GM/855GM"},␊
␉{GMA_I865_G, "865G"},␊
␉{GMA_I915_G, "915G"},␊
␉{GMA_E7221_G, "E7221 (i915)"},␊
␉{GMA_I915_GM, "915GM"},␊
␉{GMA_I945_G, "945G"},␊
// 2776 /* Desktop GMA950 */␊
// 2782 /* GMA 915 */␊
// 2792 /* Mobile GMA915 */␊
␉{GMA_I945_GM, "945GM"},␊
␉{GMA_I945_GME, "945GME"},␊
// 27A6 /* Mobile GMA950 */␊
// 29C3 /* Desktop GMA3100 */␊
␉{GMA_PINEVIEW_M, "Pineview GM"},␊
␉{GMA_GMA3150_M, "Pineview GM"},// A012 /* Mobile GMA3150 */␊
␉{GMA_PINEVIEW_G, "Pineview G"},␊
␉{GMA_GMA3150_D, "Desktop GMA3150"}, // A002 /* Desktop GMA3150 */␊
␉{GMA_I965_G, "965G"},␊
␉{GMA_G35_G, "G35"},␊
␉{GMA_I965_Q, "965Q"},␊
␉{GMA_I946_GZ, "946GZ"},␊
␉{GMA_I965_GM, "965GM"},␊
␉{GMA_I965_GME, "965GME/GLE"},␊
␉{GMA_G33_G, "G33"},␊
// 2A13 /* GMAX3100 */␊
// 2A43 /* GMAX3100 */␊
␉{GMA_Q35_G, "Q35"},␊
␉{GMA_Q33_G, "Q33"},␊
␉{GMA_GM45_GM, "GM45"},␊
␉{GMA_G45_E_G, "4 Series"},␊
␉{GMA_G45_G, "G45/G43"},␊
␉{GMA_Q45_G, "Q45/Q43"},␊
␉{GMA_G41_G, "G41"},␊
␉{GMA_B43_G, "B43"},␊
␉{GMA_B43_G1, "B43"},␊
/**/␊
␉{GMA_IRONLAKE_D_G, HD_GRAPHICS},␊
␉{GMA_IRONLAKE_M_G, HD_GRAPHICS},␊
// 004A /* HD2000 */␊
␉{GMA_I810,␉␉␉"i810"},␊
␉{GMA_I810_DC100,␉␉"i810-dc100"},␊
␉{GMA_I810_E,␉␉␉"i810e"},␊
␉{GMA_I815,␉␉␉"i815"},␊
␉{GMA_I830_M,␉␉␉"i830M"},␊
␉{GMA_845_G,␉␉␉"845G"},␊
␉{GMA_I854,␉␉␉"854"},␊
␉{GMA_I855_GM,␉␉␉"852GM/855GM"},␊
␉{GMA_I865_G,␉␉␉"865G"},␊
␉{GMA_I915_G,␉␉␉"915G"},␊
␉{GMA_E7221_G,␉␉␉"E7221 (i915)"},␊
␉{GMA_I915_GM,␉␉␉"915GM"},␊
␉{GMA_I945_G,␉␉␉"945G"},␊
␉// 2776 /* Desktop GMA950 */␊
␉// 2782 /* GMA 915 */␊
␉// 2792 /* Mobile GMA915 */␊
␉{GMA_I945_GM,␉␉␉"945GM"},␊
␉{GMA_I945_GME,␉␉␉"945GME"},␊
␉// 27A6 /* Mobile GMA950 */␊
␉// 29C3 /* Desktop GMA3100 */␊
␉{GMA_PINEVIEW_M,␉␉"Pineview GM"},␊
␉{GMA_GMA3150_M,␉␉␉"Pineview GM"},␉␉// A012 /* Mobile GMA3150 */␊
␉{GMA_PINEVIEW_G,␉␉"Pineview G"},␊
␉{GMA_GMA3150_D,␉␉␉"Desktop GMA3150"},␉// A002 /* Desktop GMA3150 */␊
␉{GMA_I965_G,␉␉␉"965G"},␊
␉{GMA_G35_G,␉␉␉"G35"},␊
␉{GMA_I965_Q,␉␉␉"965Q"},␊
␉{GMA_I946_GZ,␉␉␉"946GZ"},␊
␉{GMA_I965_GM,␉␉␉"965GM"},␊
␉{GMA_I965_GME,␉␉␉"965GME/GLE"},␊
␉{GMA_G33_G,␉␉␉"G33"},␊
␉// 2A13 /* GMAX3100 */␊
␉// 2A43 /* GMAX3100 */␊
␉{GMA_Q35_G,␉␉␉"Q35"},␊
␉{GMA_Q33_G,␉␉␉"Q33"},␊
␉{GMA_GM45_GM,␉␉␉"GM45"},␊
␉{GMA_G45_E_G,␉␉␉"4 Series"},␊
␉{GMA_G45_G,␉␉␉"G45/G43"},␊
␉{GMA_Q45_G,␉␉␉"Q45/Q43"},␊
␉{GMA_G41_G,␉␉␉"G41"},␊
␉{GMA_B43_G,␉␉␉"B43"},␊
␉{GMA_B43_G1,␉␉␉"B43"},␊
␉/**/␊
␉{GMA_IRONLAKE_D_G,␉␉HD_GRAPHICS},␊
␉{GMA_IRONLAKE_M_G,␉␉HD_GRAPHICS},␊
␉// 004A /* HD2000 */␊
␊
/* Sandy */␊
␉{GMA_SANDYBRIDGE_GT1, HD_GRAPHICS_2000 },␊
␉{GMA_SANDYBRIDGE_GT2, HD_GRAPHICS_3000 },␊
␉/* Sandy */␊
␉{GMA_SANDYBRIDGE_GT1,␉␉HD_GRAPHICS_2000 },␊
␉{GMA_SANDYBRIDGE_GT2,␉␉HD_GRAPHICS_3000 },␊
␉{GMA_SANDYBRIDGE_GT2_PLUS,␉HD_GRAPHICS_3000 },␊
␉{GMA_SANDYBRIDGE_M_GT1,␉␉HD_GRAPHICS_2000 },␊
␉{GMA_SANDYBRIDGE_M_GT2,␉␉HD_GRAPHICS_3000 },␊
␉{GMA_SANDYBRIDGE_M_GT2_PLUS,␉HD_GRAPHICS_3000 },␊
␉{GMA_SANDYBRIDGE_S_GT, HD_GRAPHICS },␊
// 010B /* ??? */␊
// 010E /* ??? */␊
␉{GMA_SANDYBRIDGE_S_GT,␉␉HD_GRAPHICS },␊
␉// 010B /* ??? */␊
␉// 010E /* ??? */␊
␊
/* Ivy */␊
␉{GMA_IVYBRIDGE_M_GT1, HD_GRAPHICS_2500 },␊
␉{GMA_IVYBRIDGE_M_GT2, HD_GRAPHICS_4000 },␊
␉{GMA_IVYBRIDGE_D_GT1, HD_GRAPHICS_2500 },␊
␉{GMA_IVYBRIDGE_D_GT2, HD_GRAPHICS_4000 },␊
␉{GMA_IVYBRIDGE_S_GT1, HD_GRAPHICS },␊
␉{GMA_IVYBRIDGE_S_GT2, "HD Graphics P4000" },␊
␉{GMA_IVYBRIDGE_S_GT3, HD_GRAPHICS }, // 015e␊
␉{GMA_IVYBRIDGE_S_GT4, HD_GRAPHICS_2500 }, // 0172 /* HD Graphics 2500 Mobile */␊
␉{GMA_IVYBRIDGE_S_GT5, HD_GRAPHICS_2500 }, // 0176 /* HD Graphics 2500 Mobile */␊
␉/* Ivy */␊
␉{GMA_IVYBRIDGE_M_GT1,␉␉HD_GRAPHICS_2500 },␊
␉{GMA_IVYBRIDGE_M_GT2,␉␉HD_GRAPHICS_4000 },␊
␉{GMA_IVYBRIDGE_D_GT1,␉␉HD_GRAPHICS_2500 },␊
␉{GMA_IVYBRIDGE_D_GT2,␉␉HD_GRAPHICS_4000 },␊
␉{GMA_IVYBRIDGE_S_GT1,␉␉HD_GRAPHICS },␊
␉{GMA_IVYBRIDGE_S_GT2,␉␉"HD Graphics P4000" },␊
␉{GMA_IVYBRIDGE_S_GT3,␉␉ HD_GRAPHICS },␉␉// 015e␊
␉{GMA_IVYBRIDGE_S_GT4,␉␉HD_GRAPHICS_2500 },␉// 0172 /* HD Graphics 2500 Mobile */␊
␉{GMA_IVYBRIDGE_S_GT5,␉␉HD_GRAPHICS_2500 },␉// 0176 /* HD Graphics 2500 Mobile */␊
␊
/* Haswell */␊
// 0090 /* ??? */␊
// 0091 /* ??? */␊
// 0092 /* ??? */␊
␉{GMA_HASWELL_D_GT1, HD_GRAPHICS },␊
␉{GMA_HASWELL_D_GT2, HD_GRAPHICS_4600 }, /* 0412 */␊
␉{GMA_HASWELL_D_GT3, HD_GRAPHICS_5000 }, /* ??? */␊
␉{GMA_HASWELL_M_GT1, HD_GRAPHICS },␊
␉{GMA_HASWELL_M_GT2, HD_GRAPHICS_4600 }, /* 0416 */␊
␉{GMA_HASWELL_M_GT3, HD_GRAPHICS_5000 }, /* ??? */␊
␉{GMA_HASWELL_S_GT1, HD_GRAPHICS },␊
␉{GMA_HASWELL_S_GT2, "HD Graphics P4600/P4700" },␊
␉{GMA_HASWELL_S_GT3, HD_GRAPHICS_5000 }, /* ??? */␊
␉{GMA_HASWELL_B_GT1, HD_GRAPHICS }, /* ??? */␊
␉{GMA_HASWELL_B_GT2, HD_GRAPHICS }, /* ??? */␊
␉{GMA_HASWELL_B_GT3, HD_GRAPHICS }, /* ??? */␊
␉{GMA_HASWELL_E_GT1, HD_GRAPHICS },␊
␉{GMA_HASWELL_E_GT2, HD_GRAPHICS_4400 }, /* 041e */␊
␉{GMA_HASWELL_E_GT3, HD_GRAPHICS }, /* ??? */␊
␉{GMA_HASWELL_ULT_D_GT1,␉␉HD_GRAPHICS }, /* ??? */␊
␉{GMA_HASWELL_ULT_D_GT2,␉␉HD_GRAPHICS }, /* ??? */␊
␉/* Haswell */␊
␉// 0090 /* ??? */␊
␉// 0091 /* ??? */␊
␉// 0092 /* ??? */␊
␉{GMA_HASWELL_D_GT1,␉␉HD_GRAPHICS },␊
␉{GMA_HASWELL_D_GT2,␉␉HD_GRAPHICS_4600 },␉/* 0412 */␊
␉{GMA_HASWELL_D_GT3,␉␉HD_GRAPHICS_5000 },␉/* ??? */␊
␉{GMA_HASWELL_M_GT1,␉␉HD_GRAPHICS },␊
␉{GMA_HASWELL_M_GT2,␉␉HD_GRAPHICS_4600 },␉/* 0416 */␊
␉{GMA_HASWELL_M_GT3,␉␉HD_GRAPHICS_5000 },␉/* ??? */␊
␉{GMA_HASWELL_S_GT1,␉␉HD_GRAPHICS },␊
␉{GMA_HASWELL_S_GT2,␉␉"HD Graphics P4600/P4700" },␊
␉{GMA_HASWELL_S_GT3,␉␉HD_GRAPHICS_5000 },␉/* ??? */␊
␉{GMA_HASWELL_B_GT1,␉␉HD_GRAPHICS },␉␉/* ??? */␊
␉{GMA_HASWELL_B_GT2,␉␉HD_GRAPHICS },␉␉/* ??? */␊
␉{GMA_HASWELL_B_GT3,␉␉HD_GRAPHICS },␉␉/* ??? */␊
␉{GMA_HASWELL_E_GT1,␉␉HD_GRAPHICS },␊
␉{GMA_HASWELL_E_GT2,␉␉HD_GRAPHICS_4400 },␉/* 041e */␊
␉{GMA_HASWELL_E_GT3,␉␉HD_GRAPHICS },␉␉/* ??? */␊
␉{GMA_HASWELL_ULT_D_GT1,␉␉HD_GRAPHICS },␉␉/* ??? */␊
␉{GMA_HASWELL_ULT_D_GT2,␉␉HD_GRAPHICS },␉␉/* ??? */␊
␉{GMA_HASWELL_ULT_D_GT3,␉␉IRIS_5100 },␊
␉{GMA_HASWELL_ULT_M_GT1,␉␉HD_GRAPHICS },␊
␉{GMA_HASWELL_ULT_M_GT2,␉␉HD_GRAPHICS_4400 }, /* 0a16 */␊
␉{GMA_HASWELL_ULT_M_GT3,␉␉HD_GRAPHICS_5000 }, /* 0a26 */␊
␉{GMA_HASWELL_ULT_S_GT1,␉␉HD_GRAPHICS }, /* ??? */␊
␉{GMA_HASWELL_ULT_S_GT2,␉␉HD_GRAPHICS }, /* ??? */␊
␉{GMA_HASWELL_ULT_M_GT2,␉␉HD_GRAPHICS_4400 },␉/* 0a16 */␊
␉{GMA_HASWELL_ULT_M_GT3,␉␉HD_GRAPHICS_5000 },␉/* 0a26 */␊
␉{GMA_HASWELL_ULT_S_GT1,␉␉HD_GRAPHICS },␉␉/* ??? */␊
␉{GMA_HASWELL_ULT_S_GT2,␉␉HD_GRAPHICS },␉␉/* ??? */␊
␉{GMA_HASWELL_ULT_S_GT3,␉␉IRIS_5100 },␊
␉{GMA_HASWELL_ULT_B_GT1,␉␉HD_GRAPHICS }, /* ??? */␊
␉{GMA_HASWELL_ULT_B_GT2,␉␉HD_GRAPHICS }, /* ??? */␊
␉{GMA_HASWELL_ULT_B_GT1,␉␉HD_GRAPHICS },␉␉/* ??? */␊
␉{GMA_HASWELL_ULT_B_GT2,␉␉HD_GRAPHICS },␉␉/* ??? */␊
␉{GMA_HASWELL_ULT_B_GT3,␉␉IRIS_5100 },␊
␉{GMA_HASWELL_ULT_E_GT1,␉␉HD_GRAPHICS_4400 }, /* 0a0e */␊
␉{GMA_HASWELL_ULT_E_GT2,␉␉HD_GRAPHICS_4200 }, /* 0a1e */␊
␉{GMA_HASWELL_ULT_E_GT1,␉␉HD_GRAPHICS_4400 },␉/* 0a0e */␊
␉{GMA_HASWELL_ULT_E_GT2,␉␉HD_GRAPHICS_4200 },␉/* 0a1e */␊
␉// 0A2A /* ??? */␊
␉{GMA_HASWELL_ULT_E_GT3,␉␉IRIS_5100 },␊
␉{GMA_HASWELL_SDV_D_GT1_IG,␉␉HD_GRAPHICS }, // 0C02 /* Intel Haswell HD Graphics - GTL */␊
␉{GMA_HASWELL_SDV_D_GT1_IG,␉HD_GRAPHICS },␉␉// 0C02 /* Intel Haswell HD Graphics - GTL */␊
␉// 0C04 /* DRAM Controller */␊
␉{GMA_HASWELL_SDV_M_GT1_IG,␉␉HD_GRAPHICS }, // 0C06 /* Intel Haswell HD Graphics - GTL */␊
␉{GMA_HASWELL_SDV_D_GT2_IG,␉␉HD_GRAPHICS }, // 0C12 /* Intel Haswell HD Graphics - GTM */␊
␉{GMA_HASWELL_SDV_M_GT2_IG,␉␉HD_GRAPHICS }, // 0C16 /* Intel Haswell HD Graphics - GTH */␊
␉{GMA_HASWELL_SDV_D_GT2_PLUS_IG,␉␉HD_GRAPHICS }, // 0C22 /* Intel Haswell HD Graphics - GTH */␊
␉{GMA_HASWELL_SDV_M_GT2_PLUS_IG,␉␉HD_GRAPHICS }, // 0C26 /* Intel Haswell HD Graphics - GTH */␊
␉{GMA_HASWELL_CRW_D_GT1,␉␉HD_GRAPHICS }, /* 0d02 */␊
␉{GMA_HASWELL_SDV_M_GT1_IG,␉HD_GRAPHICS },␉␉// 0C06 /* Intel Haswell HD Graphics - GTL */␊
␉{GMA_HASWELL_SDV_D_GT2_IG,␉HD_GRAPHICS },␉␉// 0C12 /* Intel Haswell HD Graphics - GTM */␊
␉{GMA_HASWELL_SDV_M_GT2_IG,␉HD_GRAPHICS },␉␉// 0C16 /* Intel Haswell HD Graphics - GTH */␊
␉{GMA_HASWELL_SDV_D_GT2_PLUS_IG,␉HD_GRAPHICS },␉␉// 0C22 /* Intel Haswell HD Graphics - GTH */␊
␉{GMA_HASWELL_SDV_M_GT2_PLUS_IG,␉HD_GRAPHICS },␉␉// 0C26 /* Intel Haswell HD Graphics - GTH */␊
␉{GMA_HASWELL_CRW_D_GT1,␉␉HD_GRAPHICS },␉␉/* 0d02 */␊
␉{GMA_HASWELL_CRW_D_GT2,␉␉HD_GRAPHICS_4600 },␊
␉{GMA_HASWELL_CRW_D_GT3,␉␉IRIS_5200 }, /* 0d22 */␊
␉{GMA_HASWELL_CRW_M_GT1,␉␉HD_GRAPHICS }, /* 0d06 */␊
␉{GMA_HASWELL_CRW_M_GT2,␉␉HD_GRAPHICS_4600 }, /* 0d16 */␊
␉{GMA_HASWELL_CRW_M_GT3,␉␉IRIS_5200 }, /* 0d26 */␊
␉{GMA_HASWELL_CRW_S_GT1,␉␉HD_GRAPHICS }, /* 0d0a */␊
␉{GMA_HASWELL_CRW_S_GT2,␉␉HD_GRAPHICS }, /* 0d1a */␊
␉{GMA_HASWELL_CRW_D_GT3,␉␉IRIS_5200 },␉␉/* 0d22 */␊
␉{GMA_HASWELL_CRW_M_GT1,␉␉HD_GRAPHICS },␉␉/* 0d06 */␊
␉{GMA_HASWELL_CRW_M_GT2,␉␉HD_GRAPHICS_4600 },␉/* 0d16 */␊
␉{GMA_HASWELL_CRW_M_GT3,␉␉IRIS_5200 },␉␉/* 0d26 */␊
␉{GMA_HASWELL_CRW_S_GT1,␉␉HD_GRAPHICS },␉␉/* 0d0a */␊
␉{GMA_HASWELL_CRW_S_GT2,␉␉HD_GRAPHICS },␉␉/* 0d1a */␊
␉{GMA_HASWELL_CRW_S_GT3,␉␉IRIS_5200 },␊
␉{GMA_HASWELL_CRW_B_GT1,␉␉HD_GRAPHICS }, /* 0d0b */␊
␉{GMA_HASWELL_CRW_B_GT2,␉␉HD_GRAPHICS }, /* 0d1b */␊
␉{GMA_HASWELL_CRW_B_GT1,␉␉HD_GRAPHICS },␉␉/* 0d0b */␊
␉{GMA_HASWELL_CRW_B_GT2,␉␉HD_GRAPHICS },␉␉/* 0d1b */␊
␉{GMA_HASWELL_CRW_B_GT3,␉␉IRIS_5200 },␊
␉{GMA_HASWELL_CRW_E_GT1,␉␉HD_GRAPHICS }, /* 0d0e */␊
␉{GMA_HASWELL_CRW_E_GT2,␉␉HD_GRAPHICS }, /* od1e */␊
␉{GMA_HASWELL_CRW_E_GT1,␉␉HD_GRAPHICS },␉␉/* 0d0e */␊
␉{GMA_HASWELL_CRW_E_GT2,␉␉HD_GRAPHICS },␉␉/* od1e */␊
␉{GMA_HASWELL_CRW_E_GT3,␉␉IRIS_5200 },␊
␉{GMA_HASWELL_CRW_M_GT2_PLUS_IG,␉␉HD_GRAPHICS }␊
␉{GMA_HASWELL_CRW_M_GT2_PLUS_IG,␉HD_GRAPHICS }␊
};␊
␊
#define GFX_DEVICES_LEN (sizeof(intel_gfx_chipsets) / sizeof(intel_gfx_chipsets[0]))␊
␉verbose("Class code: [%04x]\n%s [%04x:%04x] (rev %02x)\nSubsystem: [%04x:%04x] :: %s\n",␊
␉␉␉gma_dev->class_id, model, gma_dev->vendor_id, gma_dev->device_id, gma_dev->revision_id, gma_dev->subsys_id.subsys.vendor_id, gma_dev->subsys_id.subsys.device_id, devicepath);␊
␊
␉if (!string) {␊
␉if (!string)␊
␉{␊
␉␉string = devprop_create_string();␊
␉}␊
␊
␉struct DevPropDevice *device = devprop_add_device(string, devicepath);␊
␉if (!device) {␊
␉if (!device)␊
␉{␊
␉␉printf("[setup_gma_devprop] Failed initializing dev-prop string dev-entry!\n");␊
␉␉pause();␊
␉␉return false;␊
␊
␉switch ((device_id << 16) | vendor_id)␊
␉{␊
case GMA_IRONLAKE_D_G: // 0042␊
case GMA_IRONLAKE_M_G: // 0046␊
devprop_add_value(device, "built-in", &BuiltIn, 1);␊
devprop_add_value(device, "class-code", ClassFix, 4);␊
//devprop_add_value(device, "hda-gfx",␉␉␉(uint8_t *)"onboard-1", 10);␊
devprop_add_value(device, "AAPL,os-info",␉␉␉HDx000_os_info, 20);␊
break;␊
/* 27A2, 27AE, 27A6, A001, A011, A012, */␊
case GMA_I945_GM: // Mobile GMA950 Mobile GMA3150␊
case GMA_I945_GME:␊
//case GMA_945GM:␊
case GMA_PINEVIEW_G:␊
case GMA_PINEVIEW_M:␊
case GMA_GMA3150_M:␊
devprop_add_value(device, "AAPL,HasPanel", reg_TRUE, 4);␊
devprop_add_value(device, "built-in", &BuiltIn, 1);␊
devprop_add_value(device, "class-code", ClassFix, 4);␊
break;␊
␉␉case GMA_IRONLAKE_D_G: // 0042␊
␉␉case GMA_IRONLAKE_M_G: // 0046␊
␉␉␉devprop_add_value(device, "built-in",␉␉&BuiltIn, 1);␊
␉␉␉devprop_add_value(device, "class-code",␉␉ClassFix, 4);␊
␉␉␉//devprop_add_value(device, "hda-gfx",␉␉(uint8_t *)"onboard-1", 10);␊
␉␉␉devprop_add_value(device, "AAPL,os-info",␉HDx000_os_info, 20);␊
␉␉␉break;␊
␉␉/* 27A2, 27AE, 27A6, A001, A011, A012, */␊
␉␉case GMA_I945_GM: // Mobile GMA950 Mobile GMA3150␊
␉␉case GMA_I945_GME:␊
␉␉//case GMA_945GM:␊
␉␉case GMA_PINEVIEW_G:␊
␉␉case GMA_PINEVIEW_M:␊
␉␉case GMA_GMA3150_M:␊
␉␉␉devprop_add_value(device, "AAPL,HasPanel",␉reg_TRUE, 4);␊
␉␉␉devprop_add_value(device, "built-in",␉␉&BuiltIn, 1);␊
␉␉␉devprop_add_value(device, "class-code",␉␉ClassFix, 4);␊
␉␉␉break;␊
␊
/* 2772 ,2776, A002 */␊
case GMA_I945_G: // Desktop GMA950 Desktop GMA3150␊
//case GMA_82945G:␊
case GMA_GMA3150_D:␊
BuiltIn = 0x01;␊
devprop_add_value(device, "built-in", &BuiltIn, 1);␊
devprop_add_value(device, "class-code", ClassFix, 4);␊
break;␊
␉␉/* 2772 ,2776, A002 */␊
␉␉case GMA_I945_G: // Desktop GMA950 Desktop GMA3150␊
␉␉//case GMA_82945G:␊
␉␉case GMA_GMA3150_D:␊
␉␉␉BuiltIn = 0x01;␊
␉␉␉devprop_add_value(device, "built-in",␉␉&BuiltIn, 1);␊
␉␉␉devprop_add_value(device, "class-code",␉␉ClassFix, 4);␊
␉␉␉break;␊
␊
/* 2A02, 2A12, 2A13, 2A42, 2A43 */␊
case GMA_I965_GM: // GMAX3100␊
case GMA_I965_GME:␊
//case 0x80862A13:␊
case GMA_GM45_GM:␊
//case GMA_GM45_GM2:␊
devprop_add_value(device, "AAPL,HasPanel", GMAX3100_vals[0], 4);␊
devprop_add_value(device, "AAPL,SelfRefreshSupported",␉GMAX3100_vals[1], 4);␊
devprop_add_value(device, "AAPL,aux-power-connected",␉GMAX3100_vals[2], 4);␊
devprop_add_value(device, "AAPL,backlight-control", GMAX3100_vals[3], 4);␊
devprop_add_value(device, "AAPL00,blackscreen-preferences",␉GMAX3100_vals[4], 4);␊
devprop_add_value(device, "AAPL01,BacklightIntensity",␉GMAX3100_vals[5], 4);␊
devprop_add_value(device, "AAPL01,blackscreen-preferences",␉GMAX3100_vals[6], 4);␊
devprop_add_value(device, "AAPL01,DataJustify", GMAX3100_vals[7], 4);␊
devprop_add_value(device, "AAPL01,Depth", GMAX3100_vals[8], 4);␊
devprop_add_value(device, "AAPL01,Dither", GMAX3100_vals[9], 4);␊
devprop_add_value(device, "AAPL01,DualLink", GMAX3100_vals[10], 4);␊
devprop_add_value(device, "AAPL01,Height", GMAX3100_vals[11], 4);␊
devprop_add_value(device, "AAPL01,Interlace", GMAX3100_vals[12], 4);␊
devprop_add_value(device, "AAPL01,Inverter", GMAX3100_vals[13], 4);␊
devprop_add_value(device, "AAPL01,InverterCurrent", GMAX3100_vals[14], 4);␊
devprop_add_value(device, "AAPL01,InverterCurrency",␉GMAX3100_vals[15], 4);␊
devprop_add_value(device, "AAPL01,LinkFormat", GMAX3100_vals[16], 4);␊
devprop_add_value(device, "AAPL01,LinkType", GMAX3100_vals[17], 4);␊
devprop_add_value(device, "AAPL01,Pipe", GMAX3100_vals[18], 4);␊
devprop_add_value(device, "AAPL01,PixelFormat", GMAX3100_vals[19], 4);␊
devprop_add_value(device, "AAPL01,Refresh", GMAX3100_vals[20], 4);␊
devprop_add_value(device, "AAPL01,Stretch", GMAX3100_vals[21], 4);␊
//devprop_add_value(device, "AAPL01,InverterFrequency",␉GMAX3100_vals[22], 4);␊
devprop_add_value(device, "class-code", ClassFix, 4);␊
break;␊
␉␉/* 2A02, 2A12, 2A13, 2A42, 2A43 */␊
␉␉case GMA_I965_GM: // GMAX3100␊
␉␉case GMA_I965_GME:␊
␉␉//case 0x80862A13:␊
␉␉case GMA_GM45_GM:␊
␉␉//case GMA_GM45_GM2:␊
␉␉␉devprop_add_value(device, "AAPL,HasPanel",␉␉␉GMAX3100_vals[0], 4);␊
␉␉␉devprop_add_value(device, "AAPL,SelfRefreshSupported",␉␉GMAX3100_vals[1], 4);␊
␉␉␉devprop_add_value(device, "AAPL,aux-power-connected",␉␉GMAX3100_vals[2], 4);␊
␉␉␉devprop_add_value(device, "AAPL,backlight-control",␉␉GMAX3100_vals[3], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,blackscreen-preferences",␉GMAX3100_vals[4], 4);␊
␉␉␉devprop_add_value(device, "AAPL01,BacklightIntensity",␉␉GMAX3100_vals[5], 4);␊
␉␉␉devprop_add_value(device, "AAPL01,blackscreen-preferences",␉GMAX3100_vals[6], 4);␊
␉␉␉devprop_add_value(device, "AAPL01,DataJustify",␉␉␉GMAX3100_vals[7], 4);␊
␉␉␉devprop_add_value(device, "AAPL01,Depth",␉␉␉GMAX3100_vals[8], 4);␊
␉␉␉devprop_add_value(device, "AAPL01,Dither",␉␉␉GMAX3100_vals[9], 4);␊
␉␉␉devprop_add_value(device, "AAPL01,DualLink",␉␉␉GMAX3100_vals[10], 4);␊
␉␉␉devprop_add_value(device, "AAPL01,Height",␉␉␉GMAX3100_vals[11], 4);␊
␉␉␉devprop_add_value(device, "AAPL01,Interlace",␉␉␉GMAX3100_vals[12], 4);␊
␉␉␉devprop_add_value(device, "AAPL01,Inverter",␉␉␉GMAX3100_vals[13], 4);␊
␉␉␉devprop_add_value(device, "AAPL01,InverterCurrent",␉␉GMAX3100_vals[14], 4);␊
␉␉␉devprop_add_value(device, "AAPL01,InverterCurrency",␉␉GMAX3100_vals[15], 4);␊
␉␉␉devprop_add_value(device, "AAPL01,LinkFormat",␉␉␉GMAX3100_vals[16], 4);␊
␉␉␉devprop_add_value(device, "AAPL01,LinkType",␉␉␉GMAX3100_vals[17], 4);␊
␉␉␉devprop_add_value(device, "AAPL01,Pipe",␉␉␉GMAX3100_vals[18], 4);␊
␉␉␉devprop_add_value(device, "AAPL01,PixelFormat",␉␉␉GMAX3100_vals[19], 4);␊
␉␉␉devprop_add_value(device, "AAPL01,Refresh",␉␉␉GMAX3100_vals[20], 4);␊
␉␉␉devprop_add_value(device, "AAPL01,Stretch",␉␉␉GMAX3100_vals[21], 4);␊
␉␉␉//devprop_add_value(device, "AAPL01,InverterFrequency",␉␉GMAX3100_vals[22], 4);␊
␉␉␉devprop_add_value(device, "class-code",␉␉␉␉ClassFix, 4);␊
␉␉␉break;␊
␊
/* 0106 */␊
case GMA_SANDYBRIDGE_M_GT1: // HD Graphics 2000 Mobile␊
devprop_add_value(device, "class-code", ClassFix, 4);␊
//devprop_add_value(device, "hda-gfx",␉␉␉(uint8_t *)"onboard-1", 10);␊
devprop_add_value(device, "AAPL00,PixelFormat",␉␉HD2000_vals[0], 4);␊
devprop_add_value(device, "AAPL00,T1",␉␉␉HD2000_vals[1], 4);␊
devprop_add_value(device, "AAPL00,T2",␉␉␉HD2000_vals[2], 4);␊
devprop_add_value(device, "AAPL00,T3",␉␉␉HD2000_vals[3], 4);␊
devprop_add_value(device, "AAPL00,T4",␉␉␉HD2000_vals[4], 4);␊
devprop_add_value(device, "AAPL00,T5",␉␉␉HD2000_vals[5], 4);␊
devprop_add_value(device, "AAPL00,T6",␉␉␉HD2000_vals[6], 4);␊
devprop_add_value(device, "AAPL00,T7",␉␉␉HD2000_vals[7], 4);␊
devprop_add_value(device, "AAPL00,LinkType",␉␉HD2000_vals[8], 4);␊
devprop_add_value(device, "AAPL00,LinkFormat",␉␉HD2000_vals[9], 4);␊
devprop_add_value(device, "AAPL00,DualLink",␉␉HD2000_vals[10], 4);␊
devprop_add_value(device, "AAPL00,Dither",␉␉␉HD2000_vals[11], 4);␊
devprop_add_value(device, "AAPL00,DataJustify",␉␉HD3000_vals[12], 4);␊
devprop_add_value(device, "graphic-options",␉␉HD2000_vals[13], 4);␊
devprop_add_value(device, "AAPL,tbl-info",␉␉␉HD2000_tbl_info, 18);␊
devprop_add_value(device, "AAPL,os-info",␉␉␉HD2000_os_info, 20);␊
break;␊
␉␉/* 0106 */␊
␉␉case GMA_SANDYBRIDGE_M_GT1: // HD Graphics 2000 Mobile␊
␉␉␉devprop_add_value(device, "class-code", ClassFix, 4);␊
␉␉␉//devprop_add_value(device, "hda-gfx",␉␉␉(uint8_t *)"onboard-1", 10);␊
␉␉␉devprop_add_value(device, "AAPL00,PixelFormat",␉␉HD2000_vals[0], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,T1",␉␉␉HD2000_vals[1], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,T2",␉␉␉HD2000_vals[2], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,T3",␉␉␉HD2000_vals[3], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,T4",␉␉␉HD2000_vals[4], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,T5",␉␉␉HD2000_vals[5], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,T6",␉␉␉HD2000_vals[6], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,T7",␉␉␉HD2000_vals[7], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,LinkType",␉␉HD2000_vals[8], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,LinkFormat",␉␉HD2000_vals[9], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,DualLink",␉␉HD2000_vals[10], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,Dither",␉␉HD2000_vals[11], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,DataJustify",␉␉HD3000_vals[12], 4);␊
␉␉␉devprop_add_value(device, "graphic-options",␉␉HD2000_vals[13], 4);␊
␉␉␉devprop_add_value(device, "AAPL,tbl-info",␉␉HD2000_tbl_info, 18);␊
␉␉␉devprop_add_value(device, "AAPL,os-info",␉␉HD2000_os_info, 20);␊
␉␉␉break;␊
␊
/* 0116, 0126 */␊
case GMA_SANDYBRIDGE_M_GT2: // HD Graphics 3000 Mobile␊
case GMA_SANDYBRIDGE_M_GT2_PLUS:␊
devprop_add_value(device, "class-code",␉␉␉ClassFix, 4);␊
//devprop_add_value(device, "hda-gfx",␉␉␉(uint8_t *)"onboard-1", 10);␊
devprop_add_value(device, "AAPL00,PixelFormat",␉␉HD3000_vals[0], 4);␊
devprop_add_value(device, "AAPL00,T1",␉␉␉HD3000_vals[1], 4);␊
devprop_add_value(device, "AAPL00,T2",␉␉␉HD3000_vals[2], 4);␊
devprop_add_value(device, "AAPL00,T3",␉␉␉HD3000_vals[3], 4);␊
devprop_add_value(device, "AAPL00,T4",␉␉␉HD3000_vals[4], 4);␊
devprop_add_value(device, "AAPL00,T5",␉␉␉HD3000_vals[5], 4);␊
devprop_add_value(device, "AAPL00,T6",␉␉␉HD3000_vals[6], 4);␊
devprop_add_value(device, "AAPL00,T7",␉␉␉HD3000_vals[7], 4);␊
devprop_add_value(device, "AAPL00,LinkType",␉␉HD3000_vals[8], 4);␊
devprop_add_value(device, "AAPL00,LinkFormat",␉␉HD3000_vals[9], 4);␊
devprop_add_value(device, "AAPL00,DualLink",␉␉HD3000_vals[10], 4);␊
devprop_add_value(device, "AAPL00,Dither",␉␉␉HD3000_vals[11], 4);␊
devprop_add_value(device, "AAPL00,DataJustify",␉␉HD3000_vals[12], 4);␊
devprop_add_value(device, "graphic-options",␉␉HD3000_vals[13], 4);␊
devprop_add_value(device, "AAPL,tbl-info",␉␉␉HD3000_tbl_info, 18);␊
devprop_add_value(device, "AAPL,os-info",␉␉␉HD3000_os_info, 20);␊
devprop_add_value(device, "AAPL,snb-platform-id",␉␉HD3000_vals[16], 4);// previusly commented␊
break;␊
␉␉/* 0116, 0126 */␊
␉␉case GMA_SANDYBRIDGE_M_GT2: // HD Graphics 3000 Mobile␊
␉␉case GMA_SANDYBRIDGE_M_GT2_PLUS:␊
␉␉␉devprop_add_value(device, "class-code",␉␉␉ClassFix, 4);␊
␉␉␉//devprop_add_value(device, "hda-gfx",␉␉␉(uint8_t *)"onboard-1", 10);␊
␉␉␉devprop_add_value(device, "AAPL00,PixelFormat",␉␉HD3000_vals[0], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,T1",␉␉␉HD3000_vals[1], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,T2",␉␉␉HD3000_vals[2], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,T3",␉␉␉HD3000_vals[3], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,T4",␉␉␉HD3000_vals[4], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,T5",␉␉␉HD3000_vals[5], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,T6",␉␉␉HD3000_vals[6], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,T7",␉␉␉HD3000_vals[7], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,LinkType",␉␉HD3000_vals[8], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,LinkFormat",␉␉HD3000_vals[9], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,DualLink",␉␉HD3000_vals[10], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,Dither",␉␉HD3000_vals[11], 4);␊
␉␉␉devprop_add_value(device, "AAPL00,DataJustify",␉␉HD3000_vals[12], 4);␊
␉␉␉devprop_add_value(device, "graphic-options",␉␉HD3000_vals[13], 4);␊
␉␉␉devprop_add_value(device, "AAPL,tbl-info",␉␉HD3000_tbl_info, 18);␊
␉␉␉devprop_add_value(device, "AAPL,os-info",␉␉HD3000_os_info, 20);␊
␉␉␉devprop_add_value(device, "AAPL,snb-platform-id",␉HD3000_vals[16], 4);// previusly commented␊
␉␉break;␊
␊
/* 0102 */␊
/* HD Graphics 2000 */␊
case GMA_SANDYBRIDGE_GT1: // 0102␊
device_id = 0x00000102;␉␉␉␉␉// Inject a valid mobile GPU device id instead of patching kexts␊
devprop_add_value(device, "built-in",␉␉␉&BuiltIn, 1);␊
devprop_add_value(device, "class-code",␉␉␉ClassFix, 4);␊
devprop_add_value(device, "device-id",␉␉␉(uint8_t *)&device_id, sizeof(device_id));␊
//devprop_add_value(device, "hda-gfx",␉␉␉(uint8_t *)"onboard-1", 10);␊
devprop_add_value(device, "AAPL,tbl-info",␉␉␉HD2000_tbl_info, 18);␊
devprop_add_value(device, "AAPL,os-info",␉␉␉HD2000_os_info, 20);␊
break;␊
␉␉/* 0102 */␊
␉␉/* HD Graphics 2000 */␊
␉␉case GMA_SANDYBRIDGE_GT1: // 0102␊
␉␉␉device_id = 0x00000102;␉␉␉␉␉// Inject a valid mobile GPU device id instead of patching kexts␊
␉␉␉devprop_add_value(device, "built-in",␉␉␉&BuiltIn, 1);␊
␉␉␉devprop_add_value(device, "class-code",␉␉␉ClassFix, 4);␊
␉␉␉devprop_add_value(device, "device-id",␉␉␉(uint8_t *)&device_id, sizeof(device_id));␊
␉␉␉//devprop_add_value(device, "hda-gfx",␉␉␉(uint8_t *)"onboard-1", 10);␊
␉␉␉devprop_add_value(device, "AAPL,tbl-info",␉␉␉HD2000_tbl_info, 18);␊
␉␉␉devprop_add_value(device, "AAPL,os-info",␉␉␉HD2000_os_info, 20);␊
␉␉␉break;␊
␊
/* Sandy Bridge */␊
/* HD Graphics 3000 */␊
case GMA_SANDYBRIDGE_GT2: // 0112␊
case GMA_SANDYBRIDGE_GT2_PLUS: // 0122␊
devprop_add_value(device, "built-in",␉␉␉&BuiltIn, 1);␊
devprop_add_value(device, "class-code",␉␉␉ClassFix, 4);␊
device_id = 0x00000126;␉␉␉␉␉// Inject a valid mobile GPU device id instead of patching kexts␊
devprop_add_value(device, "device-id",␉␉␉(uint8_t *)&device_id, sizeof(device_id));␊
//devprop_add_value(device, "hda-gfx",␉␉␉(uint8_t *)"onboard-1", 10);␊
devprop_add_value(device, "AAPL,tbl-info",␉␉␉HD3000_tbl_info, 18);␊
devprop_add_value(device, "AAPL,os-info",␉␉␉HD3000_os_info, 20);␊
break;␊
␉␉/* Sandy Bridge */␊
␉␉/* HD Graphics 3000 */␊
␉␉case GMA_SANDYBRIDGE_GT2: // 0112␊
␉␉case GMA_SANDYBRIDGE_GT2_PLUS: // 0122␊
␉␉␉devprop_add_value(device, "built-in",␉␉␉&BuiltIn, 1);␊
␉␉␉devprop_add_value(device, "class-code",␉␉␉ClassFix, 4);␊
␉␉␉device_id = 0x00000126;␉␉␉␉␉// Inject a valid mobile GPU device id instead of patching kexts␊
␉␉␉devprop_add_value(device, "device-id",␉␉␉(uint8_t *)&device_id, sizeof(device_id));␊
␉␉␉//devprop_add_value(device, "hda-gfx",␉␉␉(uint8_t *)"onboard-1", 10);␊
␉␉␉devprop_add_value(device, "AAPL,tbl-info",␉␉␉HD3000_tbl_info, 18);␊
␉␉␉devprop_add_value(device, "AAPL,os-info",␉␉␉HD3000_os_info, 20);␊
␉␉␉break;␊
␊
/* Ivy Bridge */␊
/* HD Graphics 4000, HD Graphics 4000 Mobile, HD Graphics P4000, HD Graphics 2500 HD, Graphics 2500 Mobile */␊
case GMA_IVYBRIDGE_D_GT1: // 0152␊
case GMA_IVYBRIDGE_M_GT1: // 0156␊
case GMA_IVYBRIDGE_S_GT1: // 015A␊
case GMA_IVYBRIDGE_S_GT3: // 015e␊
case GMA_IVYBRIDGE_D_GT2: // 0162␊
case GMA_IVYBRIDGE_M_GT2: // 0166␊
case GMA_IVYBRIDGE_S_GT2: // 016A␊
case GMA_IVYBRIDGE_S_GT4: // 0172␊
case GMA_IVYBRIDGE_S_GT5: // 0176␊
␉␉/* Ivy Bridge */␊
␉␉/* HD Graphics 4000, HD Graphics 4000 Mobile, HD Graphics P4000, HD Graphics 2500 HD, Graphics 2500 Mobile */␊
␉␉case GMA_IVYBRIDGE_D_GT1: // 0152␊
␉␉case GMA_IVYBRIDGE_M_GT1: // 0156␊
␉␉case GMA_IVYBRIDGE_S_GT1: // 015A␊
␉␉case GMA_IVYBRIDGE_S_GT3: // 015e␊
␉␉case GMA_IVYBRIDGE_D_GT2: // 0162␊
␉␉case GMA_IVYBRIDGE_M_GT2: // 0166␊
␉␉case GMA_IVYBRIDGE_S_GT2: // 016A␊
␉␉case GMA_IVYBRIDGE_S_GT4: // 0172␊
␉␉case GMA_IVYBRIDGE_S_GT5: // 0176␊
␊
␉␉if (getValueForKey(kAAPLCustomIG, &value, &len, &bootInfo->chameleonConfig) && len == AAPL_LEN_IVY * 2)␊
␉␉{␊
␉␉␉uint8_t new_aapl0[AAPL_LEN_IVY];␊
␊
␉␉␉if (hex2bin(value, new_aapl0, AAPL_LEN_IVY) == 0)␊
␉␉␉if (getValueForKey(kAAPLCustomIG, &value, &len, &bootInfo->chameleonConfig) && len == AAPL_LEN_IVY * 2)␊
␉␉␉{␊
␉␉␉␉memcpy(default_aapl_ivy, new_aapl0, AAPL_LEN_IVY);␊
␉␉␉␉uint8_t new_aapl0[AAPL_LEN_IVY];␊
␊
␉␉␉␉verbose("Using user supplied AAPL,ig-platform-id\n");␊
␉␉␉␉verbose("AAPL,ig-platform-id: %02x%02x%02x%02x\n",␊
␉␉␉␉default_aapl_ivy[0], default_aapl_ivy[1], default_aapl_ivy[2], default_aapl_ivy[3]);␊
␉␉␉␉if (hex2bin(value, new_aapl0, AAPL_LEN_IVY) == 0)␊
␉␉␉␉{␊
␉␉␉␉␉memcpy(default_aapl_ivy, new_aapl0, AAPL_LEN_IVY);␊
␊
␉␉␉␉␉verbose("Using user supplied AAPL,ig-platform-id\n");␊
␉␉␉␉␉verbose("AAPL,ig-platform-id: %02x%02x%02x%02x\n",␊
␉␉␉␉␉default_aapl_ivy[0], default_aapl_ivy[1], default_aapl_ivy[2], default_aapl_ivy[3]);␊
␉␉␉␉}␊
␉␉␉␉devprop_add_value(device, "AAPL,ig-platform-id", default_aapl_ivy, AAPL_LEN_IVY);␊
␉␉␉}␊
␉␉␉devprop_add_value(device, "AAPL,ig-platform-id", default_aapl_ivy, AAPL_LEN_IVY);␊
␉␉}␊
␉␉else if (getIntForKey(kIntelCapriFB, &n_igs, &bootInfo->chameleonConfig))␊
␉␉{␊
␉␉␉if ((n_igs >= 0) || (n_igs <= 11))␊
␉␉␉else if (getIntForKey(kIntelCapriFB, &n_igs, &bootInfo->chameleonConfig))␊
␉␉␉{␊
␉␉␉␉verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with value %d\n", n_igs);␊
␉␉␉␉devprop_add_value(device, "AAPL,ig-platform-id", ivy_bridge_ig_vals[n_igs], 4);␊
␉␉␉␉if ((n_igs >= 0) || (n_igs <= 11))␊
␉␉␉␉{␊
␉␉␉␉␉verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with value %d\n", n_igs);␊
␉␉␉␉␉devprop_add_value(device, "AAPL,ig-platform-id", ivy_bridge_ig_vals[n_igs], 4);␊
␉␉␉␉}␊
␉␉␉␉else␊
␉␉␉␉{␊
␉␉␉␉␉verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with bad value please choose a number between 0 and 11.\n");␊
␉␉␉␉}␊
␉␉␉}␊
␉␉␉else␊
␉␉␉{␊
␉␉␉␉verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with bad value please choose a number between 0 and 11.\n");␊
␉␉␉}␊
␉␉}␊
␉␉else␊
␉␉{␊
␉␉␉uint32_t ig_platform_id;␊
␉␉␉uint32_t ram = (((getVBEVideoRam() + 512) / 1024) + 512) / 1024;␊
␉␉␉switch (ram)␊
␉␉␉{␊
␉␉␉␉case 96:␊
␉␉␉␉␉ig_platform_id = 0x01660000; // 96mb Mobile␊
␉␉␉␉␉break;␊
␉␉␉␉uint32_t ig_platform_id;␊
␉␉␉␉uint32_t ram = (((getVBEVideoRam() + 512) / 1024) + 512) / 1024;␊
␉␉␉␉switch (ram)␊
␉␉␉␉{␊
␉␉␉␉␉case 96:␊
␉␉␉␉␉␉ig_platform_id = 0x01660000; // 96mb Mobile␊
␉␉␉␉␉␉break;␊
␊
␉␉␉␉case 64:␊
␉␉␉␉␉ig_platform_id = 0x01660009; // 64mb Mobile␊
␉␉␉␉␉break;␊
␉␉␉␉␉case 64:␊
␉␉␉␉␉␉ig_platform_id = 0x01660009; // 64mb Mobile␊
␉␉␉␉␉␉break;␊
␊
␉␉␉␉case 32:␊
␉␉␉␉␉ig_platform_id = 0x01620005; // 32mb Desktop␊
␉␉␉␉␉break;␊
␉␉␉␉␉case 32:␊
␉␉␉␉␉␉ig_platform_id = 0x01620005; // 32mb Desktop␊
␉␉␉␉␉␉break;␊
␊
␉␉␉␉default:␊
␉␉␉␉␉printf("Please specify 96, 64, or 32MB RAM for the HD4000 in the bios.\n"␊
␉␉␉␉␉"The selected %dMB RAM configuration is not supported for the HD4000.\n", ram);␊
␉␉␉␉␉pause();␊
␉␉␉␉␉return false;␉// Exit early before the AAPL,ig-platform-id property is set.␊
␉␉␉␉␉break;␊
␉␉␉␉␉default:␊
␉␉␉␉␉␉printf("Please specify 96, 64, or 32MB RAM for the HD4000 in the bios.\n"␊
␉␉␉␉␉␉␉"The selected %dMB RAM configuration is not supported for the HD4000.\n", ram);␊
␉␉␉␉␉␉pause();␊
␉␉␉␉␉␉return false;␉// Exit early before the AAPL,ig-platform-id property is set.␊
␉␉␉␉␉␉break;␊
␉␉␉␉}␊
␉␉␉␉devprop_add_value(device, "AAPL,ig-platform-id", (uint8_t *)&ig_platform_id, 4);␊
␉␉␉}␊
␉␉␉devprop_add_value(device, "AAPL,ig-platform-id", (uint8_t *)&ig_platform_id, 4);␊
␉␉}␊
␊
␉␉devprop_add_value(device, "AAPL00,DualLink", HD4000_vals[10], 4);␊
␉␉devprop_add_value(device, "built-in", &BuiltIn, 1);␊
␉␉devprop_add_value(device, "class-code", ClassFix, 4);␊
␉␉//devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);␊
␉␉break;␊
␉␉␉devprop_add_value(device, "AAPL00,DualLink", HD4000_vals[10], 4);␊
␉␉␉devprop_add_value(device, "built-in", &BuiltIn, 1);␊
␉␉␉devprop_add_value(device, "class-code", ClassFix, 4);␊
␉␉␉//devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);␊
␉␉␉break;␊
␊
␉/* Haswell */␊
␉/* HD Graphics 5000, HD Graphics 5000 Mobile, HD Graphics P5000, HD Graphics 4600, HD Graphics 4600 Mobile */␊
␉//case 0x80860090:␊
␉//case 0x80860091:␊
␉//case 0x80860092:␊
␉case GMA_HASWELL_M_GT2: // 0416␊
case GMA_HASWELL_E_GT2: // 041e␊
case GMA_HASWELL_ULT_M_GT2: // 0a16␊
case GMA_HASWELL_ULT_E_GT2: // 0a1e␊
␉␉verbose(" Inject a valid desktop GPU device id (0x0412) instead of patching kexts");␊
␉␉device_id = 0x0412;␉␉// Inject a valid desktop GPU device id (0x0412) instead of patching kexts␊
␉␉devprop_add_value(device, "vendor-id",␉(uint8_t *)INTEL_VENDORID, 4);␊
␉␉devprop_add_value(device, "device-id",␉(uint8_t *)&device_id, sizeof(device_id));␊
␉␉devprop_add_value(device, "compatible",␉(uint8_t *)"pci8086,0412", 13); // GT2 Desktop␊
␉␉/* Haswell */␊
␉␉/* HD Graphics 5000, HD Graphics 5000 Mobile, HD Graphics P5000, HD Graphics 4600, HD Graphics 4600 Mobile */␊
␉␉//case 0x80860090:␊
␉␉//case 0x80860091:␊
␉␉//case 0x80860092:␊
␉␉case GMA_HASWELL_M_GT2: // 0416␊
␉␉case GMA_HASWELL_E_GT2: // 041e␊
␉␉case GMA_HASWELL_ULT_M_GT2: // 0a16␊
␉␉case GMA_HASWELL_ULT_E_GT2: // 0a1e␊
␉␉␉verbose("Injecting a valid desktop GPU device id (0x0412) instead of patching kexts.\n");␊
␉␉␉device_id = 0x0412;␉␉// Inject a valid desktop GPU device id (0x0412) instead of patching kexts␊
␉␉␉devprop_add_value(device, "vendor-id",␉(uint8_t *)INTEL_VENDORID, 4);␊
␉␉␉devprop_add_value(device, "device-id",␉(uint8_t *)&device_id, sizeof(device_id));␊
␉␉␉devprop_add_value(device, "compatible",␉(uint8_t *)"pci8086,0412", 13); // GT2 Desktop␊
␊
␉case GMA_HASWELL_D_GT1: // 0402␊
␉case GMA_HASWELL_M_GT1: // 0406␊
␉case GMA_HASWELL_S_GT1: // 040a␊
␉case GMA_HASWELL_D_GT2: // 0412␊
␉case GMA_HASWELL_S_GT2: // 041a␊
␉case GMA_HASWELL_E_GT1: // 040e␊
␉case GMA_HASWELL_E_GT3: // 042e␊
␉case GMA_HASWELL_D_GT3: // 0422␊
␉case GMA_HASWELL_M_GT3: // 0426␊
␉case GMA_HASWELL_S_GT3: // 042a␊
␉case GMA_HASWELL_ULT_M_GT1: // 0a06␊
␉case GMA_HASWELL_ULT_E_GT1: // 0a0e␊
␉case GMA_HASWELL_ULT_D_GT3: // 0a22␊
␉case GMA_HASWELL_ULT_M_GT3: // 0a26␊
␉case GMA_HASWELL_ULT_S_GT3: // 0a2a␊
␉case GMA_HASWELL_ULT_E_GT3: // 0a2e␊
␉case GMA_HASWELL_SDV_D_GT1_IG: // 0c02␊
␉case GMA_HASWELL_SDV_M_GT1_IG: // 0c06␊
␉case GMA_HASWELL_SDV_D_GT2_IG: // 0c12␊
␉case GMA_HASWELL_SDV_M_GT2_IG: // 0c16␊
␉case GMA_HASWELL_SDV_D_GT2_PLUS_IG: // 0c22␊
␉case GMA_HASWELL_SDV_M_GT2_PLUS_IG: // 0c26␊
␉case GMA_HASWELL_CRW_D_GT1: // 0d02␊
␉case GMA_HASWELL_CRW_D_GT2: // 0d12␊
␉case GMA_HASWELL_CRW_D_GT3: // 0d22␊
␉case GMA_HASWELL_CRW_M_GT1: // 0d06␊
␉case GMA_HASWELL_CRW_M_GT2: // 0d16␊
␉case GMA_HASWELL_CRW_M_GT3: // 0d26␊
␉case GMA_HASWELL_CRW_S_GT1: // 0d0a␊
␉case GMA_HASWELL_CRW_S_GT2: // 0d1a␊
␉case GMA_HASWELL_CRW_S_GT3: // 0d2a␊
␉case GMA_HASWELL_CRW_B_GT1: // 0d0b␊
␉case GMA_HASWELL_CRW_B_GT2: // 0d1b␊
␉case GMA_HASWELL_CRW_B_GT3: // 0d2b␊
␉case GMA_HASWELL_CRW_E_GT1: // 0d0e␊
␉case GMA_HASWELL_CRW_E_GT2: // 0d1e␊
␉case GMA_HASWELL_CRW_E_GT3: // 0d2e␊
␉case GMA_HASWELL_CRW_M_GT2_PLUS_IG: // 0d36␊
␉␉case GMA_HASWELL_D_GT1: // 0402␊
␉␉case GMA_HASWELL_M_GT1: // 0406␊
␉␉case GMA_HASWELL_S_GT1: // 040a␊
␉␉case GMA_HASWELL_D_GT2: // 0412␊
␉␉case GMA_HASWELL_S_GT2: // 041a␊
␉␉case GMA_HASWELL_E_GT1: // 040e␊
␉␉case GMA_HASWELL_E_GT3: // 042e␊
␉␉case GMA_HASWELL_D_GT3: // 0422␊
␉␉case GMA_HASWELL_M_GT3: // 0426␊
␉␉case GMA_HASWELL_S_GT3: // 042a␊
␉␉case GMA_HASWELL_ULT_M_GT1: // 0a06␊
␉␉case GMA_HASWELL_ULT_E_GT1: // 0a0e␊
␉␉case GMA_HASWELL_ULT_D_GT3: // 0a22␊
␉␉case GMA_HASWELL_ULT_M_GT3: // 0a26␊
␉␉case GMA_HASWELL_ULT_S_GT3: // 0a2a␊
␉␉case GMA_HASWELL_ULT_E_GT3: // 0a2e␊
␉␉case GMA_HASWELL_SDV_D_GT1_IG: // 0c02␊
␉␉case GMA_HASWELL_SDV_M_GT1_IG: // 0c06␊
␉␉case GMA_HASWELL_SDV_D_GT2_IG: // 0c12␊
␉␉case GMA_HASWELL_SDV_M_GT2_IG: // 0c16␊
␉␉case GMA_HASWELL_SDV_D_GT2_PLUS_IG: // 0c22␊
␉␉case GMA_HASWELL_SDV_M_GT2_PLUS_IG: // 0c26␊
␉␉case GMA_HASWELL_CRW_D_GT1: // 0d02␊
␉␉case GMA_HASWELL_CRW_D_GT2: // 0d12␊
␉␉case GMA_HASWELL_CRW_D_GT3: // 0d22␊
␉␉case GMA_HASWELL_CRW_M_GT1: // 0d06␊
␉␉case GMA_HASWELL_CRW_M_GT2: // 0d16␊
␉␉case GMA_HASWELL_CRW_M_GT3: // 0d26␊
␉␉case GMA_HASWELL_CRW_S_GT1: // 0d0a␊
␉␉case GMA_HASWELL_CRW_S_GT2: // 0d1a␊
␉␉case GMA_HASWELL_CRW_S_GT3: // 0d2a␊
␉␉case GMA_HASWELL_CRW_B_GT1: // 0d0b␊
␉␉case GMA_HASWELL_CRW_B_GT2: // 0d1b␊
␉␉case GMA_HASWELL_CRW_B_GT3: // 0d2b␊
␉␉case GMA_HASWELL_CRW_E_GT1: // 0d0e␊
␉␉case GMA_HASWELL_CRW_E_GT2: // 0d1e␊
␉␉case GMA_HASWELL_CRW_E_GT3: // 0d2e␊
␉␉case GMA_HASWELL_CRW_M_GT2_PLUS_IG: // 0d36␊
␊
␉␉if (getValueForKey(kAAPLCustomIG, &value, &len, &bootInfo->chameleonConfig) && len == AAPL_LEN_HSW * 2)␊
␉␉{␊
␉␉␉uint8_t new_aapl0[AAPL_LEN_HSW];␊
␊
␉␉␉if (hex2bin(value, new_aapl0, AAPL_LEN_HSW) == 0)␊
␉␉␉if (getValueForKey(kAAPLCustomIG, &value, &len, &bootInfo->chameleonConfig) && len == AAPL_LEN_HSW * 2)␊
␉␉␉{␊
␉␉␉␉memcpy(default_aapl_haswell, new_aapl0, AAPL_LEN_HSW);␊
␉␉␉␉uint8_t new_aapl0[AAPL_LEN_HSW];␊
␊
␉␉␉␉verbose("Using user supplied AAPL,ig-platform-id\n");␊
␉␉␉␉verbose("AAPL,ig-platform-id: %02x%02x%02x%02x\n",␊
␉␉␉␉␉default_aapl_haswell[0], default_aapl_haswell[1], default_aapl_haswell[2], default_aapl_haswell[3]);␊
␉␉␉␉if (hex2bin(value, new_aapl0, AAPL_LEN_HSW) == 0)␊
␉␉␉␉{␊
␉␉␉␉␉memcpy(default_aapl_haswell, new_aapl0, AAPL_LEN_HSW);␊
␊
␉␉␉␉␉verbose("Using user supplied AAPL,ig-platform-id\n");␊
␉␉␉␉␉verbose("AAPL,ig-platform-id: %02x%02x%02x%02x\n",␊
␉␉␉␉␉␉default_aapl_haswell[0], default_aapl_haswell[1], default_aapl_haswell[2], default_aapl_haswell[3]);␊
␉␉␉␉}␊
␉␉␉␉devprop_add_value(device, "AAPL,ig-platform-id", default_aapl_haswell, AAPL_LEN_HSW);␊
␉␉␉}␊
␉␉␉devprop_add_value(device, "AAPL,ig-platform-id", default_aapl_haswell, AAPL_LEN_HSW);␊
␉␉}␊
␉␉else if (getIntForKey(kIntelAzulFB, &n_igs, &bootInfo->chameleonConfig))␊
␉␉{␊
␉␉␉if ((n_igs >= 0) || (n_igs <= 15))␊
␉␉␉else if (getIntForKey(kIntelAzulFB, &n_igs, &bootInfo->chameleonConfig))␊
␉␉␉{␊
␉␉␉␉verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with value %d\n", n_igs);␊
␉␉␉␉devprop_add_value(device, "AAPL,ig-platform-id", haswell_ig_vals[n_igs], 4);␊
␉␉␉␉if ((n_igs >= 0) || (n_igs <= 15))␊
␉␉␉␉{␊
␉␉␉␉␉verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with value %d\n", n_igs);␊
␉␉␉␉␉devprop_add_value(device, "AAPL,ig-platform-id", haswell_ig_vals[n_igs], 4);␊
␉␉␉␉}␊
␉␉␉␉else␊
␉␉␉␉{␊
␉␉␉␉␉verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with bad value please choose a number between 0 and 15.\n");␊
␉␉␉␉}␊
␉␉␉}␊
␉␉␉else␊
␉␉␉{␊
␉␉␉␉verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with bad value please choose a number between 0 and 15.\n");␊
␉␉␉␉uint32_t ig_platform_id = 0x0000260c; // set the default platform ig␊
␉␉␉␉devprop_add_value(device, "AAPL,ig-platform-id", (uint8_t *)&ig_platform_id, 4);␊
␉␉␉}␊
␉␉}␊
␉␉else␊
␉␉{␊
␉␉␉uint32_t ig_platform_id = 0x0000260c; // set the default platform ig␊
␉␉␉devprop_add_value(device, "AAPL,ig-platform-id", (uint8_t *)&ig_platform_id, 4);␊
␉␉}␊
␊
␉␉devprop_add_value(device, "AAPL00,DualLink", HD4000_vals[10], 4);␊
␉␉devprop_add_value(device, "built-in", &BuiltIn, 1);␊
␉␉devprop_add_value(device, "class-code", ClassFix, 4);␊
␉␉//devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);␊
␉␉break;␊
␉␉␉devprop_add_value(device, "AAPL00,DualLink", HD4000_vals[10], 4);␊
␉␉␉devprop_add_value(device, "built-in", &BuiltIn, 1);␊
␉␉␉devprop_add_value(device, "class-code", ClassFix, 4);␊
␉␉␉//devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);␊
␉␉␉break;␊
␊
␉default:␊
␉␉break;␊
␉␉default:␊
␉␉␉break;␊
␉}␊
␊
␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
trunk/i386/libsaio/gma.h
243243
244244
245245
246
247
248
249
246
247
248
249
250250
251
252
253
254
255
256
257
258
259
260
261
262
251263
252264
253265
//#define GMA_HASWELL_CRW_S_GT2_PLUS_IG GFX_MODEL_CONSTRUCT(INTEL, 0x0D3A)␊
␊
#define GMA_BRODWELLL_BDW_U_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x1606) // BDW U GT1␊
#define GMA_BRODWELLL_BDW_U_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x1616) // BDW U GT2␊
#define GMA_BRODWELLL_BDW_U_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x1626) // BDW U GT3 15W␊
#define GMA_BRODWELLL_BDW_U_GT3_2 GFX_MODEL_CONSTRUCT(INTEL, 0x162B) // BDW U GT3 28W␊
#define GMA_BRODWELLL_BDW_Y_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x161E) // BDW Y GT2␊
#define GMA_BRODWELLL_BDW_U_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x1616) // BDW U GT2 Intel(R) HD Graphics 5500 Drivers␊
#define GMA_BRODWELLL_BDW_U_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x1626) // BDW U GT3 15W Intel(R) HD Graphics 6000 Drivers␊
#define GMA_BRODWELLL_BDW_U_GT3_2 GFX_MODEL_CONSTRUCT(INTEL, 0x162B) // BDW U GT3 28W Intel(R) Iris(TM) Pro Graphics 6100 Drivers␊
#define GMA_BRODWELLL_BDW_Y_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x161E) // BDW Y GT2 Intel(R) HD Graphics 5300 Drivers␊
␊
// 0x1602␉Intel(R) HD Graphics Drivers␊
// 0x160e␉Intel(R) HD Graphics Drivers␊
// 0x1612␉Intel(R) HD Graphics 5600 Drivers␊
// 0x1622␉Intel(R) Iris(TM) Pro Graphics 6200 Drivers␊
// 0x162a␉Intel(R) Iris(TM) Pro Graphics 6300P Drivers␊
// 0x162b␉Intel(R) Iris(TM) Pro Graphics 6100 Drivers␊
// 0x0bd0␉Intel Broadwell HD Graphics HAS GT0 Drivers␊
// 0x0bd1␉Intel Broadwell HD Graphics HAS GT1 Drivers␊
// 0x0bd2␉Intel Broadwell HD Graphics HAS GT2 Drivers␊
// 0x0bd3␉Intel Broadwell HD Graphics HAS GT3 Drivers␊
// 0x0bd4␉Intel Broadwell HD Graphics HAS GT4 Drivers␊
␊
/* END */␊
␊
#endif /* !__LIBSAIO_GMA_H */␊
trunk/i386/libsaio/hda.c
201201
202202
203203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
472474
475
473476
474477
475478
// ErmaC: TODO build function to probe the codecID␊
/*␊
static hdacc_codecs know_codecs[] = {␊
{ HDA_CODEC_CS4206, 0, "Cirrus Logic CS4206" },␊
{ HDA_CODEC_CS4207, 0, "Cirrus Logic CS4207" },␊
{ HDA_CODEC_CS4210, 0, "Cirrus Logic CS4210" },␊
{ HDA_CODEC_ALC221, 0, "Realtek ALC221" },␊
{ HDA_CODEC_ALC260, 0, "Realtek ALC260" },␊
{ HDA_CODEC_ALC262, 0, "Realtek ALC262" },␊
{ HDA_CODEC_ALC267, 0, "Realtek ALC267" },␊
{ HDA_CODEC_ALC268, 0, "Realtek ALC268" },␊
{ HDA_CODEC_ALC269, 0, "Realtek ALC269" },␊
{ HDA_CODEC_ALC270, 0, "Realtek ALC270" },␊
{ HDA_CODEC_ALC272, 0, "Realtek ALC272" },␊
{ HDA_CODEC_ALC273, 0, "Realtek ALC273" },␊
{ HDA_CODEC_ALC275, 0, "Realtek ALC275" },␊
{ HDA_CODEC_ALC276, 0, "Realtek ALC276" },␊
{ HDA_CODEC_ALC660, 0, "Realtek ALC660-VD" },␊
{ HDA_CODEC_ALC662, 0x0002, "Realtek ALC662 rev2" },␊
{ HDA_CODEC_ALC662, 0, "Realtek ALC662" },␊
{ HDA_CODEC_ALC663, 0, "Realtek ALC663" },␊
{ HDA_CODEC_ALC665, 0, "Realtek ALC665" },␊
{ HDA_CODEC_ALC670, 0, "Realtek ALC670" },␊
{ HDA_CODEC_ALC680, 0, "Realtek ALC680" },␊
{ HDA_CODEC_ALC861, 0x0340, "Realtek ALC660" },␊
{ HDA_CODEC_ALC861, 0, "Realtek ALC861" },␊
{ HDA_CODEC_ALC861VD, 0, "Realtek ALC861-VD" },␊
{ HDA_CODEC_ALC880, 0, "Realtek ALC880" },␊
{ HDA_CODEC_ALC882, 0, "Realtek ALC882" },␊
{ HDA_CODEC_ALC883, 0, "Realtek ALC883" },␊
{ HDA_CODEC_ALC885, 0x0101, "Realtek ALC889A" },␊
{ HDA_CODEC_ALC885, 0x0103, "Realtek ALC889A" },␊
{ HDA_CODEC_ALC885, 0, "Realtek ALC885" },␊
{ HDA_CODEC_ALC887, 0, "Realtek ALC887" },␊
{ HDA_CODEC_ALC888, 0x0101, "Realtek ALC1200" },␊
{ HDA_CODEC_ALC888, 0, "Realtek ALC888" },␊
{ HDA_CODEC_ALC889, 0, "Realtek ALC889" },␊
{ HDA_CODEC_ALC892, 0, "Realtek ALC892" },␊
{ HDA_CODEC_ALC898, 0, "Realtek ALC898" },␊
{ HDA_CODEC_ALC899, 0, "Realtek ALC899" },␊
{ HDA_CODEC_ALC900, 0, "Realtek ALC1150" },␊
{ HDA_CODEC_AD1882, 0, "Analog Devices AD1882" },␊
{ HDA_CODEC_AD1882A, 0, "Analog Devices AD1882A" },␊
{ HDA_CODEC_AD1883, 0, "Analog Devices AD1883" },␊
{ HDA_CODEC_AD1884, 0, "Analog Devices AD1884" },␊
{ HDA_CODEC_AD1884A, 0, "Analog Devices AD1884A" },␊
{ HDA_CODEC_AD1981HD, 0, "Analog Devices AD1981HD" },␊
{ HDA_CODEC_AD1983, 0, "Analog Devices AD1983" },␊
{ HDA_CODEC_AD1984, 0, "Analog Devices AD1984" },␊
{ HDA_CODEC_AD1984A, 0, "Analog Devices AD1984A" },␊
{ HDA_CODEC_AD1984B, 0, "Analog Devices AD1984B" },␊
{ HDA_CODEC_AD1986A, 0, "Analog Devices AD1986A" },␊
{ HDA_CODEC_AD1987, 0, "Analog Devices AD1987" },␊
{ HDA_CODEC_AD1988, 0, "Analog Devices AD1988A" },␊
{ HDA_CODEC_AD1988B, 0, "Analog Devices AD1988B" },␊
{ HDA_CODEC_AD1989A, 0, "Analog Devices AD1989A" },␊
{ HDA_CODEC_AD1989B, 0, "Analog Devices AD1989B" },␊
{ HDA_CODEC_CA0110, 0, "Creative CA0110-IBG" },␊
{ HDA_CODEC_CA0110_2, 0, "Creative CA0110-IBG" },␊
{ HDA_CODEC_CA0132, 0, "Creative CA0132" },␊
{ HDA_CODEC_SB0880, 0, "Creative SB0880 X-Fi" },␊
{ HDA_CODEC_CMI9880, 0, "CMedia CMI9880" },␊
{ HDA_CODEC_CMI98802, 0, "CMedia CMI9880" },␊
{ HDA_CODEC_CXD9872RDK, 0, "Sigmatel CXD9872RD/K" },␊
{ HDA_CODEC_CXD9872AKD, 0, "Sigmatel CXD9872AKD" },␊
{ HDA_CODEC_STAC9200D, 0, "Sigmatel STAC9200D" },␊
{ HDA_CODEC_STAC9204X, 0, "Sigmatel STAC9204X" },␊
{ HDA_CODEC_STAC9204D, 0, "Sigmatel STAC9204D" },␊
{ HDA_CODEC_STAC9205X, 0, "Sigmatel STAC9205X" },␊
{ HDA_CODEC_STAC9205D, 0, "Sigmatel STAC9205D" },␊
{ HDA_CODEC_STAC9220, 0, "Sigmatel STAC9220" },␊
{ HDA_CODEC_STAC9220_A1, 0, "Sigmatel STAC9220_A1" },␊
{ HDA_CODEC_STAC9220_A2, 0, "Sigmatel STAC9220_A2" },␊
{ HDA_CODEC_STAC9221, 0, "Sigmatel STAC9221" },␊
{ HDA_CODEC_STAC9221_A2, 0, "Sigmatel STAC9221_A2" },␊
{ HDA_CODEC_STAC9221D, 0, "Sigmatel STAC9221D" },␊
{ HDA_CODEC_STAC922XD, 0, "Sigmatel STAC9220D/9223D" },␊
{ HDA_CODEC_STAC9227X, 0, "Sigmatel STAC9227X" },␊
{ HDA_CODEC_STAC9227D, 0, "Sigmatel STAC9227D" },␊
{ HDA_CODEC_STAC9228X, 0, "Sigmatel STAC9228X" },␊
{ HDA_CODEC_STAC9228D, 0, "Sigmatel STAC9228D" },␊
{ HDA_CODEC_STAC9229X, 0, "Sigmatel STAC9229X" },␊
{ HDA_CODEC_STAC9229D, 0, "Sigmatel STAC9229D" },␊
{ HDA_CODEC_STAC9230X, 0, "Sigmatel STAC9230X" },␊
{ HDA_CODEC_STAC9230D, 0, "Sigmatel STAC9230D" },␊
{ HDA_CODEC_STAC9250, 0, "Sigmatel STAC9250" },␊
{ HDA_CODEC_STAC9251, 0, "Sigmatel STAC9251" },␊
{ HDA_CODEC_STAC9255, 0, "Sigmatel STAC9255" },␊
{ HDA_CODEC_STAC9255D, 0, "Sigmatel STAC9255D" },␊
{ HDA_CODEC_STAC9254, 0, "Sigmatel STAC9254" },␊
{ HDA_CODEC_STAC9254D, 0, "Sigmatel STAC9254D" },␊
{ HDA_CODEC_STAC9271X, 0, "Sigmatel STAC9271X" },␊
{ HDA_CODEC_STAC9271D, 0, "Sigmatel STAC9271D" },␊
{ HDA_CODEC_STAC9272X, 0, "Sigmatel STAC9272X" },␊
{ HDA_CODEC_STAC9272D, 0, "Sigmatel STAC9272D" },␊
{ HDA_CODEC_STAC9273X, 0, "Sigmatel STAC9273X" },␊
{ HDA_CODEC_STAC9273D, 0, "Sigmatel STAC9273D" },␊
{ HDA_CODEC_STAC9274, 0, "Sigmatel STAC9274" },␊
{ HDA_CODEC_STAC9274D, 0, "Sigmatel STAC9274D" },␊
{ HDA_CODEC_STAC9274X5NH, 0, "Sigmatel STAC9274X5NH" },␊
{ HDA_CODEC_STAC9274D5NH, 0, "Sigmatel STAC9274D5NH" },␊
{ HDA_CODEC_STAC9872AK, 0, "Sigmatel STAC9872AK" },␊
{ HDA_CODEC_IDT92HD005, 0, "IDT 92HD005" },␊
{ HDA_CODEC_IDT92HD005D, 0, "IDT 92HD005D" },␊
{ HDA_CODEC_IDT92HD206X, 0, "IDT 92HD206X" },␊
{ HDA_CODEC_IDT92HD206D, 0, "IDT 92HD206D" },␊
{ HDA_CODEC_IDT92HD66B1X5, 0, "IDT 92HD66B1X5" },␊
{ HDA_CODEC_IDT92HD66B2X5, 0, "IDT 92HD66B2X5" },␊
{ HDA_CODEC_IDT92HD66B3X5, 0, "IDT 92HD66B3X5" },␊
{ HDA_CODEC_IDT92HD66C1X5, 0, "IDT 92HD66C1X5" },␊
{ HDA_CODEC_IDT92HD66C2X5, 0, "IDT 92HD66C2X5" },␊
{ HDA_CODEC_IDT92HD66C3X5, 0, "IDT 92HD66C3X5" },␊
{ HDA_CODEC_IDT92HD66B1X3, 0, "IDT 92HD66B1X3" },␊
{ HDA_CODEC_IDT92HD66B2X3, 0, "IDT 92HD66B2X3" },␊
{ HDA_CODEC_IDT92HD66B3X3, 0, "IDT 92HD66B3X3" },␊
{ HDA_CODEC_IDT92HD66C1X3, 0, "IDT 92HD66C1X3" },␊
{ HDA_CODEC_IDT92HD66C2X3, 0, "IDT 92HD66C2X3" },␊
{ HDA_CODEC_IDT92HD66C3_65, 0, "IDT 92HD66C3_65" },␊
{ HDA_CODEC_IDT92HD700X, 0, "IDT 92HD700X" },␊
{ HDA_CODEC_IDT92HD700D, 0, "IDT 92HD700D" },␊
{ HDA_CODEC_IDT92HD71B5, 0, "IDT 92HD71B5" },␊
{ HDA_CODEC_IDT92HD71B5_2, 0, "IDT 92HD71B5" },␊
{ HDA_CODEC_IDT92HD71B6, 0, "IDT 92HD71B6" },␊
{ HDA_CODEC_IDT92HD71B6_2, 0, "IDT 92HD71B6" },␊
{ HDA_CODEC_IDT92HD71B7, 0, "IDT 92HD71B7" },␊
{ HDA_CODEC_IDT92HD71B7_2, 0, "IDT 92HD71B7" },␊
{ HDA_CODEC_IDT92HD71B8, 0, "IDT 92HD71B8" },␊
{ HDA_CODEC_IDT92HD71B8_2, 0, "IDT 92HD71B8" },␊
{ HDA_CODEC_IDT92HD73C1, 0, "IDT 92HD73C1" },␊
{ HDA_CODEC_IDT92HD73D1, 0, "IDT 92HD73D1" },␊
{ HDA_CODEC_IDT92HD73E1, 0, "IDT 92HD73E1" },␊
{ HDA_CODEC_IDT92HD75B3, 0, "IDT 92HD75B3" },␊
{ HDA_CODEC_IDT92HD75BX, 0, "IDT 92HD75BX" },␊
{ HDA_CODEC_IDT92HD81B1C, 0, "IDT 92HD81B1C" },␊
{ HDA_CODEC_IDT92HD81B1X, 0, "IDT 92HD81B1X" },␊
{ HDA_CODEC_IDT92HD83C1C, 0, "IDT 92HD83C1C" },␊
{ HDA_CODEC_IDT92HD83C1X, 0, "IDT 92HD83C1X" },␊
{ HDA_CODEC_IDT92HD87B1_3, 0, "IDT 92HD87B1/3" },␊
{ HDA_CODEC_IDT92HD87B2_4, 0, "IDT 92HD87B2/4" },␊
{ HDA_CODEC_IDT92HD89C3, 0, "IDT 92HD89C3" },␊
{ HDA_CODEC_IDT92HD89C2, 0, "IDT 92HD89C2" },␊
{ HDA_CODEC_IDT92HD89C1, 0, "IDT 92HD89C1" },␊
{ HDA_CODEC_IDT92HD89B3, 0, "IDT 92HD89B3" },␊
{ HDA_CODEC_IDT92HD89B2, 0, "IDT 92HD89B2" },␊
{ HDA_CODEC_IDT92HD89B1, 0, "IDT 92HD89B1" },␊
{ HDA_CODEC_IDT92HD89E3, 0, "IDT 92HD89E3" },␊
{ HDA_CODEC_IDT92HD89E2, 0, "IDT 92HD89E2" },␊
{ HDA_CODEC_IDT92HD89E1, 0, "IDT 92HD89E1" },␊
{ HDA_CODEC_IDT92HD89D3, 0, "IDT 92HD89D3" },␊
{ HDA_CODEC_IDT92HD89D2, 0, "IDT 92HD89D2" },␊
{ HDA_CODEC_IDT92HD89D1, 0, "IDT 92HD89D1" },␊
{ HDA_CODEC_IDT92HD89F3, 0, "IDT 92HD89F3" },␊
{ HDA_CODEC_IDT92HD89F2, 0, "IDT 92HD89F2" },␊
{ HDA_CODEC_IDT92HD89F1, 0, "IDT 92HD89F1" },␊
{ HDA_CODEC_IDT92HD90BXX, 0, "IDT 92HD90BXX" },␊
{ HDA_CODEC_IDT92HD91BXX, 0, "IDT 92HD91BXX" },␊
{ HDA_CODEC_IDT92HD93BXX, 0, "IDT 92HD93BXX" },␊
{ HDA_CODEC_IDT92HD98BXX, 0, "IDT 92HD98BXX" },␊
{ HDA_CODEC_IDT92HD99BXX, 0, "IDT 92HD99BXX" },␊
{ HDA_CODEC_CX20549, 0, "Conexant CX20549 (Venice)" },␊
{ HDA_CODEC_CX20551, 0, "Conexant CX20551 (Waikiki)" },␊
{ HDA_CODEC_CX20561, 0, "Conexant CX20561 (Hermosa)" },␊
{ HDA_CODEC_CX20582, 0, "Conexant CX20582 (Pebble)" },␊
{ HDA_CODEC_CX20583, 0, "Conexant CX20583 (Pebble HSF)" },␊
{ HDA_CODEC_CX20584, 0, "Conexant CX20584" },␊
{ HDA_CODEC_CX20585, 0, "Conexant CX20585" },␊
{ HDA_CODEC_CX20588, 0, "Conexant CX20588" },␊
{ HDA_CODEC_CX20590, 0, "Conexant CX20590" },␊
{ HDA_CODEC_CX20631, 0, "Conexant CX20631" },␊
{ HDA_CODEC_CX20632, 0, "Conexant CX20632" },␊
{ HDA_CODEC_CX20641, 0, "Conexant CX20641" },␊
{ HDA_CODEC_CX20642, 0, "Conexant CX20642" },␊
{ HDA_CODEC_CX20651, 0, "Conexant CX20651" },␊
{ HDA_CODEC_CX20652, 0, "Conexant CX20652" },␊
{ HDA_CODEC_CX20664, 0, "Conexant CX20664" },␊
{ HDA_CODEC_CX20665, 0, "Conexant CX20665" },␊
{ HDA_CODEC_VT1708_8, 0, "VIA VT1708_8" },␊
{ HDA_CODEC_VT1708_9, 0, "VIA VT1708_9" },␊
{ HDA_CODEC_VT1708_A, 0, "VIA VT1708_A" },␊
{ HDA_CODEC_VT1708_B, 0, "VIA VT1708_B" },␊
{ HDA_CODEC_VT1709_0, 0, "VIA VT1709_0" },␊
{ HDA_CODEC_VT1709_1, 0, "VIA VT1709_1" },␊
{ HDA_CODEC_VT1709_2, 0, "VIA VT1709_2" },␊
{ HDA_CODEC_VT1709_3, 0, "VIA VT1709_3" },␊
{ HDA_CODEC_VT1709_4, 0, "VIA VT1709_4" },␊
{ HDA_CODEC_VT1709_5, 0, "VIA VT1709_5" },␊
{ HDA_CODEC_VT1709_6, 0, "VIA VT1709_6" },␊
{ HDA_CODEC_VT1709_7, 0, "VIA VT1709_7" },␊
{ HDA_CODEC_VT1708B_0, 0, "VIA VT1708B_0" },␊
{ HDA_CODEC_VT1708B_1, 0, "VIA VT1708B_1" },␊
{ HDA_CODEC_VT1708B_2, 0, "VIA VT1708B_2" },␊
{ HDA_CODEC_VT1708B_3, 0, "VIA VT1708B_3" },␊
{ HDA_CODEC_VT1708B_4, 0, "VIA VT1708B_4" },␊
{ HDA_CODEC_VT1708B_5, 0, "VIA VT1708B_5" },␊
{ HDA_CODEC_VT1708B_6, 0, "VIA VT1708B_6" },␊
{ HDA_CODEC_VT1708B_7, 0, "VIA VT1708B_7" },␊
{ HDA_CODEC_VT1708S_0, 0, "VIA VT1708S_0" },␊
{ HDA_CODEC_VT1708S_1, 0, "VIA VT1708S_1" },␊
{ HDA_CODEC_VT1708S_2, 0, "VIA VT1708S_2" },␊
{ HDA_CODEC_VT1708S_3, 0, "VIA VT1708S_3" },␊
{ HDA_CODEC_VT1708S_4, 0, "VIA VT1708S_4" },␊
{ HDA_CODEC_VT1708S_5, 0, "VIA VT1708S_5" },␊
{ HDA_CODEC_VT1708S_6, 0, "VIA VT1708S_6" },␊
{ HDA_CODEC_VT1708S_7, 0, "VIA VT1708S_7" },␊
{ HDA_CODEC_VT1702_0, 0, "VIA VT1702_0" },␊
{ HDA_CODEC_VT1702_1, 0, "VIA VT1702_1" },␊
{ HDA_CODEC_VT1702_2, 0, "VIA VT1702_2" },␊
{ HDA_CODEC_VT1702_3, 0, "VIA VT1702_3" },␊
{ HDA_CODEC_VT1702_4, 0, "VIA VT1702_4" },␊
{ HDA_CODEC_VT1702_5, 0, "VIA VT1702_5" },␊
{ HDA_CODEC_VT1702_6, 0, "VIA VT1702_6" },␊
{ HDA_CODEC_VT1702_7, 0, "VIA VT1702_7" },␊
{ HDA_CODEC_VT1716S_0, 0, "VIA VT1716S_0" },␊
{ HDA_CODEC_VT1716S_1, 0, "VIA VT1716S_1" },␊
{ HDA_CODEC_VT1718S_0, 0, "VIA VT1718S_0" },␊
{ HDA_CODEC_VT1718S_1, 0, "VIA VT1718S_1" },␊
{ HDA_CODEC_VT1802_0, 0, "VIA VT1802_0" },␊
{ HDA_CODEC_VT1802_1, 0, "VIA VT1802_1" },␊
{ HDA_CODEC_VT1812, 0, "VIA VT1812" },␊
{ HDA_CODEC_VT1818S, 0, "VIA VT1818S" },␊
{ HDA_CODEC_VT1828S, 0, "VIA VT1828S" },␊
{ HDA_CODEC_VT2002P_0, 0, "VIA VT2002P_0" },␊
{ HDA_CODEC_VT2002P_1, 0, "VIA VT2002P_1" },␊
{ HDA_CODEC_VT2020, 0, "VIA VT2020" },␊
{ HDA_CODEC_ATIRS600_1, 0, "ATI RS600" },␊
{ HDA_CODEC_ATIRS600_2, 0, "ATI RS600" },␊
{ HDA_CODEC_ATIRS690, 0, "ATI RS690/780" },␊
{ HDA_CODEC_ATIR6XX, 0, "ATI R6xx" },␊
{ HDA_CODEC_NVIDIAMCP67, 0, "NVIDIA MCP67" },␊
{ HDA_CODEC_NVIDIAMCP73, 0, "NVIDIA MCP73" },␊
{ HDA_CODEC_NVIDIAMCP78, 0, "NVIDIA MCP78" },␊
{ HDA_CODEC_NVIDIAMCP78_2, 0, "NVIDIA MCP78" },␊
{ HDA_CODEC_NVIDIAMCP78_3, 0, "NVIDIA MCP78" },␊
{ HDA_CODEC_NVIDIAMCP78_4, 0, "NVIDIA MCP78" },␊
{ HDA_CODEC_NVIDIAMCP7A, 0, "NVIDIA MCP7A" },␊
{ HDA_CODEC_NVIDIAGT220, 0, "NVIDIA GT220" },␊
{ HDA_CODEC_NVIDIAGT21X, 0, "NVIDIA GT21x" },␊
{ HDA_CODEC_NVIDIAMCP89, 0, "NVIDIA MCP89" },␊
{ HDA_CODEC_NVIDIAGT240, 0, "NVIDIA GT240" },␊
{ HDA_CODEC_NVIDIAGTS450, 0, "NVIDIA GTS450" },␊
{ HDA_CODEC_NVIDIAGT440, 0, "NVIDIA GT440" },␊
{ HDA_CODEC_NVIDIAGTX550, 0, "NVIDIA GTX550" },␊
{ HDA_CODEC_NVIDIAGTX570, 0, "NVIDIA GTX570" },␊
{ HDA_CODEC_INTELIP, 0, "Intel Ibex Peak" },␊
{ HDA_CODEC_INTELBL, 0, "Intel Bearlake" },␊
{ HDA_CODEC_INTELCA, 0, "Intel Cantiga" },␊
{ HDA_CODEC_INTELEL, 0, "Intel Eaglelake" },␊
{ HDA_CODEC_INTELIP2, 0, "Intel Ibex Peak" },␊
{ HDA_CODEC_INTELCPT, 0, "Intel Cougar Point" },␊
{ HDA_CODEC_INTELPPT, 0, "Intel Panther Point" },␊
{ HDA_CODEC_INTELCL, 0, "Intel Crestline" },␊
{ HDA_CODEC_SII1390, 0, "Silicon Image SiI1390" },␊
{ HDA_CODEC_SII1392, 0, "Silicon Image SiI1392" },␊
// Unknown CODECs␊
{ HDA_CODEC_ADXXXX, 0, "Analog Devices" },␊
{ HDA_CODEC_AGEREXXXX, 0, "Lucent/Agere Systems" },␊
{ HDA_CODEC_ALCXXXX, 0, "Realtek" },␊
{ HDA_CODEC_ATIXXXX, 0, "ATI" },␊
{ HDA_CODEC_CAXXXX, 0, "Creative" },␊
{ HDA_CODEC_CMIXXXX, 0, "CMedia" },␊
{ HDA_CODEC_CMIXXXX2, 0, "CMedia" },␊
{ HDA_CODEC_CSXXXX, 0, "Cirrus Logic" },␊
{ HDA_CODEC_CXXXXX, 0, "Conexant" },␊
{ HDA_CODEC_CHXXXX, 0, "Chrontel" },␊
{ HDA_CODEC_IDTXXXX, 0, "IDT" },␊
{ HDA_CODEC_INTELXXXX, 0, "Intel" },␊
{ HDA_CODEC_MOTOXXXX, 0, "Motorola" },␊
{ HDA_CODEC_NVIDIAXXXX, 0, "NVIDIA" },␊
{ HDA_CODEC_SIIXXXX, 0, "Silicon Image" },␊
{ HDA_CODEC_STACXXXX, 0, "Sigmatel" },␊
{ HDA_CODEC_VTXXXX, 0, "VIA" },␊
␉{ HDA_CODEC_CS4206, 0, "Cirrus Logic CS4206" },␊
␉{ HDA_CODEC_CS4207, 0, "Cirrus Logic CS4207" },␊
␉{ HDA_CODEC_CS4210, 0, "Cirrus Logic CS4210" },␊
␉{ HDA_CODEC_ALC221, 0, "Realtek ALC221" },␊
␉{ HDA_CODEC_ALC260, 0, "Realtek ALC260" },␊
␉{ HDA_CODEC_ALC262, 0, "Realtek ALC262" },␊
␉{ HDA_CODEC_ALC267, 0, "Realtek ALC267" },␊
␉{ HDA_CODEC_ALC268, 0, "Realtek ALC268" },␊
␉{ HDA_CODEC_ALC269, 0, "Realtek ALC269" },␊
␉{ HDA_CODEC_ALC270, 0, "Realtek ALC270" },␊
␉{ HDA_CODEC_ALC272, 0, "Realtek ALC272" },␊
␉{ HDA_CODEC_ALC273, 0, "Realtek ALC273" },␊
␉{ HDA_CODEC_ALC275, 0, "Realtek ALC275" },␊
␉{ HDA_CODEC_ALC276, 0, "Realtek ALC276" },␊
␉{ HDA_CODEC_ALC660, 0, "Realtek ALC660-VD" },␊
␉{ HDA_CODEC_ALC662, 0x0002, "Realtek ALC662 rev2" },␊
␉{ HDA_CODEC_ALC662, 0, "Realtek ALC662" },␊
␉{ HDA_CODEC_ALC663, 0, "Realtek ALC663" },␊
␉{ HDA_CODEC_ALC665, 0, "Realtek ALC665" },␊
␉{ HDA_CODEC_ALC670, 0, "Realtek ALC670" },␊
␉{ HDA_CODEC_ALC680, 0, "Realtek ALC680" },␊
␉{ HDA_CODEC_ALC861, 0x0340, "Realtek ALC660" },␊
␉{ HDA_CODEC_ALC861, 0, "Realtek ALC861" },␊
␉{ HDA_CODEC_ALC861VD, 0, "Realtek ALC861-VD" },␊
␉{ HDA_CODEC_ALC880, 0, "Realtek ALC880" },␊
␉{ HDA_CODEC_ALC882, 0, "Realtek ALC882" },␊
␉{ HDA_CODEC_ALC883, 0, "Realtek ALC883" },␊
␉{ HDA_CODEC_ALC885, 0x0101, "Realtek ALC889A" },␊
␉{ HDA_CODEC_ALC885, 0x0103, "Realtek ALC889A" },␊
␉{ HDA_CODEC_ALC885, 0, "Realtek ALC885" },␊
␉{ HDA_CODEC_ALC887, 0, "Realtek ALC887" },␊
␉{ HDA_CODEC_ALC888, 0x0101, "Realtek ALC1200" },␊
␉{ HDA_CODEC_ALC888, 0, "Realtek ALC888" },␊
␉{ HDA_CODEC_ALC889, 0, "Realtek ALC889" },␊
␉{ HDA_CODEC_ALC892, 0, "Realtek ALC892" },␊
␉{ HDA_CODEC_ALC898, 0, "Realtek ALC898" },␊
␉{ HDA_CODEC_ALC899, 0,␉␉"Realtek ALC899" },␊
␉{ HDA_CODEC_ALC900, 0, "Realtek ALC1150" },␊
␊
␉{ HDA_CODEC_AD1882, 0, "Analog Devices AD1882" },␊
␉{ HDA_CODEC_AD1882A, 0, "Analog Devices AD1882A" },␊
␉{ HDA_CODEC_AD1883, 0, "Analog Devices AD1883" },␊
␉{ HDA_CODEC_AD1884, 0, "Analog Devices AD1884" },␊
␉{ HDA_CODEC_AD1884A, 0, "Analog Devices AD1884A" },␊
␉{ HDA_CODEC_AD1981HD, 0, "Analog Devices AD1981HD" },␊
␉{ HDA_CODEC_AD1983, 0, "Analog Devices AD1983" },␊
␉{ HDA_CODEC_AD1984, 0, "Analog Devices AD1984" },␊
␉{ HDA_CODEC_AD1984A, 0, "Analog Devices AD1984A" },␊
␉{ HDA_CODEC_AD1984B, 0, "Analog Devices AD1984B" },␊
␉{ HDA_CODEC_AD1986A, 0, "Analog Devices AD1986A" },␊
␉{ HDA_CODEC_AD1987, 0, "Analog Devices AD1987" },␊
␉{ HDA_CODEC_AD1988, 0, "Analog Devices AD1988A" },␊
␉{ HDA_CODEC_AD1988B, 0, "Analog Devices AD1988B" },␊
␉{ HDA_CODEC_AD1989A, 0, "Analog Devices AD1989A" },␊
␉{ HDA_CODEC_AD1989B, 0, "Analog Devices AD1989B" },␊
␉{ HDA_CODEC_CA0110, 0, "Creative CA0110-IBG" },␊
␉{ HDA_CODEC_CA0110_2, 0, "Creative CA0110-IBG" },␊
␉{ HDA_CODEC_CA0132, 0, "Creative CA0132" },␊
␉{ HDA_CODEC_SB0880, 0, "Creative SB0880 X-Fi" },␊
␉{ HDA_CODEC_CMI9880, 0, "CMedia CMI9880" },␊
␉{ HDA_CODEC_CMI98802, 0, "CMedia CMI9880" },␊
␉{ HDA_CODEC_CXD9872RDK, 0, "Sigmatel CXD9872RD/K" },␊
␉{ HDA_CODEC_CXD9872AKD, 0, "Sigmatel CXD9872AKD" },␊
␉{ HDA_CODEC_STAC9200D, 0, "Sigmatel STAC9200D" },␊
␉{ HDA_CODEC_STAC9204X, 0, "Sigmatel STAC9204X" },␊
␉{ HDA_CODEC_STAC9204D, 0, "Sigmatel STAC9204D" },␊
␉{ HDA_CODEC_STAC9205X, 0, "Sigmatel STAC9205X" },␊
␉{ HDA_CODEC_STAC9205D, 0, "Sigmatel STAC9205D" },␊
␉{ HDA_CODEC_STAC9220, 0, "Sigmatel STAC9220" },␊
␉{ HDA_CODEC_STAC9220_A1, 0, "Sigmatel STAC9220_A1" },␊
␉{ HDA_CODEC_STAC9220_A2, 0, "Sigmatel STAC9220_A2" },␊
␉{ HDA_CODEC_STAC9221, 0, "Sigmatel STAC9221" },␊
␉{ HDA_CODEC_STAC9221_A2, 0, "Sigmatel STAC9221_A2" },␊
␉{ HDA_CODEC_STAC9221D, 0, "Sigmatel STAC9221D" },␊
␉{ HDA_CODEC_STAC922XD, 0, "Sigmatel STAC9220D/9223D" },␊
␉{ HDA_CODEC_STAC9227X, 0, "Sigmatel STAC9227X" },␊
␉{ HDA_CODEC_STAC9227D, 0, "Sigmatel STAC9227D" },␊
␉{ HDA_CODEC_STAC9228X, 0, "Sigmatel STAC9228X" },␊
␉{ HDA_CODEC_STAC9228D, 0, "Sigmatel STAC9228D" },␊
␉{ HDA_CODEC_STAC9229X, 0, "Sigmatel STAC9229X" },␊
␉{ HDA_CODEC_STAC9229D, 0, "Sigmatel STAC9229D" },␊
␉{ HDA_CODEC_STAC9230X, 0, "Sigmatel STAC9230X" },␊
␉{ HDA_CODEC_STAC9230D, 0, "Sigmatel STAC9230D" },␊
␉{ HDA_CODEC_STAC9250, 0, "Sigmatel STAC9250" },␊
␉{ HDA_CODEC_STAC9251, 0, "Sigmatel STAC9251" },␊
␉{ HDA_CODEC_STAC9255, 0, "Sigmatel STAC9255" },␊
␉{ HDA_CODEC_STAC9255D, 0, "Sigmatel STAC9255D" },␊
␉{ HDA_CODEC_STAC9254, 0, "Sigmatel STAC9254" },␊
␉{ HDA_CODEC_STAC9254D, 0, "Sigmatel STAC9254D" },␊
␉{ HDA_CODEC_STAC9271X, 0, "Sigmatel STAC9271X" },␊
␉{ HDA_CODEC_STAC9271D, 0, "Sigmatel STAC9271D" },␊
␉{ HDA_CODEC_STAC9272X, 0, "Sigmatel STAC9272X" },␊
␉{ HDA_CODEC_STAC9272D, 0, "Sigmatel STAC9272D" },␊
␉{ HDA_CODEC_STAC9273X, 0, "Sigmatel STAC9273X" },␊
␉{ HDA_CODEC_STAC9273D, 0, "Sigmatel STAC9273D" },␊
␉{ HDA_CODEC_STAC9274, 0, "Sigmatel STAC9274" },␊
␉{ HDA_CODEC_STAC9274D, 0, "Sigmatel STAC9274D" },␊
␉{ HDA_CODEC_STAC9274X5NH, 0, "Sigmatel STAC9274X5NH" },␊
␉{ HDA_CODEC_STAC9274D5NH, 0, "Sigmatel STAC9274D5NH" },␊
␉{ HDA_CODEC_STAC9872AK, 0, "Sigmatel STAC9872AK" },␊
␉{ HDA_CODEC_IDT92HD005, 0, "IDT 92HD005" },␊
␉{ HDA_CODEC_IDT92HD005D, 0, "IDT 92HD005D" },␊
␉{ HDA_CODEC_IDT92HD206X, 0, "IDT 92HD206X" },␊
␉{ HDA_CODEC_IDT92HD206D, 0, "IDT 92HD206D" },␊
␉{ HDA_CODEC_IDT92HD66B1X5, 0, "IDT 92HD66B1X5" },␊
␉{ HDA_CODEC_IDT92HD66B2X5, 0, "IDT 92HD66B2X5" },␊
␉{ HDA_CODEC_IDT92HD66B3X5, 0, "IDT 92HD66B3X5" },␊
␉{ HDA_CODEC_IDT92HD66C1X5, 0, "IDT 92HD66C1X5" },␊
␉{ HDA_CODEC_IDT92HD66C2X5, 0, "IDT 92HD66C2X5" },␊
␉{ HDA_CODEC_IDT92HD66C3X5, 0, "IDT 92HD66C3X5" },␊
␉{ HDA_CODEC_IDT92HD66B1X3, 0, "IDT 92HD66B1X3" },␊
␉{ HDA_CODEC_IDT92HD66B2X3, 0, "IDT 92HD66B2X3" },␊
␉{ HDA_CODEC_IDT92HD66B3X3, 0, "IDT 92HD66B3X3" },␊
␉{ HDA_CODEC_IDT92HD66C1X3, 0, "IDT 92HD66C1X3" },␊
␉{ HDA_CODEC_IDT92HD66C2X3, 0, "IDT 92HD66C2X3" },␊
␉{ HDA_CODEC_IDT92HD66C3_65, 0, "IDT 92HD66C3_65" },␊
␉{ HDA_CODEC_IDT92HD700X, 0, "IDT 92HD700X" },␊
␉{ HDA_CODEC_IDT92HD700D, 0, "IDT 92HD700D" },␊
␉{ HDA_CODEC_IDT92HD71B5, 0, "IDT 92HD71B5" },␊
␉{ HDA_CODEC_IDT92HD71B5_2, 0, "IDT 92HD71B5" },␊
␉{ HDA_CODEC_IDT92HD71B6, 0, "IDT 92HD71B6" },␊
␉{ HDA_CODEC_IDT92HD71B6_2, 0, "IDT 92HD71B6" },␊
␉{ HDA_CODEC_IDT92HD71B7, 0, "IDT 92HD71B7" },␊
␉{ HDA_CODEC_IDT92HD71B7_2, 0, "IDT 92HD71B7" },␊
␉{ HDA_CODEC_IDT92HD71B8, 0, "IDT 92HD71B8" },␊
␉{ HDA_CODEC_IDT92HD71B8_2, 0, "IDT 92HD71B8" },␊
␉{ HDA_CODEC_IDT92HD73C1, 0, "IDT 92HD73C1" },␊
␉{ HDA_CODEC_IDT92HD73D1, 0, "IDT 92HD73D1" },␊
␉{ HDA_CODEC_IDT92HD73E1, 0, "IDT 92HD73E1" },␊
␉{ HDA_CODEC_IDT92HD75B3, 0, "IDT 92HD75B3" },␊
␉{ HDA_CODEC_IDT92HD75BX, 0, "IDT 92HD75BX" },␊
␉{ HDA_CODEC_IDT92HD81B1C, 0, "IDT 92HD81B1C" },␊
␉{ HDA_CODEC_IDT92HD81B1X, 0, "IDT 92HD81B1X" },␊
␉{ HDA_CODEC_IDT92HD83C1C, 0, "IDT 92HD83C1C" },␊
␉{ HDA_CODEC_IDT92HD83C1X, 0, "IDT 92HD83C1X" },␊
␉{ HDA_CODEC_IDT92HD87B1_3, 0, "IDT 92HD87B1/3" },␊
␉{ HDA_CODEC_IDT92HD87B2_4, 0, "IDT 92HD87B2/4" },␊
␉{ HDA_CODEC_IDT92HD89C3, 0, "IDT 92HD89C3" },␊
␉{ HDA_CODEC_IDT92HD89C2, 0, "IDT 92HD89C2" },␊
␉{ HDA_CODEC_IDT92HD89C1, 0, "IDT 92HD89C1" },␊
␉{ HDA_CODEC_IDT92HD89B3, 0, "IDT 92HD89B3" },␊
␉{ HDA_CODEC_IDT92HD89B2, 0, "IDT 92HD89B2" },␊
␉{ HDA_CODEC_IDT92HD89B1, 0, "IDT 92HD89B1" },␊
␉{ HDA_CODEC_IDT92HD89E3, 0, "IDT 92HD89E3" },␊
␉{ HDA_CODEC_IDT92HD89E2, 0, "IDT 92HD89E2" },␊
␉{ HDA_CODEC_IDT92HD89E1, 0, "IDT 92HD89E1" },␊
␉{ HDA_CODEC_IDT92HD89D3, 0, "IDT 92HD89D3" },␊
␉{ HDA_CODEC_IDT92HD89D2, 0, "IDT 92HD89D2" },␊
␉{ HDA_CODEC_IDT92HD89D1, 0, "IDT 92HD89D1" },␊
␉{ HDA_CODEC_IDT92HD89F3, 0, "IDT 92HD89F3" },␊
␉{ HDA_CODEC_IDT92HD89F2, 0, "IDT 92HD89F2" },␊
␉{ HDA_CODEC_IDT92HD89F1, 0, "IDT 92HD89F1" },␊
␉{ HDA_CODEC_IDT92HD90BXX, 0, "IDT 92HD90BXX" },␊
␉{ HDA_CODEC_IDT92HD91BXX, 0, "IDT 92HD91BXX" },␊
␉{ HDA_CODEC_IDT92HD93BXX, 0, "IDT 92HD93BXX" },␊
␉{ HDA_CODEC_IDT92HD98BXX, 0, "IDT 92HD98BXX" },␊
␉{ HDA_CODEC_IDT92HD99BXX, 0, "IDT 92HD99BXX" },␊
␉{ HDA_CODEC_CX20549, 0, "Conexant CX20549 (Venice)" },␊
␉{ HDA_CODEC_CX20551, 0, "Conexant CX20551 (Waikiki)" },␊
␉{ HDA_CODEC_CX20561, 0, "Conexant CX20561 (Hermosa)" },␊
␉{ HDA_CODEC_CX20582, 0, "Conexant CX20582 (Pebble)" },␊
␉{ HDA_CODEC_CX20583, 0, "Conexant CX20583 (Pebble HSF)" },␊
␉{ HDA_CODEC_CX20584, 0, "Conexant CX20584" },␊
␉{ HDA_CODEC_CX20585, 0, "Conexant CX20585" },␊
␉{ HDA_CODEC_CX20588, 0, "Conexant CX20588" },␊
␉{ HDA_CODEC_CX20590, 0, "Conexant CX20590" },␊
␉{ HDA_CODEC_CX20631, 0, "Conexant CX20631" },␊
␉{ HDA_CODEC_CX20632, 0, "Conexant CX20632" },␊
␉{ HDA_CODEC_CX20641, 0, "Conexant CX20641" },␊
␉{ HDA_CODEC_CX20642, 0, "Conexant CX20642" },␊
␉{ HDA_CODEC_CX20651, 0, "Conexant CX20651" },␊
␉{ HDA_CODEC_CX20652, 0, "Conexant CX20652" },␊
␉{ HDA_CODEC_CX20664, 0, "Conexant CX20664" },␊
␉{ HDA_CODEC_CX20665, 0, "Conexant CX20665" },␊
␉{ HDA_CODEC_VT1708_8, 0, "VIA VT1708_8" },␊
␉{ HDA_CODEC_VT1708_9, 0, "VIA VT1708_9" },␊
␉{ HDA_CODEC_VT1708_A, 0, "VIA VT1708_A" },␊
␉{ HDA_CODEC_VT1708_B, 0, "VIA VT1708_B" },␊
␉{ HDA_CODEC_VT1709_0, 0, "VIA VT1709_0" },␊
␉{ HDA_CODEC_VT1709_1, 0, "VIA VT1709_1" },␊
␉{ HDA_CODEC_VT1709_2, 0, "VIA VT1709_2" },␊
␉{ HDA_CODEC_VT1709_3, 0, "VIA VT1709_3" },␊
␉{ HDA_CODEC_VT1709_4, 0, "VIA VT1709_4" },␊
␉{ HDA_CODEC_VT1709_5, 0, "VIA VT1709_5" },␊
␉{ HDA_CODEC_VT1709_6, 0, "VIA VT1709_6" },␊
␉{ HDA_CODEC_VT1709_7, 0, "VIA VT1709_7" },␊
␉{ HDA_CODEC_VT1708B_0, 0, "VIA VT1708B_0" },␊
␉{ HDA_CODEC_VT1708B_1, 0, "VIA VT1708B_1" },␊
␉{ HDA_CODEC_VT1708B_2, 0, "VIA VT1708B_2" },␊
␉{ HDA_CODEC_VT1708B_3, 0, "VIA VT1708B_3" },␊
␉{ HDA_CODEC_VT1708B_4, 0, "VIA VT1708B_4" },␊
␉{ HDA_CODEC_VT1708B_5, 0, "VIA VT1708B_5" },␊
␉{ HDA_CODEC_VT1708B_6, 0, "VIA VT1708B_6" },␊
␉{ HDA_CODEC_VT1708B_7, 0, "VIA VT1708B_7" },␊
␉{ HDA_CODEC_VT1708S_0, 0, "VIA VT1708S_0" },␊
␉{ HDA_CODEC_VT1708S_1, 0, "VIA VT1708S_1" },␊
␉{ HDA_CODEC_VT1708S_2, 0, "VIA VT1708S_2" },␊
␉{ HDA_CODEC_VT1708S_3, 0, "VIA VT1708S_3" },␊
␉{ HDA_CODEC_VT1708S_4, 0, "VIA VT1708S_4" },␊
␉{ HDA_CODEC_VT1708S_5, 0, "VIA VT1708S_5" },␊
␉{ HDA_CODEC_VT1708S_6, 0, "VIA VT1708S_6" },␊
␉{ HDA_CODEC_VT1708S_7, 0, "VIA VT1708S_7" },␊
␉{ HDA_CODEC_VT1702_0, 0, "VIA VT1702_0" },␊
␉{ HDA_CODEC_VT1702_1, 0, "VIA VT1702_1" },␊
␉{ HDA_CODEC_VT1702_2, 0, "VIA VT1702_2" },␊
␉{ HDA_CODEC_VT1702_3, 0, "VIA VT1702_3" },␊
␉{ HDA_CODEC_VT1702_4, 0, "VIA VT1702_4" },␊
␉{ HDA_CODEC_VT1702_5, 0, "VIA VT1702_5" },␊
␉{ HDA_CODEC_VT1702_6, 0, "VIA VT1702_6" },␊
␉{ HDA_CODEC_VT1702_7, 0, "VIA VT1702_7" },␊
␉{ HDA_CODEC_VT1716S_0, 0, "VIA VT1716S_0" },␊
␉{ HDA_CODEC_VT1716S_1, 0, "VIA VT1716S_1" },␊
␉{ HDA_CODEC_VT1718S_0, 0, "VIA VT1718S_0" },␊
␉{ HDA_CODEC_VT1718S_1, 0, "VIA VT1718S_1" },␊
␉{ HDA_CODEC_VT1802_0, 0, "VIA VT1802_0" },␊
␉{ HDA_CODEC_VT1802_1, 0, "VIA VT1802_1" },␊
␉{ HDA_CODEC_VT1812, 0, "VIA VT1812" },␊
␉{ HDA_CODEC_VT1818S, 0, "VIA VT1818S" },␊
␉{ HDA_CODEC_VT1828S, 0, "VIA VT1828S" },␊
␉{ HDA_CODEC_VT2002P_0, 0, "VIA VT2002P_0" },␊
␉{ HDA_CODEC_VT2002P_1, 0, "VIA VT2002P_1" },␊
␉{ HDA_CODEC_VT2020, 0, "VIA VT2020" },␊
␉{ HDA_CODEC_ATIRS600_1, 0, "ATI RS600" },␊
␉{ HDA_CODEC_ATIRS600_2, 0, "ATI RS600" },␊
␉{ HDA_CODEC_ATIRS690, 0, "ATI RS690/780" },␊
␉{ HDA_CODEC_ATIR6XX, 0, "ATI R6xx" },␊
␉{ HDA_CODEC_NVIDIAMCP67, 0, "NVIDIA MCP67" },␊
␉{ HDA_CODEC_NVIDIAMCP73, 0, "NVIDIA MCP73" },␊
␉{ HDA_CODEC_NVIDIAMCP78, 0, "NVIDIA MCP78" },␊
␉{ HDA_CODEC_NVIDIAMCP78_2, 0, "NVIDIA MCP78" },␊
␉{ HDA_CODEC_NVIDIAMCP78_3, 0, "NVIDIA MCP78" },␊
␉{ HDA_CODEC_NVIDIAMCP78_4, 0, "NVIDIA MCP78" },␊
␉{ HDA_CODEC_NVIDIAMCP7A, 0, "NVIDIA MCP7A" },␊
␉{ HDA_CODEC_NVIDIAGT220, 0, "NVIDIA GT220" },␊
␉{ HDA_CODEC_NVIDIAGT21X, 0, "NVIDIA GT21x" },␊
␉{ HDA_CODEC_NVIDIAMCP89, 0, "NVIDIA MCP89" },␊
␉{ HDA_CODEC_NVIDIAGT240, 0, "NVIDIA GT240" },␊
␉{ HDA_CODEC_NVIDIAGTS450, 0, "NVIDIA GTS450" },␊
␉{ HDA_CODEC_NVIDIAGT440, 0, "NVIDIA GT440" },␊
␉{ HDA_CODEC_NVIDIAGTX550, 0, "NVIDIA GTX550" },␊
␉{ HDA_CODEC_NVIDIAGTX570, 0, "NVIDIA GTX570" },␊
␉{ HDA_CODEC_INTELIP, 0, "Intel Ibex Peak" },␊
␉{ HDA_CODEC_INTELBL, 0, "Intel Bearlake" },␊
␉{ HDA_CODEC_INTELCA, 0, "Intel Cantiga" },␊
␉{ HDA_CODEC_INTELEL, 0, "Intel Eaglelake" },␊
␉{ HDA_CODEC_INTELIP2, 0, "Intel Ibex Peak" },␊
␉{ HDA_CODEC_INTELCPT, 0, "Intel Cougar Point" },␊
␉{ HDA_CODEC_INTELPPT, 0, "Intel Panther Point" },␊
␉{ HDA_CODEC_INTELHSW, 0,␉"Intel Haswell" },␊
␉{ HDA_CODEC_INTELCL, 0, "Intel Crestline" },␊
␉{ HDA_CODEC_SII1390, 0, "Silicon Image SiI1390" },␊
␉{ HDA_CODEC_SII1392, 0, "Silicon Image SiI1392" },␊
␉// Unknown CODECs␊
␉{ HDA_CODEC_ADXXXX, 0, "Analog Devices" },␊
␉{ HDA_CODEC_AGEREXXXX, 0, "Lucent/Agere Systems" },␊
␉{ HDA_CODEC_ALCXXXX, 0, "Realtek" },␊
␉{ HDA_CODEC_ATIXXXX, 0, "ATI" },␊
␉{ HDA_CODEC_CAXXXX, 0, "Creative" },␊
␉{ HDA_CODEC_CMIXXXX, 0, "CMedia" },␊
␉{ HDA_CODEC_CMIXXXX2, 0, "CMedia" },␊
␉{ HDA_CODEC_CSXXXX, 0, "Cirrus Logic" },␊
␉{ HDA_CODEC_CXXXXX, 0, "Conexant" },␊
␉{ HDA_CODEC_CHXXXX, 0, "Chrontel" },␊
␉{ HDA_CODEC_IDTXXXX, 0, "IDT" },␊
␉{ HDA_CODEC_INTELXXXX, 0, "Intel" },␊
␉{ HDA_CODEC_MOTOXXXX, 0, "Motorola" },␊
␉{ HDA_CODEC_NVIDIAXXXX, 0, "NVIDIA" },␊
␉{ HDA_CODEC_SIIXXXX, 0, "Silicon Image" },␊
␉{ HDA_CODEC_STACXXXX, 0, "Sigmatel" },␊
␉{ HDA_CODEC_VTXXXX, 0, "VIA" },␊
};␊
␊
#define HDACC_CODECS_LEN (sizeof(know_codecs) / sizeof(know_codecs[0]))␊
*/␊
␊
trunk/i386/libsaio/hda.h
451451
452452
453453
454
454
455455
456456
457457
......
586586
587587
588588
589
589
590590
591591
592592
#define HDA_CODEC_CMI98802 HDA_CODEC_CONSTRUCT(CMEDIA2, 0x4980)␊
#define HDA_CODEC_CMIXXXX2 HDA_CODEC_CONSTRUCT(CMEDIA2, 0xffff)␊
␊
/* Sigmatel */␊
/* Sigmatel */␊
#define SIGMATEL_VENDORID 0x8384␊
#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612)␊
#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613)␊
#define HDA_CODEC_CX20665 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50b9)␊
#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff)␊
␊
/* VIA */␊
/* VIA */␊
#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708)␊
#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709)␊
#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a)␊
trunk/i386/libsaio/sys.c
963963
964964
965965
966
967
968
969
970
966971
967972
968973
......
980985
981986
982987
988
989
990
991
992
983993
984994
985995
......
9971007
9981008
9991009
1010
1011
1012
1013
1014
10001015
10011016
10021017
......
10371052
10381053
10391054
1055
1056
1057
1058
1059
10401060
10411061
10421062
␉{␊
␉␉for ( bvr = chain; bvr; bvr = bvr->next )␊
␉␉{␊
␉␉␉if (!bvr)␊
␉␉␉{␊
␉␉␉␉break;␊
␉␉␉}␊
␊
␉␉␉if ( (bvr->part_no == multiboot_partition) && (bvr->biosdev == gBIOSDev) )␊
␉␉␉{␊
␉␉␉␉return bvr;␊
␉{␊
␉␉for ( bvr = chain; bvr; bvr = bvr->next )␊
␉␉{␊
␉␉␉if (!bvr)␊
␉␉␉{␊
␉␉␉␉break;␊
␉␉␉}␊
␊
␉␉␉if (matchVolumeToString(bvr, val, false))␊
␉␉␉{␊
␉␉␉␉free(val);␊
␉ */␊
␉for ( bvr = chain; bvr; bvr = bvr->next )␊
␉{␊
␉␉if (!bvr)␊
␉␉{␊
␉␉␉break;␊
␉␉}␊
␊
␉␉if (multiboot_skip_partition_set)␊
␉␉{␊
␉␉␉if (bvr->part_no == multiboot_skip_partition)␊
␉{␊
␉␉for ( bvr = chain; bvr; bvr = bvr->next )␊
␉␉{␊
␉␉␉if (!bvr)␊
␉␉␉{␊
␉␉␉␉break;␊
␉␉␉}␊
␊
␉␉␉if ( (bvr->flags & kBVFlagNativeBoot) && (bvr->biosdev == gBIOSDev) )␊
␉␉␉{␊
␉␉␉␉bvr1 = bvr;␊
trunk/i386/libsaio/platform.h
7171
7272
7373
74
7574
7675
7776
......
348347
349348
350349
351
352
350
351
353352
354353
355354
356
355
357356
358357
359
358
360359
361360
362361
......
365364
366365
367366
368
369
367
368
370369
371370
372
373
374
375
376
377
378
379
380
381
382
383
371
372
373
374
375
376
377
378
379
380
381
382
384383
385
386
387
388
389
390
391
384
385
386
387
388
389
390
392391
393392
394393
395394
396
397
398
399
395
396
397
398
400399
401400
402
403
404
405
401
402
403
404
406405
407406
408407
......
412411
413412
414413
415
416
414
415
416
417417
418418
419419
//#define CPUID_MODEL_␉␉␉0x5A␉␉␉// Silvermont, Future Atom E3000, Z3000␊
//#define CPUID_MODEL_␉␉␉0x5D␉␉␉// Silvermont, Future Atom E3000, Z3000␊
␊
␊
/* CPUID Vendor */␊
#define␉CPUID_VID_INTEL␉␉␉"GenuineIntel"␊
#define␉CPUID_VID_AMD␉␉␉"AuthenticAMD"␊
␊
typedef struct _RamSlotInfo_t␊
{␊
␉uint32_t␉␉ModuleSize;␉␉␉␉␉// Size of Module in MB␊
␉uint32_t␉␉Frequency;␉␉␉␉␉// in Mhz␊
␉uint32_t␉␉ModuleSize;␉␉␉// Size of Module in MB␊
␉uint32_t␉␉Frequency;␉␉␉// in Mhz␊
␉const char*␉␉Vendor;␊
␉const char*␉␉PartNo;␊
␉const char*␉␉SerialNo;␊
␉char*␉␉␉spd;␉␉␉␉␉␉// SPD Dump␊
␉char*␉␉␉spd;␉␉␉␉// SPD Dump␊
␉bool␉␉␉InUse;␊
␉uint8_t␉␉␉Type;␊
␉uint8_t␉␉␉BankConnections;␉␉␉// table type 6, see (3.3.7)␊
␉uint8_t␉␉␉BankConnections;␉␉// table type 6, see (3.3.7)␊
␉uint8_t␉␉␉BankConnCnt;␊
} RamSlotInfo_t;␊
␊
typedef struct _PlatformInfo_t␊
{␊
␉struct CPU {␊
␉␉uint32_t␉␉Features;␉␉␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊
␉␉uint32_t␉␉Vendor;␉␉␉␉␉// Vendor␊
␉␉uint32_t␉␉Features;␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊
␉␉uint32_t␉␉Vendor;␉␉␉// Vendor␊
␉␉uint32_t␉␉CoresPerPackage;␊
␉␉uint32_t␉␉LogicalPerPackage;␊
␉␉uint32_t␉␉Signature;␉␉␉␉// Processor Signature␊
␉␉uint32_t␉␉Stepping;␉␉␉␉// Stepping␊
␉␉//uint16_t␉␉Type;␉␉␉␉␉// Type␊
␉␉uint32_t␉␉Model;␉␉␉␉␉// Model␊
␉␉uint32_t␉␉ExtModel;␉␉␉␉// Extended Model␊
␉␉uint32_t␉␉Family;␉␉␉␉␉// Family␊
␉␉uint32_t␉␉ExtFamily;␉␉␉␉// Extended Family␊
␉␉uint32_t␉␉NoCores;␉␉␉␉// No Cores per Package␊
␉␉uint32_t␉␉NoThreads;␉␉␉␉// Threads per Package␊
␉␉uint8_t␉␉␉MaxCoef;␉␉␉␉// Max Multiplier␊
␉␉uint8_t␉␉␉MaxDiv;␉␉␉␉␉// Min Multiplier␊
␉␉uint8_t␉␉␉CurrCoef;␉␉␉␉// Current Multiplier␊
␉␉uint32_t␉␉Signature;␉␉// Processor Signature␊
␉␉uint32_t␉␉Stepping;␉␉// Stepping␊
␉␉//uint16_t␉␉Type;␉␉␉// Type␊
␉␉uint32_t␉␉Model;␉␉␉// Model␊
␉␉uint32_t␉␉ExtModel;␉␉// Extended Model␊
␉␉uint32_t␉␉Family;␉␉␉// Family␊
␉␉uint32_t␉␉ExtFamily;␉␉// Extended Family␊
␉␉uint32_t␉␉NoCores;␉␉// No Cores per Package␊
␉␉uint32_t␉␉NoThreads;␉␉// Threads per Package␊
␉␉uint8_t␉␉␉MaxCoef;␉␉// Max Multiplier␊
␉␉uint8_t␉␉␉MaxDiv;␉␉␉// Min Multiplier␊
␉␉uint8_t␉␉␉CurrCoef;␉␉// Current Multiplier␊
␉␉uint8_t␉␉␉CurrDiv;␊
␉␉uint64_t␉␉TSCFrequency;␉␉␉␉// TSC Frequency Hz␊
␉␉uint64_t␉␉FSBFrequency;␉␉␉␉// FSB Frequency Hz␊
␉␉uint64_t␉␉CPUFrequency;␉␉␉␉// CPU Frequency Hz␊
␉␉uint32_t␉␉MaxRatio;␉␉␉␉// Max Bus Ratio␊
␉␉uint32_t␉␉MinRatio;␉␉␉␉// Min Bus Ratio␊
␉␉char␉␉␉BrandString[48];␉␉␉// 48 Byte Branding String␊
␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉␉␉// CPUID 0..4, 80..81 Raw Values␊
␉␉uint64_t␉␉TSCFrequency;␉␉// TSC Frequency Hz␊
␉␉uint64_t␉␉FSBFrequency;␉␉// FSB Frequency Hz␊
␉␉uint64_t␉␉CPUFrequency;␉␉// CPU Frequency Hz␊
␉␉uint32_t␉␉MaxRatio;␉␉// Max Bus Ratio␊
␉␉uint32_t␉␉MinRatio;␉␉// Min Bus Ratio␊
␉␉char␉␉␉BrandString[48];␉// 48 Byte Branding String␊
␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊
␊
␉} CPU;␊
␊
␉struct RAM {␊
␉␉uint64_t␉␉Frequency;␉␉␉␉// Ram Frequency␊
␉␉uint32_t␉␉Divider;␉␉␉␉// Memory divider␊
␉␉uint8_t␉␉␉CAS;␉␉␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊
␉␉uint8_t␉␉␉TRC;␉␉␉␉␉␊
␉␉uint64_t␉␉Frequency;␉␉// Ram Frequency␊
␉␉uint32_t␉␉Divider;␉␉// Memory divider␊
␉␉uint8_t␉␉␉CAS;␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊
␉␉uint8_t␉␉␉TRC;␉␊
␉␉uint8_t␉␉␉TRP;␊
␉␉uint8_t␉␉␉RAS;␊
␉␉uint8_t␉␉␉Channels;␉␉␉␉// Channel Configuration Single,Dual or Triple␊
␉␉uint8_t␉␉␉NoSlots;␉␉␉␉// Maximum no of slots available␊
␉␉uint8_t␉␉␉Type;␉␉␉␉␉// Standard SMBIOS v2.5 Memory Type␊
␉␉RamSlotInfo_t␉DIMM[MAX_RAM_SLOTS];␉// Information about each slot␊
␉␉uint8_t␉␉␉Channels;␉␉// Channel Configuration Single,Dual or Triple␊
␉␉uint8_t␉␉␉NoSlots;␉␉// Maximum no of slots available␊
␉␉uint8_t␉␉␉Type;␉␉␉// Standard SMBIOS v2.5 Memory Type␊
␉␉RamSlotInfo_t␉DIMM[MAX_RAM_SLOTS];␉␉// Information about each slot␊
␉} RAM;␊
␊
␉struct DMI {␊
␉␉int␉␉␉DIMM[MAX_RAM_SLOTS];␉// Information and SPD mapping for each slot␊
␉} DMI;␊
␊
␉uint8_t␉␉␉␉Type;␉␉␉// System Type: 1=Desktop, 2=Portable, 3=Workstation... according ACPI2.0 (FACP: PM_Profile)␊
␉uint8_t␉␉␉␉*UUID;␊
␉uint8_t␉␉␉␉Type;␉␉␉// system-type: 1=Desktop, 2=Portable, 3=Workstation... according ACPI2.0 (FACP: PM_Profile)␊
␉uint8_t␉␉␉␉*UUID;␉␉␉// system-id (SMBIOS Table 1: system uuid)␊
␊
} PlatformInfo_t;␊
␊
extern PlatformInfo_t Platform;␊
trunk/i386/libsaio/smbios.c
13131313
13141314
13151315
1316
1316
1317
13171318
13181319
13191320
......
14721473
14731474
14741475
1475
1476
14761477
14771478
14781479
␉␉}␊
␉}␊
␊
␉if (isZero || isOnes) { // if empty or setable...␊
␉if (isZero || isOnes) // if empty or setable...␊
␉{␊
␉␉verbose("No UUID present in SMBIOS System Information Table\n");␊
␉␉ret = FixedUUID; // ...set a fixed value for system-id = 000102030405060708090A0B0C0D0E0F␊
␉}␊
␉␉␉␉␉␉break;␊
␉␉␉␉}␊
␉␉␉␉break;␊
␉␉␉␉//␊
␊
␉␉␉case kSMBTypePhysicalMemoryArray:␊
␉␉␉␉Platform.DMI.MaxMemorySlots += ((SMBPhysicalMemoryArray *)structHeader)->numMemoryDevices;␊
␉␉␉␉break;␊
trunk/i386/libsaio/smbios.h
566566
567567
568568
569
569
570570
571571
572572
␉SMBString serialNumber;␊
␉SMBString assetTag;␊
␉SMBString partNumber;␊
␉// 2.5+ spec (40 bytes)␊
␉// 2.5+ spec (40 bytes) Apple still uses 2.4 spec␊
␉SMBByte coreCount;␊
␉SMBByte coreEnabled;␊
␉SMBByte threadCount;␊
trunk/i386/libsaio/pci.h
8181
8282
8383
84
85
86
87
84
85
86
87
88
8889
8990
9091
......
9798
9899
99100
100
101
101102
102103
103104
......
133134
134135
135136
136
137
138
139
140
141
142
137
138
139
140
141
142
143
143144
144145
145146
146
147
147
148
148149
149
150
150151
151152
152153
153154
154
155
155156
156
157
158
159
160
161
162
163
164
157
158
159
160
161
162
163
164
165
165166
166
167
168
169
167
168
169
170
170171
171172
172173
173174
174
175
176
175
176
177
177178
178
179
179180
180181
181182
......
192193
193194
194195
195
196
197
198
199
200
201
202
203
204
196
197
198
199
200
201
202
203
204
205
205206
206207
207208
208209
209
210
210211
211212
212
213
213
214
214215
215216
216217
217218
218219
219220
220
221
221
222
222223
223224
224225
225226
226227
227
228
228
229
229230
230
231
232
231
232
233
233234
234235
235236
236237
237
238
239
240
241
242
243
238
239
240
241
242
243
244
244245
245
246
246
247
247248
248
249
249250
250251
251252
252253
253254
254
255
255256
256
257
257258
258
259
260
261
262
263
264
259
260
261
262
263
264
265
265266
266267
267268
268269
269270
270271
271
272
273
274
275
276
272
273
274
275
276
277
277278
278279
279280
280
281
281282
282283
283284
284
285
285
286
286287
287
288
289
290
291
292
293
294
295
296
297
298
288
289
290
291
292
293
294
295
296
297
298
299
299300
300
301
301302
302303
303304
304
305
305306
306307
307308
......
321322
322323
323324
324
325
325
326
326327
327328
328329
......
331332
332333
333334
334
335
336
335
336
337
337338
338339
339340
340341
341342
342343
343
344
344345
345346
346347
347
348
348349
349
350
350351
351352
352353
353354
354355
355
356
357
358
359
360
361
362
363
356
357
358
359
360
361
362
363
364
364365
365366
366
367
367368
368369
369370
370
371
372
373
374
375
376
371
372
373
374
375
376
377
377378
378
379
380
381
379
380
381
382
382383
383384
384
385
386
387
388
389
390
385
386
387
388
389
390
391
391392
392393
393
394
394
395
395396
396
397
398
397
398
399
399400
400401
401402
402
403
403404
404405
405
406
406407
407408
408
409
409410
410411
411
412
412413
413414
414
415
415
416
416417
417418
418419
419
420
421
422
423
424
425
426
427
428
420
421
422
423
424
425
426
427
428
429
429430
430431
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
453454
454
455455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480480
481481
482482
483
483
484484
485485
486
487
488
489
490
491
492
493
494
486
487
488
489
490
491
492
493
494
495495
496496
497497
498
499
500
498
499
500
501501
502502
503
504
505
503
504
505
506506
507
508
509
510
507
508
509
510
511511
512
512
513513
514514
515
516
517
518
519
520
521
515
516
517
518
519
520
521
522522
523
523
524524
525525
526526
527527
528528
529
530
531
532
533
529
530
531
532
533
534534
535535
536536
537
538
537
538
539539
540540
541541
542542
543543
544544
545
546
547
548
549
550
551
552
545
546
547
548
549
550
551
552
553553
554
555
556
557
558
559
560
561
554
555
556
557
558
559
560
561
562562
563563
564564
......
567567
568568
569569
570
571
572
573
570
571
572
573
574574
575575
576576
......
582582
583583
584584
585
586
585
586
587587
588588
589589
590590
591591
592592
593
593
594594
595
596
595
596
597597
598598
599
599
600600
601601
602
602
603603
604
604
605605
606
607
608
606
607
608
609609
610610
611
612
613
611
612
613
614614
615615
616616
617617
618
619
620
621
622
623
624
625
618
619
620
621
622
623
624
625
626626
627
627
628628
629629
630630
......
642642
643643
644644
645
645
646646
647647
648648
649
649
650650
651
652
653
651
652
653
654654
655
655
656656
657657
658
659
658
659
660660
661
661
662662
663
663
664664
665665
666
667
668
669
670
666
667
668
669
670
671671
672
672
673673
674
675
676
677
678
679
674
675
676
677
678
679
680680
681
681
682682
683683
684684
......
691691
692692
693693
694
695
696
697
698
699
700
701
702
703
694
695
696
697
698
699
700
701
702
703
704704
705705
706
706
707707
708708
709709
710
710
711711
712712
713713
714
714
715715
716716
717717
718
719
720
718
719
720
721721
722722
723723
724724
725725
726
726
727727
728728
729
729
730730
731731
732732
733
733
734734
735735
736
737
738
739
740
736
737
738
739
740
741741
742742
743
743
744744
745
745
746746
747747
748748
......
754754
755755
756756
757
757
758758
759759
760
760
761761
762762
763763
764
764
765765
766766
767
767
768768
769769
770770
......
800800
801801
802802
803
803
804804
805805
806806
......
893893
894894
895895
896
897
898
899
896
897
898
899
900900
901901
902902
......
906906
907907
908908
909
910
909
910
911911
912912
913913
......
937937
938938
939939
940
940
941941
942942
943943
944944
945945
946946
947
948
949
947
948
949
950950
951951
952952
/* Option ROM header */␊
typedef struct {␊
␉uint16_t␉␉signature;␉␉// 0xAA55␊
␉uint8_t␉␉␉rom_size;␊
␉uint32_t␉␉entry_point;␊
␉uint8_t␉␉␉reserved[15];␊
␉uint16_t␉␉pci_header_offset;␊
␉uint8_t␉␉␉rom_size;␉␉// in 512 bytes blocks␊
␉uint8_t␉␉␉jump;␉␉␉// 0xE9 for ATI and Intel, 0xEB for NVidia␊
␉uint8_t␉␉␉entry_point[4];␉␉// offset to␊
␉uint8_t␉␉␉reserved[16];␊
␉uint16_t␉␉pci_header_offset;␉// @0x18␊
␉uint16_t␉␉expansion_header_offset;␊
} option_rom_header_t;␊
␊
␉uint16_t␉␉structure_length;␊
␉uint8_t␉␉␉structure_revision;␊
␉uint8_t␉␉␉class_code[3];␊
␉uint16_t␉␉image_length;␊
␉uint16_t␉␉image_length;␉␉//same as rom_size for NVidia and ATI, 0x80 for Intel␊
␉uint16_t␉␉image_revision;␊
␉uint8_t␉␉␉code_type;␊
␉uint8_t␉␉␉indicator;␊
*******************************************************/␊
#define PCI_VENDOR_ID␉␉␉␉␉␉0x00␉␉/* 16 bits */␊
#define PCI_DEVICE_ID␉␉␉␉␉␉0x02␉␉/* 16 bits */␊
#define PCI_COMMAND␉␉␉␉␉␉␉0x04␉␉/* 16 bits */␊
#define PCI_COMMAND_IO␉␉␉␉␉␉0x1␉␉␉/* Enable response in I/O space */␊
#define PCI_COMMAND_MEMORY␉␉␉␉␉0x2␉␉␉/* Enable response in Memory space */␊
#define PCI_COMMAND_MASTER␉␉␉␉␉0x4␉␉␉/* Enable bus mastering */␊
#define PCI_COMMAND_SPECIAL␉␉␉␉␉0x8␉␉␉/* Enable response to special cycles */␊
#define PCI_COMMAND_INVALIDATE␉␉␉␉0x10␉␉/* Use memory write and invalidate */␊
#define PCI_COMMAND_VGA_PALETTE␉␉␉␉0x20␉␉/* Enable palette snooping */␊
#define PCI_COMMAND␉␉␉␉␉␉0x04␉␉/* 16 bits */␊
#define PCI_COMMAND_IO␉␉␉␉␉␉0x1␉␉/* Enable response in I/O space */␊
#define PCI_COMMAND_MEMORY␉␉␉␉␉0x2␉␉/* Enable response in Memory space */␊
#define PCI_COMMAND_MASTER␉␉␉␉␉0x4␉␉/* Enable bus mastering */␊
#define PCI_COMMAND_SPECIAL␉␉␉␉␉0x8␉␉/* Enable response to special cycles */␊
#define PCI_COMMAND_INVALIDATE␉␉␉␉␉0x10␉␉/* Use memory write and invalidate */␊
#define PCI_COMMAND_VGA_PALETTE␉␉␉␉␉0x20␉␉/* Enable palette snooping */␊
#define PCI_COMMAND_PARITY␉␉␉␉␉0x40␉␉/* Enable parity checking */␊
#define PCI_COMMAND_WAIT␉␉␉␉␉0x80␉␉/* Enable address/data stepping */␊
#define PCI_COMMAND_SERR␉␉␉␉␉0x100␉␉/* Enable SERR */␊
#define PCI_COMMAND_FAST_BACK␉␉␉␉0x200␉␉/* Enable back-to-back writes */␊
#define PCI_COMMAND_DISABLE_INTx␉␉␉0x400␉␉/* PCIE: Disable INTx interrupts */␊
#define PCI_COMMAND_FAST_BACK␉␉␉␉␉0x200␉␉/* Enable back-to-back writes */␊
#define PCI_COMMAND_DISABLE_INTx␉␉␉␉0x400␉␉/* PCIE: Disable INTx interrupts */␊
␊
#define PCI_STATUS␉␉␉␉␉␉␉0x06␉␉/* 16 bits */␊
#define PCI_STATUS␉␉␉␉␉␉0x06␉␉/* 16 bits */␊
#define PCI_STATUS_INTx␉␉␉␉␉␉0x08␉␉/* PCIE: INTx interrupt pending */␊
#define PCI_STATUS_CAP_LIST␉␉␉␉␉0x10␉␉/* Support Capability List */␊
#define PCI_STATUS_66MHZ␉␉␉␉␉0x20␉␉/* Support 66 Mhz PCI 2.1 bus */␊
#define PCI_STATUS_UDF␉␉␉␉␉␉0x40␉␉/* Support User Definable Features [obsolete] */␊
#define PCI_STATUS_FAST_BACK␉␉␉␉0x80␉␉/* Accept fast-back to back */␊
#define PCI_STATUS_FAST_BACK␉␉␉␉␉0x80␉␉/* Accept fast-back to back */␊
#define PCI_STATUS_PARITY␉␉␉␉␉0x100␉␉/* Detected parity error */␊
#define PCI_STATUS_DEVSEL_MASK␉␉␉␉0x600␉␉/* DEVSEL timing */␊
#define PCI_STATUS_DEVSEL_FAST␉␉␉␉0x000␊
#define PCI_STATUS_DEVSEL_MEDIUM␉␉␉0x200␊
#define PCI_STATUS_DEVSEL_SLOW␉␉␉␉0x400␊
#define PCI_STATUS_SIG_TARGET_ABORT ␉␉0x800␉␉/* Set on target abort */␊
#define PCI_STATUS_REC_TARGET_ABORT ␉␉0x1000␉␉/* Master ack of " */␊
#define PCI_STATUS_REC_MASTER_ABORT ␉␉0x2000␉␉/* Set on master abort */␊
#define PCI_STATUS_SIG_SYSTEM_ERROR ␉␉0x4000␉␉/* Set when we drive SERR */␊
#define PCI_STATUS_DETECTED_PARITY␉␉␉0x8000␉␉/* Set on parity error */␊
#define PCI_STATUS_DEVSEL_MASK␉␉␉␉␉0x600␉␉/* DEVSEL timing */␊
#define PCI_STATUS_DEVSEL_FAST␉␉␉␉␉0x000␊
#define PCI_STATUS_DEVSEL_MEDIUM␉␉␉␉0x200␊
#define PCI_STATUS_DEVSEL_SLOW␉␉␉␉␉0x400␊
#define PCI_STATUS_SIG_TARGET_ABORT␉␉␉␉0x800␉␉/* Set on target abort */␊
#define PCI_STATUS_REC_TARGET_ABORT␉␉␉␉0x1000␉␉/* Master ack of " */␊
#define PCI_STATUS_REC_MASTER_ABORT␉␉␉␉0x2000␉␉/* Set on master abort */␊
#define PCI_STATUS_SIG_SYSTEM_ERROR␉␉␉␉0x4000␉␉/* Set when we drive SERR */␊
#define PCI_STATUS_DETECTED_PARITY␉␉␉␉0x8000␉␉/* Set on parity error */␊
␊
#define PCI_CLASS_REVISION␉␉␉␉␉0x08␉␉␉/* High 24 bits are class, low 8 revision */␊
#define PCI_CLASS_PROG␉␉␉␉␉␉0x09␉␉␉/* Reg. Level Programming Interface know also as PCI_PROG_IF */␊
#define PCI_CLASS_DEVICE␉␉␉␉␉0x0a␉␉␉/* Device subclass */␊
//#define PCI_SUBCLASS_DEVICE␉␉␉␉0x0b␉␉␉/* Device class */␊
#define PCI_CLASS_REVISION␉␉␉␉␉0x08␉␉/* High 24 bits are class, low 8 revision */␊
#define PCI_CLASS_PROG␉␉␉␉␉␉0x09␉␉/* Reg. Level Programming Interface know also as PCI_PROG_IF */␊
#define PCI_CLASS_DEVICE␉␉␉␉␉0x0a␉␉/* Device subclass */␊
//#define PCI_SUBCLASS_DEVICE␉␉␉␉␉0x0b␉␉/* Device class */␊
␊
#define PCI_CACHE_LINE_SIZE␉␉␉␉␉0x0c␉␉/* 8 bits */␊
#define PCI_LATENCY_TIMER␉␉␉␉␉0x0d␉␉/* 8 bits */␊
#define PCI_HEADER_TYPE␉␉␉␉␉␉0x0e␉␉/* 8 bits */␊
#define PCI_HEADER_TYPE_NORMAL␉␉␉␉0␊
#define PCI_HEADER_TYPE_BRIDGE␉␉␉␉1␊
#define PCI_HEADER_TYPE_CARDBUS␉␉␉␉2␉␊
#define PCI_HEADER_TYPE_NORMAL␉␉␉␉␉0␊
#define PCI_HEADER_TYPE_BRIDGE␉␉␉␉␉1␊
#define PCI_HEADER_TYPE_CARDBUS␉␉␉␉␉2␊
␊
#define PCI_BIST␉␉␉␉␉␉␉0x0f␉␉/* 8 bits */␊
#define PCI_BIST␉␉␉␉␉␉0x0f␉␉/* 8 bits */␊
#define PCI_BIST_CODE_MASK␉␉␉␉␉0x0f␉␉/* Return result */␊
#define PCI_BIST_START␉␉␉␉␉␉0x40␉␉/* 1 to start BIST, 2 secs or less */␊
#define PCI_BIST_CAPABLE␉␉␉␉␉0x80␉␉/* 1 if BIST capable */␊
#define PCI_BASE_ADDRESS_3␉␉␉␉␉0x1c␉␉/* 32 bits */␊
#define PCI_BASE_ADDRESS_4␉␉␉␉␉0x20␉␉/* 32 bits */␊
#define PCI_BASE_ADDRESS_5␉␉␉␉␉0x24␉␉/* 32 bits */␊
#define PCI_BASE_ADDRESS_SPACE␉␉␉␉0x01␉␉/* 0 = memory, 1 = I/O */␊
#define PCI_BASE_ADDRESS_SPACE_IO␉␉␉0x01␊
#define PCI_BASE_ADDRESS_SPACE_MEMORY␉␉0x00␊
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK␉␉0x06␊
#define PCI_BASE_ADDRESS_MEM_TYPE_32␉␉0x00␉␉/* 32 bit address */␊
#define PCI_BASE_ADDRESS_MEM_TYPE_1M␉␉0x02␉␉/* Below 1M [obsolete] */␊
#define PCI_BASE_ADDRESS_MEM_TYPE_64␉␉0x04␉␉/* 64 bit address */␊
#define PCI_BASE_ADDRESS_MEM_PREFETCH␉␉0x08␉␉/* prefetchable? */␊
#define PCI_BASE_ADDRESS_MEM_MASK␉␉␉(~(pciaddr_t)0x0f)␊
#define PCI_BASE_ADDRESS_IO_MASK␉␉␉(~(pciaddr_t)0x03)␊
#define PCI_BASE_ADDRESS_SPACE␉␉␉␉␉0x01␉␉/* 0 = memory, 1 = I/O */␊
#define PCI_BASE_ADDRESS_SPACE_IO␉␉␉␉0x01␊
#define PCI_BASE_ADDRESS_SPACE_MEMORY␉␉␉␉0x00␊
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK␉␉␉␉0x06␊
#define PCI_BASE_ADDRESS_MEM_TYPE_32␉␉␉␉0x00␉␉/* 32 bit address */␊
#define PCI_BASE_ADDRESS_MEM_TYPE_1M␉␉␉␉0x02␉␉/* Below 1M [obsolete] */␊
#define PCI_BASE_ADDRESS_MEM_TYPE_64␉␉␉␉0x04␉␉/* 64 bit address */␊
#define PCI_BASE_ADDRESS_MEM_PREFETCH␉␉␉␉0x08␉␉/* prefetchable? */␊
#define PCI_BASE_ADDRESS_MEM_MASK␉␉␉␉(~(pciaddr_t)0x0f)␊
#define PCI_BASE_ADDRESS_IO_MASK␉␉␉␉(~(pciaddr_t)0x03)␊
/* bit 1 is reserved if address_space = 1 */␊
␊
/* Header type 0 (normal devices) */␊
#define PCI_CARDBUS_CIS␉␉␉␉␉␉0x28␊
#define PCI_SUBSYSTEM_VENDOR_ID␉␉␉␉0x2c␊
#define PCI_SUBSYSTEM_VENDOR_ID␉␉␉␉␉0x2c␊
#define PCI_SUBSYSTEM_ID␉␉␉␉␉0x2e␊
#define PCI_ROM_ADDRESS␉␉␉␉␉␉0x30␉␉/* Bits 31..11 are address, 10..1 reserved */␊
#define PCI_ROM_ADDRESS_ENABLE␉␉␉␉0x01␊
#define PCI_ROM_ADDRESS_MASK␉␉␉␉(~(pciaddr_t)0x7ff)␊
#define PCI_ROM_ADDRESS_ENABLE␉␉␉␉␉0x01␊
#define PCI_ROM_ADDRESS_MASK␉␉␉␉␉(~(pciaddr_t)0x7ff)␊
␊
#define PCI_CAPABILITY_LIST␉␉␉␉␉0x34␉␉/* Offset of first capability list entry */␊
␊
/* 0x35-0x3b are reserved */␊
#define PCI_INTERRUPT_LINE␉␉␉␉␉0x3c␉␉/* 8 bits */␊
#define PCI_INTERRUPT_PIN␉␉␉␉␉0x3d␉␉/* 8 bits */␊
#define PCI_MIN_GNT␉␉␉␉␉␉␉0x3e␉␉/* 8 bits */␊
#define PCI_MAX_LAT␉␉␉␉␉␉␉0x3f␉␉/* 8 bits */␊
#define PCI_MIN_GNT␉␉␉␉␉␉0x3e␉␉/* 8 bits */␊
#define PCI_MAX_LAT␉␉␉␉␉␉0x3f␉␉/* 8 bits */␊
␊
/* Header type 1 (PCI-to-PCI bridges) */␊
#define PCI_PRIMARY_BUS␉␉␉␉␉␉0x18␉␉/* Primary bus number */␊
#define PCI_SECONDARY_BUS␉␉␉␉␉0x19␉␉/* Secondary bus number */␊
#define PCI_SUBORDINATE_BUS␉␉␉␉␉0x1a␉␉/* Highest bus number behind the bridge */␊
#define PCI_SEC_LATENCY_TIMER␉␉␉␉0x1b␉␉/* Latency timer for secondary interface */␊
#define PCI_IO_BASE␉␉␉␉␉␉␉0x1c␉␉/* I/O range behind the bridge */␊
#define PCI_SEC_LATENCY_TIMER␉␉␉␉␉0x1b␉␉/* Latency timer for secondary interface */␊
#define PCI_IO_BASE␉␉␉␉␉␉0x1c␉␉/* I/O range behind the bridge */␊
#define PCI_IO_LIMIT␉␉␉␉␉␉0x1d␊
#define PCI_IO_RANGE_TYPE_MASK␉␉␉␉0x0f␉␉/* I/O bridging type */␊
#define PCI_IO_RANGE_TYPE_16␉␉␉␉0x00␊
#define PCI_IO_RANGE_TYPE_32␉␉␉␉0x01␊
#define PCI_IO_RANGE_TYPE_MASK␉␉␉␉␉0x0f␉␉/* I/O bridging type */␊
#define PCI_IO_RANGE_TYPE_16␉␉␉␉␉0x00␊
#define PCI_IO_RANGE_TYPE_32␉␉␉␉␉0x01␊
#define PCI_IO_RANGE_MASK␉␉␉␉␉~0x0f␊
#define PCI_SEC_STATUS␉␉␉␉␉␉0x1e␉␉/* Secondary status register */␊
#define PCI_MEMORY_BASE␉␉␉␉␉␉0x20␉␉/* Memory range behind */␊
#define PCI_MEMORY_LIMIT␉␉␉␉␉0x22␊
#define PCI_MEMORY_RANGE_TYPE_MASK␉␉␉0x0f␊
#define PCI_MEMORY_RANGE_MASK␉␉␉␉~0x0f␊
#define PCI_PREF_MEMORY_BASE␉␉␉␉0x24␉␉/* Prefetchable memory range behind */␊
#define PCI_PREF_MEMORY_LIMIT␉␉␉␉0x26␊
#define PCI_PREF_RANGE_TYPE_MASK␉␉␉0x0f␊
#define PCI_PREF_RANGE_TYPE_32␉␉␉␉0x00␊
#define PCI_PREF_RANGE_TYPE_64␉␉␉␉0x01␊
#define PCI_MEMORY_RANGE_TYPE_MASK␉␉␉␉0x0f␊
#define PCI_MEMORY_RANGE_MASK␉␉␉␉␉~0x0f␊
#define PCI_PREF_MEMORY_BASE␉␉␉␉␉0x24␉␉/* Prefetchable memory range behind */␊
#define PCI_PREF_MEMORY_LIMIT␉␉␉␉␉0x26␊
#define PCI_PREF_RANGE_TYPE_MASK␉␉␉␉0x0f␊
#define PCI_PREF_RANGE_TYPE_32␉␉␉␉␉0x00␊
#define PCI_PREF_RANGE_TYPE_64␉␉␉␉␉0x01␊
#define PCI_PREF_RANGE_MASK␉␉␉␉␉~0x0f␊
#define PCI_PREF_BASE_UPPER32␉␉␉␉0x28␉␉/* Upper half of prefetchable memory range */␊
#define PCI_PREF_LIMIT_UPPER32␉␉␉␉0x2c␊
#define PCI_PREF_BASE_UPPER32␉␉␉␉␉0x28␉␉/* Upper half of prefetchable memory range */␊
#define PCI_PREF_LIMIT_UPPER32␉␉␉␉␉0x2c␊
#define PCI_IO_BASE_UPPER16␉␉␉␉␉0x30␉␉/* Upper half of I/O addresses */␊
#define PCI_IO_LIMIT_UPPER16␉␉␉␉0x32␊
#define PCI_IO_LIMIT_UPPER16␉␉␉␉␉0x32␊
/* 0x34 same as for htype 0 */␊
/* 0x35-0x3b is reserved */␊
#define PCI_ROM_ADDRESS1␉␉␉␉␉0x38␉␉/* Same as PCI_ROM_ADDRESS, but for htype 1 */␊
/* 0x3c-0x3d are same as for htype 0 */␊
#define PCI_BRIDGE_CONTROL␉␉␉␉␉0x3e␊
#define PCI_BRIDGE_CTL_PARITY␉␉␉␉0x01␉␉/* Enable parity detection on secondary interface */␊
#define PCI_BRIDGE_CTL_PARITY␉␉␉␉␉0x01␉␉/* Enable parity detection on secondary interface */␊
#define PCI_BRIDGE_CTL_SERR␉␉␉␉␉0x02␉␉/* The same for SERR forwarding */␊
#define PCI_BRIDGE_CTL_NO_ISA␉␉␉␉0x04␉␉/* Disable bridging of ISA ports */␊
#define PCI_BRIDGE_CTL_NO_ISA␉␉␉␉␉0x04␉␉/* Disable bridging of ISA ports */␊
#define PCI_BRIDGE_CTL_VGA␉␉␉␉␉0x08␉␉/* Forward VGA addresses */␊
#define PCI_BRIDGE_CTL_MASTER_ABORT␉␉␉0x20␉␉/* Report master aborts */␊
#define PCI_BRIDGE_CTL_BUS_RESET␉␉␉0x40␉␉/* Secondary bus reset */␊
#define PCI_BRIDGE_CTL_FAST_BACK␉␉␉0x80␉␉/* Fast Back2Back enabled on secondary interface */␊
#define PCI_BRIDGE_CTL_PRI_DISCARD_TIMER ␉0x100␉␉/* PCI-X? */␊
#define PCI_BRIDGE_CTL_SEC_DISCARD_TIMER ␉0x200␉␉/* PCI-X? */␊
#define PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS 0x400␉␉/* PCI-X? */␊
#define PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800␉␉/* PCI-X? */␊
#define PCI_BRIDGE_CTL_MASTER_ABORT␉␉␉␉0x20␉␉/* Report master aborts */␊
#define PCI_BRIDGE_CTL_BUS_RESET␉␉␉␉0x40␉␉/* Secondary bus reset */␊
#define PCI_BRIDGE_CTL_FAST_BACK␉␉␉␉0x80␉␉/* Fast Back2Back enabled on secondary interface */␊
#define PCI_BRIDGE_CTL_PRI_DISCARD_TIMER␉␉␉0x100␉␉/* PCI-X? */␊
#define PCI_BRIDGE_CTL_SEC_DISCARD_TIMER␉␉␉0x200␉␉/* PCI-X? */␊
#define PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS␉␉␉0x400␉␉/* PCI-X? */␊
#define PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN␉␉␉0x800␉␉/* PCI-X? */␊
␊
/* Header type 2 (CardBus bridges) */␊
/* 0x14-0x15 reserved */␊
#define PCI_CB_SEC_STATUS␉␉␉␉␉0x16␉␉/* Secondary status */␊
#define PCI_CB_PRIMARY_BUS␉␉␉␉␉0x18␉␉/* PCI bus number */␊
#define PCI_CB_CARD_BUS␉␉␉␉␉␉0x19␉␉/* CardBus bus number */␊
#define PCI_CB_SUBORDINATE_BUS␉␉␉␉0x1a␉␉/* Subordinate bus number */␊
#define PCI_CB_LATENCY_TIMER␉␉␉␉0x1b␉␉/* CardBus latency timer */␊
#define PCI_CB_MEMORY_BASE_0␉␉␉␉0x1c␊
#define PCI_CB_MEMORY_LIMIT_0␉␉␉␉0x20␊
#define PCI_CB_MEMORY_BASE_1␉␉␉␉0x24␊
#define PCI_CB_MEMORY_LIMIT_1␉␉␉␉0x28␊
#define PCI_CB_SUBORDINATE_BUS␉␉␉␉␉0x1a␉␉/* Subordinate bus number */␊
#define PCI_CB_LATENCY_TIMER␉␉␉␉␉0x1b␉␉/* CardBus latency timer */␊
#define PCI_CB_MEMORY_BASE_0␉␉␉␉␉0x1c␊
#define PCI_CB_MEMORY_LIMIT_0␉␉␉␉␉0x20␊
#define PCI_CB_MEMORY_BASE_1␉␉␉␉␉0x24␊
#define PCI_CB_MEMORY_LIMIT_1␉␉␉␉␉0x28␊
#define PCI_CB_IO_BASE_0␉␉␉␉␉0x2c␊
#define PCI_CB_IO_BASE_0_HI␉␉␉␉␉0x2e␊
#define PCI_CB_IO_LIMIT_0␉␉␉␉␉0x30␊
#define PCI_CB_IO_LIMIT_0_HI␉␉␉␉0x32␊
#define PCI_CB_IO_LIMIT_0_HI␉␉␉␉␉0x32␊
#define PCI_CB_IO_BASE_1␉␉␉␉␉0x34␊
#define PCI_CB_IO_BASE_1_HI␉␉␉␉␉0x36␊
#define PCI_CB_IO_LIMIT_1␉␉␉␉␉0x38␊
#define PCI_CB_IO_LIMIT_1_HI␉␉␉␉0x3a␊
#define␉ PCI_CB_IO_RANGE_MASK␉␉␉␉~0x03␊
#define PCI_CB_IO_LIMIT_1_HI␉␉␉␉␉0x3a␊
#define␉ PCI_CB_IO_RANGE_MASK␉␉␉␉␉~0x03␊
/* 0x3c-0x3d are same as for htype 0 */␊
#define PCI_CB_BRIDGE_CONTROL␉␉␉␉0x3e␊
#define PCI_CB_BRIDGE_CTL_PARITY␉␉␉0x01␉␉/* Similar to standard bridge control register */␊
#define PCI_CB_BRIDGE_CTL_SERR␉␉␉␉0x02␊
#define PCI_CB_BRIDGE_CTL_ISA␉␉␉␉0x04␊
#define PCI_CB_BRIDGE_CTL_VGA␉␉␉␉0x08␊
#define PCI_CB_BRIDGE_CTL_MASTER_ABORT␉␉0x20␊
#define PCI_CB_BRIDGE_CTL_CB_RESET␉␉␉0x40␉␉/* CardBus reset */␊
#define PCI_CB_BRIDGE_CTL_16BIT_INT␉␉␉0x80␉␉/* Enable interrupt for 16-bit cards */␊
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 ␉0x100␉␉/* Prefetch enable for both memory regions */␊
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 ␉0x200␊
#define PCI_CB_BRIDGE_CTL_POST_WRITES␉␉0x400␊
#define PCI_CB_SUBSYSTEM_VENDOR_ID␉␉␉0x40␊
#define PCI_CB_BRIDGE_CONTROL␉␉␉␉␉0x3e␊
#define PCI_CB_BRIDGE_CTL_PARITY␉␉␉␉0x01␉␉/* Similar to standard bridge control register */␊
#define PCI_CB_BRIDGE_CTL_SERR␉␉␉␉␉0x02␊
#define PCI_CB_BRIDGE_CTL_ISA␉␉␉␉␉0x04␊
#define PCI_CB_BRIDGE_CTL_VGA␉␉␉␉␉0x08␊
#define PCI_CB_BRIDGE_CTL_MASTER_ABORT␉␉␉␉0x20␊
#define PCI_CB_BRIDGE_CTL_CB_RESET␉␉␉␉0x40␉␉/* CardBus reset */␊
#define PCI_CB_BRIDGE_CTL_16BIT_INT␉␉␉␉0x80␉␉/* Enable interrupt for 16-bit cards */␊
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0␉␉␉␉0x100␉␉/* Prefetch enable for both memory regions */␊
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1␉␉␉␉0x200␊
#define PCI_CB_BRIDGE_CTL_POST_WRITES␉␉␉␉0x400␊
#define PCI_CB_SUBSYSTEM_VENDOR_ID␉␉␉␉0x40␊
#define PCI_CB_SUBSYSTEM_ID␉␉␉␉␉0x42␊
#define PCI_CB_LEGACY_MODE_BASE␉␉␉␉0x44␉␉/* 16-bit PC Card legacy mode base address (ExCa) */␊
#define PCI_CB_LEGACY_MODE_BASE␉␉␉␉␉0x44␉␉/* 16-bit PC Card legacy mode base address (ExCa) */␊
/* 0x48-0x7f reserved */␊
␊
/* Capability Identification Numbers list */␊
#define PCI_CAP_LIST_ID␉␉␉␉␉␉0␉␉␉/* Capability ID */␊
#define PCI_CAP_LIST_ID␉␉␉␉␉␉0␉␉/* Capability ID */␊
#define PCI_CAP_ID_PM␉␉␉␉␉␉0x01␉␉/* Power Management */␊
#define PCI_CAP_ID_AGP␉␉␉␉␉␉0x02␉␉/* Accelerated Graphics Port */␊
#define PCI_CAP_ID_VPD␉␉␉␉␉␉0x03␉␉/* Vital Product Data */␊
#define PCI_CAP_ID_MSIX␉␉␉␉␉␉0x11␉␉/* MSI-X */␊
#define PCI_CAP_ID_SATA␉␉␉␉␉␉0x12␉␉/* Serial-ATA HBA */␊
#define PCI_CAP_ID_AF␉␉␉␉␉␉0x13␉␉/* Advanced features of PCI devices integrated in PCIe root cplx */␊
#define PCI_CAP_LIST_NEXT␉␉␉␉␉1␉␉␉/* Next capability in the list */␊
#define PCI_CAP_FLAGS␉␉␉␉␉␉2␉␉␉/* Capability defined flags (16 bits) */␊
#define PCI_CAP_LIST_NEXT␉␉␉␉␉1␉␉/* Next capability in the list */␊
#define PCI_CAP_FLAGS␉␉␉␉␉␉2␉␉/* Capability defined flags (16 bits) */␊
#define PCI_CAP_SIZEOF␉␉␉␉␉␉4␊
␊
/* Capabilities residing in the␊
#define PCI_EXT_CAP_ID_VC␉␉␉␉␉0x02␉␉/* Virtual Channel */␊
#define PCI_EXT_CAP_ID_DSN␉␉␉␉␉0x03␉␉/* Device Serial Number */␊
#define PCI_EXT_CAP_ID_PB␉␉␉␉␉0x04␉␉/* Power Budgeting */␊
#define PCI_EXT_CAP_ID_RCLINK␉␉␉␉0x05␉␉/* Root Complex Link Declaration */␊
#define PCI_EXT_CAP_ID_RCILINK␉␉␉␉0x06␉␉/* Root Complex Internal Link Declaration */␊
#define PCI_EXT_CAP_ID_RCECOLL␉␉␉␉0x07␉␉/* Root Complex Event Collector */␊
#define PCI_EXT_CAP_ID_RCLINK␉␉␉␉␉0x05␉␉/* Root Complex Link Declaration */␊
#define PCI_EXT_CAP_ID_RCILINK␉␉␉␉␉0x06␉␉/* Root Complex Internal Link Declaration */␊
#define PCI_EXT_CAP_ID_RCECOLL␉␉␉␉␉0x07␉␉/* Root Complex Event Collector */␊
#define PCI_EXT_CAP_ID_MFVC␉␉␉␉␉0x08␉␉/* Multi-Function Virtual Channel */␊
#define PCI_EXT_CAP_ID_RBCB␉␉␉␉␉0x0a␉␉/* Root Bridge Control Block */␊
#define PCI_EXT_CAP_ID_VNDR␉␉␉␉␉0x0b␉␉/* Vendor specific */␊
#define PCI_EXT_CAP_ID_ACS␉␉␉␉␉0x0d␉␉/* Access Controls */␊
#define PCI_EXT_CAP_ID_ARI␉␉␉␉␉0x0e␉␉/* Alternative Routing-ID Interpretation */␊
#define PCI_EXT_CAP_ID_ATS␉␉␉␉␉0x0f␉␉/* Address Translation Service */␊
#define PCI_EXT_CAP_ID_SRIOV␉␉␉␉0x10␉␉/* Single Root I/O Virtualization */␊
#define PCI_EXT_CAP_ID_SRIOV␉␉␉␉␉0x10␉␉/* Single Root I/O Virtualization */␊
␊
/* Power Management Registers */␊
#define PCI_PM_CAP_VER_MASK␉␉␉␉␉0x0007␉␉/* Version (2=PM1.1) */␊
#define PCI_PM_CAP_PME_CLOCK␉␉␉␉0x0008␉␉/* Clock required for PME generation */␊
#define PCI_PM_CAP_PME_CLOCK␉␉␉␉␉0x0008␉␉/* Clock required for PME generation */␊
#define PCI_PM_CAP_DSI␉␉␉␉␉␉0x0020␉␉/* Device specific initialization required */␊
#define PCI_PM_CAP_AUX_C_MASK␉␉␉␉0x01c0␉␉/* Maximum aux current required in D3cold */␊
#define PCI_PM_CAP_AUX_C_MASK␉␉␉␉␉0x01c0␉␉/* Maximum aux current required in D3cold */␊
#define PCI_PM_CAP_D1␉␉␉␉␉␉0x0200␉␉/* D1 power state support */␊
#define PCI_PM_CAP_D2␉␉␉␉␉␉0x0400␉␉/* D2 power state support */␊
#define PCI_PM_CAP_PME_D0␉␉␉␉␉0x0800␉␉/* PME can be asserted from D0 */␊
#define PCI_PM_CAP_PME_D1␉␉␉␉␉0x1000␉␉/* PME can be asserted from D1 */␊
#define PCI_PM_CAP_PME_D2␉␉␉␉␉0x2000␉␉/* PME can be asserted from D2 */␊
#define PCI_PM_CAP_PME_D3_HOT␉␉␉␉0x4000␉␉/* PME can be asserted from D3hot */␊
#define PCI_PM_CAP_PME_D3_COLD␉␉␉␉0x8000␉␉/* PME can be asserted from D3cold */␊
#define PCI_PM_CTRL␉␉␉␉␉␉␉4␉␉␉/* PM control and status register */␊
#define PCI_PM_CTRL_STATE_MASK␉␉␉␉0x0003␉␉/* Current power state (D0 to D3) */␊
#define PCI_PM_CTRL_PME_ENABLE␉␉␉␉0x0100␉␉/* PME pin enable */␊
#define PCI_PM_CTRL_DATA_SEL_MASK␉␉␉0x1e00␉␉/* PM table data index */␊
#define PCI_PM_CTRL_DATA_SCALE_MASK␉␉␉0x6000␉␉/* PM table data scaling factor */␊
#define PCI_PM_CTRL_PME_STATUS␉␉␉␉0x8000␉␉/* PME pin status */␊
#define PCI_PM_PPB_EXTENSIONS␉␉␉␉6␉␉␉/* PPB support extensions */␊
#define PCI_PM_CAP_PME_D3_HOT␉␉␉␉␉0x4000␉␉/* PME can be asserted from D3hot */␊
#define PCI_PM_CAP_PME_D3_COLD␉␉␉␉␉0x8000␉␉/* PME can be asserted from D3cold */␊
#define PCI_PM_CTRL␉␉␉␉␉␉4␉␉/* PM control and status register */␊
#define PCI_PM_CTRL_STATE_MASK␉␉␉␉␉0x0003␉␉/* Current power state (D0 to D3) */␊
#define PCI_PM_CTRL_PME_ENABLE␉␉␉␉␉0x0100␉␉/* PME pin enable */␊
#define PCI_PM_CTRL_DATA_SEL_MASK␉␉␉␉0x1e00␉␉/* PM table data index */␊
#define PCI_PM_CTRL_DATA_SCALE_MASK␉␉␉␉0x6000␉␉/* PM table data scaling factor */␊
#define PCI_PM_CTRL_PME_STATUS␉␉␉␉␉0x8000␉␉/* PME pin status */␊
#define PCI_PM_PPB_EXTENSIONS␉␉␉␉␉6␉␉/* PPB support extensions */␊
#define PCI_PM_PPB_B2_B3␉␉␉␉␉0x40␉␉/* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */␊
#define PCI_PM_BPCC_ENABLE␉␉␉␉␉0x80␉␉/* Secondary bus is power managed */␊
#define PCI_PM_DATA_REGISTER␉␉␉␉7␉␉␉/* PM table contents read here */␊
#define PCI_PM_DATA_REGISTER␉␉␉␉␉7␉␉/* PM table contents read here */␊
#define PCI_PM_SIZEOF␉␉␉␉␉␉8␊
␊
/* AGP registers */␊
#define PCI_AGP_VERSION␉␉␉␉␉␉2␉␉␉/* BCD version number */␊
#define PCI_AGP_RFU␉␉␉␉␉␉␉3␉␉␉/* Rest of capability flags */␊
#define PCI_AGP_STATUS␉␉␉␉␉␉4␉␉␉/* Status register */␊
#define PCI_AGP_STATUS_RQ_MASK␉␉␉␉0xff000000␉/* Maximum number of requests - 1 */␊
#define PCI_AGP_STATUS_ISOCH␉␉␉␉0x10000␉␉/* Isochronous transactions supported */␊
#define PCI_AGP_STATUS_ARQSZ_MASK␉␉␉0xe000␉␉/* log2(optimum async req size in bytes) - 4 */␊
#define PCI_AGP_STATUS_CAL_MASK␉␉␉␉0x1c00␉␉/* Calibration cycle timing */␊
#define PCI_AGP_VERSION␉␉␉␉␉␉2␉␉/* BCD version number */␊
#define PCI_AGP_RFU␉␉␉␉␉␉3␉␉/* Rest of capability flags */␊
#define PCI_AGP_STATUS␉␉␉␉␉␉4␉␉/* Status register */␊
#define PCI_AGP_STATUS_RQ_MASK␉␉␉␉␉0xff000000␉/* Maximum number of requests - 1 */␊
#define PCI_AGP_STATUS_ISOCH␉␉␉␉␉0x10000␉␉/* Isochronous transactions supported */␊
#define PCI_AGP_STATUS_ARQSZ_MASK␉␉␉␉0xe000␉␉/* log2(optimum async req size in bytes) - 4 */␊
#define PCI_AGP_STATUS_CAL_MASK␉␉␉␉␉0x1c00␉␉/* Calibration cycle timing */␊
#define PCI_AGP_STATUS_SBA␉␉␉␉␉0x0200␉␉/* Sideband addressing supported */␊
#define PCI_AGP_STATUS_ITA_COH␉␉␉␉0x0100␉␉/* In-aperture accesses always coherent */␊
#define PCI_AGP_STATUS_GART64␉␉␉␉0x0080␉␉/* 64-bit GART entries supported */␊
#define PCI_AGP_STATUS_HTRANS␉␉␉␉0x0040␉␉/* If 0, core logic can xlate host CPU accesses thru aperture */␊
#define PCI_AGP_STATUS_64BIT␉␉␉␉0x0020␉␉/* 64-bit addressing cycles supported */␊
#define PCI_AGP_STATUS_ITA_COH␉␉␉␉␉0x0100␉␉/* In-aperture accesses always coherent */␊
#define PCI_AGP_STATUS_GART64␉␉␉␉␉0x0080␉␉/* 64-bit GART entries supported */␊
#define PCI_AGP_STATUS_HTRANS␉␉␉␉␉0x0040␉␉/* If 0, core logic can xlate host CPU accesses thru aperture */␊
#define PCI_AGP_STATUS_64BIT␉␉␉␉␉0x0020␉␉/* 64-bit addressing cycles supported */␊
#define PCI_AGP_STATUS_FW␉␉␉␉␉0x0010␉␉/* Fast write transfers supported */␊
#define PCI_AGP_STATUS_AGP3␉␉␉␉␉0x0008␉␉/* AGP3 mode supported */␊
#define PCI_AGP_STATUS_RATE4␉␉␉␉0x0004␉␉/* 4x transfer rate supported (RFU in AGP3 mode) */␊
#define PCI_AGP_STATUS_RATE2␉␉␉␉0x0002␉␉/* 2x transfer rate supported (8x in AGP3 mode) */␊
#define PCI_AGP_STATUS_RATE1␉␉␉␉0x0001␉␉/* 1x transfer rate supported (4x in AGP3 mode) */␊
#define PCI_AGP_COMMAND␉␉␉␉␉␉8␉␉␉/* Control register */␊
#define PCI_AGP_COMMAND_RQ_MASK␉␉␉␉0xff000000␉/* Master: Maximum number of requests */␊
#define PCI_AGP_COMMAND_ARQSZ_MASK␉␉␉0xe000␉␉/* log2(optimum async req size in bytes) - 4 */␊
#define PCI_AGP_COMMAND_CAL_MASK␉␉␉0x1c00␉␉/* Calibration cycle timing */␊
#define PCI_AGP_STATUS_RATE4␉␉␉␉␉0x0004␉␉/* 4x transfer rate supported (RFU in AGP3 mode) */␊
#define PCI_AGP_STATUS_RATE2␉␉␉␉␉0x0002␉␉/* 2x transfer rate supported (8x in AGP3 mode) */␊
#define PCI_AGP_STATUS_RATE1␉␉␉␉␉0x0001␉␉/* 1x transfer rate supported (4x in AGP3 mode) */␊
#define PCI_AGP_COMMAND␉␉␉␉␉␉8␉␉/* Control register */␊
#define PCI_AGP_COMMAND_RQ_MASK␉␉␉␉␉0xff000000␉/* Master: Maximum number of requests */␊
#define PCI_AGP_COMMAND_ARQSZ_MASK␉␉␉␉0xe000␉␉/* log2(optimum async req size in bytes) - 4 */␊
#define PCI_AGP_COMMAND_CAL_MASK␉␉␉␉0x1c00␉␉/* Calibration cycle timing */␊
#define PCI_AGP_COMMAND_SBA␉␉␉␉␉0x0200␉␉/* Sideband addressing enabled */␊
#define PCI_AGP_COMMAND_AGP␉␉␉␉␉0x0100␉␉/* Allow processing of AGP transactions */␊
#define PCI_AGP_COMMAND_GART64␉␉␉␉0x0080␉␉/* 64-bit GART entries enabled */␊
#define PCI_AGP_COMMAND_64BIT␉␉␉␉0x0020␉␉/* Allow generation of 64-bit addr cycles */␊
#define PCI_AGP_COMMAND_GART64␉␉␉␉␉0x0080␉␉/* 64-bit GART entries enabled */␊
#define PCI_AGP_COMMAND_64BIT␉␉␉␉␉0x0020␉␉/* Allow generation of 64-bit addr cycles */␊
#define PCI_AGP_COMMAND_FW␉␉␉␉␉0x0010␉␉/* Enable FW transfers */␊
#define PCI_AGP_COMMAND_RATE4␉␉␉␉0x0004␉␉/* Use 4x rate (RFU in AGP3 mode) */␊
#define PCI_AGP_COMMAND_RATE2␉␉␉␉0x0002␉␉/* Use 2x rate (8x in AGP3 mode) */␊
#define PCI_AGP_COMMAND_RATE1␉␉␉␉0x0001␉␉/* Use 1x rate (4x in AGP3 mode) */␊
#define PCI_AGP_COMMAND_RATE4␉␉␉␉␉0x0004␉␉/* Use 4x rate (RFU in AGP3 mode) */␊
#define PCI_AGP_COMMAND_RATE2␉␉␉␉␉0x0002␉␉/* Use 2x rate (8x in AGP3 mode) */␊
#define PCI_AGP_COMMAND_RATE1␉␉␉␉␉0x0001␉␉/* Use 1x rate (4x in AGP3 mode) */␊
#define PCI_AGP_SIZEOF␉␉␉␉␉␉12␊
␊
/* Vital Product Data */␊
#define PCI_VPD_ADDR␉␉␉␉␉␉2␉␉␉/* Address to access (15 bits!) */␊
#define PCI_VPD_ADDR␉␉␉␉␉␉2␉␉/* Address to access (15 bits!) */␊
#define PCI_VPD_ADDR_MASK␉␉␉␉␉0x7fff␉␉/* Address mask */␊
#define PCI_VPD_ADDR_F␉␉␉␉␉␉0x8000␉␉/* Write 0, 1 indicates completion */␊
#define PCI_VPD_DATA␉␉␉␉␉␉4␉␉␉/* 32-bits of data returned here */␊
#define PCI_VPD_DATA␉␉␉␉␉␉4␉␉/* 32-bits of data returned here */␊
␊
/* Slot Identification */␊
#define PCI_SID_ESR␉␉␉␉␉␉␉2␉␉␉/* Expansion Slot Register */␊
#define PCI_SID_ESR␉␉␉␉␉␉2␉␉/* Expansion Slot Register */␊
#define PCI_SID_ESR_NSLOTS␉␉␉␉␉0x1f␉␉/* Number of expansion slots available */␊
#define PCI_SID_ESR_FIC␉␉␉␉␉␉0x20␉␉/* First In Chassis Flag */␊
#define PCI_SID_CHASSIS_NR␉␉␉␉␉3␉␉␉/* Chassis Number */␊
#define PCI_SID_CHASSIS_NR␉␉␉␉␉3␉␉/* Chassis Number */␊
␊
/* Message Signaled Interrupts registers */␊
#define PCI_MSI_FLAGS␉␉␉␉␉␉2␉␉␉/* Various flags */␊
#define PCI_MSI_FLAGS_MASK_BIT␉␉␉␉0x100␉␉/* interrupt masking & reporting supported */␊
#define PCI_MSI_FLAGS␉␉␉␉␉␉2␉␉/* Various flags */␊
#define PCI_MSI_FLAGS_MASK_BIT␉␉␉␉␉0x100␉␉/* interrupt masking & reporting supported */␊
#define PCI_MSI_FLAGS_64BIT␉␉␉␉␉0x080␉␉/* 64-bit addresses allowed */␊
#define PCI_MSI_FLAGS_QSIZE␉␉␉␉␉0x070␉␉/* Message queue size configured */␊
#define PCI_MSI_FLAGS_QMASK␉␉␉␉␉0x00e␉␉/* Maximum queue size available */␊
#define PCI_MSI_FLAGS_ENABLE␉␉␉␉0x001␉␉/* MSI feature enabled */␊
#define PCI_MSI_RFU␉␉␉␉␉␉␉3␉␉␉/* Rest of capability flags */␊
#define PCI_MSI_ADDRESS_LO␉␉␉␉␉4␉␉␉/* Lower 32 bits */␊
#define PCI_MSI_ADDRESS_HI␉␉␉␉␉8␉␉␉/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */␊
#define PCI_MSI_DATA_32␉␉␉␉␉␉8␉␉␉/* 16 bits of data for 32-bit devices */␊
#define PCI_MSI_DATA_64␉␉␉␉␉␉12␉␉␉/* 16 bits of data for 64-bit devices */␊
#define PCI_MSI_MASK_BIT_32␉␉␉␉␉12␉␉␉/* per-vector masking for 32-bit devices */␊
#define PCI_MSI_MASK_BIT_64␉␉␉␉␉16␉␉␉/* per-vector masking for 64-bit devices */␊
#define PCI_MSI_PENDING_32␉␉␉␉␉16␉␉␉/* per-vector interrupt pending for 32-bit devices */␊
#define PCI_MSI_PENDING_64␉␉␉␉␉20␉␉␉/* per-vector interrupt pending for 64-bit devices */␊
#define PCI_MSI_FLAGS_ENABLE␉␉␉␉␉0x001␉␉/* MSI feature enabled */␊
#define PCI_MSI_RFU␉␉␉␉␉␉3␉␉/* Rest of capability flags */␊
#define PCI_MSI_ADDRESS_LO␉␉␉␉␉4␉␉/* Lower 32 bits */␊
#define PCI_MSI_ADDRESS_HI␉␉␉␉␉8␉␉/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */␊
#define PCI_MSI_DATA_32␉␉␉␉␉␉8␉␉/* 16 bits of data for 32-bit devices */␊
#define PCI_MSI_DATA_64␉␉␉␉␉␉12␉␉/* 16 bits of data for 64-bit devices */␊
#define PCI_MSI_MASK_BIT_32␉␉␉␉␉12␉␉/* per-vector masking for 32-bit devices */␊
#define PCI_MSI_MASK_BIT_64␉␉␉␉␉16␉␉/* per-vector masking for 64-bit devices */␊
#define PCI_MSI_PENDING_32␉␉␉␉␉16␉␉/* per-vector interrupt pending for 32-bit devices */␊
#define PCI_MSI_PENDING_64␉␉␉␉␉20␉␉/* per-vector interrupt pending for 64-bit devices */␊
␊
/* PCI-X */␊
#define PCI_PCIX_COMMAND␉␉␉␉␉␉␉␉␉␉␉␉2 /* Command register offset */␊
#define PCI_PCIX_COMMAND_DPERE␉␉␉␉␉␉␉␉␉ 0x0001 /* Data Parity Error Recover Enable */␊
#define PCI_PCIX_COMMAND_ERO␉␉␉␉␉␉␉␉␉ 0x0002 /* Enable Relaxed Ordering */␊
#define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT␉␉␉␉ 0x000c /* Maximum Memory Read Byte Count */␊
#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS␉␉␉ 0x0070␊
#define PCI_PCIX_COMMAND_RESERVED␉␉␉␉␉␉␉␉␉0xf80␊
#define PCI_PCIX_STATUS␉␉␉␉␉␉␉␉␉␉␉␉␉4 /* Status register offset */␊
#define PCI_PCIX_STATUS_FUNCTION␉␉␉␉␉␉␉ 0x00000007␊
#define PCI_PCIX_STATUS_DEVICE␉␉␉␉␉␉␉␉ 0x000000f8␊
#define PCI_PCIX_STATUS_BUS␉␉␉␉␉␉␉␉␉ 0x0000ff00␊
#define PCI_PCIX_STATUS_64BIT␉␉␉␉␉␉␉␉ 0x00010000␊
#define PCI_PCIX_STATUS_133MHZ␉␉␉␉␉␉␉␉ 0x00020000␊
#define PCI_PCIX_STATUS_SC_DISCARDED␉␉␉␉␉␉ 0x00040000 /* Split Completion Discarded */␊
#define PCI_PCIX_STATUS_UNEXPECTED_SC␉␉␉␉␉␉ 0x00080000 /* Unexpected Split Completion */␊
#define PCI_PCIX_STATUS_DEVICE_COMPLEXITY␉␉␉␉␉ 0x00100000 /* 0 = simple device, 1 = bridge device */␊
#define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT␉ 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */␊
#define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000␊
#define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE␉ 0x1c000000␊
#define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS␉␉␉␉␉ 0x20000000 /* Received Split Completion Error Message */␊
#define PCI_PCIX_STATUS_266MHZ␉␉␉␉␉␉␉␉ 0x40000000 /* 266 MHz capable */␊
#define PCI_PCIX_STATUS_533MHZ␉␉␉␉␉␉␉␉ 0x80000000 /* 533 MHz capable */␊
#define PCI_PCIX_SIZEOF␉␉4␊
#define PCI_PCIX_COMMAND␉␉␉␉␉2␉␉/* Command register offset */␊
#define PCI_PCIX_COMMAND_DPERE␉␉␉␉␉0x0001␉␉/* Data Parity Error Recover Enable */␊
#define PCI_PCIX_COMMAND_ERO␉␉␉␉␉0x0002␉␉/* Enable Relaxed Ordering */␊
#define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT␉␉0x000c␉␉/* Maximum Memory Read Byte Count */␊
#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS␉␉0x0070␊
#define PCI_PCIX_COMMAND_RESERVED␉␉␉␉0xf80␊
#define PCI_PCIX_STATUS␉␉␉␉␉␉4␉␉/* Status register offset */␊
#define PCI_PCIX_STATUS_FUNCTION␉␉␉␉0x00000007␊
#define PCI_PCIX_STATUS_DEVICE␉␉␉␉␉0x000000f8␊
#define PCI_PCIX_STATUS_BUS␉␉␉␉␉0x0000ff00␊
#define PCI_PCIX_STATUS_64BIT␉␉␉␉␉0x00010000␊
#define PCI_PCIX_STATUS_133MHZ␉␉␉␉␉0x00020000␊
#define PCI_PCIX_STATUS_SC_DISCARDED␉␉␉␉0x00040000␉/* Split Completion Discarded */␊
#define PCI_PCIX_STATUS_UNEXPECTED_SC␉␉␉␉0x00080000␉/* Unexpected Split Completion */␊
#define PCI_PCIX_STATUS_DEVICE_COMPLEXITY␉␉␉0x00100000␉/* 0 = simple device, 1 = bridge device */␊
#define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT␉0x00600000␉/* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */␊
#define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS␉0x03800000␊
#define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE␉0x1c000000␊
#define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS␉␉␉0x20000000␉/* Received Split Completion Error Message */␊
#define PCI_PCIX_STATUS_266MHZ␉␉␉␉␉0x40000000␉/* 266 MHz capable */␊
#define PCI_PCIX_STATUS_533MHZ␉␉␉␉␉0x80000000␉/* 533 MHz capable */␊
#define PCI_PCIX_SIZEOF␉␉␉␉␉␉4␊
␊
␊
/* PCI-X Bridges */␊
#define PCI_PCIX_BRIDGE_SEC_STATUS␉␉␉␉␉␉␉␉␉␉2 /* Secondary bus status register offset */␊
#define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT␉␉␉␉␉␉ 0x0001␊
#define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ␉␉␉␉␉␉ 0x0002␊
#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED␉␉␉␉␉ 0x0004 /* Split Completion Discarded on secondary bus */␊
#define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC␉␉␉␉ 0x0008 /* Unexpected Split Completion on secondary bus */␊
#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN␉␉␉␉␉ 0x0010 /* Split Completion Overrun on secondary bus */␊
#define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED␉␉ 0x0020␊
#define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ␉␉␉␉␉ 0x01c0␊
#define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED␉␉␉␉␉␉ 0xfe00␊
#define PCI_PCIX_BRIDGE_STATUS␉␉␉␉␉␉␉␉␉␉␉4 /* Primary bus status register offset */␊
#define PCI_PCIX_BRIDGE_STATUS_FUNCTION␉␉␉␉␉␉ 0x00000007␊
#define PCI_PCIX_BRIDGE_STATUS_DEVICE␉␉␉␉␉␉ 0x000000f8␊
#define PCI_PCIX_BRIDGE_STATUS_BUS␉␉␉␉␉␉␉ 0x0000ff00␊
#define PCI_PCIX_BRIDGE_STATUS_64BIT␉␉␉␉␉␉ 0x00010000␊
#define PCI_PCIX_BRIDGE_STATUS_133MHZ␉␉␉␉␉␉ 0x00020000␊
#define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED␉␉␉␉␉ 0x00040000 /* Split Completion Discarded */␊
#define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC␉␉␉␉ 0x00080000 /* Unexpected Split Completion */␊
#define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN␉␉␉␉␉ 0x00100000 /* Split Completion Overrun */␊
#define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED␉␉ 0x00200000␊
#define PCI_PCIX_BRIDGE_STATUS_RESERVED␉␉␉␉␉␉ 0xffc00000␊
#define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL␉␉␉␉␉␉8 /* Upstream Split Transaction Register offset */␊
#define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL␉␉␉␉␉ 12 /* Downstream Split Transaction Register offset */␊
#define PCI_PCIX_BRIDGE_STR_CAPACITY␉␉␉␉␉␉ 0x0000ffff␊
#define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT␉␉␉␉ 0xffff0000␊
#define PCI_PCIX_BRIDGE_SEC_STATUS␉␉␉␉2␉␉/* Secondary bus status register offset */␊
#define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT␉␉␉0x0001␊
#define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ␉␉␉0x0002␊
#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED␉␉␉0x0004␉␉/* Split Completion Discarded on secondary bus */␊
#define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC␉␉0x0008␉␉/* Unexpected Split Completion on secondary bus */␊
#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN␉␉␉0x0010␉␉/* Split Completion Overrun on secondary bus */␊
#define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED␉0x0020␊
#define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ␉␉␉0x01c0␊
#define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED␉␉␉0xfe00␊
#define PCI_PCIX_BRIDGE_STATUS␉␉␉␉␉4␉␉/* Primary bus status register offset */␊
#define PCI_PCIX_BRIDGE_STATUS_FUNCTION␉␉␉␉0x00000007␊
#define PCI_PCIX_BRIDGE_STATUS_DEVICE␉␉␉␉0x000000f8␊
#define PCI_PCIX_BRIDGE_STATUS_BUS␉␉␉␉0x0000ff00␊
#define PCI_PCIX_BRIDGE_STATUS_64BIT␉␉␉␉0x00010000␊
#define PCI_PCIX_BRIDGE_STATUS_133MHZ␉␉␉␉0x00020000␊
#define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED␉␉␉0x00040000␉/* Split Completion Discarded */␊
#define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC␉␉␉0x00080000␉/* Unexpected Split Completion */␊
#define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN␉␉␉0x00100000␉/* Split Completion Overrun */␊
#define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED␉␉0x00200000␊
#define PCI_PCIX_BRIDGE_STATUS_RESERVED␉␉␉␉0xffc00000␊
#define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL␉␉8␉␉/* Upstream Split Transaction Register offset */␊
#define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL␉␉12␉␉/* Downstream Split Transaction Register offset */␊
#define PCI_PCIX_BRIDGE_STR_CAPACITY␉␉␉␉0x0000ffff␊
#define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT␉␉␉0xffff0000␊
#define PCI_PCIX_BRIDGE_SIZEOF 12␊
␊
/* PCI Express */␊
#define PCI_EXP_FLAGS␉␉␉␉␉␉0x2␉␉␉/* Capabilities register */␊
#define PCI_EXP_FLAGS␉␉␉␉␉␉0x2␉␉/* Capabilities register */␊
#define PCI_EXP_FLAGS_VERS␉␉␉␉␉0x000f␉␉/* Capability version */␊
#define PCI_EXP_FLAGS_TYPE␉␉␉␉␉0x00f0␉␉/* Device/Port type */␊
#define PCI_EXP_TYPE_ENDPOINT␉␉␉␉0x0 ␉␉/* Express Endpoint */␊
#define PCI_EXP_TYPE_LEG_END␉␉␉␉0x1 ␉␉/* Legacy Endpoint */␊
#define PCI_EXP_TYPE_ROOT_PORT␉␉␉␉0x4 ␉␉/* Root Port */␊
#define PCI_EXP_TYPE_UPSTREAM␉␉␉␉0x5 ␉␉/* Upstream Port */␊
#define PCI_EXP_TYPE_DOWNSTREAM␉␉␉␉0x6 ␉␉/* Downstream Port */␊
#define PCI_EXP_TYPE_PCI_BRIDGE␉␉␉␉0x7 ␉␉/* PCI/PCI-X Bridge */␊
#define PCI_EXP_TYPE_PCIE_BRIDGE␉␉␉0x8 ␉␉/* PCI/PCI-X to PCIE Bridge */␊
#define PCI_EXP_TYPE_ROOT_INT_EP␉␉␉0x9 ␉␉/* Root Complex Integrated Endpoint */␊
#define PCI_EXP_TYPE_ROOT_EC␉␉␉␉0xa ␉␉/* Root Complex Event Collector */␊
#define PCI_EXP_TYPE_ENDPOINT␉␉␉␉␉0x0 ␉␉/* Express Endpoint */␊
#define PCI_EXP_TYPE_LEG_END␉␉␉␉␉0x1 ␉␉/* Legacy Endpoint */␊
#define PCI_EXP_TYPE_ROOT_PORT␉␉␉␉␉0x4 ␉␉/* Root Port */␊
#define PCI_EXP_TYPE_UPSTREAM␉␉␉␉␉0x5 ␉␉/* Upstream Port */␊
#define PCI_EXP_TYPE_DOWNSTREAM␉␉␉␉␉0x6 ␉␉/* Downstream Port */␊
#define PCI_EXP_TYPE_PCI_BRIDGE␉␉␉␉␉0x7 ␉␉/* PCI/PCI-X Bridge */␊
#define PCI_EXP_TYPE_PCIE_BRIDGE␉␉␉␉0x8 ␉␉/* PCI/PCI-X to PCIE Bridge */␊
#define PCI_EXP_TYPE_ROOT_INT_EP␉␉␉␉0x9 ␉␉/* Root Complex Integrated Endpoint */␊
#define PCI_EXP_TYPE_ROOT_EC␉␉␉␉␉0xa ␉␉/* Root Complex Event Collector */␊
#define PCI_EXP_FLAGS_SLOT␉␉␉␉␉0x0100␉␉/* Slot implemented */␊
#define PCI_EXP_FLAGS_IRQ␉␉␉␉␉0x3e00␉␉/* Interrupt message number */␊
#define PCI_EXP_DEVCAP␉␉␉␉␉␉0x4 ␉␉/* Device capabilities */␊
#define PCI_EXP_DEVCAP_PAYLOAD␉␉␉␉0x07␉␉/* Max_Payload_Size */␊
#define PCI_EXP_DEVCAP_PHANTOM␉␉␉␉0x18␉␉/* Phantom functions */␊
#define PCI_EXP_DEVCAP_EXT_TAG␉␉␉␉0x20␉␉/* Extended tags */␊
#define PCI_EXP_DEVCAP_PAYLOAD␉␉␉␉␉0x07␉␉/* Max_Payload_Size */␊
#define PCI_EXP_DEVCAP_PHANTOM␉␉␉␉␉0x18␉␉/* Phantom functions */␊
#define PCI_EXP_DEVCAP_EXT_TAG␉␉␉␉␉0x20␉␉/* Extended tags */␊
#define PCI_EXP_DEVCAP_L0S␉␉␉␉␉0x1c0␉␉/* L0s Acceptable Latency */␊
#define PCI_EXP_DEVCAP_L1␉␉␉␉␉0xe00␉␉/* L1 Acceptable Latency */␊
#define PCI_EXP_DEVCAP_ATN_BUT␉␉␉␉0x1000␉␉/* Attention Button Present */␊
#define PCI_EXP_DEVCAP_ATN_IND␉␉␉␉0x2000␉␉/* Attention Indicator Present */␊
#define PCI_EXP_DEVCAP_PWR_IND␉␉␉␉0x4000␉␉/* Power Indicator Present */␊
#define PCI_EXP_DEVCAP_ATN_BUT␉␉␉␉␉0x1000␉␉/* Attention Button Present */␊
#define PCI_EXP_DEVCAP_ATN_IND␉␉␉␉␉0x2000␉␉/* Attention Indicator Present */␊
#define PCI_EXP_DEVCAP_PWR_IND␉␉␉␉␉0x4000␉␉/* Power Indicator Present */␊
#define PCI_EXP_DEVCAP_RBE␉␉␉␉␉0x8000␉␉/* Role-Based Error Reporting */␊
#define PCI_EXP_DEVCAP_PWR_VAL␉␉␉␉0x3fc0000␉/* Slot Power Limit Value */␊
#define PCI_EXP_DEVCAP_PWR_SCL␉␉␉␉0xc000000␉/* Slot Power Limit Scale */␊
#define PCI_EXP_DEVCAP_FLRESET␉␉␉␉0x10000000␉/* Function-Level Reset */␊
#define PCI_EXP_DEVCTL␉␉␉␉␉␉0x8␉␉␉/* Device Control */␊
#define PCI_EXP_DEVCAP_PWR_VAL␉␉␉␉␉0x3fc0000␉/* Slot Power Limit Value */␊
#define PCI_EXP_DEVCAP_PWR_SCL␉␉␉␉␉0xc000000␉/* Slot Power Limit Scale */␊
#define PCI_EXP_DEVCAP_FLRESET␉␉␉␉␉0x10000000␉/* Function-Level Reset */␊
#define PCI_EXP_DEVCTL␉␉␉␉␉␉0x8␉␉/* Device Control */␊
#define PCI_EXP_DEVCTL_CERE␉␉␉␉␉0x0001␉␉/* Correctable Error Reporting En. */␊
#define PCI_EXP_DEVCTL_NFERE␉␉␉␉0x0002␉␉/* Non-Fatal Error Reporting Enable */␊
#define PCI_EXP_DEVCTL_NFERE␉␉␉␉␉0x0002␉␉/* Non-Fatal Error Reporting Enable */␊
#define PCI_EXP_DEVCTL_FERE␉␉␉␉␉0x0004␉␉/* Fatal Error Reporting Enable */␊
#define PCI_EXP_DEVCTL_URRE␉␉␉␉␉0x0008␉␉/* Unsupported Request Reporting En. */␊
#define PCI_EXP_DEVCTL_RELAXED␉␉␉␉0x0010␉␉/* Enable Relaxed Ordering */␊
#define PCI_EXP_DEVCTL_PAYLOAD␉␉␉␉0x00e0␉␉/* Max_Payload_Size */␊
#define PCI_EXP_DEVCTL_EXT_TAG␉␉␉␉0x0100␉␉/* Extended Tag Field Enable */␊
#define PCI_EXP_DEVCTL_PHANTOM␉␉␉␉0x0200␉␉/* Phantom Functions Enable */␊
#define PCI_EXP_DEVCTL_AUX_PME␉␉␉␉0x0400␉␉/* Auxiliary Power PM Enable */␊
#define PCI_EXP_DEVCTL_NOSNOOP␉␉␉␉0x0800␉␉/* Enable No Snoop */␊
#define PCI_EXP_DEVCTL_READRQ␉␉␉␉0x7000␉␉/* Max_Read_Request_Size */␊
#define PCI_EXP_DEVCTL_RELAXED␉␉␉␉␉0x0010␉␉/* Enable Relaxed Ordering */␊
#define PCI_EXP_DEVCTL_PAYLOAD␉␉␉␉␉0x00e0␉␉/* Max_Payload_Size */␊
#define PCI_EXP_DEVCTL_EXT_TAG␉␉␉␉␉0x0100␉␉/* Extended Tag Field Enable */␊
#define PCI_EXP_DEVCTL_PHANTOM␉␉␉␉␉0x0200␉␉/* Phantom Functions Enable */␊
#define PCI_EXP_DEVCTL_AUX_PME␉␉␉␉␉0x0400␉␉/* Auxiliary Power PM Enable */␊
#define PCI_EXP_DEVCTL_NOSNOOP␉␉␉␉␉0x0800␉␉/* Enable No Snoop */␊
#define PCI_EXP_DEVCTL_READRQ␉␉␉␉␉0x7000␉␉/* Max_Read_Request_Size */␊
#define PCI_EXP_DEVCTL_BCRE␉␉␉␉␉0x8000␉␉/* Bridge Configuration Retry Enable */␊
#define PCI_EXP_DEVCTL_FLRESET␉␉␉␉0x8000␉␉/* Function-Level Reset [bit shared with BCRE] */␊
#define PCI_EXP_DEVCTL_FLRESET␉␉␉␉␉0x8000␉␉/* Function-Level Reset [bit shared with BCRE] */␊
#define PCI_EXP_DEVSTA␉␉␉␉␉␉0xa ␉␉/* Device Status */␊
#define PCI_EXP_DEVSTA_CED␉␉␉␉␉0x01␉␉/* Correctable Error Detected */␊
#define PCI_EXP_DEVSTA_NFED␉␉␉␉␉0x02␉␉/* Non-Fatal Error Detected */␊
#define PCI_EXP_DEVSTA_FED␉␉␉␉␉0x04␉␉/* Fatal Error Detected */␊
#define PCI_EXP_DEVSTA_URD␉␉␉␉␉0x08␉␉/* Unsupported Request Detected */␊
#define PCI_EXP_DEVSTA_AUXPD␉␉␉␉0x10␉␉/* AUX Power Detected */␊
#define PCI_EXP_DEVSTA_TRPND␉␉␉␉0x20␉␉/* Transactions Pending */␊
#define PCI_EXP_LNKCAP␉␉␉␉␉␉0xc␉␉␉/* Link Capabilities */␊
#define PCI_EXP_LNKCAP_SPEED␉␉␉␉0x0000f ␉/* Maximum Link Speed */␊
#define PCI_EXP_LNKCAP_WIDTH␉␉␉␉0x003f0 ␉/* Maximum Link Width */␊
#define PCI_EXP_DEVSTA_AUXPD␉␉␉␉␉0x10␉␉/* AUX Power Detected */␊
#define PCI_EXP_DEVSTA_TRPND␉␉␉␉␉0x20␉␉/* Transactions Pending */␊
#define PCI_EXP_LNKCAP␉␉␉␉␉␉0xc␉␉/* Link Capabilities */␊
#define PCI_EXP_LNKCAP_SPEED␉␉␉␉␉0x0000f ␉/* Maximum Link Speed */␊
#define PCI_EXP_LNKCAP_WIDTH␉␉␉␉␉0x003f0 ␉/* Maximum Link Width */␊
#define PCI_EXP_LNKCAP_ASPM␉␉␉␉␉0x00c00 ␉/* Active State Power Management */␊
#define PCI_EXP_LNKCAP_L0S␉␉␉␉␉0x07000 ␉/* L0s Acceptable Latency */␊
#define PCI_EXP_LNKCAP_L1␉␉␉␉␉0x38000 ␉/* L1 Acceptable Latency */␊
#define PCI_EXP_LNKCAP_CLOCKPM␉␉␉␉0x40000 ␉/* Clock Power Management */␊
#define PCI_EXP_LNKCAP_SURPRISE␉␉␉␉0x80000 ␉/* Surprise Down Error Reporting */␊
#define PCI_EXP_LNKCAP_CLOCKPM␉␉␉␉␉0x40000 ␉/* Clock Power Management */␊
#define PCI_EXP_LNKCAP_SURPRISE␉␉␉␉␉0x80000 ␉/* Surprise Down Error Reporting */␊
#define PCI_EXP_LNKCAP_DLLA␉␉␉␉␉0x100000␉/* Data Link Layer Active Reporting */␊
#define PCI_EXP_LNKCAP_LBNC␉␉␉␉␉0x200000␉/* Link Bandwidth Notification Capability */␊
#define PCI_EXP_LNKCAP_PORT␉␉␉␉␉0xff000000␉/* Port Number */␊
#define PCI_EXP_LNKCTL␉␉␉␉␉␉0x10␉␉/* Link Control */␊
#define PCI_EXP_LNKCTL_ASPM␉␉␉␉␉0x0003␉␉/* ASPM Control */␊
#define PCI_EXP_LNKCTL_RCB␉␉␉␉␉0x0008␉␉/* Read Completion Boundary */␊
#define PCI_EXP_LNKCTL_DISABLE␉␉␉␉0x0010␉␉/* Link Disable */␊
#define PCI_EXP_LNKCTL_RETRAIN␉␉␉␉0x0020␉␉/* Retrain Link */␊
#define PCI_EXP_LNKCTL_CLOCK␉␉␉␉0x0040␉␉/* Common Clock Configuration */␊
#define PCI_EXP_LNKCTL_XSYNCH␉␉␉␉0x0080␉␉/* Extended Synch */␊
#define PCI_EXP_LNKCTL_CLOCKPM␉␉␉␉0x0100␉␉/* Clock Power Management */␊
#define PCI_EXP_LNKCTL_HWAUTWD␉␉␉␉0x0200␉␉/* Hardware Autonomous Width Disable */␊
#define PCI_EXP_LNKCTL_BWMIE␉␉␉␉0x0400␉␉/* Bandwidth Mgmt Interrupt Enable */␊
#define PCI_EXP_LNKCTL_AUTBWIE␉␉␉␉0x0800␉␉/* Autonomous Bandwidth Mgmt Interrupt Enable */␊
#define PCI_EXP_LNKCTL_DISABLE␉␉␉␉␉0x0010␉␉/* Link Disable */␊
#define PCI_EXP_LNKCTL_RETRAIN␉␉␉␉␉0x0020␉␉/* Retrain Link */␊
#define PCI_EXP_LNKCTL_CLOCK␉␉␉␉␉0x0040␉␉/* Common Clock Configuration */␊
#define PCI_EXP_LNKCTL_XSYNCH␉␉␉␉␉0x0080␉␉/* Extended Synch */␊
#define PCI_EXP_LNKCTL_CLOCKPM␉␉␉␉␉0x0100␉␉/* Clock Power Management */␊
#define PCI_EXP_LNKCTL_HWAUTWD␉␉␉␉␉0x0200␉␉/* Hardware Autonomous Width Disable */␊
#define PCI_EXP_LNKCTL_BWMIE␉␉␉␉␉0x0400␉␉/* Bandwidth Mgmt Interrupt Enable */␊
#define PCI_EXP_LNKCTL_AUTBWIE␉␉␉␉␉0x0800␉␉/* Autonomous Bandwidth Mgmt Interrupt Enable */␊
#define PCI_EXP_LNKSTA␉␉␉␉␉␉0x12␉␉/* Link Status */␊
#define PCI_EXP_LNKSTA_SPEED␉␉␉␉0x000f␉␉/* Negotiated Link Speed */␊
#define PCI_EXP_LNKSTA_WIDTH␉␉␉␉0x03f0␉␉/* Negotiated Link Width */␊
#define PCI_EXP_LNKSTA_TR_ERR␉␉␉␉0x0400␉␉/* Training Error (obsolete) */␊
#define PCI_EXP_LNKSTA_TRAIN␉␉␉␉0x0800␉␉/* Link Training */␊
#define PCI_EXP_LNKSTA_SL_CLK␉␉␉␉0x1000␉␉/* Slot Clock Configuration */␊
#define PCI_EXP_LNKSTA_DL_ACT␉␉␉␉0x2000␉␉/* Data Link Layer in DL_Active State */␊
#define PCI_EXP_LNKSTA_BWMGMT␉␉␉␉0x4000␉␉/* Bandwidth Mgmt Status */␊
#define PCI_EXP_LNKSTA_AUTBW␉␉␉␉0x8000␉␉/* Autonomous Bandwidth Mgmt Status */␊
#define PCI_EXP_LNKSTA_SPEED␉␉␉␉␉0x000f␉␉/* Negotiated Link Speed */␊
#define PCI_EXP_LNKSTA_WIDTH␉␉␉␉␉0x03f0␉␉/* Negotiated Link Width */␊
#define PCI_EXP_LNKSTA_TR_ERR␉␉␉␉␉0x0400␉␉/* Training Error (obsolete) */␊
#define PCI_EXP_LNKSTA_TRAIN␉␉␉␉␉0x0800␉␉/* Link Training */␊
#define PCI_EXP_LNKSTA_SL_CLK␉␉␉␉␉0x1000␉␉/* Slot Clock Configuration */␊
#define PCI_EXP_LNKSTA_DL_ACT␉␉␉␉␉0x2000␉␉/* Data Link Layer in DL_Active State */␊
#define PCI_EXP_LNKSTA_BWMGMT␉␉␉␉␉0x4000␉␉/* Bandwidth Mgmt Status */␊
#define PCI_EXP_LNKSTA_AUTBW␉␉␉␉␉0x8000␉␉/* Autonomous Bandwidth Mgmt Status */␊
#define PCI_EXP_SLTCAP␉␉␉␉␉␉0x14␉␉/* Slot Capabilities */␊
#define PCI_EXP_SLTCAP_ATNB␉␉␉␉␉0x0001␉␉/* Attention Button Present */␊
#define PCI_EXP_SLTCAP_PWRC␉␉␉␉␉0x0002␉␉/* Power Controller Present */␊
#define PCI_EXP_SLTCAP_PWRI␉␉␉␉␉0x0010␉␉/* Power Indicator Present */␊
#define PCI_EXP_SLTCAP_HPS␉␉␉␉␉0x0020␉␉/* Hot-Plug Surprise */␊
#define PCI_EXP_SLTCAP_HPC␉␉␉␉␉0x0040␉␉/* Hot-Plug Capable */␊
#define PCI_EXP_SLTCAP_PWR_VAL␉␉␉␉0x00007f80␉/* Slot Power Limit Value */␊
#define PCI_EXP_SLTCAP_PWR_SCL␉␉␉␉0x00018000␉/* Slot Power Limit Scale */␊
#define PCI_EXP_SLTCAP_INTERLOCK␉␉␉0x020000␉/* Electromechanical Interlock Present */␊
#define PCI_EXP_SLTCAP_NOCMDCOMP␉␉␉0x040000␉/* No Command Completed Support */␊
#define PCI_EXP_SLTCAP_PWR_VAL␉␉␉␉␉0x00007f80␉/* Slot Power Limit Value */␊
#define PCI_EXP_SLTCAP_PWR_SCL␉␉␉␉␉0x00018000␉/* Slot Power Limit Scale */␊
#define PCI_EXP_SLTCAP_INTERLOCK␉␉␉␉0x020000␉/* Electromechanical Interlock Present */␊
#define PCI_EXP_SLTCAP_NOCMDCOMP␉␉␉␉0x040000␉/* No Command Completed Support */␊
#define PCI_EXP_SLTCAP_PSN␉␉␉␉␉0xfff80000␉/* Physical Slot Number */␊
#define PCI_EXP_SLTCTL␉␉␉␉␉␉0x18␉␉/* Slot Control */␊
#define PCI_EXP_SLTCTL_ATNB␉␉␉␉␉0x0001␉␉/* Attention Button Pressed Enable */␊
#define PCI_EXP_SLTCTL_ATNI␉␉␉␉␉0x00c0␉␉/* Attention Indicator Control */␊
#define PCI_EXP_SLTCTL_PWRI␉␉␉␉␉0x0300␉␉/* Power Indicator Control */␊
#define PCI_EXP_SLTCTL_PWRC␉␉␉␉␉0x0400␉␉/* Power Controller Control */␊
#define PCI_EXP_SLTCTL_INTERLOCK␉␉␉0x0800␉␉/* Electromechanical Interlock Control */␊
#define PCI_EXP_SLTCTL_LLCHG␉␉␉␉0x1000␉␉/* Data Link Layer State Changed Enable */␊
#define PCI_EXP_SLTCTL_INTERLOCK␉␉␉␉0x0800␉␉/* Electromechanical Interlock Control */␊
#define PCI_EXP_SLTCTL_LLCHG␉␉␉␉␉0x1000␉␉/* Data Link Layer State Changed Enable */␊
#define PCI_EXP_SLTSTA␉␉␉␉␉␉0x1a␉␉/* Slot Status */␊
#define PCI_EXP_SLTSTA_ATNB␉␉␉␉␉0x0001␉␉/* Attention Button Pressed */␊
#define PCI_EXP_SLTSTA_PWRF␉␉␉␉␉0x0002␉␉/* Power Fault Detected */␊
#define PCI_EXP_SLTSTA_MRLS␉␉␉␉␉0x0004␉␉/* MRL Sensor Changed */␊
#define PCI_EXP_SLTSTA_PRSD␉␉␉␉␉0x0008␉␉/* Presence Detect Changed */␊
#define PCI_EXP_SLTSTA_CMDC␉␉␉␉␉0x0010␉␉/* Command Completed */␊
#define PCI_EXP_SLTSTA_MRL_ST␉␉␉␉0x0020␉␉/* MRL Sensor State */␊
#define PCI_EXP_SLTSTA_MRL_ST␉␉␉␉␉0x0020␉␉/* MRL Sensor State */␊
#define PCI_EXP_SLTSTA_PRES␉␉␉␉␉0x0040␉␉/* Presence Detect State */␊
#define PCI_EXP_SLTSTA_INTERLOCK␉␉␉0x0080␉␉/* Electromechanical Interlock Status */␊
#define PCI_EXP_SLTSTA_LLCHG␉␉␉␉0x0100␉␉/* Data Link Layer State Changed */␊
#define PCI_EXP_SLTSTA_INTERLOCK␉␉␉␉0x0080␉␉/* Electromechanical Interlock Status */␊
#define PCI_EXP_SLTSTA_LLCHG␉␉␉␉␉0x0100␉␉/* Data Link Layer State Changed */␊
#define PCI_EXP_RTCTL␉␉␉␉␉␉0x1c␉␉/* Root Control */␊
#define PCI_EXP_RTCTL_SECEE␉␉␉␉␉0x0001␉␉/* System Error on Correctable Error */␊
#define PCI_EXP_RTCTL_SENFEE␉␉␉␉0x0002␉␉/* System Error on Non-Fatal Error */␊
#define PCI_EXP_RTCTL_SENFEE␉␉␉␉␉0x0002␉␉/* System Error on Non-Fatal Error */␊
#define PCI_EXP_RTCTL_SEFEE␉␉␉␉␉0x0004␉␉/* System Error on Fatal Error */␊
#define PCI_EXP_RTCTL_PMEIE␉␉␉␉␉0x0008␉␉/* PME Interrupt Enable */␊
#define PCI_EXP_RTCTL_CRSVIS␉␉␉␉0x0010␉␉/* Configuration Request Retry Status Visible to SW */␊
#define PCI_EXP_RTCTL_CRSVIS␉␉␉␉␉0x0010␉␉/* Configuration Request Retry Status Visible to SW */␊
#define PCI_EXP_RTCAP␉␉␉␉␉␉0x1e␉␉/* Root Capabilities */␊
#define PCI_EXP_RTCAP_CRSVIS␉␉␉␉0x0010␉␉/* Configuration Request Retry Status Visible to SW */␊
#define PCI_EXP_RTCAP_CRSVIS␉␉␉␉␉0x0010␉␉/* Configuration Request Retry Status Visible to SW */␊
#define PCI_EXP_RTSTA␉␉␉␉␉␉0x20␉␉/* Root Status */␊
#define PCI_EXP_RTSTA_PME_REQID␉␉␉␉0x0000ffff␉/* PME Requester ID */␊
#define PCI_EXP_RTSTA_PME_STATUS␉␉␉0x00010000␉/* PME Status */␊
#define PCI_EXP_RTSTA_PME_PENDING␉␉␉0x00020000␉/* PME is Pending */␊
#define PCI_EXP_RTSTA_PME_REQID␉␉␉␉␉0x0000ffff␉/* PME Requester ID */␊
#define PCI_EXP_RTSTA_PME_STATUS␉␉␉␉0x00010000␉/* PME Status */␊
#define PCI_EXP_RTSTA_PME_PENDING␉␉␉␉0x00020000␉/* PME is Pending */␊
#define PCI_EXP_DEVCAP2␉␉␉␉␉␉0x24␉␉/* Device capabilities 2 */␊
#define PCI_EXP_DEVCTL2␉␉␉␉␉␉0x28␉␉/* Device Control */␊
#define PCI_EXP_DEV2_TIMEOUT_RANGE(x)␉␉((x) & 0xf) /* Completion Timeout Ranges Supported */␊
#define PCI_EXP_DEV2_TIMEOUT_VALUE(x)␉␉((x) & 0xf) /* Completion Timeout Value */␊
#define PCI_EXP_DEV2_TIMEOUT_DIS␉␉␉0x0010␉␉/* Completion Timeout Disable Supported */␊
#define PCI_EXP_DEV2_TIMEOUT_RANGE(x)␉␉␉␉((x) & 0xf)␉/* Completion Timeout Ranges Supported */␊
#define PCI_EXP_DEV2_TIMEOUT_VALUE(x)␉␉␉␉((x) & 0xf)␉/* Completion Timeout Value */␊
#define PCI_EXP_DEV2_TIMEOUT_DIS␉␉␉␉0x0010␉␉/* Completion Timeout Disable Supported */␊
#define PCI_EXP_DEV2_ARI␉␉␉␉␉0x0020␉␉/* ARI Forwarding */␊
#define PCI_EXP_DEVSTA2␉␉␉␉␉␉0x2a␉␉/* Device Status */␊
#define PCI_EXP_LNKCAP2␉␉␉␉␉␉0x2c␉␉/* Link Capabilities */␊
#define PCI_EXP_LNKCTL2␉␉␉␉␉␉0x30␉␉/* Link Control */␊
#define PCI_EXP_LNKCTL2_SPEED(x)␉␉␉((x) & 0xf) /* Target Link Speed */␊
#define PCI_EXP_LNKCTL2_CMPLNC␉␉␉␉0x0010␉␉/* Enter Compliance */␊
#define PCI_EXP_LNKCTL2_SPEED_DIS␉␉␉0x0020␉␉/* Hardware Autonomous Speed Disable */␊
#define PCI_EXP_LNKCTL2_DEEMPHASIS(x)␉␉(((x) >> 6) & 1) /* Selectable De-emphasis */␊
#define PCI_EXP_LNKCTL2_MARGIN(x)␉␉␉(((x) >> 7) & 7) /* Transmit Margin */␊
#define PCI_EXP_LNKCTL2_MOD_CMPLNC␉␉␉0x0400␉␉/* Enter Modified Compliance */␊
#define PCI_EXP_LNKCTL2_CMPLNC_SOS␉␉␉0x0800␉␉/* Compliance SOS */␊
#define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x)␉(((x) >> 12) & 1) /* Compliance De-emphasis */␊
#define PCI_EXP_LNKCTL2_SPEED(x)␉␉␉␉((x) & 0xf)␉/* Target Link Speed */␊
#define PCI_EXP_LNKCTL2_CMPLNC␉␉␉␉␉0x0010␉␉/* Enter Compliance */␊
#define PCI_EXP_LNKCTL2_SPEED_DIS␉␉␉␉0x0020␉␉/* Hardware Autonomous Speed Disable */␊
#define PCI_EXP_LNKCTL2_DEEMPHASIS(x)␉␉␉␉(((x) >> 6) & 1)␉/* Selectable De-emphasis */␊
#define PCI_EXP_LNKCTL2_MARGIN(x)␉␉␉␉(((x) >> 7) & 7)␉/* Transmit Margin */␊
#define PCI_EXP_LNKCTL2_MOD_CMPLNC␉␉␉␉0x0400␉␉/* Enter Modified Compliance */␊
#define PCI_EXP_LNKCTL2_CMPLNC_SOS␉␉␉␉0x0800␉␉/* Compliance SOS */␊
#define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x)␉␉␉(((x) >> 12) & 1)␉/* Compliance De-emphasis */␊
#define PCI_EXP_LNKSTA2␉␉␉␉␉␉0x32␉␉/* Link Status */␊
#define PCI_EXP_LINKSTA2_DEEMPHASIS(x)␉␉((x) & 1)␉/* Current De-emphasis Level */␊
#define PCI_EXP_LINKSTA2_DEEMPHASIS(x)␉␉␉␉((x) & 1)␉/* Current De-emphasis Level */␊
#define PCI_EXP_SLTCAP2␉␉␉␉␉␉0x34␉␉/* Slot Capabilities */␊
#define PCI_EXP_SLTCTL2␉␉␉␉␉␉0x38␉␉/* Slot Control */␊
#define PCI_EXP_SLTSTA2␉␉␉␉␉␉0x3a␉␉/* Slot Status */␊
#define PCI_SSVID_DEVICE␉␉␉␉␉6␊
␊
/* Advanced Error Reporting */␊
#define PCI_ERR_UNCOR_STATUS␉␉␉␉4␉␉␉/* Uncorrectable Error Status */␊
#define PCI_ERR_UNCOR_STATUS␉␉␉␉␉4␉␉/* Uncorrectable Error Status */␊
#define PCI_ERR_UNC_TRAIN␉␉␉␉␉0x00000001␉/* Undefined in PCIe rev1.1 & 2.0 spec */␊
#define PCI_ERR_UNC_DLP␉␉␉␉␉␉0x00000010␉/* Data Link Protocol */␊
#define PCI_ERR_UNC_SDES␉␉␉␉␉0x00000020␉/* Surprise Down Error */␊
#define PCI_ERR_UNC_POISON_TLP␉␉␉␉0x00001000␉/* Poisoned TLP */␊
#define PCI_ERR_UNC_POISON_TLP␉␉␉␉␉0x00001000␉/* Poisoned TLP */␊
#define PCI_ERR_UNC_FCP␉␉␉␉␉␉0x00002000␉/* Flow Control Protocol */␊
#define PCI_ERR_UNC_COMP_TIME␉␉␉␉0x00004000␉/* Completion Timeout */␊
#define PCI_ERR_UNC_COMP_ABORT␉␉␉␉0x00008000␉/* Completer Abort */␊
#define PCI_ERR_UNC_UNX_COMP␉␉␉␉0x00010000␉/* Unexpected Completion */␊
#define PCI_ERR_UNC_COMP_TIME␉␉␉␉␉0x00004000␉/* Completion Timeout */␊
#define PCI_ERR_UNC_COMP_ABORT␉␉␉␉␉0x00008000␉/* Completer Abort */␊
#define PCI_ERR_UNC_UNX_COMP␉␉␉␉␉0x00010000␉/* Unexpected Completion */␊
#define PCI_ERR_UNC_RX_OVER␉␉␉␉␉0x00020000␉/* Receiver Overflow */␊
#define PCI_ERR_UNC_MALF_TLP␉␉␉␉0x00040000␉/* Malformed TLP */␊
#define PCI_ERR_UNC_MALF_TLP␉␉␉␉␉0x00040000␉/* Malformed TLP */␊
#define PCI_ERR_UNC_ECRC␉␉␉␉␉0x00080000␉/* ECRC Error Status */␊
#define PCI_ERR_UNC_UNSUP␉␉␉␉␉0x00100000␉/* Unsupported Request */␊
#define PCI_ERR_UNC_ACS_VIOL␉␉␉␉0x00200000␉/* ACS Violation */␊
#define PCI_ERR_UNCOR_MASK␉␉␉␉␉8␉␉␉/* Uncorrectable Error Mask */␊
#define PCI_ERR_UNC_ACS_VIOL␉␉␉␉␉0x00200000␉/* ACS Violation */␊
#define PCI_ERR_UNCOR_MASK␉␉␉␉␉8␉␉/* Uncorrectable Error Mask */␊
/* Same bits as above */␊
#define PCI_ERR_UNCOR_SEVER␉␉␉␉␉12␉␉␉/* Uncorrectable Error Severity */␊
#define PCI_ERR_UNCOR_SEVER␉␉␉␉␉12␉␉/* Uncorrectable Error Severity */␊
/* Same bits as above */␊
#define PCI_ERR_COR_STATUS␉␉␉␉␉16␉␉␉/* Correctable Error Status */␊
#define PCI_ERR_COR_STATUS␉␉␉␉␉16␉␉/* Correctable Error Status */␊
#define PCI_ERR_COR_RCVR␉␉␉␉␉0x00000001␉/* Receiver Error Status */␊
#define PCI_ERR_COR_BAD_TLP␉␉␉␉␉0x00000040␉/* Bad TLP Status */␊
#define PCI_ERR_COR_BAD_DLLP␉␉␉␉0x00000080␉/* Bad DLLP Status */␊
#define PCI_ERR_COR_REP_ROLL␉␉␉␉0x00000100␉/* REPLAY_NUM Rollover */␊
#define PCI_ERR_COR_REP_TIMER␉␉␉␉0x00001000␉/* Replay Timer Timeout */␊
#define PCI_ERR_COR_REP_ANFE␉␉␉␉0x00002000␉/* Advisory Non-Fatal Error */␊
#define PCI_ERR_COR_MASK␉␉␉␉␉20␉␉␉/* Correctable Error Mask */␊
#define PCI_ERR_COR_BAD_DLLP␉␉␉␉␉0x00000080␉/* Bad DLLP Status */␊
#define PCI_ERR_COR_REP_ROLL␉␉␉␉␉0x00000100␉/* REPLAY_NUM Rollover */␊
#define PCI_ERR_COR_REP_TIMER␉␉␉␉␉0x00001000␉/* Replay Timer Timeout */␊
#define PCI_ERR_COR_REP_ANFE␉␉␉␉␉0x00002000␉/* Advisory Non-Fatal Error */␊
#define PCI_ERR_COR_MASK␉␉␉␉␉20␉␉/* Correctable Error Mask */␊
/* Same bits as above */␊
#define PCI_ERR_CAP␉␉␉␉␉␉␉24␉␉␉/* Advanced Error Capabilities */␊
#define PCI_ERR_CAP␉␉␉␉␉␉24␉␉/* Advanced Error Capabilities */␊
#define PCI_ERR_CAP_FEP(x)␉␉␉␉␉((x) & 31)␉/* First Error Pointer */␊
#define PCI_ERR_CAP_ECRC_GENC␉␉␉␉0x00000020␉/* ECRC Generation Capable */␊
#define PCI_ERR_CAP_ECRC_GENE␉␉␉␉0x00000040␉/* ECRC Generation Enable */␊
#define PCI_ERR_CAP_ECRC_CHKC␉␉␉␉0x00000080␉/* ECRC Check Capable */␊
#define PCI_ERR_CAP_ECRC_CHKE␉␉␉␉0x00000100␉/* ECRC Check Enable */␊
#define PCI_ERR_HEADER_LOG␉␉␉␉␉28␉␉␉/* Header Log Register (16 bytes) */␊
#define PCI_ERR_ROOT_COMMAND␉␉␉␉44␉␉␉/* Root Error Command */␊
#define PCI_ERR_CAP_ECRC_GENC␉␉␉␉␉0x00000020␉/* ECRC Generation Capable */␊
#define PCI_ERR_CAP_ECRC_GENE␉␉␉␉␉0x00000040␉/* ECRC Generation Enable */␊
#define PCI_ERR_CAP_ECRC_CHKC␉␉␉␉␉0x00000080␉/* ECRC Check Capable */␊
#define PCI_ERR_CAP_ECRC_CHKE␉␉␉␉␉0x00000100␉/* ECRC Check Enable */␊
#define PCI_ERR_HEADER_LOG␉␉␉␉␉28␉␉/* Header Log Register (16 bytes) */␊
#define PCI_ERR_ROOT_COMMAND␉␉␉␉␉44␉␉/* Root Error Command */␊
#define PCI_ERR_ROOT_STATUS␉␉␉␉␉48␊
#define PCI_ERR_ROOT_COR_SRC␉␉␉␉52␊
#define PCI_ERR_ROOT_COR_SRC␉␉␉␉␉52␊
#define PCI_ERR_ROOT_SRC␉␉␉␉␉54␊
␊
/* Virtual Channel */␊
#define PCI_VC_RES_STATUS␉␉␉␉␉26␊
␊
/* Power Budgeting */␊
#define PCI_PWR_DSR␉␉␉␉␉␉␉4␉␉␉␉␉/* Data Select Register */␊
#define PCI_PWR_DATA␉␉␉␉␉␉8␉␉␉␉␉/* Data Register */␊
#define PCI_PWR_DATA_BASE(x)␉␉␉␉((x) & 0xff)␉␉/* Base Power */␊
#define PCI_PWR_DATA_SCALE(x)␉␉␉␉(((x) >> 8) & 3)␉/* Data Scale */␊
#define PCI_PWR_DATA_PM_SUB(x)␉␉␉␉(((x) >> 10) & 7)␉/* PM Sub State */␊
#define PCI_PWR_DATA_PM_STATE(x)␉␉␉(((x) >> 13) & 3)␉/* PM State */␊
#define PCI_PWR_DATA_TYPE(x)␉␉␉␉(((x) >> 15) & 7)␉/* Type */␊
#define PCI_PWR_DATA_RAIL(x)␉␉␉␉(((x) >> 18) & 7)␉/* Power Rail */␊
#define PCI_PWR_CAP␉␉␉␉␉␉␉12␉␉␉␉␉/* Capability */␊
#define PCI_PWR_CAP_BUDGET(x)␉␉␉␉((x) & 1)␉␉␉/* Included in system budget */␊
#define PCI_PWR_DSR␉␉␉␉␉␉4␉␉/* Data Select Register */␊
#define PCI_PWR_DATA␉␉␉␉␉␉8␉␉/* Data Register */␊
#define PCI_PWR_DATA_BASE(x)␉␉␉␉␉((x) & 0xff)␉/* Base Power */␊
#define PCI_PWR_DATA_SCALE(x)␉␉␉␉␉(((x) >> 8) & 3)␉/* Data Scale */␊
#define PCI_PWR_DATA_PM_SUB(x)␉␉␉␉␉(((x) >> 10) & 7)␉/* PM Sub State */␊
#define PCI_PWR_DATA_PM_STATE(x)␉␉␉␉(((x) >> 13) & 3)␉/* PM State */␊
#define PCI_PWR_DATA_TYPE(x)␉␉␉␉␉(((x) >> 15) & 7)␉/* Type */␊
#define PCI_PWR_DATA_RAIL(x)␉␉␉␉␉(((x) >> 18) & 7)␉/* Power Rail */␊
#define PCI_PWR_CAP␉␉␉␉␉␉12␉␉/* Capability */␊
#define PCI_PWR_CAP_BUDGET(x)␉␉␉␉␉((x) & 1)␉/* Included in system budget */␊
␊
/* Access Control Services */␊
#define PCI_ACS_CAP␉␉␉␉␉␉␉0x04␉␉/* ACS Capability Register */␊
#define PCI_ACS_CAP␉␉␉␉␉␉0x04␉␉/* ACS Capability Register */␊
#define PCI_ACS_CAP_VALID␉␉␉␉␉0x0001␉␉/* ACS Source Validation */␊
#define PCI_ACS_CAP_BLOCK␉␉␉␉␉0x0002␉␉/* ACS Translation Blocking */␊
#define PCI_ACS_CAP_REQ_RED␉␉␉␉␉0x0004␉␉/* ACS P2P Request Redirect */␊
#define PCI_ACS_CAP_CMPLT_RED␉␉␉␉0x0008␉␉/* ACS P2P Completion Redirect */␊
#define PCI_ACS_CAP_CMPLT_RED␉␉␉␉␉0x0008␉␉/* ACS P2P Completion Redirect */␊
#define PCI_ACS_CAP_FORWARD␉␉␉␉␉0x0010␉␉/* ACS Upstream Forwarding */␊
#define PCI_ACS_CAP_EGRESS␉␉␉␉␉0x0020␉␉/* ACS P2P Egress Control */␊
#define PCI_ACS_CAP_TRANS␉␉␉␉␉0x0040␉␉/* ACS Direct Translated P2P */␊
#define PCI_ACS_CAP_VECTOR(x)␉␉␉␉(((x) >> 8) & 0xff) /* Egress Control Vector Size */␊
#define PCI_ACS_CAP_VECTOR(x)␉␉␉␉␉(((x) >> 8) & 0xff)␉/* Egress Control Vector Size */␊
#define PCI_ACS_CTRL␉␉␉␉␉␉0x06␉␉/* ACS Control Register */␊
#define PCI_ACS_CTRL_VALID␉␉␉␉␉0x0001␉␉/* ACS Source Validation Enable */␊
#define PCI_ACS_CTRL_BLOCK␉␉␉␉␉0x0002␉␉/* ACS Translation Blocking Enable */␊
#define PCI_ACS_CTRL_REQ_RED␉␉␉␉0x0004␉␉/* ACS P2P Request Redirect Enable */␊
#define PCI_ACS_CTRL_CMPLT_RED␉␉␉␉0x0008␉␉/* ACS P2P Completion Redirect Enable */␊
#define PCI_ACS_CTRL_FORWARD␉␉␉␉0x0010␉␉/* ACS Upstream Forwarding Enable */␊
#define PCI_ACS_CTRL_REQ_RED␉␉␉␉␉0x0004␉␉/* ACS P2P Request Redirect Enable */␊
#define PCI_ACS_CTRL_CMPLT_RED␉␉␉␉␉0x0008␉␉/* ACS P2P Completion Redirect Enable */␊
#define PCI_ACS_CTRL_FORWARD␉␉␉␉␉0x0010␉␉/* ACS Upstream Forwarding Enable */␊
#define PCI_ACS_CTRL_EGRESS␉␉␉␉␉0x0020␉␉/* ACS P2P Egress Control Enable */␊
#define PCI_ACS_CTRL_TRANS␉␉␉␉␉0x0040␉␉/* ACS Direct Translated P2P Enable */␊
#define PCI_ACS_EGRESS_CTRL␉␉␉␉␉0x08␉␉/* Egress Control Vector */␊
␊
/* Alternative Routing-ID Interpretation */␊
#define PCI_ARI_CAP␉␉␉␉␉␉␉0x04␉␉/* ARI Capability Register */␊
#define PCI_ARI_CAP␉␉␉␉␉␉0x04␉␉/* ARI Capability Register */␊
#define PCI_ARI_CAP_MFVC␉␉␉␉␉0x0001␉␉/* MFVC Function Groups Capability */␊
#define PCI_ARI_CAP_ACS␉␉␉␉␉␉0x0002␉␉/* ACS Function Groups Capability */␊
#define PCI_ARI_CAP_NFN(x)␉␉␉␉␉(((x) >> 8) & 0xff) /* Next Function Number */␊
#define PCI_ARI_CAP_NFN(x)␉␉␉␉␉(((x) >> 8) & 0xff)␉/* Next Function Number */␊
#define PCI_ARI_CTRL␉␉␉␉␉␉0x06␉␉/* ARI Control Register */␊
#define PCI_ARI_CTRL_MFVC␉␉␉␉␉0x0001␉␉/* MFVC Function Groups Enable */␊
#define PCI_ARI_CTRL_ACS␉␉␉␉␉0x0002␉␉/* ACS Function Groups Enable */␊
#define PCI_ARI_CTRL_FG(x)␉␉␉␉␉(((x) >> 4) & 7) /* Function Group */␊
#define PCI_ARI_CTRL_FG(x)␉␉␉␉␉(((x) >> 4) & 7)␉/* Function Group */␊
␊
/* Address Translation Service */␊
#define PCI_ATS_CAP␉␉␉␉␉␉␉0x04␉␉ /* ATS Capability Register */␊
#define PCI_ATS_CAP_IQD(x)␉␉␉␉␉((x) & 0x1f) /* Invalidate Queue Depth */␊
#define PCI_ATS_CTRL␉␉␉␉␉␉0x06␉␉ /* ATS Control Register */␊
#define PCI_ATS_CTRL_STU(x)␉␉␉␉␉((x) & 0x1f) /* Smallest Translation Unit */␊
#define PCI_ATS_CTRL_ENABLE␉␉␉␉␉0x8000␉␉ /* ATS Enable */␊
#define PCI_ATS_CAP␉␉␉␉␉␉0x04␉␉/* ATS Capability Register */␊
#define PCI_ATS_CAP_IQD(x)␉␉␉␉␉((x) & 0x1f)␉/* Invalidate Queue Depth */␊
#define PCI_ATS_CTRL␉␉␉␉␉␉0x06␉␉/* ATS Control Register */␊
#define PCI_ATS_CTRL_STU(x)␉␉␉␉␉((x) & 0x1f)␉/* Smallest Translation Unit */␊
#define PCI_ATS_CTRL_ENABLE␉␉␉␉␉0x8000␉␉/* ATS Enable */␊
␊
/* Single Root I/O Virtualization */␊
#define PCI_IOV_CAP␉␉␉␉␉␉␉0x04␉␉/* SR-IOV Capability Register */␊
#define PCI_IOV_CAP␉␉␉␉␉␉0x04␉␉/* SR-IOV Capability Register */␊
#define PCI_IOV_CAP_VFM␉␉␉␉␉␉0x00000001␉/* VF Migration Capable */␊
#define PCI_IOV_CAP_IMN(x)␉␉␉␉␉((x) >> 21) /* VF Migration Interrupt Message Number */␊
#define PCI_IOV_CAP_IMN(x)␉␉␉␉␉((x) >> 21)␉/* VF Migration Interrupt Message Number */␊
#define PCI_IOV_CTRL␉␉␉␉␉␉0x08␉␉/* SR-IOV Control Register */␊
#define PCI_IOV_CTRL_VFE␉␉␉␉␉0x0001␉␉/* VF Enable */␊
#define PCI_IOV_CTRL_VFME␉␉␉␉␉0x0002␉␉/* VF Migration Enable */␊
#define PCI_IOV_INITIALVF␉␉␉␉␉0x0c␉␉/* Number of VFs that are initially associated */␊
#define PCI_IOV_TOTALVF␉␉␉␉␉␉0x0e␉␉/* Maximum number of VFs that could be associated */␊
#define PCI_IOV_NUMVF␉␉␉␉␉␉0x10␉␉/* Number of VFs that are available */␊
#define PCI_IOV_FDL␉␉␉␉␉␉␉0x12␉␉/* Function Dependency Link */␊
#define PCI_IOV_FDL␉␉␉␉␉␉0x12␉␉/* Function Dependency Link */␊
#define PCI_IOV_OFFSET␉␉␉␉␉␉0x14␉␉/* First VF Offset */␊
#define PCI_IOV_STRIDE␉␉␉␉␉␉0x16␉␉/* Routing ID offset from one VF to the next one */␊
#define PCI_IOV_DID␉␉␉␉␉␉␉0x1a␉␉/* VF Device ID */␊
#define PCI_IOV_DID␉␉␉␉␉␉0x1a␉␉/* VF Device ID */␊
#define PCI_IOV_SUPPS␉␉␉␉␉␉0x1c␉␉/* Supported Page Sizes */␊
#define PCI_IOV_SYSPS␉␉␉␉␉␉0x20␉␉/* System Page Size */␊
#define PCI_IOV_BAR_BASE␉␉␉␉␉0x24␉␉/* VF BAR0, VF BAR1, ... VF BAR5 */␊
#define PCI_IOV_NUM_BAR␉␉␉␉␉␉6␉␉␉/* Number of VF BARs */␊
#define PCI_IOV_NUM_BAR␉␉␉␉␉␉6␉␉/* Number of VF BARs */␊
#define PCI_IOV_MSAO␉␉␉␉␉␉0x3c␉␉/* VF Migration State Array Offset */␊
#define PCI_IOV_MSA_BIR(x)␉␉␉␉␉((x) & 7)␉/* VF Migration State BIR */␊
#define PCI_IOV_MSA_OFFSET(x)␉␉␉␉((x) & 0xfffffff8) /* VF Migration State Offset */␊
#define PCI_IOV_MSA_OFFSET(x)␉␉␉␉␉((x) & 0xfffffff8)␉/* VF Migration State Offset */␊
␊
/*␊
* The PCI interface treats multi-function devices as independent␊
// values for the class_sub field for class_base = 0x02 (Network Controller)␊
#define PCI_BASE_CLASS_NETWORK␉␉␉␉␉0x02␊
#define PCI_CLASS_NETWORK_ETHERNET␉␉␉␉0x0200␊
#define PCI_CLASS_NETWORK_TOKEN_RING␉␉␉0x0201␊
#define PCI_CLASS_NETWORK_TOKEN_RING␉␉␉␉0x0201␊
#define PCI_CLASS_NETWORK_FDDI␉␉␉␉␉0x0202␊
#define PCI_CLASS_NETWORK_ATM␉␉␉␉␉0x0203␊
#define PCI_CLASS_NETWORK_ISDN␉␉␉␉␉0x0204␊
#define PCI_CLASS_SERIAL_ACCESS␉␉␉␉␉0x0c01␊
#define PCI_CLASS_SERIAL_SSA␉␉␉␉␉0x0c02␊
#define PCI_CLASS_SERIAL_USB␉␉␉␉␉0x0c03 /* Universal Serial Bus */␊
#define PCI_IF_UHCI␉␉␉␉␉0x00 /* Universal Host Controller Interface */␊
#define PCI_IF_OHCI␉␉␉␉␉0x10 /* Open Host Controller Interface */␊
#define PCI_IF_EHCI␉␉␉␉␉0x20 /* Enhanced Host Controller Interface */␊
#define PCI_IF_XHCI␉␉␉␉␉0x30 /* Extensible Host Controller Interface */␊
#define PCI_IF_UHCI␉␉␉␉␉␉0x00 /* Universal Host Controller Interface */␊
#define PCI_IF_OHCI␉␉␉␉␉␉0x10 /* Open Host Controller Interface */␊
#define PCI_IF_EHCI␉␉␉␉␉␉0x20 /* Enhanced Host Controller Interface */␊
#define PCI_IF_XHCI␉␉␉␉␉␉0x30 /* Extensible Host Controller Interface */␊
#define PCI_CLASS_SERIAL_FIBER␉␉␉␉␉0x0c04␊
#define PCI_CLASS_SERIAL_SMBUS␉␉␉␉␉0x0c05␊
#define PCI_CLASS_SERIAL_INFINIBAND␉␉␉␉0x0c06␊
#define PCI_CLASS_WIRELESS_IRDA␉␉␉␉␉0x0d00␊
#define PCI_CLASS_WIRELESS_IR␉␉␉␉␉0x0d01␊
#define PCI_CLASS_WIRELESS_RF␉␉␉␉␉0x0d10␊
#define PCI_CLASS_WIRELESS_BLUETOOTH␉␉␉0x0d11␊
#define PCI_CLASS_WIRELESS_BROADBAND␉␉␉0x0d12␊
#define PCI_CLASS_WIRELESS_BLUETOOTH␉␉␉␉0x0d11␊
#define PCI_CLASS_WIRELESS_BROADBAND␉␉␉␉0x0d12␊
#define PCI_CLASS_WIRELESS_80211A␉␉␉␉0x0d20␊
#define PCI_CLASS_WIRELESS_80211B␉␉␉␉0x0d21␊
#define PCI_CLASS_WIRELESS_WHCI␉␉␉␉␉0x0d1010␊
#define PCI_CLASS_SIGNAL_OTHER␉␉␉␉␉0x1180␊
␊
// values for the class_sub field for class_base = 0xff (Device does not fit any defined class)␊
#define PCI_CLASS_OTHERS 0xff␊
#define PCI_CLASS_OTHERS␉␉␉␉␉0xff␊
␊
/* Several ID's we need in the library */␊
#define PCI_VENDOR_ID_APPLE␉␉␉␉␉0x106b␊
#define PCI_VENDOR_ID_AMD␉␉␉␉␉0x1022␊
#define PCI_VENDOR_ID_ATI␉␉␉␉␉0x1002␊
#define PCI_VENDOR_ID_INTEL␉␉␉␉␉0x8086␊
#define PCI_VENDOR_ID_NVIDIA␉␉␉␉0x10de␊
#define PCI_VENDOR_ID_REALTEK␉␉␉␉0x10ec␊
#define PCI_VENDOR_ID_TEXAS_INSTRUMENTS ␉0x104c␊
#define PCI_VENDOR_ID_NVIDIA␉␉␉␉␉0x10de␊
#define PCI_VENDOR_ID_REALTEK␉␉␉␉␉0x10ec␊
#define PCI_VENDOR_ID_TEXAS_INSTRUMENTS␉␉␉␉0x104c␊
#define PCI_VENDOR_ID_VIA␉␉␉␉␉0x1106␊
␊
#endif /* !__LIBSAIO_PCI_H */␊
trunk/i386/libsaio/fake_efi.c
585585
586586
587587
588
588
589
589590
590
591
592
593
594
591595
592596
593597
......
602606
603607
604608
605
609
610
606611
607612
608613
609614
610615
611616
612
617
618
619
613620
614621
615622
......
729736
730737
731738
732
739
733740
734741
735742
......
895902
896903
897904
898
905
899906
900907
901908
␉// too so we might as well create it so we have a pointer for it too.␊
␉node = DT__AddChild(node, "efi");␊
/* Bungo␊
␉if (archCpuType == CPU_TYPE_I386) {␊
␉if (archCpuType == CPU_TYPE_I386)␊
␉{␊
␉␉DT__AddProperty(node, FIRMWARE_ABI_PROP, sizeof(FIRMWARE_ABI_32_PROP_VALUE), (char*)FIRMWARE_ABI_32_PROP_VALUE);␊
␉} else { */␊
␉}␊
␉else␊
␉{␊
␉*/␊
␉␉DT__AddProperty(node, FIRMWARE_ABI_PROP, sizeof(FIRMWARE_ABI_64_PROP_VALUE), (char *)FIRMWARE_ABI_64_PROP_VALUE);␊
//␉}␊
␊
␉// is set up. That is, name and table properties␊
␉Node *runtimeServicesNode = DT__AddChild(node, "runtime-services");␊
␊
␉if (archCpuType == CPU_TYPE_I386) {␊
␉if (archCpuType == CPU_TYPE_I386)␊
␉{␊
␉␉// The value of the table property is the 32-bit physical address for the RuntimeServices table.␊
␉␉// Since the EFI system table already has a pointer to it, we simply use the address of that pointer␊
␉␉// for the pointer to the property data. Warning.. DT finalization calls free on that but we're not␊
␉␉// the only thing to use a non-malloc'd pointer for something in the DT␊
␊
␉␉DT__AddProperty(runtimeServicesNode, "table", sizeof(uint64_t), &gST32->RuntimeServices);␊
␉} else {␊
␉}␊
␉else␊
␉{␊
␉␉DT__AddProperty(runtimeServicesNode, "table", sizeof(uint64_t), &gST64->RuntimeServices);␊
␉}␊
␊
␉␉EFI_UINT32 rcx, rdx, rsi, rdi;␊
␊
␉␉randomValue = tempValue = ecx = esi = edi = 0;␉␉␉␉␉// xor␉␉%ecx,␉%ecx␊
␉␉rcx = rdx = rsi = rdi = cpuTick = 0;␊
␉␉cpuTick = rcx = rdx = rsi = rdi = 0;␊
␊
␉␉// LEAF_1 - Feature Information (Function 01h).␊
␉␉if (Platform.CPU.CPUID[CPUID_1][2] & 0x40000000)␉␉␉␉// Checking ecx:bit-30␊
*/␊
void setupFakeEfi(void)␊
{␊
␉// Generate efi device strings ␊
␉// Generate efi device strings␊
␉setup_pci_devs(root_pci_dev);␊
␊
␉readSMBIOSInfo(getSmbios(SMBIOS_ORIGINAL));␊
trunk/i386/boot2/graphics.c
11201120
11211121
11221122
1123
1124
1123
1124
11251125
11261126
11271127
......
12671267
12681268
12691269
1270
1270
12711271
12721272
12731273
unsigned long numbers[],␊
unsigned long maxArrayCount )␊
{␊
␉char *propStr;␊
␉unsigned long count = 0;␊
␉char␉␉*propStr;␊
␉unsigned long␉count = 0;␊
␊
␉propStr = newStringForKey((char *)propKey , &bootInfo->chameleonConfig);␊
␊
// Display and clear the activity indicator.␊
␊
// BASIC Indicator␊
static char indicator[] = {'-', '\\', '|', '/', '-', '\\', '|', '/', '\0'};␊
static char indicator[] = {'-', '\\', '|', '/', '\0'};␊
␊
// To prevent a ridiculously fast-spinning indicator,␊
// ensure a minimum of 1/9 sec between animation frames.␊
trunk/i386/boot2/boot.c
721721
722722
723723
724
724
725725
726726
727727
␉␉}␊
␉␉else␊
␉␉{␊
␉␉␉verbose("Kernel Cache using disabled by user.");␊
␉␉␉DBG("Kernel Cache using disabled by user.\n");␊
␉␉}␊
␊
␉␉do␊
trunk/i386/libsa/memory.h
9090
9191
9292
93
9493
94
95
9596
9697
9798
#define KERNEL_LEN 0x08000000␊
␊
#define ZALLOC_ADDR 0x08100000 // 256M zalloc area␊
#define ZALLOC_LEN 0x10000000␊
␊
#define ZALLOC_LEN 0x14000000 // Pike R. Alpha: was 0x10000000␊
␊
#define LOAD_ADDR 0x18100000 // 64M File load buffer␊
#define LOAD_LEN 0x04000000␊
␊

Archive Download the corresponding diff file

Revision: 2554