Chameleon

Chameleon Commit Details

Date:2015-01-26 00:46:58 (9 years 2 months ago)
Author:ErmaC
Commit:2555
Parents: 2554
Message:Update HDA data for internal HDAEnabler injector
Changes:
M/trunk/i386/libsaio/hda.h
M/trunk/i386/libsaio/hda.c

File differences

trunk/i386/libsaio/hda.c
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␊
static hda_controller_devices know_hda_controller[] = {␊
␉//8086 Intel Corporation␊
␉{ HDA_INTEL_HASWELL,␉"Haswell-ULT" },␊
␉{ HDA_INTEL_HASWELL2,␉"Haswell" },␊
␉{ HDA_INTEL_CRYSTAL,␉"Crystal Well" },␊
␉{ HDA_INTEL_CPT,␉"6 Series/C200 Series Chipset Family" },␊
␉{ HDA_INTEL_PATSBURG,␉"C600/X79 series chipset" },␊
␉{ HDA_INTEL_PPT1,␉"7 Series/C210 Series Chipset Family" },␊
␉{ HDA_INTEL_82801F,␉"82801FB/FBM/FR/FW/FRW (ICH6 Family)" },␊
␉{ HDA_INTEL_63XXESB,␉"631x/631xESB/632xESB" },␊
␉{ HDA_INTEL_82801G,␉"NM10/ICH7 Family" },␊
␉{ HDA_INTEL_82801H,␉"82801H (ICH8 Family)" },␊
␉{ HDA_INTEL_82801I,␉"82801I (ICH9 Family)" },␊
␉{ HDA_INTEL_82801JI,␉"82801JI (ICH10 Family)" },␊
␉{ HDA_INTEL_82801JD,␉"82801JD/DO (ICH10 Family) " },␊
␉{ HDA_INTEL_PCH,␉"5 Series/3400 Series" },␊
␉{ HDA_INTEL_PCH2,␉"5 Series/3400 Series" },␊
␉{ HDA_INTEL_SCH,␉"System Controller Hub (SCH Poulsbo)" },␊
␉{ HDA_INTEL_SCH2,␉"Wildcat Point" },␊
␉{ HDA_INTEL_LPT1,␉"Wellsburg" },␊
␉{ HDA_INTEL_LPT2,␉"Wellsburg" },␊
␉{ HDA_INTEL_LYNX,␉"Lynx Point" },␊
␉{ HDA_INTEL_LYNX2,␉"Lynx Point" },␊
␉{ HDA_INTEL_OAK,␉"Oaktrail"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_BAY,␉"BayTrail"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_HSW1,␉"Haswell"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_HSW2,␉"Haswell"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_HSW3,␉"Haswell"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_CPT,␉"Cougar Point"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_PATSBURG,␉"Patsburg"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_PPT1,␉"Panther Point"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_LPT1,␉"Lynx Point"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_LPT2,␉"Lynx Point"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_WCPT,␉"Wildcat Point"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_WELLS1,␉"Wellsburg"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_WELLS2,␉"Wellsburg"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_LPTLP1,␉"Lynx Point-LP"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_LPTLP2,␉"Lynx Point-LP"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801F,␉"82801F"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_63XXESB,␉"631x/632xESB"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801G,␉"82801G"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801H,␉"82801H"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801I,␉"82801I"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801JI,␉"82801JI"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801JD,␉"82801JD"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_PCH,␉"5 Series/3400 Series" /*, 0, 0 */ },␊
␉{ HDA_INTEL_PCH2,␉"5 Series/3400 Series" /*, 0, 0 */ },␊
␉{ HDA_INTEL_SCH,␉"SCH"␉␉/*, 0, 0 */ },␊
␉//10de NVIDIA Corporation␊
␉{ HDA_NVIDIA_MCP51,␉"MCP51" },␊
␉{ HDA_NVIDIA_MCP55,␉"MCP55" },␊
␉{ HDA_NVIDIA_MCP61_1, "MCP61" },␊
␉{ HDA_NVIDIA_MCP61_2, "MCP61" },␊
␉{ HDA_NVIDIA_MCP65_1, "MCP65" },␊
␉{ HDA_NVIDIA_MCP65_2, "MCP65" },␊
␉{ HDA_NVIDIA_MCP67_1, "MCP67" },␊
␉{ HDA_NVIDIA_MCP67_2, "MCP67" },␊
␉{ HDA_NVIDIA_MCP73_1, "MCP73" },␊
␉{ HDA_NVIDIA_MCP73_2, "MCP73" },␊
␉{ HDA_NVIDIA_MCP78_1, "MCP78" },␊
␉{ HDA_NVIDIA_MCP78_2, "MCP78" },␊
␉{ HDA_NVIDIA_MCP78_3, "MCP78" },␊
␉{ HDA_NVIDIA_MCP78_4, "MCP78" },␊
␉{ HDA_NVIDIA_MCP79_1, "MCP79" },␊
␉{ HDA_NVIDIA_MCP79_2, "MCP79" },␊
␉{ HDA_NVIDIA_MCP79_3, "MCP79" },␊
␉{ HDA_NVIDIA_MCP79_4, "MCP79" },␊
␉{ HDA_NVIDIA_MCP89_1, "MCP89" },␊
␉{ HDA_NVIDIA_MCP89_2, "MCP89" },␊
␉{ HDA_NVIDIA_MCP89_3, "MCP89" },␊
␉{ HDA_NVIDIA_MCP89_4, "MCP89" },␊
␉{ HDA_NVIDIA_0BE2, "(0x0be2)" },␊
␉{ HDA_NVIDIA_0BE3, "(0x0be3)" },␊
␉{ HDA_NVIDIA_0BE4, "(0x0be4)" },␊
␉{ HDA_NVIDIA_GT100, "GT100" },␊
␉{ HDA_NVIDIA_GT104, "GT104" },␊
␉{ HDA_NVIDIA_GT106, "GT106" },␊
␉{ HDA_NVIDIA_GT108, "GT108" },␊
␉{ HDA_NVIDIA_GT116, "GT116" },␊
␉{ HDA_NVIDIA_GF119, "GF119" },␊
␉{ HDA_NVIDIA_GF110, "GF110" },␊
␉{ HDA_NVIDIA_GF114, "GF114" }, // HDMi␊
␉{ HDA_NVIDIA_GK110, "GK110" },␊
␉{ HDA_NVIDIA_GK106, "GK106" },␊
␉{ HDA_NVIDIA_GK107, "GK107" },␊
␉{ HDA_NVIDIA_GK104, "GK104" },␊
␉{ HDA_NVIDIA_MCP51,␉"MCP51" /*, 0, HDAC_QUIRK_MSI */ },␊
␉{ HDA_NVIDIA_MCP55,␉"MCP55" /*, 0, HDAC_QUIRK_MSI */ },␊
␉{ HDA_NVIDIA_MCP61_1,␉"MCP61" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_MCP61_2,␉"MCP61" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_MCP65_1,␉"MCP65" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_MCP65_2,␉"MCP65" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_MCP67_1,␉"MCP67" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_MCP67_2,␉"MCP67" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_MCP73_1,␉"MCP73" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_MCP73_2,␉"MCP73" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_MCP78_1,␉"MCP78" /*, 0, HDAC_QUIRK_64BIT */ },␊
␉{ HDA_NVIDIA_MCP78_2,␉"MCP78" /*, 0, HDAC_QUIRK_64BIT */ },␊
␉{ HDA_NVIDIA_MCP78_3,␉"MCP78" /*, 0, HDAC_QUIRK_64BIT */ },␊
␉{ HDA_NVIDIA_MCP78_4,␉"MCP78" /*, 0, HDAC_QUIRK_64BIT */ },␊
␉{ HDA_NVIDIA_MCP79_1,␉"MCP79" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_MCP79_2,␉"MCP79" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_MCP79_3,␉"MCP79" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_MCP79_4,␉"MCP79" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_MCP89_1,␉"MCP89" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_MCP89_2,␉"MCP89" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_MCP89_3,␉"MCP89" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_MCP89_4,␉"MCP89" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_0BE2,␉"(0x0be2)" /*, 0, HDAC_QUIRK_MSI */ },␊
␉{ HDA_NVIDIA_0BE3,␉"(0x0be3)" /*, 0, HDAC_QUIRK_MSI */ },␊
␉{ HDA_NVIDIA_0BE4,␉"(0x0be4)" /*, 0, HDAC_QUIRK_MSI */ },␊
␉{ HDA_NVIDIA_GT100,␉"GT100" /*, 0, HDAC_QUIRK_MSI */ },␊
␉{ HDA_NVIDIA_GT104,␉"GT104" /*, 0, HDAC_QUIRK_MSI */ },␊
␉{ HDA_NVIDIA_GT106,␉"GT106" /*, 0, HDAC_QUIRK_MSI */ },␊
␉{ HDA_NVIDIA_GT108,␉"GT108" /*, 0, HDAC_QUIRK_MSI */ },␊
␉{ HDA_NVIDIA_GT116,␉"GT116" /*, 0, HDAC_QUIRK_MSI */ },␊
␉{ HDA_NVIDIA_GF119,␉"GF119" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_GF110_1,␉"GF110" /*, 0, HDAC_QUIRK_MSI */ },␊
␉{ HDA_NVIDIA_GF110_2,␉"GF110" /*, 0, HDAC_QUIRK_MSI */ },␊
␉{ HDA_NVIDIA_GK110,␉"GK110" /*, 0, ? */ },␊
␉{ HDA_NVIDIA_GK106,␉"GK106" /*, 0, ? */ },␊
␉{ HDA_NVIDIA_GK107,␉"GK107" /*, 0, ? */ },␊
␉{ HDA_NVIDIA_GK104,␉"GK104" /*, 0, ? */ },␊
␉//1002 Advanced Micro Devices [AMD] nee ATI Technologies Inc␊
␉{ HDA_ATI_SB450, "IXP SB4x0" },␊
␉{ HDA_ATI_SB600, "SB600" },␊
␉{ HDA_ATI_RS600, "RS600" },␊
␉{ HDA_ATI_RS690, "RS690" },␊
␉{ HDA_ATI_RS780, "RS780" },␊
␉{ HDA_ATI_RS880, "RS880" },␊
␉{ HDA_ATI_TRINITY, "Trinity" },␊
␉{ HDA_ATI_R600, "R600" },␊
␉{ HDA_ATI_RV610, "RV610" },␊
␉{ HDA_ATI_RV620, "RV620" },␊
␉{ HDA_ATI_RV630, "RV630" },␊
␉{ HDA_ATI_RV635, "RV635" },␊
␉{ HDA_ATI_RV710, "RV710" },␊
␉{ HDA_ATI_RV730, "RV730" },␊
␉{ HDA_ATI_RV740, "RV740" },␊
␉{ HDA_ATI_RV770, "RV770" },␊
␉{ HDA_ATI_RV810, "RV810" },␊
␉{ HDA_ATI_RV830, "RV830" },␊
␉{ HDA_ATI_RV840, "RV840" },␊
␉{ HDA_ATI_RV870, "RV870" },␊
␉{ HDA_ATI_RV910, "Caicos" },␊
␉{ HDA_ATI_RV930, "RV930" },␊
␉{ HDA_ATI_RV940, "RV940" },␊
␉{ HDA_ATI_RV970, "RV970" },␊
␉{ HDA_ATI_R1000, "Tahiti XT" }, // HDMi␊
␉{ HDA_ATI_VERDE, "Cape Verde" }, // HDMi␊
␉{ HDA_ATI_SB450,␉"SB4x0" /*, 0, 0 */ },␊
␉{ HDA_ATI_SB600,␉"SB600" /*, 0, 0 */ },␊
␉{ HDA_ATI_RS600,␉"RS600" /*, 0, 0 */ },␊
␉{ HDA_ATI_RS690,␉"RS690" /*, 0, 0 */ },␊
␉{ HDA_ATI_RS780,␉"RS780" /*, 0, 0 */ },␊
␉{ HDA_ATI_RS880,␉"RS880" /*, 0, 0 */ },␊
␉{ HDA_ATI_TRINITY,␉"Trinity" /*, 0, ? */ },␊
␉{ HDA_ATI_R600,␉␉"R600" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV610,␉"RV610" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV620,␉"RV620" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV630,␉"RV630" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV635,␉"RV635" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV710,␉"RV710" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV730,␉"RV730" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV740,␉"RV740" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV770,␉"RV770" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV810,␉"RV810" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV830,␉"RV830" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV840,␉"RV840" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV870,␉"RV870" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV910,␉"RV910" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV930,␉"RV930" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV940,␉"RV940" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV970,␉"RV970" /*, 0, 0 */ },␊
␉{ HDA_ATI_R1000,␉"R1000" /*, 0, 0 */ }, // HDMi␊
␉{ HDA_ATI_VERDE,␉"Cape Verde" /*, 0, ? */ }, // HDMi␊
␉//17f3 RDC Semiconductor, Inc.␊
␉{ HDA_RDC_M3010, "M3010" },␊
␉{ HDA_RDC_M3010,␉"M3010" /*, 0, 0 */ },␊
␉//1106 VIA Technologies, Inc.␊
␉{ HDA_VIA_VT82XX, "VT8251/8237A" },␊
␉{ HDA_VIA_VT82XX,␉"VT8251/8237A" /*, 0, 0 */ },␊
␉//1039 Silicon Integrated Systems [SiS]␊
␉{ HDA_SIS_966, "966" },␊
␉{ HDA_SIS_966,␉␉"966" /*, 0, 0 */ },␊
␉//10b9 ULi Electronics Inc.(Split off ALi Corporation in 2003)␊
␉{ HDA_ULI_M5461, "M5461" },␊
␉{ HDA_ULI_M5461,␉"M5461" /*, 0, 0 */ },␊
␉/* Unknown */␊
␉{ HDA_INTEL_ALL, "Unknown Intel device" },␊
␉{ HDA_NVIDIA_ALL, "Unknown NVIDIA device" },␊
␉{ HDA_ATI_ALL, "Unknown ATI device" },␊
␉{ HDA_VIA_ALL, "Unknown VIA device" },␊
␉{ HDA_SIS_ALL, "Unknown SiS device" },␊
␉{ HDA_ULI_ALL, "Unknown ULI device" },␊
␉{ HDA_INTEL_ALL,␉"Unknown Intel device" /*, 0, 0 */ },␊
␉{ HDA_NVIDIA_ALL,␉"Unknown NVIDIA device" /*, 0, 0 */ },␊
␉{ HDA_ATI_ALL,␉␉"Unknown ATI device" /*, 0, 0 */ },␊
␉{ HDA_VIA_ALL,␉␉"Unknown VIA device" /*, 0, 0 */ },␊
␉{ HDA_SIS_ALL,␉␉"Unknown SiS device" /*, 0, 0 */ },␊
␉{ HDA_ULI_ALL,␉␉"Unknown ULI device" /*, 0, 0 */ },␊
};␊
#define HDAC_DEVICES_LEN (sizeof(know_hda_controller) / sizeof(know_hda_controller[0]))␊
␊
␉/***********************************************************************␊
␉* The above case are intended as for HDEF device at address 0x001B0000␊
␉***********************************************************************/␊
␉␉case HDA_INTEL_HASWELL:␊
␉␉case HDA_INTEL_HASWELL2:␊
␉␉case HDA_INTEL_CRYSTAL:␊
␉␉case HDA_INTEL_OAK:␊
␉␉case HDA_INTEL_BAY:␊
␉␉case HDA_INTEL_HSW1:␊
␉␉case HDA_INTEL_HSW2:␊
␉␉case HDA_INTEL_HSW3:␊
␉␉case HDA_INTEL_CPT:␊
␉␉case HDA_INTEL_PATSBURG:␊
␉␉case HDA_INTEL_PPT1:␊
␉␉case HDA_INTEL_LPT1:␊
␉␉case HDA_INTEL_LPT2:␊
␉␉case HDA_INTEL_WCPT:␊
␉␉case HDA_INTEL_WELLS1:␊
␉␉case HDA_INTEL_WELLS2:␊
␉␉case HDA_INTEL_LPTLP1:␊
␉␉case HDA_INTEL_LPTLP2:␊
␉␉case HDA_INTEL_82801F:␊
␉␉case HDA_INTEL_63XXESB:␊
␉␉case HDA_INTEL_82801G:␊
␉␉case HDA_INTEL_PCH:␊
␉␉case HDA_INTEL_PCH2:␊
␉␉case HDA_INTEL_SCH:␊
␉␉case HDA_INTEL_SCH2:␊
␉␉case HDA_INTEL_LPT1:␊
␉␉case HDA_INTEL_LPT2:␊
␉␉case HDA_INTEL_LYNX:␊
␉␉case HDA_INTEL_LYNX2:␊
␊
␉/* if the key value kHDEFLayoutID as a value set that value, if not will assign a default layout */␊
␉if (getValueForKey(kHDEFLayoutID, &value, &len, &bootInfo->chameleonConfig) && len == HDEF_LEN * 2)␊
␉{␊
␉* The above case are intended as for HDAU (NVIDIA) device onboard audio for GFX card with Audio controller HDMi␊
␉****************************************************************************************************************/␊
␉case HDA_NVIDIA_GK107:␊
␉case HDA_NVIDIA_GF114:␊
␉case HDA_NVIDIA_GF110_1:␊
␉case HDA_NVIDIA_GF110_2:␊
␉case HDA_NVIDIA_GK106:␊
␉case HDA_NVIDIA_GK104:␊
␉case HDA_NVIDIA_GF110:␊
␉case HDA_NVIDIA_GF119:␊
␉case HDA_NVIDIA_GT116:␊
␉case HDA_NVIDIA_GT104:␊
trunk/i386/libsaio/hda.h
9090
9191
9292
93
94
95
93
94
95
96
97
9698
9799
98100
......
105107
106108
107109
110
108111
109
110
111
112
113
112
113
114
115
116
117
118
114119
115120
116121
......
148153
149154
150155
151
156
157
152158
153159
154
155160
156161
157162
......
667672
668673
669674
670
671
672
673
674
675
676
677
678
675
676
677
678
679
680
681
682
683
684
679685
680686
681687
␊
/* Intel */␊
#define INTEL_VENDORID␉␉0x8086␊
#define HDA_INTEL_HASWELL␉HDA_MODEL_CONSTRUCT(INTEL, 0x0a0c)␊
#define HDA_INTEL_HASWELL2␉HDA_MODEL_CONSTRUCT(INTEL, 0x0c0c)␊
#define HDA_INTEL_CRYSTAL␉HDA_MODEL_CONSTRUCT(INTEL, 0x0d0c)␊
#define HDA_INTEL_OAK␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x080a) // NEW␊
#define HDA_INTEL_BAY␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0f04) // NEW␊
#define HDA_INTEL_HSW1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0a0c)␊
#define HDA_INTEL_HSW2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0c0c)␊
#define HDA_INTEL_HSW3␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0d0c)␊
#define HDA_INTEL_CPT␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x1c20)␊
#define HDA_INTEL_PATSBURG␉HDA_MODEL_CONSTRUCT(INTEL, 0x1d20)␊
#define HDA_INTEL_PPT1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x1e20) // Macmini6,2␊
#define HDA_INTEL_82801JD␉HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e)␊
#define HDA_INTEL_PCH␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x3b56)␊
#define HDA_INTEL_PCH2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x3b57)␊
#define HDA_INTEL_MACBOOKPRO92␉HDA_MODEL_CONSTRUCT(INTEL, 0x7270) // NEW␊
#define HDA_INTEL_SCH␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x811b)␊
#define HDA_INTEL_SCH2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8ca0)␊
#define HDA_INTEL_LPT1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8d20)␊
#define HDA_INTEL_LPT2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8d21)␊
#define HDA_INTEL_LYNX HDA_MODEL_CONSTRUCT(INTEL, 0x9c20)␊
#define HDA_INTEL_LYNX2 HDA_MODEL_CONSTRUCT(INTEL, 0x9c21)␊
#define HDA_INTEL_LPT1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8c20) // NEW␊
#define HDA_INTEL_LPT2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8c21) // NEW␊
#define HDA_INTEL_WCPT␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8ca0)␊
#define HDA_INTEL_WELLS1␉HDA_MODEL_CONSTRUCT(INTEL, 0x8d20)␊
#define HDA_INTEL_WELLS2␉HDA_MODEL_CONSTRUCT(INTEL, 0x8d21)␊
#define HDA_INTEL_LPTLP1␉HDA_MODEL_CONSTRUCT(INTEL, 0x9c20)␊
#define HDA_INTEL_LPTLP2␉HDA_MODEL_CONSTRUCT(INTEL, 0x9c21)␊
#define HDA_INTEL_ALL␉␉HDA_MODEL_CONSTRUCT(INTEL, 0xffff)␊
␊
/* Nvidia */␊
#define HDA_NVIDIA_MCP89_3␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96)␊
#define HDA_NVIDIA_MCP89_4␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97)␊
#define HDA_NVIDIA_GF119␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e08)␊
#define HDA_NVIDIA_GF110␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e09)␊
#define HDA_NVIDIA_GF110_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e09)␊
#define HDA_NVIDIA_GF110_2␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e0c) // HDACodec de101600 (10de0016), Controller Binary de100c0e x2␊
#define HDA_NVIDIA_GK104␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e0a)␊
#define HDA_NVIDIA_GK106␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e0b)␊
#define HDA_NVIDIA_GF114␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e0c) // HDACodec de101600 (10de0016), Controller Binary de100c0e x2␊
#define HDA_NVIDIA_GK110␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e1a)␊
#define HDA_NVIDIA_GK107␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e1b) // HDACodec de104200 (10de0042)␊
#define HDA_NVIDIA_ALL␉␉HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff)␊
#define HDA_CODEC_CHXXXX HDA_CODEC_CONSTRUCT(CHRONTEL, 0xffff)␊
␊
/* INTEL */␊
#define HDA_CODEC_INTELIP HDA_CODEC_CONSTRUCT(INTEL, 0x0054)␊
#define HDA_CODEC_INTELBL HDA_CODEC_CONSTRUCT(INTEL, 0x2801)␊
#define HDA_CODEC_INTELCA HDA_CODEC_CONSTRUCT(INTEL, 0x2802)␊
#define HDA_CODEC_INTELEL HDA_CODEC_CONSTRUCT(INTEL, 0x2803)␊
#define HDA_CODEC_INTELIP2 HDA_CODEC_CONSTRUCT(INTEL, 0x2804)␊
#define HDA_CODEC_INTELCPT HDA_CODEC_CONSTRUCT(INTEL, 0x2805)␊
#define HDA_CODEC_INTELPPT HDA_CODEC_CONSTRUCT(INTEL, 0x2806)␊
#define HDA_CODEC_INTELCL HDA_CODEC_CONSTRUCT(INTEL, 0x29fb)␊
#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff)␊
#define HDA_CODEC_INTELIP␉HDA_CODEC_CONSTRUCT(INTEL, 0x0054)␊
#define HDA_CODEC_INTELBL␉HDA_CODEC_CONSTRUCT(INTEL, 0x2801)␊
#define HDA_CODEC_INTELCA␉HDA_CODEC_CONSTRUCT(INTEL, 0x2802)␊
#define HDA_CODEC_INTELEL␉HDA_CODEC_CONSTRUCT(INTEL, 0x2803)␊
#define HDA_CODEC_INTELIP2␉HDA_CODEC_CONSTRUCT(INTEL, 0x2804)␊
#define HDA_CODEC_INTELCPT␉HDA_CODEC_CONSTRUCT(INTEL, 0x2805)␊
#define HDA_CODEC_INTELPPT␉HDA_CODEC_CONSTRUCT(INTEL, 0x2806)␊
#define HDA_CODEC_INTELHSW␉HDA_CODEC_CONSTRUCT(INTEL, 0x2807)␊
#define HDA_CODEC_INTELCL␉HDA_CODEC_CONSTRUCT(INTEL, 0x29fb)␊
#define HDA_CODEC_INTELXXXX␉HDA_CODEC_CONSTRUCT(INTEL, 0xffff)␊
␊
/****************************************************************************␊
* HDA Controller Register Set␊

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