| ␉boolean_t␉fine_grain_clock_mod = 0;␊ |
| ␊ |
| #if BUILD_ACPI_TSS || pstate_power_support␊ |
| ␉if (Platform.CPU.CPUID[CPUID_0][0] >= 0x5) { ␊ |
| ␉if (Platform.CPU.CPUID[CPUID_0][0] >= 0x5) {␊ |
| ␉␉/*␊ |
| ␉␉ * Extract the Monitor/Mwait Leaf info:␊ |
| ␉␉ */␊ |
| sub_Cstates = Platform.CPU.CPUID[CPUID_5][3];␊ |
| extensions = Platform.CPU.CPUID[CPUID_5][2];␉␊ |
| ␉}␊ |
| ␉␊ |
| ␉if (Platform.CPU.CPUID[CPUID_0][0] >= 6) {␊ |
| ␊ |
| ␉if (Platform.CPU.CPUID[CPUID_0][0] >= 6)␊ |
| ␉{␊ |
| ␉␉dynamic_acceleration = bitfield(Platform.CPU.CPUID[CPUID_6][0], 1, 1); // "Dynamic Acceleration Technology (Turbo Mode)"␊ |
| ␉␉invariant_APIC_timer = bitfield(Platform.CPU.CPUID[CPUID_6][0], 2, 2); // "Invariant APIC Timer"␊ |
| fine_grain_clock_mod = bitfield(Platform.CPU.CPUID[CPUID_6][0], 4, 4);␊ |
| ␉}␊ |
| cpu->turbo_available = (U32)dynamic_acceleration;␊ |
| ␉␊ |
| ␉cpu->turbo_available = (U32)dynamic_acceleration;␊ |
| ␊ |
| ␉{␊ |
| ␉␉U32 temp32 = 0;␊ |
| ␉␉U64 temp64= 0;␊ |
|
| ␉␉if (getIntForKey("TDP", &tdp, &bootInfo->chameleonConfig))␊ |
| ␉␉{␊ |
| ␉␉␉temp32 = (U32) (tdp*8) ; ␊ |
| ␉␉␉␊ |
| ␊ |
| ␉␉␉int tdc;␊ |
| ␉␉␉if (getIntForKey("TDC", &tdc, &bootInfo->chameleonConfig))␊ |
| ␉␉␉{␊ |
| ␉␉␉␉temp32 = (U32) (temp32) | tdc<<16 ; ␊ |
| ␉␉␉␉␊ |
| ␉␉␉␉temp32 = (U32) (temp32) | tdc<<16 ;␊ |
| ␊ |
| ␉␉␉}␊ |
| ␉␉␉else if (tdp)␊ |
| ␉␉␉{␊ |
| ␉␉␉␉temp32 = (U32) (temp32) | ((tdp)*8)<<16 ;␊ |
| ␉␉␉}␊ |
| ␉␉␉␊ |
| ␊ |
| ␉␉}␊ |
| ␉␉else if (!is_sandybridge() && !is_jaketown())␊ |
| ␉␉{␊ |
|
| ␉␉␉␉// in your boot.plist ␊ |
| ␉␉␉␉temp32 = (U32)0x02a802f8;␊ |
| ␉␉␉}␊ |
| ␉␉␉␊ |
| ␊ |
| ␉␉}␊ |
| ␉␉if (temp32) {␊ |
| ␉␉if (temp32)␊ |
| ␉␉{␊ |
| ␉␉␉cpu->tdp_limit = ( temp32 & 0x7fff );␊ |
| ␉␉␉cpu->tdc_limit = ( (temp32 >> 16) & 0x7fff );␊ |
| ␉␉}␊ |
| ␉} ␊ |
| ␊ |
| ␊ |
| #endif␊ |
| ␊ |
| ␊ |
| ␉switch (Platform.CPU.Family)␊ |
| ␉{␊ |
| ␉␉case 0x06: ␊ |
|
| ␉␉␉␉case CPUID_MODEL_PENRYN: // Penryn␊ |
| ␉␉␉␉case CPUID_MODEL_ATOM: // Intel Atom (45nm)␊ |
| ␉␉␉␉{␊ |
| ␉␉␉␉␉␊ |
| ␊ |
| ␉␉␉␉␉cpu->core_c1_supported = ((sub_Cstates >> 4) & 0xf) ? 1 : 0;␊ |
| ␉␉␉␉␉cpu->core_c4_supported = ((sub_Cstates >> 16) & 0xf) ? 1 : 0;␊ |
| ␉␉␉␉␉␊ |
| ␊ |
| ␉␉␉␉␉if (Platform.CPU.Model == CPUID_MODEL_ATOM)␊ |
| ␉␉␉␉␉{␊ |
| ␉␉␉␉␉␉cpu->core_c2_supported = cpu->core_c3_supported = ((sub_Cstates >> 8) & 0xf) ? 1 : 0;␊ |
| ␉␉␉␉␉␉cpu->core_c6_supported = ((sub_Cstates >> 12) & 0xf) ? 1 : 0;␊ |
| ␊ |
| ␊ |
| ␉␉␉␉␉} ␊ |
| ␉␉␉␉␉else␊ |
| ␉␉␉␉␉{␊ |
| ␉␉␉␉␉␉cpu->core_c3_supported = ((sub_Cstates >> 12) & 0xf) ? 1 : 0;␊ |
| ␉␉␉␉␉␉cpu->core_c2_supported = ((sub_Cstates >> 8) & 0xf) ? 1 : 0;␊ |
| ␉␉␉␉␉␉cpu->core_c6_supported = 0;␊ |
| ␊ |
| ␊ |
| ␉␉␉␉␉}␊ |
| ␊ |
| ␊ |
| ␉␉␉␉␉cpu->core_c7_supported = 0;␊ |
| ␊ |
| ␊ |
| #if BETA␊ |
| ␉␉␉␉␉GetMaxRatio(&cpu->max_ratio_as_mfg);␊ |
| ␉␉␉␉␉U64 msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
|
| ␉␉␉␉␉U16 idhi = (msr >> 32) & 0xffff;␊ |
| ␉␉␉␉␉cpu->min_ratio = (U32) (idlo >> 8) & 0xff;␊ |
| ␉␉␉␉␉cpu->max_ratio_as_cfg = (U32) (idhi >> 8) & 0xff;␊ |
| ␉␉␉␉␉␊ |
| ␊ |
| #else␊ |
| ␉␉␉␉␉if (Platform.CPU.MaxCoef) ␊ |
| ␉␉␉␉␉{␊ |
|
| ␉␉␉␉␉␉}␊ |
| ␉␉␉␉␉}␊ |
| #endif␊ |
| ␉␉␉␉␉␊ |
| ␊ |
| ␉␉␉␉␉break;␊ |
| ␉␉␉␉} ␊ |
| ␉␉␉␉case CPUID_MODEL_FIELDS:␊ |
|
| ␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
| ␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
| ␉␉␉␉{␉␉␊ |
| ␉␉␉␉␉␊ |
| ␊ |
| ␉␉␉␉␉cpu->core_c1_supported = ((sub_Cstates >> 4) & 0xf) ? 1 : 0;␊ |
| ␉␉␉␉␉cpu->core_c3_supported = ((sub_Cstates >> 8) & 0xf) ? 1 : 0;␊ |
| ␉␉␉␉␉cpu->core_c6_supported = ((sub_Cstates >> 12) & 0xf) ? 1 : 0;␊ |
| ␉␉␉␉␉cpu->core_c7_supported = ((sub_Cstates >> 16) & 0xf) ? 1 : 0;␊ |
| ␉␉␉␉␉cpu->core_c2_supported = 0;␊ |
| ␉␉␉␉␉cpu->core_c4_supported = 0;␊ |
| ␉␉␉␉␉␊ |
| ␊ |
| ␉␉␉␉␉GetMaxRatio(&cpu->max_ratio_as_mfg);␊ |
| U64 platform_info = rdmsr64(MSR_PLATFORM_INFO); ␊ |
| cpu->max_ratio_as_cfg = (U32) ((U32)platform_info >> 8) & 0xff; ␊ |
| ␉␉␉␉␉cpu->min_ratio = (U32) ((platform_info >> 40) & 0xff);␊ |
| ␉␉␉␉␉␊ |
| ␊ |
| cpu->tdc_tdp_limits_for_turbo_flag = (platform_info & (1ULL << 29)) ? 1 : 0;␊ |
| ␉␉␉␉␉cpu->ratio_limits_for_turbo_flag = (platform_info & (1ULL << 28)) ? 1 : 0;␊ |
| ␉␉␉␉␉cpu->xe_available = cpu->tdc_tdp_limits_for_turbo_flag | cpu->ratio_limits_for_turbo_flag;␊ |
| ␉␉␉␉␉␊ |
| ␊ |
| ␊ |
| ␊ |
| ␊ |
| ␉␉␉␉␉if (is_sandybridge() || is_jaketown())␊ |
| ␉␉␉␉␉{␊ |
| ␉␉␉␉␉␉cpu->package_power_limit = rdmsr64(MSR_PKG_RAPL_POWER_LIMIT);␊ |
|
| ␉␉default:␉␉␉␊ |
| ␉␉␉break;␊ |
| ␉}␊ |
| ␊ |
| ␊ |
| ␉cpu->mwait_supported = (extensions & (1UL << 0)) ? 1 : 0;␉␊ |
| ␊ |
| ␉cpu->invariant_apic_timer_flag = (U32)invariant_APIC_timer;␊ |
| ␊ |
| cpu->invariant_apic_timer_flag = (U32)invariant_APIC_timer;␊ |
| ␊ |
| #if DEBUG_ACPI␊ |
| ␉printf("CPU INFO : \n");␊ |
| #if BETA ␊ |
|
| #endif␊ |
| ␉printf("max_ratio_as_cfg : %d\n", cpu->max_ratio_as_cfg);␊ |
| ␉printf("max_ratio_as_mfg : %d\n", cpu->max_ratio_as_mfg);␊ |
| ␊ |
| ␊ |
| ␉printf("turbo_available : %d\n",cpu->turbo_available);␊ |
| ␊ |
| ␊ |
| ␉printf("core_c1_supported : %d\n",cpu->core_c1_supported);␊ |
| ␉printf("core_c2_supported : %d\n",cpu->core_c1_supported);␊ |
| ␉printf("core_c3_supported : %d\n",cpu->core_c3_supported);␊ |
| ␉printf("core_c6_supported : %d\n",cpu->core_c6_supported);␊ |
| ␉printf("core_c7_supported : %d\n",cpu->core_c7_supported);␊ |
| ␉printf("mwait_supported : %d\n",cpu->mwait_supported);␊ |
| ␊ |
| ␊ |
| #if BUILD_ACPI_TSS || pstate_power_support␊ |
| ␉if (is_sandybridge() || is_jaketown())␊ |
| ␉{␊ |
| ␊ |
| ␊ |
| ␉␉printf("package_power_limit : %d\n",cpu->package_power_limit);␊ |
| ␉␉printf("package_power_sku_unit : %d\n",cpu->package_power_sku_unit); ␊ |
| ␊ |
| ␊ |
| ␉}␊ |
| #endif␊ |
| ␉␊ |
| ␊ |
| ␉DBG("invariant_apic_timer_flag : %d\n",cpu->invariant_apic_timer_flag);␊ |
| ␉␊ |
| ␊ |
| ␊ |
| #endif␊ |
| }␊ |
| ␊ |
|
| //-----------------------------------------------------------------------------␊ |
| static U32 BuildPstateInfo(CPU_DETAILS * cpu)␊ |
| {␉␊ |
| ␊ |
| ␉struct p_state p_states[32];␊ |
| ␉U8 p_states_count = 0;␉␊ |
| ␉␊ |
| if (!cpu)␊ |
| {␊ |
| return (0);␊ |
| }␊ |
| ␊ |
| ␊ |
| ␉if (!cpu)␊ |
| ␉{␊ |
| ␉␉return (0);␊ |
| ␉}␊ |
| ␊ |
| ␉{␊ |
| #if UNUSED␊ |
| ␉␉struct p_state initial;␊ |
| #endif␉␊ |
| #endif␊ |
| ␉␉struct p_state maximum, minimum;␊ |
| ␉␉// Retrieving P-States, ported from code by superhai (c)␊ |
| ␉␉switch (Platform.CPU.Family)␊ |
