Chameleon

Chameleon Commit Details

Date:2015-04-23 16:47:08 (4 years 3 months ago)
Author:MacMan
Commit:2658
Parents: 2657
Message:Added Braodwell CPU and IGP support. Useed Chameleon 2.2 r2421 as codebase.
Changes:
A/branches/Chimera/Chimera 4.1.0 Changes.txt
M/branches/Chimera/i386/modules/AcpiCodec/acpi_codec.c
M/branches/Chimera/i386/libsaio/nvidia.c
M/branches/Chimera/i386/boot2/modules.c
M/branches/Chimera/i386/libsaio/stringTable.c
M/branches/Chimera/i386/libsaio/aml_generator.c
M/branches/Chimera/i386/libsaio/pci.h
M/branches/Chimera/i386/libsaio/acpi_patcher.c
M/branches/Chimera/i386/libsaio/bootargs.h
M/branches/Chimera/i386/util/Makefile
M/branches/Chimera/i386/boot2/gui.c
M/branches/Chimera/i386/boot2/modules_support.s
M/branches/Chimera/i386/libsaio/device_inject.c
M/branches/Chimera/i386/libsaio/smbios.c
M/branches/Chimera/i386/boot2/gui.h
M/branches/Chimera/i386/boot2/lzss.c
M/branches/Chimera/i386/boot1/boot1hp.s
M/branches/Chimera/i386/boot1/Makefile
M/branches/Chimera/i386/libsaio/smbios.h
M/branches/Chimera/i386/boot2/picopng.c
M/branches/Chimera/i386/config/confdata.c
M/branches/Chimera/i386/libsaio/console.c
M/branches/Chimera/i386/libsaio/efi.h
M/branches/Chimera/i386/libsaio/vbe.c
M/branches/Chimera/i386/libsaio/device_tree.c
M/branches/Chimera/i386/libsaio/device_tree.h
M/branches/Chimera/i386/libsaio/saio_types.h
M/branches/Chimera/i386/boot0/boot0md.s
M/branches/Chimera/i386/libsaio/spd.c
M/branches/Chimera/i386/libsaio/smbios_getters.c
M/branches/Chimera/i386/libsaio/smbios_getters.h
M/branches/Chimera/i386/libsaio/smbios_decode.c
M/branches/Chimera/i386/boot2/Makefile
M/branches/Chimera/i386/libsaio/gma.c
M/branches/Chimera/i386/boot0/boot0hfs.s
M/branches/Chimera/i386/libsaio/bootstruct.c
M/branches/Chimera/i386/modules/KernelPatcher/Makefile
M/branches/Chimera/i386/libsaio/dram_controllers.c
M/branches/Chimera/i386/libsaio/gma.h
M/branches/Chimera/i386/include/sys/socket.h
M/branches/Chimera/i386/libsaio/bootstruct.h
M/branches/Chimera/i386/libsaio/load.c
M/branches/Chimera/i386/config/textbox.c
M/branches/Chimera/i386/libsaio/platform.c
M/branches/Chimera/i386/boot2/appleClut8.h
M/branches/Chimera/i386/libsaio/platform.h
M/branches/Chimera/i386/libsaio/disk.c
M/branches/Chimera/i386/libsaio/saio_internal.h
M/branches/Chimera/i386/libsaio/hda.c
M/branches/Chimera/i386/klibc/Makefile
M/branches/Chimera/i386/boot2/options.c
M/branches/Chimera/i386/boot2/graphics.c
M/branches/Chimera/i386/libsa/Makefile
M/branches/Chimera/i386/boot2/graphics.h
M/branches/Chimera/i386/libsaio/ati.c
M/branches/Chimera/i386/boot1/boot1h.s
M/branches/Chimera/i386/libsaio/sys.c
M/branches/Chimera/i386/libsaio/ati.h
M/branches/Chimera/i386/boot2/mboot.c
M/branches/Chimera/i386/boot2/prompt.c
M/branches/Chimera/i386/cdboot/Makefile
M/branches/Chimera/i386/libsaio/cpu.c
M/branches/Chimera/i386/libsaio/md5c.c
M/branches/Chimera/i386/libsaio/fake_efi.c
M/branches/Chimera/i386/libsa/zalloc.c
M/branches/Chimera/i386/boot0/Makefile
M/branches/Chimera/i386/boot0/boot0.s

File differences

branches/Chimera/i386/libsaio/smbios_getters.h
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kSMBString,
kSMBByte,
kSMBWord,
kSMBDWord
//kSMBQWord
kSMBDWord,
kSMBQWord
} SMBValueType;
typedef union
uint8_tbyte;
uint16_tword;
uint32_tdword;
//uint64_tqword;
uint64_tqword;
} returnType;
extern bool getProcessorInformationExternalClock(returnType *value);
branches/Chimera/i386/libsaio/console.c
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msgbuf = malloc(BOOTER_LOG_SIZE);
bzero(msgbuf, BOOTER_LOG_SIZE);
cursor = msgbuf;
//msglog("%s\n", "Chimera 4.0.0 Branch of " "Chameleon " I386BOOT_CHAMELEONVERSION " (svn-r" I386BOOT_CHAMELEONREVISION ")" " [" I386BOOT_BUILDDATE "]");
msglog("%s\n", "Chimera 4.0.1 Branch of Chameleon" " [" I386BOOT_BUILDDATE "]");
msglog("%s\n", "Chimera 4.1.0 Branch of Chameleon" " [" I386BOOT_BUILDDATE "]");
}
void msglog(const char * fmt, ...)
// Kabyl: BooterLog
struct putc_info pi;
if (!msgbuf) {
if (!msgbuf)
{
return 0;
}
if (((cursor - msgbuf) > (BOOTER_LOG_SIZE - SAFE_LOG_SIZE))) {
if (((cursor - msgbuf) > (BOOTER_LOG_SIZE - SAFE_LOG_SIZE)))
{
return 0;
}
pi.str = cursor;
// Kabyl: BooterLog
struct putc_info pi;
if (!msgbuf) {
if (!msgbuf)
{
return 0;
}
if (((cursor - msgbuf) > (BOOTER_LOG_SIZE - SAFE_LOG_SIZE))) {
if (((cursor - msgbuf) > (BOOTER_LOG_SIZE - SAFE_LOG_SIZE)))
{
return 0;
}
pi.str = cursor;
branches/Chimera/i386/libsaio/bootstruct.c
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Node *node;
int nameLen;
static int init_done = 0;
if ( !init_done )
{
bootArgs = (boot_args *)malloc(sizeof(boot_args));
bootInfo = (PrivateBootInfo_t *)malloc(sizeof(PrivateBootInfo_t));
if (bootArgs == 0 || bootInfo == 0)
stop("Couldn't allocate boot info\n");
bzero(bootArgs, sizeof(boot_args));
bzero(bootArgsPreLion, sizeof(boot_args_pre_lion));
bzero(bootInfo, sizeof(PrivateBootInfo_t));
// Get system memory map. Also update the size of the
// conventional/extended memory for backwards compatibility.
bootInfo->memoryMapCount =
getMemoryMap( bootInfo->memoryMap, kMemoryMapCountMax,
(unsigned long *) &bootInfo->convmem,
(unsigned long *) &bootInfo->extmem );
if ( bootInfo->memoryMapCount == 0 )
{
// BIOS did not provide a memory map, systems with
// discontiguous memory or unusual memory hole locations
// may have problems.
bootInfo->convmem = getConventionalMemorySize();
bootInfo->extmem = getExtendedMemorySize();
}
bootInfo->configEnd = bootInfo->config;
bootArgs->Video.v_display = VGA_TEXT_MODE;
DT__Initialize();
node = DT__FindNode("/", true);
if (node == 0) {
stop("Couldn't create root node");
nameLen = strlen(platformName) + 1;
DT__AddProperty(node, "compatible", nameLen, platformName);
DT__AddProperty(node, "model", nameLen, platformName);
gMemoryMapNode = DT__FindNode("/chosen/memory-map", true);
bootArgs->Version = kBootArgsVersion;
bootArgs->Revision = kBootArgsRevision;
bootArgsPreLion->Version = kBootArgsPreLionVersion;
bootArgsPreLion->Revision = kBootArgsPreLionRevision;
init_done = 1;
}
}
/* Copy boot args after kernel and record address. */
void
void *oldAddr = bootArgs;
bootArgs = (boot_args *)AllocateKernelMemory(sizeof(boot_args));
bcopy(oldAddr, bootArgs, sizeof(boot_args));
}
else
{
} else {
void *oldAddr = bootArgsPreLion;
bootArgsPreLion = (boot_args_pre_lion *)AllocateKernelMemory(sizeof(boot_args_pre_lion));
bcopy(oldAddr, bootArgsPreLion, sizeof(boot_args_pre_lion));
}
}
void
finalizeBootStruct(void)
//==============================================================================
void finalizeBootStruct(void)
{
uint32_t size;
void *addr;
EfiMemoryRange *memoryMap;
MemoryRange *range;
int memoryMapCount = bootInfo->memoryMapCount;
if (memoryMapCount == 0) {
if (memoryMapCount == 0)
{
// XXX could make a two-part map here
stop("Unable to convert memory map into proper format\n");
}
// convert memory map to boot_args memory map
memoryMap = (EfiMemoryRange *)AllocateKernelMemory(sizeof(EfiMemoryRange) * memoryMapCount);
bootArgs->MemoryMap = (uint32_t)memoryMap;
bootArgs->MemoryMapSize = sizeof(EfiMemoryRange) * memoryMapCount;
bootArgs->MemoryMapDescriptorSize = sizeof(EfiMemoryRange);
bootArgs->MemoryMapDescriptorVersion = 0;
for (i = 0; i < memoryMapCount; i++, memoryMap++) {
for (i = 0; i < memoryMapCount; i++, memoryMap++)
{
range = &bootInfo->memoryMap[i];
switch(range->type) {
switch(range->type)
{
case kMemoryRangeACPI:
memoryMap->Type = kEfiACPIReclaimMemory;
break;
case kMemoryRangeNVS:
memoryMap->Type = kEfiACPIMemoryNVS;
break;
case kMemoryRangeUsable:
memoryMap->Type = kEfiConventionalMemory;
break;
case kMemoryRangeReserved:
default:
memoryMap->Type = kEfiReservedMemoryType;
break;
}
memoryMap->PhysicalStart = range->base;
memoryMap->VirtualStart = range->base;
memoryMap->NumberOfPages = range->length >> I386_PGSHIFT;
// copy bootFile into device tree
// XXX
// add PCI info somehow into device tree
// XXX
// Flatten device tree
DT__FlattenDeviceTree(0, &size);
addr = (void *)AllocateKernelMemory(size);
if (addr == 0) {
if (addr == 0)
{
stop("Couldn't allocate device tree\n");
}
DT__FlattenDeviceTree((void **)&addr, &size);
bootArgs->deviceTreeP = (uint32_t)addr;
bootArgs->deviceTreeLength = size;
// Copy BootArgs values to older structure
memcpy(&bootArgsPreLion->CommandLine, &bootArgs->CommandLine, BOOT_LINE_LENGTH);
memcpy(&bootArgsPreLion->Video, &bootArgs->Video, sizeof(Boot_Video));
bootArgsPreLion->MemoryMap = bootArgs->MemoryMap;
bootArgsPreLion->MemoryMapSize = bootArgs->MemoryMapSize;
bootArgsPreLion->MemoryMapDescriptorSize = bootArgs->MemoryMapDescriptorSize;
bootArgsPreLion->MemoryMapDescriptorVersion = bootArgs->MemoryMapDescriptorVersion;
bootArgsPreLion->deviceTreeP = bootArgs->deviceTreeP;
bootArgsPreLion->deviceTreeLength = bootArgs->deviceTreeLength;
bootArgsPreLion->kaddr = bootArgs->kaddr;
bootArgsPreLion->ksize = bootArgs->ksize;
bootArgsPreLion->efiRuntimeServicesPageStart = bootArgs->efiRuntimeServicesPageStart;
bootArgsPreLion->efiRuntimeServicesPageCount = bootArgs->efiRuntimeServicesPageCount;
bootArgsPreLion->efiSystemTable = bootArgs->efiSystemTable;
bootArgsPreLion->efiMode = bootArgs->efiMode;
bootArgsPreLion->performanceDataStart = bootArgs->performanceDataStart;
bootArgsPreLion->performanceDataSize = bootArgs->performanceDataSize;
bootArgsPreLion->efiRuntimeServicesVirtualPageStart = bootArgs->efiRuntimeServicesVirtualPageStart;
branches/Chimera/i386/libsaio/efi.h
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// range requires a runtime mapping
#define EFI_MEMORY_RUNTIME 0x8000000000000000ULL
#define EFI_MEMORY_KERN_RESERVED (1ULL << 59)
typedef EFI_UINT64 EFI_PHYSICAL_ADDRESS;
typedef EFI_UINT64 EFI_VIRTUAL_ADDRESS;
IN EFI_UINTN DescriptorSize,
IN EFI_UINT32 DescriptorVersion,
IN EFI_MEMORY_DESCRIPTOR * VirtualMap
) __attribute__((regparm(0)));
);
typedef
EFI_RUNTIMESERVICE
(EFIAPI *EFI_CONVERT_POINTER) (
IN EFI_UINTN DebugDisposition,
IN OUT VOID **Address
) __attribute__((regparm(0)));
);
// Variable attributes
OUT EFI_UINT32 * Attributes OPTIONAL,
IN OUT EFI_UINTN * DataSize,
OUT VOID * Data
) __attribute__((regparm(0)));
);
typedef
EFI_RUNTIMESERVICE
IN OUT EFI_UINTN * VariableNameSize,
IN OUT EFI_CHAR16 * VariableName,
IN OUT EFI_GUID * VendorGuid
) __attribute__((regparm(0)));
);
typedef
EFI_RUNTIMESERVICE
IN EFI_UINT32 Attributes,
IN EFI_UINTN DataSize,
IN VOID * Data
) __attribute__((regparm(0)));
);
// EFI Time
(EFIAPI *EFI_GET_TIME) (
OUT EFI_TIME * Time,
OUT EFI_TIME_CAPABILITIES * Capabilities OPTIONAL
) __attribute__((regparm(0)));
);
typedef
EFI_RUNTIMESERVICE
EFI_STATUS
(EFIAPI *EFI_SET_TIME) (
IN EFI_TIME * Time
) __attribute__((regparm(0)));
);
typedef
EFI_RUNTIMESERVICE
OUT EFI_BOOLEAN * Enabled,
OUT EFI_BOOLEAN * Pending,
OUT EFI_TIME * Time
) __attribute__((regparm(0)));
);
typedef
EFI_RUNTIMESERVICE
(EFIAPI *EFI_SET_WAKEUP_TIME) (
IN EFI_BOOLEAN Enable,
IN EFI_TIME * Time OPTIONAL
) __attribute((regparm(0)));
);
typedef enum {
EfiResetCold,
IN EFI_STATUS ResetStatus,
IN EFI_UINTN DataSize,
IN EFI_CHAR16 * ResetData OPTIONAL
) __attribute__((regparm(0)));
);
typedef
EFI_RUNTIMESERVICE
IN EFI_UINT32 Instance,
IN EFI_GUID * CallerId OPTIONAL,
IN EFI_STATUS_CODE_DATA * Data OPTIONAL
) __attribute__((regparm(0)));
);
#endif
//
branches/Chimera/i386/libsaio/vbe.c
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static biosBuf_t bb;
//==============================================================================
#if UNUSED
static inline void
outi (int port, int index, int val)
{
outb (port, index);
outb (port + 1, (inb (port + 1) & ~clear) | set);
}
#endif /* UNUSED */
//==============================================================================
int getVBEInfo( void * infoBlock )
branches/Chimera/i386/libsaio/bootstruct.h
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/*
* Maximum number of boot drivers that can be loaded.
*/
#define NDRIVERS 500
#define NDRIVERS500
#define CONFIG_SIZE (40 * 4096)
unsigned char BIOSPresent;
} PCI_bus_info_t;
typedef struct {
typedef struct
{
unsigned long address; // address where driver was loaded
unsigned long size; // number of bytes
unsigned long type; // driver type
/*
* ACPI defined memory range types.
*/
enum {
enum
{
kMemoryRangeUsable = 1, // RAM usable by the OS.
kMemoryRangeReserved = 2, // Reserved. (Do not use)
kMemoryRangeACPI = 3, // ACPI tables. Can be reclaimed.
branches/Chimera/i386/libsaio/device_tree.c
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}
//==============================================================================
// Bungo
Property *
DT__GetProperty(Node *node, const char *name)
{
Property *prop;
for (prop = node->properties; prop; prop = prop->next)
{
if (strcmp(prop->name, name) == 0)
{
return prop;
}
}
return NULL;
}
//==============================================================================
Node *
DT__FindNode(const char *path, bool createIfMissing)
{
branches/Chimera/i386/libsaio/acpi_patcher.c
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#elif DEBUG_ACPI==1
#define DBG(x...) printf(x)
#else
#define DBG(x...)
#define DBG(x...) msglog(x)
#endif
// Slice: New signature compare function
fd = open(dirSpec, 0);
if (fd < 0) {
// NOT FOUND:
verbose("ACPI Table not found: %s\n", filename);
DBG("ACPI Table not found: %s\n", filename);
*dirSpec = '\0';
}
}
{
if (read (fd, tableAddr, file_size (fd))!=file_size (fd))
{
printf("Couldn't read table %s\n",dirspec);
DBG("Couldn't read table %s\n",dirspec);
free (tableAddr);
close (fd);
return NULL;
return tableAddr;
}
close (fd);
printf("Couldn't allocate memory for table \n", dirspec);
DBG("Couldn't allocate memory for table \n", dirspec);
}
//printf("Couldn't find table %s\n", filename);
return NULL;
{
uint32_t i;
DBG("start finding cpu names. length %d\n", length);
DBG("Start finding cpu names. length %d\n", length);
for (i=0; i<length-7; i++)
{
if (dsdt[i] == 0x5B && dsdt[i+1] == 0x83) // ProcessorOP
{
DBG("dsdt: %x%x\n", dsdt[i], dsdt[i+1]);
DBG("DSDT: %x%x\n", dsdt[i], dsdt[i+1]);
uint32_t offset = i + 3 + (dsdt[i+2] >> 6);
if (!aml_isvalidchar(c))
{
add_name = false;
verbose("Invalid character found in ProcessorOP 0x%x!\n", c);
DBG("Invalid character found in ProcessorOP 0x%x!\n", c);
break;
}
}
if (acpi_cpu_count == 0)
acpi_cpu_p_blk = dsdt[i] | (dsdt[i+1] << 8);
verbose("Found ACPI CPU: %c%c%c%c\n", acpi_cpu_name[acpi_cpu_count][0], acpi_cpu_name[acpi_cpu_count][1], acpi_cpu_name[acpi_cpu_count][2], acpi_cpu_name[acpi_cpu_count][3]);
DBG("Found ACPI CPU: %c%c%c%c\n", acpi_cpu_name[acpi_cpu_count][0], acpi_cpu_name[acpi_cpu_count][1], acpi_cpu_name[acpi_cpu_count][2], acpi_cpu_name[acpi_cpu_count][3]);
if (++acpi_cpu_count == 32) {
return;
}
}
DBG("end finding cpu names: cpu names found: %d\n", acpi_cpu_count);
DBG("End finding cpu names: cpu names found: %d\n", acpi_cpu_count);
}
struct acpi_2_ssdt *generate_cst_ssdt(struct acpi_2_fadt* fadt)
};
if (Platform.CPU.Vendor != 0x756E6547) {
verbose ("Not an Intel platform: C-States will not be generated !!!\n");
DBG("Not an Intel platform: C-States will not be generated !!!\n");
return NULL;
}
if (fadt == NULL) {
verbose ("FACP not exists: C-States will not be generated !!!\n");
DBG("FACP not exists: C-States will not be generated !!!\n");
return NULL;
}
struct acpi_2_dsdt* dsdt = (void*)fadt->DSDT;
if (dsdt == NULL) {
verbose ("DSDT not found: C-States will not be generated !!!\n");
DBG("DSDT not found: C-States will not be generated !!!\n");
return NULL;
}
// dumpPhysAddr("C-States SSDT content: ", ssdt, ssdt->Length);
verbose ("SSDT with CPU C-States generated successfully\n");
DBG("SSDT with CPU C-States generated successfully\n");
return ssdt;
} else {
verbose ("ACPI CPUs not found: C-States not generated !!!\n");
DBG("ACPI CPUs not found: C-States not generated !!!\n");
}
return NULL;
};
if (Platform.CPU.Vendor != 0x756E6547) {
verbose ("Not an Intel platform: P-States will not be generated !!!\n");
DBG("Not an Intel platform: P-States will not be generated !!!\n");
return NULL;
}
if (!(Platform.CPU.Features & CPU_FEATURE_MSR)) {
verbose ("Unsupported CPU: P-States will not be generated !!! No MSR support\n");
DBG("Unsupported CPU: P-States will not be generated !!! No MSR support\n");
return NULL;
}
minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff;
verbose("P-States: min 0x%x, max 0x%x\n", minimum.Control, maximum.Control);
DBG("P-States: min 0x%x, max 0x%x\n", minimum.Control, maximum.Control);
// Sanity check
if (maximum.Control < minimum.Control) {
break;
}
default:
verbose ("Unsupported CPU (0x%X): P-States not generated !!!\n", Platform.CPU.Family);
DBG("Unsupported CPU (0x%X): P-States not generated !!!\n", Platform.CPU.Family);
break;
}
}
//dumpPhysAddr("P-States SSDT content: ", ssdt, ssdt->Length);
verbose ("SSDT with CPU P-States generated successfully\n");
DBG("SSDT with CPU P-States generated successfully\n");
return ssdt;
}
} else {
verbose ("ACPI CPUs not found: P-States not generated !!!\n");
DBG("ACPI CPUs not found: P-States not generated !!!\n");
}
return NULL;
getBoolForKey(kRestartFix, &fix_restart, &bootInfo->chameleonConfig);
}
} else {
verbose ("Not an Intel platform: Restart Fix not applied !!!\n");
DBG("Not an Intel platform: Restart Fix not applied !!!\n");
fix_restart = false;
}
} else {
Platform.Type = 1;/* Set a fixed value (Desktop) */
}
verbose("Error: system-type must be 0..6. Defaulting to %d !\n", Platform.Type);
DBG("Error: system-type must be 0..6. Defaulting to %d !\n", Platform.Type);
} else {
Platform.Type = (unsigned char) strtoul(value, NULL, 10);
}
if (fadt_mod->PM_Profile != Platform.Type) {
if (value) {
// user has overriden the SystemType so take care of it in FACP
verbose("FADT: changing PM_Profile from 0x%02x to 0x%02x\n", fadt_mod->PM_Profile, Platform.Type);
DBG("FADT: changing PM_Profile from 0x%02x to 0x%02x\n", fadt_mod->PM_Profile, Platform.Type);
fadt_mod->PM_Profile = Platform.Type;
} else {
// PM_Profile has a different value and no override has been set, so reflect the user value to ioregs
}
}
// We now have to write the systemm-type in ioregs: we cannot do it before in setupDeviceTree()
// because we need to take care of facp original content, if it is correct.
// because we need to take care of FACP original content, if it is correct.
setupSystemType();
// Patch FADT to fix restart
fadt_mod->Reset_AccessWidth= 0x01; // Byte access
fadt_mod->Reset_Address= 0x64; // Address of the register
fadt_mod->Reset_Value= 0xfe; // Value to write to reset the system
msglog("FADT: PS2 Restart Fix applied!\n");
DBG("FADT: PS2 Restart Fix applied!\n");
} else {
fadt_mod->Flags|= 0x400;
fadt_mod->Reset_SpaceID= 0x01; // System I/O
fadt_mod->Reset_AccessWidth= 0x01; // Byte access
fadt_mod->Reset_Address= 0x0cf9; // Address of the register
fadt_mod->Reset_Value= 0x06; // Value to write to reset the system
verbose("FADT: ACPI Restart Fix applied!\n");
DBG("FADT: ACPI Restart Fix applied!\n");
}
}
DBG("New @%x,%x\n",fadt_mod->DSDT,fadt_mod->X_DSDT);
verbose("FADT: Using custom DSDT!\n");
DBG("FADT: Using custom DSDT!\n");
}
// Correct the checksum
if(acpi20_p) {
addConfigurationTable(&gEfiAcpi20TableGuid, &acpi20_p, "ACPI_20");
} else {
verbose("No ACPI 2.\n");
DBG("No ACPI 2.\n");
}
return 1;
}
int setupAcpi(void)
{
int version;
void *new_dsdt;
void *new_dsdt = NULL;
const char *filename;
// Load replacement DSDT
new_dsdt = loadACPITable(dirSpec);
// Mozodojo: going to patch FACP and load SSDT's even if DSDT.aml is not present
/*if (!new_dsdt)
{
getBoolForKey(kGeneratePStates, &generate_pstates, &bootInfo->chameleonConfig);
getBoolForKey(kGenerateCStates, &generate_cstates, &bootInfo->chameleonConfig);
DBG("Generating P-States config: %d\n", generate_pstates);
DBG("Generating C-States config: %d\n", generate_cstates);
DBG("Generating P-States config: %s\n", generate_pstates ? "YES" : "NO");
DBG("Generating C-States config: %s\n", generate_cstates ? "YES" : "NO");
{
int i;
for (i = 0; i < 30; i++) {
char filename[512];
sprintf(filename, i > 0?"SSDT-%d.aml":"SSDT.aml", i);
sprintf(filename, i > 0 ? "SSDT-%d.aml" : "SSDT.aml", i);
if ( (new_ssdt[ssdt_count] = loadACPITable(filename)) ) {
ssdt_count++;
int rsdplength;
// Find original rsdp
rsdp=(struct acpi_2_rsdp *)(version?getAddressOfAcpi20Table():getAddressOfAcpiTable());
rsdp=(struct acpi_2_rsdp *)(version ? getAddressOfAcpi20Table() : getAddressOfAcpiTable());
if (!rsdp) {
DBG("No ACPI version %d found. Ignoring\n", version+1);
if (version) {
}
continue;
}
rsdplength=version?rsdp->Length:20;
rsdplength=version ? rsdp->Length : 20;
DBG("RSDP version %d found @%x. Length=%d\n",version+1,rsdp,rsdplength);
rsdt_entries[i-dropoffset]=rsdt_entries[i];
if (drop_ssdt && tableSign(table, "SSDT")) {
verbose("OEM SSDT tables was dropped\n");
DBG("OEM SSDT tables was dropped\n");
dropoffset++;
continue;
}
if (tableSign(table, "DSDT")) {
DBG("DSDT found\n");
verbose("Custom DSDT table was found\n");
if(new_dsdt) {
rsdt_entries[i-dropoffset]=(uint32_t)new_dsdt;
}
continue;
}
DBG("FADT found @%x, Length %d\n",fadt, fadt->Length);
if (!fadt || (uint32_t)fadt == 0xffffffff || fadt->Length>0x10000) {
printf("FADT incorrect. Not modified\n");
DBG("FADT incorrect. Not modified\n");
continue;
}
generate_pstates = false; // Generate SSDT only once!
ssdt_count++;
}
continue;
}
}
rsdt_entries=(uint32_t *)(rsdt_mod+1);
// Mozodojo: Insert additional SSDTs into RSDT
if(ssdt_count>0) {
if(ssdt_count > 0) {
int j;
for (j=0; j<ssdt_count; j++) {
rsdt_entries[i-dropoffset+j]=(uint32_t)new_ssdt[j];
}
DBG("RSDT: Added %d SSDT table(s)\n", ssdt_count);
verbose("RSDT: Added %d SSDT table(s)\n", ssdt_count);
}
// Correct the checksum of RSDT
DBG("New checksum %d at %x\n", rsdt_mod->Checksum,rsdt_mod);
} else {
rsdp_mod->RsdtAddress=0;
printf("RSDT not found or RSDT incorrect\n");
DBG("RSDT not found or RSDT incorrect\n");
}
DBG("\n");
if (version) {
struct acpi_2_xsdt *xsdt, *xsdt_mod;
xsdt_entries[i-dropoffset]=xsdt_entries[i];
if (drop_ssdt && tableSign(table, "SSDT")) {
verbose("OEM SSDT tables was dropped\n");
DBG("OEM SSDT tables was dropped\n");
dropoffset++;
continue;
}
if (new_dsdt) {
xsdt_entries[i-dropoffset]=(uint32_t)new_dsdt;
DBG("Custom Table Added\n");
}
DBG("TABLE %c%c%c%c@%x \n", table[0],table[1],table[2],table[3],xsdt_entries[i]);
continue;
}
if (tableSign(table, "FACP")) {
fadt->Length);
if (!fadt || (uint64_t)xsdt_entries[i] >= 0xffffffff || fadt->Length>0x10000) {
verbose("FADT incorrect or after 4GB. Dropping XSDT\n");
DBG("FADT incorrect or after 4GB. Dropping XSDT\n");
goto drop_xsdt;
}
fadt_mod = patch_fadt(fadt, new_dsdt);
xsdt_entries[i-dropoffset]=(uint32_t)fadt_mod;
DBG("TABLE %c%c%c%c@%x \n", table[0],table[1],table[2],table[3],xsdt_entries[i]);
// DBG("TABLE %c%c%c%c@%x \n", table[0],table[1],table[2],table[3],xsdt_entries[i]);
// Generate _CST SSDT
if (generate_cstates && (new_ssdt[ssdt_count] = generate_cst_ssdt(fadt_mod))) {
DBG("C-States generated\n");
generate_cstates = false; // Generate SSDT only once!
ssdt_count++;
}
// Generating _PSS SSDT
if (generate_pstates && (new_ssdt[ssdt_count] = generate_pss_ssdt((void*)fadt_mod->DSDT))) {
DBG("P-States generated\n");
generate_pstates = false; // Generate SSDT only once!
ssdt_count++;
}
continue;
}
DBG("TABLE %c%c%c%c@%x \n", table[0],table[1],table[2],table[3],xsdt_entries[i]);
DBG("copied (OEM)\n");
// DBG("TABLE %c%c%c%c@%x \n", table[0],table[1],table[2],table[3],xsdt_entries[i]);
}
// Allocate xsdt in Kernel memory area
verbose("XSDT not found or XSDT incorrect\n");
}
}
DBG("\n");
// Correct the checksum of RSDP
// Correct the checksum of RSDP
DBG("RSDP: Original checksum %d, ", rsdp_mod->Checksum);
rsdp_mod->Checksum=0;
rsdp_mod->Checksum=256-checksum8(rsdp_mod,20);
DBG("New checksum %d\n", rsdp_mod->Checksum);
if (version) {
DBG("RSDP: Original extended checksum %d", rsdp_mod->ExtendedChecksum);
DBG("RSDP: Original extended checksum %d, ", rsdp_mod->ExtendedChecksum);
rsdp_mod->ExtendedChecksum=0;
rsdp_mod->ExtendedChecksum=256-checksum8(rsdp_mod,rsdp_mod->Length);
DBG("New extended checksum %d\n", rsdp_mod->ExtendedChecksum);
}
//verbose("Patched ACPI version %d DSDT\n", version+1);
if (version) {
/* XXX aserebln why uint32 cast if pointer is uint64 ? */
acpi20_p = (uint64_t)(uint32_t)rsdp_mod;
acpi10_p = (uint64_t)(uint32_t)rsdp_mod;
addConfigurationTable(&gEfiAcpiTableGuid, &acpi10_p, "ACPI");
}
DBG("ACPI version %d patching finished\n\n", version+1);
}
#if DEBUG_ACPI
printf("Press a key to continue... (DEBUG_ACPI)\n");
branches/Chimera/i386/libsaio/device_tree.h
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extern char *
DT__GetName(Node *node);
extern Property *
DT__GetProperty(Node *node, const char *name);
void
DT__Initialize(void);
branches/Chimera/i386/libsaio/bootargs.h
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/* Snapshot constants of previous revisions that are supported */
#define kBootArgsEfiMode3232
#define kBootArgsEfiMode6464
#define kBootArgsEfiMode32 32
#define kBootArgsEfiMode64 64
typedef struct boot_args {
uint16_t Revision;/* Revision of boot_args structure */
uint16_t Version;/* Version of boot_args structure */
uint8_t efiMode; /* 32 = 32-bit, 64 = 64-bit */
uint8_t efiMode; /* 32 means 32-bit mode, 64 means 64-bit mode */
uint8_t debugMode; /* Bit field with behavior changes */
uint8_t __reserved1[2];
uint32_t efiRuntimeServicesPageCount;
uint32_t efiSystemTable; /* physical address of system table in runtime area */
uint8_t efiMode; /* 32 = 32-bit, 64 = 64-bit */
uint8_t efiMode; /* 32 means 32-bit mode, 64 means 64-bit mode */
uint8_t __reserved1[3];
uint32_t __reserved2[1];
uint32_t performanceDataStart; /* physical address of log */
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"RAM", /* 00h Undefined */
"FPM", /* 01h FPM */
"EDO", /* 02h EDO */
"",/* 03h PIPELINE NIBBLE */
"", /* 03h PIPELINE NIBBLE */
"SDRAM", /* 04h SDRAM */
"",/* 05h MULTIPLEXED ROM */
"", /* 05h MULTIPLEXED ROM */
"DDR SGRAM",/* 06h SGRAM DDR */
"DDR SDRAM",/* 07h SDRAM DDR */
"DDR2 SDRAM", /* 08h SDRAM DDR 2 */
"",/* 09h Undefined */
"",/* 0Ah Undefined */
"", /* 09h Undefined */
"", /* 0Ah Undefined */
"DDR3 SDRAM"/* 0Bh SDRAM DDR 3 */
};
static struct smbus_controllers_t smbus_controllers[] = {
{0x8086, 0x1C22, "6 Series", read_smb_intel },
{0x8086, 0x1D22, "C600/X79 Series", read_smb_intel },
{0x8086, 0x1D70, "C600/X79 Series", read_smb_intel },
{0x8086, 0x1D71, "C608/C606/X79 Series", read_smb_intel },
{0x8086, 0x1D72, "C608", read_smb_intel },
{0x8086, 0x1E22, "7 Series/C210 Series", read_smb_intel },
{0x8086, 0x2330, "DH89xxCC", read_smb_intel },
{0x8086, 0x2413, "82801AA", read_smb_intel },
{0x8086, 0x2423, "82801BA/BAM", read_smb_intel },
{0x8086, 0x2443, "82801BA/BAM", read_smb_intel },
{0x8086, 0x2483, "82801CA/CAM", read_smb_intel },
{0x8086, 0x24C3, "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M)", read_smb_intel },
{0x8086, 0x24D3, "82801EB/ER (ICH5/ICH5R)", read_smb_intel },
{0x8086, 0x25A4, "6300ESB", read_smb_intel },
{0x8086, 0x266A, "82801FB/FBM/FR/FW/FRW (ICH6 Family)", read_smb_intel },
{0x8086, 0x269B, "631xESB/632xESB/3100", read_smb_intel },
{0x8086, 0x27DA, "N10/ICH 7 Family", read_smb_intel },
{0x8086, 0x283E, "82801H (ICH8 Family) ", read_smb_intel },
{0x8086, 0x2930, "82801I (ICH9 Family)", read_smb_intel },
{0x8086, 0x3A30, "82801JI (ICH10 Family)", read_smb_intel },
{0x8086, 0x3A60, "82801JD/DO (ICH10 Family)", read_smb_intel },
{0x8086, 0x3B30, "5 Series/3400 Series", read_smb_intel },
{0x8086, 0x5032, "EP80579", read_smb_intel },
{0x8086, 0x8C22, "8 Series/C220", read_smb_intel },
{0x8086, 0x9C22, "Lynx Point-LP", read_smb_intel }
{0x8086, 0x1C22, "6 Series/C200 Series", read_smb_intel },
{0x8086, 0x1C41, "Mobile 6 Series", read_smb_intel },
{0x8086, 0x1C42, "6 Series/C200 Series", read_smb_intel },
{0x8086, 0x1C43, "Mobile 6 Series", read_smb_intel },
{0x8086, 0x1C44, "6 Series", read_smb_intel },
{0x8086, 0x1C46, "6 Series", read_smb_intel },
{0x8086, 0x1C47, "6 Series", read_smb_intel },
{0x8086, 0x1C49, "Mobile 6 Series", read_smb_intel },
{0x8086, 0x1C4A, "6 Series", read_smb_intel },
{0x8086, 0x1C4B, "Mobile 6 Series", read_smb_intel },
{0x8086, 0x1C4C, "6 Series", read_smb_intel },
{0x8086, 0x1C4D, "6 Series", read_smb_intel },
{0x8086, 0x1C4E, "6 Series", read_smb_intel },
{0x8086, 0x1C4F, "Mobile 6 Series", read_smb_intel },
{0x8086, 0x1C50, "6 Series", read_smb_intel },
{0x8086, 0x1C52, "6 Series/C202 Series", read_smb_intel },
{0x8086, 0x1C54, "6 Series/C204 Series", read_smb_intel },
{0x8086, 0x1C56, "6 Series/C206 Series", read_smb_intel },
{0x8086, 0x1C5C, "6 Series", read_smb_intel },
{0x8086, 0x1D22, "C600/X79 Series", read_smb_intel },
{0x8086, 0x1D41, "C600/X79 Series", read_smb_intel },
{0x8086, 0x1D70, "C600/X79 Series", read_smb_intel },
{0x8086, 0x1D71, "C608/C606/X79 series", read_smb_intel },
{0x8086, 0x1D72, "C608", read_smb_intel },
{0x8086, 0x1E22, "7 Series/C210 Series", read_smb_intel },
{0x8086, 0x1E42, "7 Series", read_smb_intel },
{0x8086, 0x1E43, "7 Series", read_smb_intel },
{0x8086, 0x1E44, "7 Series", read_smb_intel },
{0x8086, 0x1E55, "Mobile 7 Series", read_smb_intel },
{0x8086, 0x1E56, "7 Series", read_smb_intel },
{0x8086, 0x1E57, "Mobile 7 Series", read_smb_intel },
{0x8086, 0x1E58, "Mobile 7 Series", read_smb_intel },
{0x8086, 0x1E59, "Mobile 7 Series", read_smb_intel },
{0x8086, 0x1E5D, "Mobile 7 Series", read_smb_intel },
{0x8086, 0x2330, "DH89xxCC", read_smb_intel },
{0x8086, 0x2413, "82801AA", read_smb_intel },
{0x8086, 0x2423, "82801AB", read_smb_intel },
{0x8086, 0x2443, "82801BA/BAM", read_smb_intel },
{0x8086, 0x2483, "82801CA/CAM", read_smb_intel },
{0x8086, 0x24C3, "82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M)", read_smb_intel },
{0x8086, 0x24D3, "82801EB/ER (ICH5/ICH5R)", read_smb_intel },
{0x8086, 0x25A4, "6300ESB", read_smb_intel },
{0x8086, 0x266A, "82801FB/FBM/FR/FW/FRW (ICH6 Family)", read_smb_intel },
{0x8086, 0x2670, "631xESB/632xESB/3100", read_smb_intel },
{0x8086, 0x269B, "631xESB/632xESB/3100", read_smb_intel },
{0x8086, 0x27B9, "82801GBM (ICH7-M)", read_smb_intel },
{0x8086, 0x27BD, "82801GHM (ICH7-M DH)", read_smb_intel },
{0x8086, 0x27DA, "82801GB/GBM/GR/GH/GHM (ICH7 Family)", read_smb_intel },
{0x8086, 0x2811, "82801HEM (ICH8M-E)", read_smb_intel },
{0x8086, 0x2815, "82801HM (ICH8M)", read_smb_intel },
{0x8086, 0x283E, "82801H (ICH8 Family) ", read_smb_intel },
{0x8086, 0x2916, "82801IR (ICH9R)", read_smb_intel },
{0x8086, 0x2930, "82801I (ICH9 Family)", read_smb_intel },
{0x8086, 0x3A18, "82801JIB (ICH10)", read_smb_intel },
{0x8086, 0x3A30, "82801JI (ICH10 Family)", read_smb_intel },
{0x8086, 0x3A60, "82801JD/DO (ICH10 Family)", read_smb_intel },
{0x8086, 0x3B00, "5 Series/3400 Series", read_smb_intel },
{0x8086, 0x3B01, "Mobile 5 Series", read_smb_intel },
{0x8086, 0x3B02, "5 Series", read_smb_intel },
{0x8086, 0x3B09, "Mobile 5 Series", read_smb_intel },
{0x8086, 0x3B30, "5 Series/3400 Series", read_smb_intel },
{0x8086, 0x5032, "EP80579", read_smb_intel },
{0x8086, 0x8119, "6 Series/C200 Series", read_smb_intel },
{0x8086, 0x8119, "US15W", read_smb_intel },
{0x8086, 0x8C22, "8 Series/C220 Series", read_smb_intel },
{0x8086, 0x8C44, "8 Series", read_smb_intel },
{0x8086, 0x8C4B, "Mobile 8 Series", read_smb_intel },
{0x8086, 0x8CA2, "9 Series", read_smb_intel },
{0x8086, 0x8D22, "X99/C610 Series", read_smb_intel },
{0x8086, 0x9C22, "8 Series", read_smb_intel },
{0x8086, 0x9C43, "8 Series", read_smb_intel },
{0x8086, 0x9CC1, "9 Series", read_smb_intel },
{0x8086, 0x9CC2, "9 Series", read_smb_intel },
{0x8086, 0x9CC3, "9 Series", read_smb_intel },
{0x8086, 0x9CC5, "9 Series", read_smb_intel },
{0x8086, 0x9CC6, "9 Series", read_smb_intel },
{0x8086, 0x9CC7, "9 Series", read_smb_intel },
{0x8086, 0x9CC9, "9 Series", read_smb_intel }
};
// initial call : pci_dt = root_pci_dev;
branches/Chimera/i386/libsaio/gma.c
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{GMA_HASWELL_CRW_E_GT1, HD_GRAPHICS }, /* ??? */
{GMA_HASWELL_CRW_E_GT2, HD_GRAPHICS }, /* ??? */
{GMA_HASWELL_CRW_E_GT3, IRIS_5200 },
{GMA_HASWELL_CRW_M_GT2_PLUS_IG, HD_GRAPHICS }
{GMA_HASWELL_CRW_M_GT2_PLUS_IG, HD_GRAPHICS },
/* Brodwell */
{GMA_BRODWELL_BDW_M_GT1,HD_GRAPHICS }, /* 1602 */
{GMA_BRODWELL_BDW_M_GT2,HD_GRAPHICS_5600},/* 1612 */
{GMA_BRODWELL_BDW_M_GT3e,IRIS_Pro_6200}, /* 1622 */
{GMA_BRODWELL_BDW_M_1632,HD_GRAPHICS },/* 1632 */
{GMA_BRODWELL_ULT_M_GT1, HD_GRAPHICS }, /* 1606 */
{GMA_BRODWELL_ULT_M_GT2, HD_GRAPHICS_5500}, /* 1616 */
{GMA_BRODWELL_ULT_M_GT3,HD_GRAPHICS_6000},/* 1626 */
{GMA_BRODWELL_ULT_M_1636,HD_GRAPHICS },/* 1636 */
{GMA_BRODWELL_BDW_S_GT1, HD_GRAPHICS }, /* 160a */
{GMA_BRODWELL_BDW_S_GT2,HD_GRAPHICS },/* 161a */
{GMA_BRODWELL_BDW_S_GT3e,IRIS_Pro_P6300}, /* 162a */
{GMA_BRODWELL_BDW_S_163A,HD_GRAPHICS },/* 163a */
{GMA_BRODWELL_LVT_M_GT1, HD_GRAPHICS }, /* 160b */
{GMA_BRODWELL_LVT_M_GT2, HD_GRAPHICS }, /* 161b */
{GMA_BRODWELL_LVT_M_GT3,IRIS_6100 },/* 162b */
{GMA_BRODWELL_LVT_M_163B,HD_GRAPHICS },/* 163b */
{GMA_BRODWELL_BDW_D_GT1,HD_GRAPHICS }, /* 160d */
{GMA_BRODWELL_BDW_D_GT2,HD_GRAPHICS },/* 161d */
{GMA_BRODWELL_BDW_D_GT3,HD_GRAPHICS },/* 162d */
{GMA_BRODWELL_BDW_D_163D,HD_GRAPHICS },/* 163d */
{GMA_BRODWELL_ULX_M_GT1, HD_GRAPHICS }, /* 160e */
{GMA_BRODWELL_ULX_M_GT2,HD_GRAPHICS_5300},/* 161e */
{GMA_BRODWELL_ULX_M_GT3,HD_GRAPHICS },/* 162e */
{GMA_BRODWELL_ULX_M_163E,HD_GRAPHICS }/* 163e */
};
#define GFX_DEVICES_LEN (sizeof(intel_gfx_chipsets) / sizeof(intel_gfx_chipsets[0]))
uint8_t ig_id_4k_mobile[4] = { 0x03, 0x00, 0x66, 0x01 }; // MacMan
uint8_t ig_id_4600[4] = { 0x03, 0x00, 0x22, 0x0D }; // MacMan
uint8_t ig_id_4600_mobile[4] = { 0x06, 0x00, 0x26, 0x0A }; // MacMan
uint8_t ig_id_5500_mobile[4] = { 0x00, 0x00, 0x16, 0x16 }; // MacMan
uint8_t ig_platform_id[4] = { 0x00, 0x00, 0x00, 0x00 }; // MacMan
devicepath = get_pci_dev_path(gma_dev);
devprop_add_value(device, "AAPL,os-info",HD2000_os_info, 20);
if (getValueForKey(kIGPlatformID, &value, &len, &bootInfo->chameleonConfig)) // MacMan
{
verbose("Setting %s for snb-platform-id\n", value);
verbose("Setting 0x%s for snb-platform-id\n", value);
hex2devprop(value, ig_platform_id, 4);
devprop_add_value(device, "AAPL,snb-platform-id", ig_platform_id, 4);
}
else
{
devprop_add_value(device, "AAPL,snb-platform-id", snb_id_3k, 4);
verbose("Using default snb-platform-id of 00030010\n");
verbose("Using default snb-platform-id of 0x00030010\n");
}
break;
devprop_add_value(device, "AAPL,os-info",HD2000_os_info, 20);
if (getValueForKey(kIGPlatformID, &value, &len, &bootInfo->chameleonConfig)) // MacMan
{
verbose("Setting %s for snb-platform-id\n", value);
verbose("Setting 0x%s for snb-platform-id\n", value);
hex2devprop(value, ig_platform_id, 4);
devprop_add_value(device, "AAPL,snb-platform-id", ig_platform_id, 4);
}
else
{
devprop_add_value(device, "AAPL,snb-platform-id", snb_id_3k_mobile, 4);
verbose("Using default snb-platform-id of 00030010\n");
verbose("Using default snb-platform-id of 0x00030010\n");
}
break;
devprop_add_value(device, "AAPL,os-info",HD3000_os_info, 20);
if (getValueForKey(kIGPDeviceID, &value, &len, &bootInfo->chameleonConfig)) // MacMan
{
verbose("Using %s for unsupported device id injection.\n", value);
verbose("Using 0x%s for unsupported device id injection.\n", value);
hex2devprop(value, igp_device_id, 2);
devprop_add_value(device, "device-id",igp_device_id, 4);
}
else
{
devprop_add_value(device, "device-id", hd3k_kmobile_device_id, 4); // MacMan Inject Mobile ID Instead of Patching Kext
verbose("Using default unsupported device id injection of 0126\n");
verbose("Using default unsupported device id injection of 0x0126\n");
}
if (getValueForKey(kIGPlatformID, &value, &len, &bootInfo->chameleonConfig)) // MacMan
{
verbose("Using %s for snb-platform-id\n", value);
verbose("Using 0x%s for snb-platform-id\n", value);
hex2devprop(value, ig_platform_id, 4);
devprop_add_value(device, "AAPL,snb-platform-id", ig_platform_id, 4);
}
else
{
devprop_add_value(device, "AAPL,snb-platform-id", snb_id_3k, 4);
verbose("Using default snb-platform-id of 00030010\n");
verbose("Using default snb-platform-id of 0x00030010\n");
}
break;
devprop_add_value(device, "AAPL,os-info",HD3000_os_info, 20);
if (getValueForKey(kIGPlatformID, &value, &len, &bootInfo->chameleonConfig)) // MacMan
{
verbose("Setting %s for snb-platform-id\n", value);
verbose("Setting 0x%s for snb-platform-id\n", value);
hex2devprop(value, ig_platform_id, 4);
devprop_add_value(device, "AAPL,snb-platform-id", ig_platform_id, 4);
}
else
{
devprop_add_value(device, "AAPL,snb-platform-id", snb_id_3k_mobile, 4);
verbose("Using default snb-platform-id of 00010000\n");
verbose("Using default snb-platform-id of 0x00010000\n");
}
break;
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
if (getValueForKey(kIGPlatformID, &value, &len, &bootInfo->chameleonConfig)) // MacMan
{
verbose("Using %s for ig-platform-id\n", value);
verbose("Using 0x%s for ig-platform-id\n", value);
hex2devprop(value, ig_platform_id, 4);
devprop_add_value(device, "AAPL,ig-platform-id", ig_platform_id, 4);
}
else
{
devprop_add_value(device, "AAPL,ig-platform-id", ig_id_4k, 4);
verbose("Using default ig-platform-id of 0166000a\n");
verbose("Using default ig-platform-id of 0x0166000a\n");
}
break;
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
if (getValueForKey(kIGPlatformID, &value, &len, &bootInfo->chameleonConfig)) // MacMan
{
verbose("Using %s for ig-platform-id\n", value);
verbose("Using 0x%s for ig-platform-id\n", value);
hex2devprop(value, ig_platform_id, 4);
devprop_add_value(device, "AAPL,ig-platform-id", ig_platform_id, 4);
}
else
{
devprop_add_value(device, "AAPL,ig-platform-id", ig_id_4k_mobile, 4);
verbose("Using default ig-platform-id of 01660003\n");
verbose("Using default ig-platform-id of 0x01660003\n");
}
break;
}
if (getValueForKey(kIGPlatformID, &value, &len, &bootInfo->chameleonConfig))
{
verbose("Using %s for ig-platform-id\n", value);
verbose("Using 0x%s for ig-platform-id\n", value);
hex2devprop(value, ig_platform_id, 4);
devprop_add_value(device, "AAPL,ig-platform-id", ig_platform_id, 4);
}
else
{
devprop_add_value(device, "AAPL,ig-platform-id", ig_id_4k, 4);
verbose("Using default ig-platform-id of 0166000a\n");
verbose("Using default ig-platform-id of 0x0166000a\n");
}
break;
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
if (getValueForKey(kIGPlatformID, &value, &len, &bootInfo->chameleonConfig))
{
verbose("Using %s for ig-platform-id\n", value);
verbose("Using 0x%s for ig-platform-id\n", value);
hex2devprop(value, ig_platform_id, 4);
devprop_add_value(device, "AAPL,ig-platform-id", ig_platform_id, 4);
}
else
{
devprop_add_value(device, "AAPL,ig-platform-id", ig_id_4600, 4);
verbose("Using default ig-platform-id of 0d220003\n");
verbose("Using default ig-platform-id of 0x0d220003\n");
}
break;
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
if (getValueForKey(kIGPlatformID, &value, &len, &bootInfo->chameleonConfig))
{
verbose("Using %s for ig-platform-id\n", value);
verbose("Using 0x%s for ig-platform-id\n", value);
hex2devprop(value, ig_platform_id, 4);
devprop_add_value(device, "AAPL,ig-platform-id", ig_platform_id, 4);
}
else
{
devprop_add_value(device, "AAPL,ig-platform-id", ig_id_4600_mobile, 4);
verbose("Using default ig-platform-id of 0a260006\n");
verbose("Using default ig-platform-id of 0x0a260006\n");
}
break;
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
if (getValueForKey(kIGPDeviceID, &value, &len, &bootInfo->chameleonConfig)) // MacMan
{
verbose("Using %s for unsupported device id injection.\n", value);
verbose("Using 0x%s for unsupported device id injection.\n", value);
hex2devprop(value, igp_device_id, 2);
devprop_add_value(device, "device-id",igp_device_id, 4);
}
else
{
devprop_add_value(device, "device-id", hd4600_device_id, 4); // MacMan Inject Supported ID Instead of Patching Kext
verbose("Using default unsupported device id injection of 0412\n");
verbose("Using default unsupported device id injection of 0x0412\n");
}
if (getValueForKey(kIGPlatformID, &value, &len, &bootInfo->chameleonConfig))
{
verbose("Using %s for ig-platform-id\n", value);
verbose("Using 0x%s for ig-platform-id\n", value);
hex2devprop(value, ig_platform_id, 4);
devprop_add_value(device, "AAPL,ig-platform-id", ig_platform_id, 4);
}
else
{
devprop_add_value(device, "AAPL,ig-platform-id", ig_id_4600, 4);
verbose("Using default ig-platform-id of 0d220003\n");
verbose("Using default ig-platform-id of 0x0d220003\n");
}
break;
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
if (getValueForKey(kIGPDeviceID, &value, &len, &bootInfo->chameleonConfig)) // MacMan
{
verbose("Using %s for unsupported device id injection.\n", value);
verbose("Using 0x%s for unsupported device id injection.\n", value);
hex2devprop(value, igp_device_id, 2);
devprop_add_value(device, "device-id",igp_device_id, 4);
}
}
if (getValueForKey(kIGPlatformID, &value, &len, &bootInfo->chameleonConfig))
{
verbose("Using %s for ig-platform-id\n", value);
verbose("Using 0x%s for ig-platform-id\n", value);
hex2devprop(value, ig_platform_id, 4);
devprop_add_value(device, "AAPL,ig-platform-id", ig_platform_id, 4);
}
else
{
devprop_add_value(device, "AAPL,ig-platform-id", ig_id_4600, 4);
verbose("Using default ig-platform-id of 0d220003\n");
verbose("Using default ig-platform-id of 0x0d220003\n");
}
break;
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
if (getValueForKey(kIGPDeviceID, &value, &len, &bootInfo->chameleonConfig)) // MacMan
{
verbose("Using %s for unsupported device id injection.\n", value);
verbose("Using 0x%s for unsupported device id injection.\n", value);
hex2devprop(value, igp_device_id, 2);
devprop_add_value(device, "device-id",igp_device_id, 4);
}
else
{
devprop_add_value(device, "device-id", hd4600_mobile_device_id, 4); // MacMan Inject Supported ID Instead of Patching Kext
verbose("Using default unsupported device id injection of 0416\n");
verbose("Using default unsupported device id injection of 0x0416\n");
}
if (getValueForKey(kIGPlatformID, &value, &len, &bootInfo->chameleonConfig))
{
verbose("Using %s for ig-platform-id\n", value);
verbose("Using 0x%s for ig-platform-id\n", value);
hex2devprop(value, ig_platform_id, 4);
devprop_add_value(device, "AAPL,ig-platform-id", ig_platform_id, 4);
}
else
{
devprop_add_value(device, "AAPL,ig-platform-id", ig_id_4600_mobile, 4);
verbose("Using default ig-platform-id of 0a260006\n");
verbose("Using default ig-platform-id of 0x0a260006\n");
}
break;
//
// Supported Broadwell Desktop Device IDs
//
//
// Currently none available as of 2015-04-08
//
//
// Supported Broadwell Mobile Device IDs
//
case GMA_BRODWELL_ULT_M_GT1:// HD Graphics ??? found in kext
case GMA_BRODWELL_ULX_M_GT1:// HD Graphics ??? found in kext
case GMA_BRODWELL_BDW_M_GT2:// HD Graphics 5600 and found in kext
case GMA_BRODWELL_ULT_M_GT2:// HD Graphics 5500 and found in kext
case GMA_BRODWELL_ULX_M_GT2:// HD Graphics 5300 and found in kext
case GMA_BRODWELL_ULT_M_GT3:// HD Graphics 6000 and found in kext
case GMA_BRODWELL_BDW_M_GT3e:// Iris Pro 6200 and found in kext
case GMA_BRODWELL_LVT_M_GT3:// Iris 6100 and found in kext
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
devprop_add_value(device, "device-id",(uint8_t*)&device_id, sizeof(device_id));
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
if (getValueForKey(kIGPlatformID, &value, &len, &bootInfo->chameleonConfig))
{
verbose("Using 0x%s for ig-platform-id\n", value);
hex2devprop(value, ig_platform_id, 4);
devprop_add_value(device, "AAPL,ig-platform-id", ig_platform_id, 4);
}
else
{
devprop_add_value(device, "AAPL,ig-platform-id", ig_id_5500_mobile, 4);
verbose("Using default ig-platform-id of 0x16160000\n");
}
break;
default:
break;
branches/Chimera/i386/libsaio/gma.h
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#define HD_GRAPHICS_5000 "HD Graphics 5000"
#define IRIS_5100 "Iris(TM) Graphics 5100"
#define IRIS_5200 "Iris(TM) Pro Graphics 5200"
#define HD_GRAPHICS_5300 "HD Graphics 5300"
#define HD_GRAPHICS_5500 "HD Graphics 5500"
#define HD_GRAPHICS_5600 "HD Graphics 5600"
#define HD_GRAPHICS_6000 "HD Graphics 6000"
#define IRIS_6100 "Iris(TM) Graphics 6100"
#define IRIS_Pro_6200 "Iris(TM) Pro Graphics 6200"
#define IRIS_Pro_P6300 "Iris(TM) Pro P6300"
#define INTEL_VENDORID0x8086
/* http://cgit.freedesktop.org/xorg/driver/xf86-video-intel/tree/src/intel_driver.h */
//#define GMA_VALLEYVIEW_IG GFX_MODEL_CONSTRUCT(INTEL, 0x0F30)
/* ============ Haswell =============== */
// 0090 // AppleIntelHD5000Graphics.kext
// 0091 // AppleIntelHD5000Graphics.kext
// 0092 // AppleIntelHD5000Graphics.kext
//#define GMA_HASWELL_HB GFX_MODEL_CONSTRUCT(INTEL, 0x0400) /* Desktop */
#define GMA_HASWELL_D_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x0402) // HD Graphics
#define GMA_HASWELL_D_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x0412) // HD Graphics 4600 and found in kext
#define GMA_HASWELL_D_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x0422) // HD Graphics 5000
//#define GMA_HASWELL_M_HB GFX_MODEL_CONSTRUCT(INTEL, 0x0404) /* Mobile */
#define GMA_HASWELL_M_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x0406) // HD Graphics Mobile and found in kext
#define GMA_HASWELL_M_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x0416) // HD Graphics 4600 Mobile and found in kext
#define GMA_HASWELL_M_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x0426) // HD Graphics 5000 Mobile and found in kext
#define GMA_HASWELL_S_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x040A) // HD Graphics
//#define GMA_HASWELL_S_HB GFX_MODEL_CONSTRUCT(INTEL, 0x0408) /* Server */
#define GMA_HASWELL_S_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x041A) // HD Graphics
#define GMA_HASWELL_S_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x042A)
#define GMA_HASWELL_B_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x040B)
#define GMA_HASWELL_B_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x041B) // HD Graphics
#define GMA_HASWELL_B_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x042B)
#define GMA_HASWELL_E_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x040E)
#define GMA_HASWELL_E_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x041E) // HD Graphics 4400
#define GMA_HASWELL_E_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x042E)
#define GMA_HASWELL_ULT_D_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x0A02)
#define GMA_HASWELL_ULT_D_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x0A12)
#define GMA_HASWELL_ULT_D_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x0A22) // HD Graphics 5000 Iris
#define GMA_HASWELL_ULT_D_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x0A22) // HD Graphics 5000 Iris
#define GMA_HASWELL_ULT_M_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x0A06) // HD Graphics
#define GMA_HASWELL_ULT_M_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x0A16) // HD Graphics 4400 Mobile and found in kext
#define GMA_HASWELL_ULT_M_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x0A26) // HD Graphics 5000 Iris Mobile and found in kext
#define GMA_HASWELL_ULT_S_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x0A0A)
#define GMA_HASWELL_ULT_S_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x0A1A)
#define GMA_HASWELL_ULT_S_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x0A2A)
#define GMA_HASWELL_ULT_B_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x0A0B)
#define GMA_HASWELL_ULT_B_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x0A1B)
#define GMA_HASWELL_ULT_B_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x0A2B)
#define GMA_HASWELL_ULT_E_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x0A0E) // HD Graphics
#define GMA_HASWELL_ULT_E_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x0A1E) // HD Graphics 4200 Mobile and found in kext
#define GMA_HASWELL_ULT_E_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x0A2E) // HD Graphics 5100 Iris Mobile and found in kext
#define GMA_HASWELL_CRW_D_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x0D02)
#define GMA_HASWELL_CRW_D_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x0D12) // HD Graphics
#define GMA_HASWELL_CRW_D_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x0D22) // HD Graphics 5200 Iris Pro and found in kext
//#define GMA_HASWELL_CRW_D_GT2_PLUS_IGGFX_MODEL_CONSTRUCT(INTEL, 0x0D32)
#define GMA_HASWELL_CRW_D_GT2_PLUS_IGGFX_MODEL_CONSTRUCT(INTEL, 0x0D32)
#define GMA_HASWELL_CRW_M_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x0D06)
#define GMA_HASWELL_CRW_M_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x0D16) // HD Graphics 4600 Mobile
#define GMA_HASWELL_CRW_M_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x0D26) // HD Graphics 5200 Iris Pro Mobile and found in kext
#define GMA_HASWELL_CRW_M_GT2_PLUS_IG GFX_MODEL_CONSTRUCT(INTEL, 0x0D36)
#define GMA_HASWELL_CRW_S_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x0D0A)
#define GMA_HASWELL_CRW_S_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x0D1A)
#define GMA_HASWELL_CRW_S_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x0D2A) // HD Graphics Iris Pro
#define GMA_HASWELL_CRW_S_GT2_PLUS_IG GFX_MODEL_CONSTRUCT(INTEL, 0x0D3A)
#define GMA_HASWELL_CRW_B_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x0D0B)
#define GMA_HASWELL_CRW_B_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x0D1B)
#define GMA_HASWELL_CRW_B_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x0D2B)
#define GMA_HASWELL_CRW_E_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x0D0E)
#define GMA_HASWELL_CRW_E_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x0D1E)
#define GMA_HASWELL_CRW_E_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x0D2E)
#define GMA_HASWELL_CRW_M_GT2_PLUS_IG GFX_MODEL_CONSTRUCT(INTEL, 0x0D36)
//#define GMA_HASWELL_CRW_S_GT2_PLUS_IG GFX_MODEL_CONSTRUCT(INTEL, 0x0D3A)
/* Brodwell */
#define GMA_BRODWELL_BDW_M_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x1602)
#define GMA_BRODWELL_BDW_M_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x1612) // HD Graphics 5600 and found in kext
#define GMA_BRODWELL_BDW_M_GT3e GFX_MODEL_CONSTRUCT(INTEL, 0x1622) // Iris Pro 6200 and found in kext
#define GMA_BRODWELL_BDW_M_1632 GFX_MODEL_CONSTRUCT(INTEL, 0x1632)
#define GMA_BRODWELL_ULT_M_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x1606) // HD Graphics and found in kext
#define GMA_BRODWELL_ULT_M_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x1616) // HD Graphics 5500 and found in kext
#define GMA_BRODWELL_ULT_M_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x1626) // HD Graphics 6000 and found in kext
#define GMA_BRODWELL_ULT_M_1636 GFX_MODEL_CONSTRUCT(INTEL, 0x1636)
#define GMA_BRODWELL_BDW_S_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x160A)
#define GMA_BRODWELL_BDW_S_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x161A)
#define GMA_BRODWELL_BDW_S_GT3e GFX_MODEL_CONSTRUCT(INTEL, 0x162A) // Iris Pro P6300
#define GMA_BRODWELL_BDW_S_163A GFX_MODEL_CONSTRUCT(INTEL, 0x163A)
#define GMA_BRODWELL_LVT_M_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x160B)
#define GMA_BRODWELL_LVT_M_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x161B)
#define GMA_BRODWELL_LVT_M_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x162B) // Iris 6100 and found in kext
#define GMA_BRODWELL_LVT_M_163B GFX_MODEL_CONSTRUCT(INTEL, 0x163B)
#define GMA_BRODWELL_BDW_D_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x160D)
#define GMA_BRODWELL_BDW_D_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x161D)
#define GMA_BRODWELL_BDW_D_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x162D)
#define GMA_BRODWELL_BDW_D_163D GFX_MODEL_CONSTRUCT(INTEL, 0x163D)
#define GMA_BRODWELL_ULX_M_GT1 GFX_MODEL_CONSTRUCT(INTEL, 0x160E) // HD Graphics and found in kext
#define GMA_BRODWELL_ULX_M_GT2 GFX_MODEL_CONSTRUCT(INTEL, 0x161E) // HD Graphics 5300 and found in kext
#define GMA_BRODWELL_ULX_M_GT3 GFX_MODEL_CONSTRUCT(INTEL, 0x162E)
#define GMA_BRODWELL_ULX_M_163E GFX_MODEL_CONSTRUCT(INTEL, 0x163E)
/* END */
#endif /* !__LIBSAIO_GMA_H */
branches/Chimera/i386/libsaio/aml_generator.c
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{
AML_CHUNK* next = child->Next;
if (child->Buffer) {
if (child->Buffer)
{
free(child->Buffer);
}
free(child);
}
// Free node
if (node->Buffer) {
if (node->Buffer)
{
free(node->Buffer);
}
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
node->Type = AML_CHUNK_NONE;
node->Length = (uint16_t)size;
node->Buffer = malloc(node->Length);
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
node->Type = AML_CHUNK_BYTE;
node->Length = 1;
node->Buffer = malloc(node->Length);
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
node->Type = AML_CHUNK_WORD;
node->Length = 2;
node->Buffer = malloc(node->Length);
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
node->Type = AML_CHUNK_DWORD;
node->Length = 4;
node->Buffer = malloc(node->Length);
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
node->Type = AML_CHUNK_QWORD;
node->Length = 8;
node->Buffer = malloc(node->Length);
uint32_t aml_fill_simple_name(char* buffer, char* name)
{
if (strlen(name) < 4) {
if (strlen(name) < 4)
{
verbose("aml_fill_simple_name: simple name %s has incorrect lengh! Must be 4.\n", name);
return 0;
}
int len, offset, count;
uint32_t root = 0;
if (!node) {
if (!node)
{
return 0;
}
offset = 0;
count = len >> 2;
if ((len % 4) > 1 || count == 0) {
if ((len % 4) > 1 || count == 0)
{
verbose("aml_fill_name: pathname %s has incorrect length! Must be 4, 8, 12, 16, etc...\n", name);
return 0;
}
if (((len % 4) == 1) && (name[0] == '\\')) {
if (((len % 4) == 1) && (name[0] == '\\'))
{
root++;
}
if (count == 1) {
if (count == 1)
{
node->Length = (uint16_t)(4 + root);
node->Buffer = malloc(node->Length+4);
memcpy(node->Buffer, name, 4 + root);
return (uint32_t)offset;
}
if (count == 2) {
if (count == 2)
{
node->Length = 2 + 8;
node->Buffer = malloc(node->Length+4);
node->Buffer[offset++] = 0x5c; // Root Char
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
node->Type = AML_CHUNK_SCOPE;
aml_fill_name(node, name);
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
node->Type = AML_CHUNK_NAME;
aml_fill_name(node, name);
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
unsigned int offset = aml_fill_name(node, name);
node->Type = AML_CHUNK_METHOD;
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
node->Type = AML_CHUNK_PACKAGE;
node->Length = 1;
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
node->Type = AML_CHUNK_ALIAS;
node->Length = 8;
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
node->Type = AML_CHUNK_RETURN;
aml_fill_name(node, name);
}
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
node->Type = AML_CHUNK_RETURN;
aml_add_byte(node, value);
}
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
node->Type = AML_CHUNK_DEVICE;
aml_fill_name(node, name);
}
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
node->Type = AML_CHUNK_LOCAL0;
node->Length = 1;
}
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
node->Type = AML_STORE_OP;
node->Length = 1;
}
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
int offset = 0;
node->Type = AML_CHUNK_BUFFER;
node->Length = (uint8_t)(size + 2);
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
unsigned int offset = 0;
unsigned int len = strlen(StringBuf);
node->Type = AML_CHUNK_BUFFER;
node->Length = (uint8_t)(len + 3);
node->Buffer = malloc (node->Length);
node->Buffer[offset++] = AML_CHUNK_BYTE;
node->Buffer[offset++] = (char)len;
node->Buffer[offset++] = (char)(len+1);
memcpy(node->Buffer+offset, StringBuf, len);
node->Buffer[offset+len] = '\0';
//node->Buffer[offset+len] = '\0';
}
return node;
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
int len = strlen(StringBuf);
node->Type = AML_CHUNK_STRING;
node->Length = (uint8_t)(len + 1);
node->Buffer = malloc (len);
node->Buffer = malloc (len+1);
memcpy(node->Buffer, StringBuf, len);
node->Buffer[len] = '\0';
//node->Buffer[len] = '\0';
}
return node;
{
AML_CHUNK* node = aml_create_node(parent);
if (node) {
if (node)
{
node->Type = AML_CHUNK_RETURN;
//aml_add_byte(node, value);
}
uint32_t aml_calculate_size(AML_CHUNK* node)
{
if (node) {
if (node)
{
// Calculate child nodes size
AML_CHUNK* child = node->First;
uint8_t child_count = 0;
node->Size = 0;
while (child) {
while (child)
{
child_count++;
node->Size += (uint16_t)aml_calculate_size(child);
child = child->Next;
}
switch (node->Type) {
switch (node->Type)
{
case AML_CHUNK_NONE:
case AML_STORE_OP:
case AML_CHUNK_LOCAL0:
break;
case AML_CHUNK_BYTE:
if (node->Buffer[0] == 0x0 || node->Buffer[0] == 0x1) {
if (node->Buffer[0] == 0x0 || node->Buffer[0] == 0x1)
{
node->Size += node->Length;
} else {
node->Size += 1 + node->Length;
uint32_t aml_write_buffer(const char* value, uint32_t size, char* buffer, uint32_t offset)
{
if (size > 0) {
if (size > 0)
{
memcpy(buffer + offset, value, size);
}
uint32_t aml_write_size(uint32_t size, char* buffer, uint32_t offset)
{
if (size <= 0x3f) { /* simple 1 byte length in 6 bits */
if (size <= 0x3f) /* simple 1 byte length in 6 bits */
{
buffer[offset++] = (char)size;
} else if (size <= 0xfff) {
buffer[offset++] = 0x40 | (size & 0xf); /* 0x40 is type, 0x0X is first nibble of length */
uint32_t aml_write_node(AML_CHUNK* node, char* buffer, uint32_t offset)
{
if (node && buffer) {
if (node && buffer)
{
uint32_t old = offset;
AML_CHUNK* child = node->First;
switch (node->Type) {
switch (node->Type)
{
case AML_CHUNK_NONE:
offset = aml_write_buffer(node->Buffer, node->Length, buffer, offset);
break;
branches/Chimera/i386/libsaio/device_inject.c
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#if DEBUG_INJECT
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#define DBG(x...)msglog(x)
#endif
uint32_t devices_number = 1;
return 1;
}
// devprop_generate_string optimized by cparm
char *devprop_generate_string(DevPropString *string)
{
char *buffer = (char*)malloc(string->length * 2);
int len = string->length * 2;
char *buffer = (char*)malloc(len);
char *ptr = buffer;
if(!buffer)
return NULL;
}
sprintf(buffer, "%08x%08x%04x%04x", dp_swap32(string->length), string->WHAT2,
snprintf(buffer, len, "%08x%08x%04x%04x", dp_swap32(string->length), string->WHAT2,
dp_swap16(string->numentries), string->WHAT3);
buffer += 24;
len -= 24;
int i = 0, x = 0;
while(i < string->numentries)
{
sprintf(buffer, "%08x%04x%04x", dp_swap32(string->entries[i]->length),
if (!(i < DEV_PROP_DEVICE_MAX_ENTRIES)) {
break;
}
if(!len) {
break;
}
snprintf(buffer, len, "%08x%04x%04x", dp_swap32(string->entries[i]->length),
dp_swap16(string->entries[i]->numentries), string->entries[i]->WHAT2);
buffer += 16;
sprintf(buffer, "%02x%02x%04x%08x%08x", string->entries[i]->acpi_dev_path.type,
len -= 16;
snprintf(buffer, len, "%02x%02x%04x%08x%08x", string->entries[i]->acpi_dev_path.type,
string->entries[i]->acpi_dev_path.subtype,
dp_swap16(string->entries[i]->acpi_dev_path.length),
string->entries[i]->acpi_dev_path._HID,
dp_swap32(string->entries[i]->acpi_dev_path._UID));
buffer += 24;
len -= 24;
for(x = 0;x < string->entries[i]->num_pci_devpaths; x++)
{
sprintf(buffer, "%02x%02x%04x%02x%02x", string->entries[i]->pci_dev_path[x].type,
if(!len) {
break;
}
snprintf(buffer, len, "%02x%02x%04x%02x%02x", string->entries[i]->pci_dev_path[x].type,
string->entries[i]->pci_dev_path[x].subtype,
dp_swap16(string->entries[i]->pci_dev_path[x].length),
string->entries[i]->pci_dev_path[x].function,
string->entries[i]->pci_dev_path[x].device);
buffer += 12;
len -= 12;
}
sprintf(buffer, "%02x%02x%04x", string->entries[i]->path_end.type,
if(!len) {
break;
}
snprintf(buffer, len, "%02x%02x%04x", string->entries[i]->path_end.type,
string->entries[i]->path_end.subtype,
dp_swap16(string->entries[i]->path_end.length));
buffer += 8;
len -= 8;
uint8_t *dataptr = string->entries[i]->data;
for(x = 0; (uint32_t)x < (string->entries[i]->length) - (24 + (6 * string->entries[i]->num_pci_devpaths)) ; x++)
{
sprintf(buffer, "%02x", *dataptr++);
buffer += 2;
if(!len) {
break;
}
snprintf(buffer, len, "%02x", *dataptr++);
buffer += 2;
len -= 2;
}
i++;
}
branches/Chimera/i386/libsaio/hda.c
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{ HDA_INTEL_PCH2, "5 Series/3400 Series" },
{ HDA_INTEL_SCH, "System Controller Hub (SCH Poulsbo)" },
{ HDA_INTEL_SCH2, "9 Series" },
{ HDA_INTEL_LPT1, "Lynx Point" },
{ HDA_INTEL_LPT2, "Lynx Point" },
{ HDA_INTEL_LPT1, "Wellsburg" },
{ HDA_INTEL_LPT2, "Wellsburg" },
{ HDA_INTEL_LYNX, "Lynx Point-LP" },
{ HDA_INTEL_LYNX2, "Lynx Point-LP" },
//10de NVIDIA Corporation
branches/Chimera/i386/libsaio/dram_controllers.c
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{ 0x8086, 0x29C0, "82G33/G31/P35/P31",setup_p35, get_fsb_i965,get_timings_p35},
{ 0x8086, 0x29D0, "82Q33 Express",setup_p35, get_fsb_i965,get_timings_p35},
{ 0x8086, 0x29E0, "82X38/X48 Express",setup_p35, get_fsb_i965,get_timings_p35},
//{ 0x8086, 0x29F0, "3200/3210 Chipset",NULL, NULL, NULL },
{ 0x8086, 0x29F0, "3200/3210",setup_p35, get_fsb_i965,get_timings_p35},
{ 0x8086, 0x2E00, "Eaglelake",setup_p35, get_fsb_i965,get_timings_p35},
{ 0x8086, 0x2E10, "Q45/Q43",setup_p35, get_fsb_i965,get_timings_p35},
branches/Chimera/i386/libsaio/nvidia.c
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......
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{ 0x10DE0FC1,"NVIDIA GeForce GT 640" },
{ 0x10DE0FC2,"NVIDIA GeForce GT 630" },
{ 0x10DE0FC6,"NVIDIA GeForce GTX 650" },
{ 0x10DE0FC8,"NVIDIA GeForce GT 740" },
{ 0x10DE0FCD,"NVIDIA GeForce GT 755M" },
{ 0x10DE0FCE,"NVIDIA GeForce GT 640M LE" },
// 0FD0 - 0FDF
{ 0x10DE0FD1,"NVIDIA GeForce GT 650M" },
{ 0x10DE0FD2,"NVIDIA GeForce GT 640M" },
{ 0x10DE0FD5,"NVIDIA GeForce GT 650M" },
{ 0x10DE0FD8,"NVIDIA GeForce GT 640M" },
{ 0x10DE0FD9,"NVIDIA GeForce GT 645M" },
{ 0x10DE0FDA,"GK107-ES-A1" },
{ 0x10DE0FDB,"GK107-ESP-A1" },
{ 0x10DE0FDC,"GK107-INT22-A1" },
{ 0x10DE0FDF,"NVIDIA GeForce GT 740M" },
// 0FE0 - 0FEF
{ 0x10DE0FE0,"NVIDIA GeForce GTX 660M" },
{ 0x10DE0FE1,"NVIDIA GeForce GT 730M" },
{ 0x10DE0FE3,"NVIDIA GeForce GT 745M" },
{ 0x10DE0FE4,"NVIDIA GeForce GT 750M" },
{ 0x10DE0FE5,"NVIDIA GeForce K340 USM" },
{ 0x10DE0FE6,"NVS K1 USM" },
{ 0x10DE0FE7,"Generic K1 USM / GRID K100" },
{ 0x10DE0FE9,"NVIDIA GeForce GT 750M" },
{ 0x10DE0FEA,"NVIDIA GeForce GT 755M" },
{ 0x10DE0FEF,"GRID K340" },
// 0FF0 - 0FFF
{ 0x10DE0FF0,"NB1Q" },
{ 0x10DE0FF1,"NVS 1000" },
{ 0x10DE0FF2,"VGX K1" },
{ 0x10DE0FF3,"NVIDIA Quadro K420" },
{ 0x10DE0FF5,"Tesla K1 USM" },
{ 0x10DE0FF6,"NVIDIA Quadro K1100M" },
{ 0x10DE0FF7,"NVIDIA Quadro K1 USM" }, // K1 USM / GRID K120Q / GRID K140Q
{ 0x10DE0FF8,"NVIDIA Quadro K500M" },
{ 0x10DE0FF9,"NVIDIA Quadro K2000D" },
{ 0x10DE0FFA,"NVIDIA Quadro K600" },
{ 0x10DE0FFE,"NVIDIA Quadro K2000" },
{ 0x10DE0FFF,"NVIDIA Quadro 410" },
// 1000 - 100F
{ 0x10DE1001,"NVIDIA GeForce GTX TITAN Z" },
{ 0x10DE1003,"NVIDIA GeForce GTX Titan LE" },
{ 0x10DE1004,"NVIDIA GeForce GTX 780" },
{ 0x10DE1005,"NVIDIA GeForce GTX Titan" },
{ 0x10DE1006,"NVIDIA GeForce GTX 780 Ti" },
{ 0x10DE1007,"NVIDIA GeForce GTX 780" },
{ 0x10DE1008,"NVIDIA GeForce GTX 780 Ti" },
{ 0x10DE100A,"NVIDIA GeForce GTX 780 Ti" },
//{ 0x10DE100B,"Graphics Device" }, // GK110
{ 0x10DE100C,"GeForce GTX Titan Black" },
// 1010 - 101F
{ 0x10DE101E,"Tesla K20X" }, // GK110GL
{ 0x10DE101F,"NVIDIA Tesla K20" },
// 1020 - 102F
{ 0x10DE1020,"NVIDIA Tesla K20X" },
{ 0x10DE1022,"NVIDIA Tesla K20c" },
{ 0x10DE1026,"NVIDIA Tesla K20s" },
{ 0x10DE1028,"NVIDIA Tesla K20m" },
{ 0x10DE102A,"NVIDIA Tesla K40t" }, // GK110BGL
//{ 0x10DE102B,"Graphics Device" }, // GK110BGL
//{ 0x10DE102C,"Graphics Device" }, // GK110BGL
{ 0x10DE102D,"NVIDIA Tesla K80" }, // GK110BGL (2x)
{ 0x10DE102E,"NVIDIA Tesla K40d" }, // GK110BGL
{ 0x10DE102F,"TNVIDIA Tesla Stella Solo" }, // GK110BGL
// 1030 - 103F
//{ 0x10DE1030,"" }, // GK110
{ 0x10DE103F,"NVIDIA Tesla Stella SXM" }, // GK110
// 1040 - 104F
{ 0x10DE1040,"NVIDIA GeForce GT 520" },
// { 0x10DE1041,"D13M1-45" },
{ 0x10DE1049,"NVIDIA GeForce GT 620" },
{ 0x10DE104A,"NVIDIA GeForce GT 610" },
{ 0x10DE104B,"NVIDIA GeForce GT 625 (OEM)" },
{ 0x10DE104C,"NVIDIA GeForce GT 705" }, // GF119
{ 0x10DE104D,"NVIDIA GeForce GT 710" }, // GF119
// 1050 - 105F
{ 0x10DE1050,"NVIDIA GeForce GT 520M" },
{ 0x10DE1051,"NVIDIA GeForce GT 520MX" },
{ 0x10DE1140,"NVIDIA GeForce GT 610M" },
{ 0x10DE1141,"NVIDIA GeForce 610M" },
{ 0x10DE1142,"NVIDIA GeForce 620M" },
// { 0x10DE1143,"N13P-GV" },
// { 0x10DE1144,"GF117" },
// { 0x10DE1145,"GF117" },
// { 0x10DE1146,"GF117" },
// { 0x10DE1147,"GF117" },
{ 0x10DE1143,"N13P-GV" },
{ 0x10DE1144,"GF117" },
{ 0x10DE1145,"GF117" },
{ 0x10DE1146,"GF117" },
{ 0x10DE1147,"GF117" },
{ 0x10DE1149,"GF117-ES" },
// { 0x10DE114A,"GF117-INT" },
// { 0x10DE114B,"PCI-GEN3-B" },
{ 0x10DE114A,"GF117-INT" },
{ 0x10DE114B,"PCI-GEN3-B" },
// 1150 - 115F
// 1160 - 116F
// 1170 - 117F
{ 0x10DE118E,"NVIDIA GeForce GTX 760 (192-bit)" },
{ 0x10DE118F,"NVIDIA Tesla K10" },
// 1190 - 119F
{ 0x10DE1191,"NVIDIA GeForce GTX 760" }, // GK104
{ 0x10DE1192,"NVIDIA GeForce GK104" },
{ 0x10DE1193,"NVIDIA GeForce GTX 760 Ti" },
{ 0x10DE1194,"NVIDIA Tesla K8" }, // GK104
{ 0x10DE1195,"NVIDIA GeForce GTX 660" },
{ 0x10DE1198,"NVIDIA GeForce GTX 880M" },
{ 0x10DE1199,"NVIDIA GeForce GTX 870M" },
{ 0x10DE119a,"NVIDIA GeForce GTX 860M" },
{ 0x10DE119d,"NVIDIA GeForce GTX 775M" }, // Mac Edition
{ 0x10DE119e,"NVIDIA GeForce GTX 780M" }, // Mac Edition
{ 0x10DE119A,"NVIDIA GeForce GTX 860M" },
{ 0x10DE119D,"NVIDIA GeForce GTX 775M" }, // Mac Edition
{ 0x10DE119E,"NVIDIA GeForce GTX 780M" }, // Mac Edition
{ 0x10DE119F,"NVIDIA GeForce GTX 780M" },
// 11A0 - 11AF
{ 0x10DE11A0,"NVIDIA GeForce GTX 680M" },
{ 0x10DE11A2,"NVIDIA GeForce GTX 675MX" }, // Mac Edition
{ 0x10DE11A3,"NVIDIA GeForce GTX 680MX" },
{ 0x10DE11A7,"NVIDIA GeForce GTX 675MX" },
{ 0x10DE11AF,"GRID IceCube" }, // GF104M
// 11B0 - 11BF
{ 0x10DE11B0,"GRID K240Q" }, // K260Q vGPU
{ 0x10DE11B1,"GRID K2 Tesla USM" },
{ 0x10DE11B4,"NVIDIA Quadro K4200" },
{ 0x10DE11B6,"NVIDIA Quadro K3100M" },
{ 0x10DE11B6,"NVIDIA Quadro K3100M" },
{ 0x10DE11B7,"NVIDIA Quadro K4100M" },
{ 0x10DE11B8,"NVIDIA Quadro K5100M" },
{ 0x10DE11D0,"GK106-INT353" },
// 11E0 - 11EF
{ 0x10DE11E0,"NVIDIA GeForce GTX 770M" },
{ 0x10DE11E1,"N14E-GE-B-A1" },
{ 0x10DE11E1,"NVIDIA GeForce GTX 765M" },
{ 0x10DE11E2,"NVIDIA GeForce GTX 765M" },
{ 0x10DE11E3,"NVIDIA GeForce GTX 760M" },
// 11F0 - 11FF
{ 0x10DE11FA,"NVIDIA Quadro K4000" },
{ 0x10DE11FC,"NVIDIA Quadro 2100M" },
{ 0x10DE11FF,"NB1Q" }, //
// 1200 - 120F
{ 0x10DE1200,"NVIDIA GeForce GTX 560 Ti" },
{ 0x10DE1201,"NVIDIA GeForce GTX 560" },
{ 0x10DE1281,"NVIDIA GeForce GT 710" },
{ 0x10DE1282,"NVIDIA GeForce GT 640" },
{ 0x10DE1284,"NVIDIA GeForce GT 630" },
{ 0x10DE1286,"NVIDIA GeForce GT 720" },
{ 0x10DE1287,"NVIDIA GeForce GT 730" }, // GK208
// 1290 - 129F
{ 0x10DE1290,"NVIDIA GeForce GT 730M" },
{ 0x10DE1291,"NVIDIA GeForce GT 735M" },
// 12D0 - 12DF
// 12E0 - 12EF
// 12F0 - 12FF
{ 0x10DE1340,"NVIDIA GeForce 830M" },
{ 0x10DE1341,"NVIDIA GeForce 840M" },
{ 0x10DE1380,"NVIDIA GeForce GTX 750 Ti" },
{ 0x10DE1381,"NVIDIA GeForce GTX 750" },
{ 0x10DE1390,"NVIDIA GeForce 845M" },
{ 0x10DE1391,"NVIDIA GeForce GTX 850M" },
{ 0x10DE1392,"NVIDIA GeForce GTX 860M" },
{ 0x10DE1393,"NVIDIA GeForce 840M" }
{ 0x10DE1340,"NVIDIA GeForce 830M" },
{ 0x10DE1341,"NVIDIA GeForce 840M" },
{ 0x10DE1380,"NVIDIA GeForce GTX 750 Ti" },
{ 0x10DE1381,"NVIDIA GeForce GTX 750" },
{ 0x10DE1382,"NVIDIA GeForce GTX 745" },
//{ 0x10DE1383,"Graphics Device" }, // GM107
{ 0x10DE1389,"GRID M3" }, // GM107
{ 0x10DE1390,"NVIDIA GeForce 845M" },
{ 0x10DE1391,"NVIDIA GeForce GTX 850M" },
{ 0x10DE1392,"NVIDIA GeForce GTX 860M" },
{ 0x10DE1393,"NVIDIA GeForce 840M" },
{ 0x10DE1398,"NVIDIA GeForce N15S-GT1R" }, //
{ 0x10DE13AD,"GM107 INT52" }, //
{ 0x10DE13AE,"GM107 CS1" }, //
//{ 0x10DE13AF,"Graphics Device" }, // GM107GLM
{ 0x10DE13B3,"NVIDIA Quadro K2200M" }, //
{ 0x10DE13BA,"NVIDIA Quadro K2200" },
{ 0x10DE13BB,"NVIDIA Quadro K620" },
{ 0x10DE13BD,"NVIDIA Tesla M40" }, // GM107GLM
{ 0x10DE13BE,"GM107 CS1" }, //
{ 0x10DE13BF,"GM107 INT52" }, //
// 12B0 - 12BF
{ 0x10DE13C0,"NVIDIA GeForce GTX 980" }, // GM107GLM
//{ 0x10DE13C1,"Graphics Device" }, // GM107GLM
{ 0x10DE13C2,"NVIDIA GeForce GTX 970" }, // GM107GLM
//{ 0x10DE13C3,"Graphics Device" }, // GM107GLM
{ 0x10DE13D7,"NVIDIA GeForce GTX 980M" }, //
{ 0x10DE13D8,"NVIDIA GeForce GTX 970M" }, //
//{ 0x10DE13D9,"Graphics Device" }, //
//{ 0x10DE13F0,"Graphics Device" }, // GM107GLM
//{ 0x10DE13F1,"Graphics Device" }, // GM107GLM
//{ 0x10DE1401,"Graphics Device" }, //
//{ 0x10DE1402,"Graphics Device" }, //
//{ 0x10DE143F,"Graphics Device" }, //
//{ 0x10DE1600,"Graphics Device" }, //
//{ 0x10DE1601,"Graphics Device" }, //
//{ 0x10DE1602,"Graphics Device" }, //
//{ 0x10DE1603,"Graphics Device" }, //
//{ 0x10DE1630,"Graphics Device" }, //
//{ 0x10DE1631,"Graphics Device" }, //
//{ 0x10DE1780,"Graphics Device" }, //
//{ 0x10DE1781,"Graphics Device" }, //
//{ 0x10DE1782,"Graphics Device" }, //
//{ 0x10DE1783,"Graphics Device" }, //
{ 0x10DE1789,"GRID M3-3020" }, //
{ 0x10DE1790,"N15S-GX" }, //
{ 0x10DE1791,"N15P-GT" }, //
{ 0x10DE1792,"N15P-GX" }, //
//{ 0x10DE17B3,"Quadro" }, //
//{ 0x10DE17BA,"Quadro" }, //
//{ 0x10DE17BB,"Quadro" }, //
//{ 0x10DE17BD,"Graphics Device" }, //
{ 0x10DE17BE,"GM107 CS1" } // GM107
//{ 0x10DE17C1,"Graphics Device" }, //
//{ 0x10DE17C2,"Graphics Device" }, //
//{ 0x10DE17EE,"Graphics Device" }, //
//{ 0x10DE17EF,"Graphics Device" }, //
//{ 0x10DE17F0,"Graphics Device" }, //
//{ 0x10DE17FF,"Graphics Device" }, //
};
static nvidia_card_info_t nvidia_card_exceptions[] = {
{ 0x10DE1180,0x38422682,"EVGA GTX 680 SC" },
{ 0x10DE1180,0x38422683,"EVGA GTX 680 SC" },
{ 0x10DE1185,0x10DE106F,"nVidia GeForce GTX 760 OEM" }, // GK104
{ 0x10DE1187,0x14583614,"GV-N760OC-4GD" },
{ 0x10DE1189,0x10438405,"Asus GTX 670 Direct CU II TOP" },
branches/Chimera/i386/libsaio/ati.c
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......
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"Juniper",
"Redwood",
"Broadway",
//"Madison",
//"Park",
/* Northern Islands */
//"Antilles",
"Barts",
"Caicos",
"Cayman",
/* Southern Islands */
"Tahiti",
"Pitcairn",
//"CapeVerde",
//"Thames",
//"Lombok",
//"NewZealand",
"Verde",
"Oland",
"Hainan",
"Bonaire",
"Kaveri",
"Abini",
"Hawaii",
/* ... */
"Mullins",
""
};
{"Uakari",4},
{"Zonalis",6},
{"Alouatta",4},
{"Hoolock",3},
{"Hoolock",1},
{"Vervet",4},
{"Baboon",3},
{"Eulemur",3},
{"Galago",2},
{"Colobus",2},
{"Mangabey",2},
{"Nomascus",4},
{"Nomascus",5},
{"Orangutan",2},
/* AMD6000Controller */
{"Pithecia",3},
return false;
}
// -------------------------------------------------
#if 0
uint64_t fb= (uint32_t)card->fb;
uint64_t mmio= (uint32_t)card->mmio;
devprop_add_value(card->device, "ATY,RegisterSpaceOffset", &mmio, 8);
devprop_add_value(card->device, "ATY,IOSpaceOffset", &io, 8);
#endif
devprop_add_list(ati_devprop_list);
// -------------------------------------------------
branches/Chimera/i386/libsaio/sys.c
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#include "disk.h"
#include "ramdisk.h"
#include "xml.h"
#include "sl.h"
#include <libkern/crypto/md5.h>
//#include <uuid/uuid.h>
static unsigned char kFSUUIDNamespaceSHA1[] = {0xB3,0xE2,0x0F,0x39,0xF2,0x92,0x11,0xD6,0x97,0xA4,0x00,0x30,0x65,0x43,0xEC,0xAC};
#endif
#if DEBUG
#define DBG(x...)printf(x)
#else
#define DBG(x...)msglog(x)
#endif
extern int multiboot_partition;
extern int multiboot_partition_set;
extern int multiboot_skip_partition;
readFile = bvr->fs_readfile;
if (readFile != NULL) {
if (readFile != NULL)
{
// Read the first 4096 bytes (fat header)
length = readFile(bvr, (char *)filePath, *binary, 0, 0x1000);
if (length > 0) {
if (ThinFatFile(binary, &length) == 0) {
if (length == 0) {
if (length > 0)
{
if (ThinFatFile(binary, &length) == 0)
{
if (length == 0)
{
return 0;
}
// We found a fat binary; read only the thin part
DBG("Fat Binary found. Reading thin part only...\n");
length = readFile(bvr, (char *)filePath, (void *)kLoadAddr, (unsigned long)(*binary) - kLoadAddr, length);
*binary = (void *)kLoadAddr;
} else {
// Not a fat binary; read the rest of the file
DBG("Thin Binary found. Reading rest of the file...\n");
length2 = readFile(bvr, (char *)filePath, (void *)(kLoadAddr + length), length, 0);
if (length2 == -1) {
} else {
length = bvr->fs_loadfile(bvr, (char *)filePath);
if (length > 0) {
if (length > 0)
{
ThinFatFile(binary, &length);
}
}
branches/Chimera/i386/libsaio/load.c
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* under the License.
*
* @APPLE_LICENSE_HEADER_END@
*/
/*
* load.c - Functions for decoding a Mach-o Kernel.
*
* Copyright (c) 1998-2003 Apple Computer, Inc.
* load.c - Functions for decoding a Mach-o Kernel.
*
* Copyright (c) 1998-2003 Apple Computer, Inc.
*
*/
#include <mach-o/fat.h>
#include <sl.h>
#if DEBUG
#define DBG(x...)printf(x)
#else
#define DBG(x...)msglog(x)
#endif
static long DecodeSegment(long cmdBase, unsigned int*load_addr, unsigned int *load_size);
static long DecodeUnixThread(long cmdBase, unsigned int *entry);
static long DecodeSymbolTable(long cmdBase);
uint32_t fapoffset;
uint32_t fapsize;
if (fhp->magic == FAT_MAGIC) {
if (fhp->magic == FAT_MAGIC)/* 0xcafebabe */
{
nfat = fhp->nfat_arch;
swapped = 0;
} else if (fhp->magic == FAT_CIGAM) {
} else if (fhp->magic == FAT_CIGAM)/* 0xbebafeca */
{
nfat = OSSwapInt32(fhp->nfat_arch);
swapped = 1;
} else {
return -1;
}
for (; nfat > 0; nfat--, fap++) {
if (swapped) {
for (; nfat > 0; nfat--, fap++)
{
if (swapped)
{
fapcputype = OSSwapInt32(fap->cputype);
fapoffset = OSSwapInt32(fap->offset);
fapsize = OSSwapInt32(fap->size);
fapsize = fap->size;
}
if (fapcputype == archCpuType) {
if (fapcputype == archCpuType)
{
*binary = (void *) ((unsigned long)*binary + fapoffset);
size = fapsize;
break;
}
}
if (length != 0) {
if (length != 0)
{
*length = size;
}
mH = (struct mach_header *)(gBinaryAddress);
#if DEBUG
printf("magic: %x\n", (unsigned)mH->magic);
printf("cputype: %x\n", (unsigned)mH->cputype);
printf("cpusubtype: %x\n", (unsigned)mH->cpusubtype);
printf("filetype: %x\n", (unsigned)mH->filetype);
printf("ncmds: %x\n", (unsigned)mH->ncmds);
printf("sizeofcmds: %x\n", (unsigned)mH->sizeofcmds);
printf("flags: %x\n", (unsigned)mH->flags);
getchar();
#endif
/*#if DEBUG
DBG("magic: 0x%x\n", (unsigned)mH->magic);
DBG("cputype: 0x%x\n", (unsigned)mH->cputype);
DBG("cpusubtype: 0x%x\n", (unsigned)mH->cpusubtype);
DBG("filetype: 0x%x\n", (unsigned)mH->filetype);
DBG("ncmds: 0x%x\n", (unsigned)mH->ncmds);
DBG("sizeofcmds: 0x%x\n", (unsigned)mH->sizeofcmds);
DBG("flags: 0x%x\n", (unsigned)mH->flags);
DBG("archCpuType: 0x%x\n", archCpuType);
//getchar();
#endif*/
switch (archCpuType)
{
case CPU_TYPE_I386:
if (mH->magic != MH_MAGIC) {
if (mH->magic != MH_MAGIC)
{
error("Mach-O file has bad magic number\n");
return -1;
}
break;
case CPU_TYPE_X86_64:
if (mH->magic != MH_MAGIC_64 && mH->magic == MH_MAGIC) {
/*
if (mH->magic != MH_MAGIC_64 && mH->magic == MH_MAGIC)
{
return -1;
}
if (mH->magic != MH_MAGIC_64) {
*/
if (mH->magic != MH_MAGIC_64)
{
error("Mach-O file has bad magic number\n");
return -1;
}
unsigned int load_addr;
unsigned int load_size;
switch (cmd) {
switch (cmd)
{
case LC_SEGMENT_64:
case LC_SEGMENT:
ret = DecodeSegment(cmdBase, &load_addr, &load_size);
}
if (ret != 0) {
if (ret != 0)
{
return -1;
}
cmdBase = cmdstart;
for (cnt = 0; cnt < ncmds; cnt++) {
cmd = ((long *)cmdBase)[0];
cmdsize = ((long *)cmdBase)[1];
for (cnt = 0; cnt < ncmds; cnt++)
{
cmd = ((long *)cmdBase)[0];
cmdsize = ((long *)cmdBase)[1];
if (cmd == LC_SYMTAB) {
if (DecodeSymbolTable(cmdBase) != 0) {
return -1;
}
}
if (cmd == LC_SYMTAB)
{
if (DecodeSymbolTable(cmdBase) != 0)
{
return -1;
}
}
cmdBase += cmdsize;
}
long vmsize, filesize;
unsigned long vmaddr, fileaddr;
if (((long *)cmdBase)[0] == LC_SEGMENT_64) {
if (((long *)cmdBase)[0] == LC_SEGMENT_64)
{
struct segment_command_64 *segCmd;
segCmd = (struct segment_command_64 *)cmdBase;
vmaddr = (segCmd->vmaddr & 0x3fffffff);
#endif
}
if (vmsize == 0 || filesize == 0) {
if (vmsize == 0 || filesize == 0)
{
*load_addr = ~0;
*load_size = 0;
return 0;
branches/Chimera/i386/libsaio/ati.h
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#include "device_inject.h"
#include "ati_reg.h"
/* DEFINES */
#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x6e
CHIP_FAMILY_UNKNOW,
/* Old */
CHIP_FAMILY_R420,
CHIP_FAMILY_RV410,
CHIP_FAMILY_R423,
CHIP_FAMILY_RV410,
CHIP_FAMILY_RV515,
CHIP_FAMILY_R520,
CHIP_FAMILY_RV530,
CHIP_FAMILY_HEMLOCK,
CHIP_FAMILY_JUNIPER,
CHIP_FAMILY_REDWOOD,
CHIP_FAMILY_BROADWAY,
//CHIP_FAMILY_MADISON,
//CHIP_FAMILY_PARK,
/* Northern Islands */
//CHIP_FAMILY_ANTILLES,
CHIP_FAMILY_BARTS,
CHIP_FAMILY_CAICOS,
CHIP_FAMILY_CAYMAN,
CHIP_FAMILY_TURKS,
/* Southern Islands */
CHIP_FAMILY_TAHITI,
CHIP_FAMILY_PALM,
CHIP_FAMILY_LOMBOK,
CHIP_FAMILY_WRESTLER,
CHIP_FAMILY_SUMO,
CHIP_FAMILY_SUMO2,
CHIP_FAMILY_MANHATTAN,
CHIP_FAMILY_VANCOUVER,
CHIP_FAMILY_TRINITY,
CHIP_FAMILY_ARUBA,
CHIP_FAMILY_TAHITI,
CHIP_FAMILY_PITCAIRN,
CHIP_FAMILY_VERDE,
CHIP_FAMILY_THAMES,
CHIP_FAMILY_LOMBOK,
//CHIP_FAMILY_NEWZEALAND,
CHIP_FAMILY_SUMO,
CHIP_FAMILY_MANHATTAN,
CHIP_FAMILY_VANCOUVER,
CHIP_FAMILY_WRESTLER,
CHIP_FAMILY_TRINITY,
CHIP_FAMILY_OLAND,
CHIP_FAMILY_HAINAN,
CHIP_FAMILY_BONAIRE,
CHIP_FAMILY_KAVERI,
CHIP_FAMILY_KABINI,
CHIP_FAMILY_HAWAII,
/* ... */
CHIP_FAMILY_MULLINS,
CHIP_FAMILY_LAST
} ati_chip_family_t;
branches/Chimera/i386/libsaio/platform.c
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#if DEBUG_PLATFORM
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#define DBG(x...)msglog(x)
#endif
PlatformInfo_t Platform;
branches/Chimera/i386/libsaio/cpu.c
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*/
uint64_t timeRDTSC(void)
{
intattempts = 0;
uint64_t latchTime;
uint64_tsaveTime,intermediate;
unsigned int timerValue, lastValue;
//boolean_tint_enabled;
/*
* Table of correction factors to account for
* - timer counter quantization errors, and
* - undercounts 0..5
*/
intattempts = 0;
uint64_t latchTime;
uint64_tsaveTime,intermediate;
unsigned int timerValue, lastValue;
//boolean_tint_enabled;
/*
* Table of correction factors to account for
* - timer counter quantization errors, and
* - undercounts 0..5
*/
#define SAMPLE_CLKS_EXACT(((double) CLKNUM) / 20.0)
#define SAMPLE_CLKS_INT((int) CLKNUM / 20)
#define SAMPLE_NSECS(2000000000LL)
#define SAMPLE_MULTIPLIER(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)
#define ROUND64(x)((uint64_t)((x) + 0.5))
uint64_tscale[6] = {
uint64_tscale[6] = {
ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)),
ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)),
ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)),
ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)),
ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)),
ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))
};
//int_enabled = ml_set_interrupts_enabled(FALSE);
};
//int_enabled = ml_set_interrupts_enabled(FALSE);
restart:
if (attempts >= 9) // increase to up to 9 attempts.
{
// This will flash-reboot. TODO: Use tscPanic instead.
printf("Timestamp counter calibation failed with %d attempts\n", attempts);
}
attempts++;
enable_PIT2();// turn on PIT2
set_PIT2(0);// reset timer 2 to be zero
latchTime = rdtsc64();// get the time stamp to time
latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes
set_PIT2(SAMPLE_CLKS_INT);// set up the timer for (almost) 1/20th a second
saveTime = rdtsc64();// now time how long a 20th a second is...
get_PIT2(&lastValue);
get_PIT2(&lastValue);// read twice, first value may be unreliable
do {
if (attempts >= 9) // increase to up to 9 attempts.
{
// This will flash-reboot. TODO: Use tscPanic instead.
printf("Timestamp counter calibation failed with %d attempts\n", attempts);
}
attempts++;
enable_PIT2();// turn on PIT2
set_PIT2(0);// reset timer 2 to be zero
latchTime = rdtsc64();// get the time stamp to time
latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes
set_PIT2(SAMPLE_CLKS_INT);// set up the timer for (almost) 1/20th a second
saveTime = rdtsc64();// now time how long a 20th a second is...
get_PIT2(&lastValue);
get_PIT2(&lastValue);// read twice, first value may be unreliable
do {
intermediate = get_PIT2(&timerValue);
if (timerValue > lastValue)
{
{
// Timer wrapped
set_PIT2(0);
disable_PIT2();
goto restart;
}
lastValue = timerValue;
} while (timerValue > 5);
printf("timerValue %d\n",timerValue);
printf("intermediate 0x%016llx\n",intermediate);
printf("saveTime 0x%016llx\n",saveTime);
} while (timerValue > 5);
printf("timerValue %d\n",timerValue);
printf("intermediate 0x%016llx\n",intermediate);
printf("saveTime 0x%016llx\n",saveTime);
intermediate -= saveTime;// raw count for about 1/20 second
intermediate *= scale[timerValue];// rescale measured time spent
intermediate /= SAMPLE_NSECS;// so its exactly 1/20 a second
intermediate += latchTime;// add on our save fudge
intermediate -= saveTime;// raw count for about 1/20 second
intermediate *= scale[timerValue];// rescale measured time spent
intermediate /= SAMPLE_NSECS;// so its exactly 1/20 a second
intermediate += latchTime;// add on our save fudge
set_PIT2(0);// reset timer 2 to be zero
disable_PIT2();// turn off PIT 2
set_PIT2(0);// reset timer 2 to be zero
disable_PIT2();// turn off PIT 2
//ml_set_interrupts_enabled(int_enabled);
return intermediate;
//ml_set_interrupts_enabled(int_enabled);
return intermediate;
}
/*
unsigned long pollCount;
uint64_t retval = 0;
int i;
/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT
* counter 2. We run this loop 3 times to make sure the cache
* is hot and we take the minimum delta from all of the runs.
/* The poll loop must have run at least a few times for accuracy */
if (pollCount <= 1) {
continue;
}
}
/* The TSC must increment at LEAST once every millisecond.
* We should have waited exactly 30 msec so the TSC delta should
* be >= 30. Anything less and the processor is way too slow.
*/
if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC) {
continue;
}
}
// tscDelta = MIN(tscDelta, (tscEnd - tscStart))
if ( (tscEnd - tscStart) < tscDelta ) {
tscDelta = tscEnd - tscStart;
}
}
}
/* tscDelta is now the least number of TSC ticks the processor made in
* a timespan of 0.03 s (e.g. 30 milliseconds)
* Hz so we need to convert our milliseconds to seconds. Since we're
* dividing by the milliseconds, we simply multiply by 1000.
*/
/* Unlike linux, we're not limited to 32-bit, but we do need to take care
* that we're going to multiply by 1000 first so we do need at least some
* arithmetic headroom. For now, 32-bit should be enough.
unsigned long pollCount;
uint64_t retval = 0;
int i;
/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT
* counter 2. We run this loop 3 times to make sure the cache
* is hot and we take the minimum delta from all of the runs.
/* The poll loop must have run at least a few times for accuracy */
if (pollCount <= 1) {
continue;
}
}
/* The TSC must increment at LEAST once every millisecond.
* We should have waited exactly 30 msec so the APERF delta should
* be >= 30. Anything less and the processor is way too slow.
*/
if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC) {
continue;
}
}
// tscDelta = MIN(tscDelta, (tscEnd - tscStart))
if ( (aperfEnd - aperfStart) < aperfDelta ) {
aperfDelta = aperfEnd - aperfStart;
}
}
}
/* mperfDelta is now the least number of MPERF ticks the processor made in
* a timespan of 0.03 s (e.g. 30 milliseconds)
*/
if (aperfDelta > (1ULL<<32)) {
retval = 0;
} else {
+--------+----------------+--------+----+----+--------+--------+--------+
|########|Extended family |Extmodel|####|type|familyid| model |stepping|
+--------+----------------+--------+----+----+--------+--------+--------+
EAX (AMD):
31 28 27 20 19 16 1514 1312 11 8 7 4 3 0
+--------+----------------+--------+----+----+--------+--------+--------+
|########|Extended family |Extmodel|####|####|familyid| model |stepping|
+--------+----------------+--------+----+----+--------+--------+--------+
+--------+----------------+--------+----+----+--------+--------+--------+
*/
p->CPU.Vendor= p->CPU.CPUID[CPUID_0][1];
p->CPU.Signature= p->CPU.CPUID[CPUID_1][0];
// stepping = cpu_feat_eax & 0xF;
p->CPU.Stepping= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);
// model = (cpu_feat_eax >> 4) & 0xF;
p->CPU.Model= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);
// family = (cpu_feat_eax >> 8) & 0xF;
p->CPU.Family= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);
// type = (cpu_feat_eax >> 12) & 0x3;
//p->CPU.Type= bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);
// ext_model = (cpu_feat_eax >> 16) & 0xF;
p->CPU.ExtModel= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);
// ext_family = (cpu_feat_eax >> 20) & 0xFF;
p->CPU.ExtFamily= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);
p->CPU.Stepping= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0); // stepping = cpu_feat_eax & 0xF;
p->CPU.Model= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4); // model = (cpu_feat_eax >> 4) & 0xF;
p->CPU.Family= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8); // family = (cpu_feat_eax >> 8) & 0xF;
//p->CPU.Type= bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12); // type = (cpu_feat_eax >> 12) & 0x3;
p->CPU.ExtModel= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16); // ext_model = (cpu_feat_eax >> 16) & 0xF;
p->CPU.ExtFamily= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20); // ext_family = (cpu_feat_eax >> 20) & 0xFF;
p->CPU.Model += (p->CPU.ExtModel << 4);
if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&
if (p->CPU.NoThreads > p->CPU.NoCores) {
p->CPU.Features |= CPU_FEATURE_HTT;
}
tscFrequency = measure_tsc_frequency();
/* if usual method failed */
if ( tscFrequency < 1000 ) { //TEST
}
fsbFrequency = 0;
cpuFrequency = 0;
if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {
int intelCPU = p->CPU.Model;
if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {
p->CPU.Model == CPU_MODEL_HASWELL ||
p->CPU.Model == CPU_MODEL_HASWELL_SVR ||
p->CPU.Model == CPU_MODEL_HASWELL_ULT ||
p->CPU.Model == CPU_MODEL_CRYSTALWELL )){
p->CPU.Model == CPU_MODEL_CRYSTALWELL ||
p->CPU.Model == CPU_MODEL_BROADWELL )){
msr = rdmsr64(MSR_PLATFORM_INFO);
//DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));
bus_ratio_max = bitfield(msr, 15, 8);//MacMan: Changed bitfield to match Apple tsc.c
case CPU_MODEL_HASWELL: // Intel Core i3, i5, i7, Xeon E3 LGA1050 (22nm)
case CPU_MODEL_HASWELL_ULT:
case CPU_MODEL_CRYSTALWELL:
case CPU_MODEL_BROADWELL:
{
msr = rdmsr64(MSR_IA32_PERF_STATUS);
currcoef = bitfield(msr, 15, 8);
branches/Chimera/i386/libsaio/platform.h
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#define CPUID_889
#define CPUID_MAX10
#define CPU_MODEL_PRESCOTT0x03// Celeron D, Pentium 4 (90nm)
#define CPU_MODEL_NOCONA0x04// Xeon Nocona, Irwindale (90nm)
#define CPU_MODEL_PRESLER0x06// Pentium 4, Pentium D (65nm)
#define CPU_MODEL_PENTIUM_M0x09// Banias
#define CPU_MODEL_DOTHAN0x0D// Dothan
#define CPU_MODEL_YONAH0x0E// Sossaman, Yonah
#define CPU_MODEL_MEROM0x0F// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom
#define CPU_MODEL_CONROE0x0F//
#define CPU_MODEL_CELERON0x16//
#define CPU_MODEL_PENRYN0x17// Wolfdale, Yorkfield, Harpertown, Penryn
#define CPU_MODEL_WOLFDALE0x17//
#define CPU_MODEL_NEHALEM0x1A// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown
#define CPU_MODEL_ATOM0x1C// Pineview
#define CPU_MODEL_XEON_MP0x1D// MP 7400
#define CPU_MODEL_FIELDS0x1E// Lynnfield, Clarksfield, Jasper Forest
#define CPU_MODEL_DALES0x1F// Havendale, Auburndale
#define CPU_MODEL_ANY 0x00
#define CPU_MODEL_UNKNOWN 0x01
#define CPU_MODEL_PRESCOTT 0x03// Celeron D, Pentium 4 (90nm)
#define CPU_MODEL_NOCONA 0x04// Xeon Nocona, Irwindale (90nm)
#define CPU_MODEL_PRESLER 0x06// Pentium 4, Pentium D (65nm)
#define CPU_MODEL_PENTIUM_M 0x09// Banias
#define CPU_MODEL_DOTHAN 0x0D// Dothan
#define CPU_MODEL_YONAH 0x0E// Sossaman, Yonah
#define CPU_MODEL_MEROM 0x0F// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom
#define CPU_MODEL_CONROE 0x0F//
#define CPU_MODEL_CELERON 0x16//
#define CPU_MODEL_PENRYN 0x17// Wolfdale, Yorkfield, Harpertown, Penryn
#define CPU_MODEL_WOLFDALE 0x17//
#define CPU_MODEL_NEHALEM 0x1A// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown
#define CPU_MODEL_ATOM 0x1C// Pineview
#define CPU_MODEL_XEON_MP 0x1D// MP 7400
#define CPU_MODEL_FIELDS 0x1E// Lynnfield, Clarksfield, Jasper Forest
#define CPU_MODEL_DALES 0x1F// Havendale, Auburndale
#define CPU_MODEL_DALES_32NM0x25// Clarkdale, Arrandale
#define CPU_MODEL_ATOM_SAN0x26// Lincroft
#define CPU_MODEL_LINCROFT0x27//
#define CPU_MODEL_ATOM_SAN 0x26// Lincroft
#define CPU_MODEL_LINCROFT 0x27//
#define CPU_MODEL_SANDYBRIDGE0x2A// Sandy Bridge
#define CPU_MODEL_WESTMERE0x2C// Gulftown, Westmere-EP, Westmere-WS
#define CPU_MODEL_JAKETOWN0x2D// Sandy Bridge-E, Sandy Bridge-EP
#define CPU_MODEL_WESTMERE 0x2C// Gulftown, Westmere-EP, Westmere-WS
#define CPU_MODEL_JAKETOWN 0x2D// Sandy Bridge-E, Sandy Bridge-EP
#define CPU_MODEL_NEHALEM_EX0x2E// Beckton
#define CPU_MODEL_WESTMERE_EX0x2F// Westmere-EX
#define CPU_MODEL_ATOM_20000x36// Cedarview
#define CPU_MODEL_IVYBRIDGE0x3A// Ivy Bridge
#define CPU_MODEL_HASWELL0x3C// Haswell DT
#define CPU_MODEL_ATOM_2000 0x36// Cedarview / Saltwell
#define CPU_MODEL_SILVERMONT0x37// Atom Silvermont
#define CPU_MODEL_IVYBRIDGE 0x3A// Ivy Bridge
#define CPU_MODEL_HASWELL 0x3C// Haswell DT
#define CPU_MODEL_BROADWELL 0x3D// Broadwell / Core-AVX2
#define CPU_MODEL_IVYBRIDGE_XEON0x3E// Ivy Bridge Xeon
#define CPU_MODEL_HASWELL_SVR0x3F// Haswell MB
#define CPU_MODEL_HASWELL_SVR0x3F// Haswell Server
//#define CPU_MODEL_HASWELL_H0x??// Haswell H
#define CPU_MODEL_HASWELL_ULT0x45// Haswell ULT
#define CPU_MODEL_CRYSTALWELL0x46// Haswell ULX
#define CPU_MODEL_CRYSTALWELL0x46// Crystal Well
// 4A silvermont / atom
#define CPU_MODEL_AVOTON 0x4D// Silvermont/Avoton Atom C2000
// 4E Core???
#define CPU_MODEL_BRODWELL_SVR0x4F// Broadwell Server
#define CPU_MODEL_BRODWELL_MSVR0x56// Broadwell Micro Server
// 5A silvermont / atom
// 5D silvermont / atom
/* CPU Features */
#define CPU_FEATURE_MMX0x00000001// MMX Instruction Set
#define SMB_MEM_TYPE_DDR219
#define SMB_MEM_TYPE_FBDIMM20
#define SMB_MEM_TYPE_DDR324// Supported in 10.5.6+ AppleSMBIOS
#define SMB_MEM_TYPE_DDR426
/* Memory Configuration Types */
#define SMB_MEM_CHANNEL_UNKNOWN0
//==============================================================================
typedef struct _PlatformInfo_t {
typedef struct _PlatformInfo_t
{
struct CPU {
uint32_tFeatures;// CPU Features like MMX, SSE2, VT, MobileCPU
uint32_tVendor;// Vendor
uint32_tCoresPerPackage;
uint32_tLogicalPerPackage;
uint32_tSignature;// Processor Signature
uint32_tStepping;// Stepping
//uint16_tType;// Type
intDIMM[MAX_RAM_SLOTS];// Information and SPD mapping for each slot
} DMI;
uint8_tType;// System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)
uint8_tType;// System Type: 1=Desktop, 2=Portable, 3=Workstation... according ACPI2.0 (FACP: PM_Profile)
uint8_t*UUID;
} PlatformInfo_t;
branches/Chimera/i386/libsaio/disk.c
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HFSGetDirEntry,
HFSGetFileBlock,
HFSGetUUID,
HFSGetDescription,
HFSFree,
0,
kBIOSDevTypeHardDrive);
kBIOSDevTypeHardDrive, 0);
bvr->next = map->bvr;
map->bvr = bvr;
map->bvrcnt++;
{
return NULL;
}
bzero(buffer,BPS);
/* Check for alternate block size */
if (readBytes( biosdev, 0, 0, BPS, buffer ) != 0)
{
return NULL;
}
bzero(buffer,BPS);
}
factor = blksize / BPS;
}
const char *val;
int len;
if (getValueForKey(kProductVersion, &val, &len, &systemVersion)) {
if (getValueForKey(kProductVersion, &val, &len, &systemVersion))
{
// getValueForKey uses const char for val
// so copy it and trim
*str = '\0';
//strncat(str, val, MIN(len, 4)); // removed since it breaks any OS X version greater than 10.9 i.e. Yosemite 10.10
strncat(str, val, len); // just copy the whole version number instead
} else {
valid = false;
}
}
if(!valid) {
if(!valid)
{
int fh = -1;
sprintf(dirSpec, "hd(%d,%d)/.PhysicalMediaInstall", BIOS_DEV_UNIT(bvr), bvr->part_no);
fh = open(dirSpec, 0);
if (fh >= 0) {
if (fh >= 0)
{
valid = true;
bvr->OSisInstaller = true;
strcpy(bvr->OSVersion, "10.7"); // 10.7 +
close(fh);
} else {
close(fh);
}
branches/Chimera/i386/libsaio/smbios.c
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/* ==============================================
OEM Platform Feature (Apple Specific - Type 133)
================================================ */
//#define kSMBOemPlatformFeatureKey
//#define kSMBOemPlatformFeatureKey "SMoemplatformfeature"
/* ==================================================*/
#define getFieldOffset(struct, field)((uint8_t)(uint32_t)&(((struct *)0)->field))
uint8_tchassisType;
char*version;
char*serialNumber;
char*assetTag; // Bungo: renamed folowing convention
//char*skuNumber;
char*assetTag;
char*skuNumber;
} defaultChassis_t;
defaultChassis_t defaultChassis;
kSMBBaseBoardSerialNumberKey, NULL, &defaultBaseBoard.serialNumber }, // SMboardserial - C02140302D5DMT31M
{kSMBTypeBaseBoard,kSMBString,getFieldOffset(SMBBaseBoard, assetTag),
kSMBBaseBoardAssetTagKey, NULL, &defaultBaseBoard.assetTag }, // SMboardassetag - Base Board Asset Tag#
kSMBBaseBoardAssetTagKey, NULL, &defaultBaseBoard.assetTag }, // SMboardassettag - Base Board Asset Tag#
{kSMBTypeBaseBoard,kSMBString,getFieldOffset(SMBBaseBoard, locationInChassis),
kSMBBaseBoardLocationInChassisKey, NULL, &defaultBaseBoard.locationInChassis }, // SMboardlocation - Part Component
#define kDefaultMacMiniBoardProduct"Mac-F4208EAA"
// MacMini5,1 Mac-8ED6AF5B48C039E1 - MM51.88Z.0077.B0F.1110201309
// MacMini5,2 Mac-4BC72D62AD45599E
// MacMini5,3
//#define kDefaultMacMini"Macmini5,3"
//#define kDefaultMacMiniBIOSVersion" MM51.88Z.0077.B10.1201241549"
// MacBookAir4,1 - Mac-C08A6BB70A942AC2
// MacBookAir4,2 - Mac-742912EFDBEE19B3
// MacBookAir5,2
#define kDefaultMacBookAir"MacBookAir5,2"
#define kDefaultMacBookAirBIOSVersion" MBA51.88Z.00EF.B00.1205221442"
#define kDefaultMacBookAirBIOSReleaseDate"05/10/12"
#define kDefaultMacBookBoardAirProduct"Mac-2E6FAB96566FE58C"
// MacBookAir6,1 - Mac-35C1E88140C3E6CF - MBA61.88Z.0099.B04.1309271229
// MacBookAir6,2 - Mac-7DF21CB3ED6977E5 - MBA62.88Z.00EF.B00.1205221442
// MacBookAir6,1
// Bios: MBA61.88Z.0099.B04.1309271229
// Board: Mac-35C1E88140C3E6CF
// Data: 24/06/13
// MacBookAir6,2
// Bios: MBA62.88Z.00EF.B00.1205221442
// Board: Mac-7DF21CB3ED6977E5
// Data: 24/06/13
//=========== MacBookPro ===========
#define kDefaultMacBookProFamily"MacBook Pro"
//#define kDefaultMacBookProBoardAssetTagNumber"MacBook-Aluminum"
#define kDefaultiMacBIOSVersion" IM81.88Z.00C1.B00.0903051113"
#define kDefaultiMacBIOSReleaseDate"02/09/08"
#define kDefaultiMacBoardProduct"Mac-F227BEC8"
#define kDefaultMacFamily"Mac" // iMac8,1 family = "Mac" not "iMac"
// iMac10,1
// iMac11,1 core i3/i5/i7
// iMac12,1
#define kDefaultiMacSandy"iMac12,1"
#define kDefaultiMacSandyBIOSVersion" IM121.88Z.0047.B00.1102091756"
#define kDefaultiMacSandyBIOSReleaseDate"01/02/08"
#define kDefaultiMacSandyBIOSReleaseDate"04/22/11"
#define kDefaultiMacSandyBoardProduct"Mac-942B5BF58194151B"
// iMac12,2 Mac-942B59F58194171B
//#define KDefaultMacProBoardSerialNumber"J593902RA4MFE"
// Mac Pro 4,1 core i7/Xeon
#define kDefaultMacProNahWestSystemVersion"0.0"
#define kDefaultMacProNehalem"MacPro4,1"
#define kDefaultMacProNehalemBIOSVersion" MP41.88Z.0081.B07.0910130729"
#define kDefaultMacProNehalemBIOSReleaseDate"10/13/09"
bool useSMBIOSdefaults = true; // Bungo
SMBByte PlatformType= 3; // Bungo: same as Platfom.Type in platform.h
SMBByte PlatformType= 1; // Bungo: same as Platfom.Type in platform.h. Because can't get from ACPI FADT PM profile and platformCPUFeature(CPU_FEATURE_MOBILE)) doesn't work as expect, FIXING NEEDED.
/* Rewrite this function */
void setDefaultSMBData(void) // Bungo: setting data from real Macs
defaultChassis.manufacturer = kDefaultVendorManufacturer;
defaultChassis.serialNumber = kDefaultSerialNumber;
defaultChassis.assetTag = kDefaultAssetTag;
//defaultChassis.skuNumber = kDefaultSkuNumber;
defaultChassis.skuNumber = kDefaultSkuNumber;
// if (platformCPUFeature(CPU_FEATURE_MOBILE)) Bungo: doesn't recognise correctly, need fixing
if (PlatformType == 2) // this method works but it's a substitute
{
if (Platform.CPU.NoCores > 1) {
if (Platform.CPU.NoCores > 1)
{
defaultSystemInfo.productName = kDefaultMacBookPro;
defaultBIOSInfo.version = kDefaultMacBookProBIOSVersion;
defaultBIOSInfo.releaseDate = kDefaultMacBookProBIOSReleaseDate;
defaultBIOSInfo.version = kDefaultiMacBIOSVersion;
defaultBIOSInfo.releaseDate = kDefaultiMacBIOSReleaseDate;
defaultSystemInfo.productName = kDefaultiMac;
defaultSystemInfo.family = kDefaultiMacFamily;
defaultSystemInfo.family = kDefaultiMacFamily; // iMac8,1 family = Mac
defaultBaseBoard.product = kDefaultiMacBoardProduct;
defaultBaseBoard.boardType = kSMBBaseBoardMotherboard;
defaultChassis.chassisType = kSMBchassisAllInOne;
defaultBIOSInfo.version= kDefaultiMacNehalemBIOSVersion;
defaultBIOSInfo.releaseDate= kDefaultiMacNehalemBIOSReleaseDate;
defaultSystemInfo.productName= kDefaultiMacNehalem;
defaultSystemInfo.family= kDefaultiMacFamily;
defaultSystemInfo.family= kDefaultiMacFamily; // iMac8,1 family = Mac
defaultBaseBoard.product = kDefaultiMacNehalemBoardProduct;
defaultBaseBoard.boardType = kSMBBaseBoardMotherboard;
defaultChassis.chassisType = kSMBchassisAllInOne;
break;
case CPU_MODEL_SANDYBRIDGE:// Intel Core i3, i5, i7 LGA1155 (32nm)
case CPU_MODEL_IVYBRIDGE:// Intel Core i3, i5, i7 LGA1155 (22nm)
case CPU_MODEL_SANDYBRIDGE:// Intel Core i3, i5, i7 LGA1155 (32nm)
case CPU_MODEL_IVYBRIDGE:// Intel Core i3, i5, i7 LGA1155 (22nm)
defaultBIOSInfo.version = kDefaultiMacSandyBIOSVersion;
defaultBIOSInfo.releaseDate = kDefaultiMacSandyBIOSReleaseDate;
defaultSystemInfo.productName= kDefaultiMacSandy;
defaultChassis.chassisType = kSMBchassisAllInOne;
break;
case CPU_MODEL_NEHALEM:// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x
defaultBIOSInfo.version= kDefaultMacProNehalemBIOSVersion;
defaultBIOSInfo.releaseDate= kDefaultMacProNehalemBIOSReleaseDate;
case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x
defaultBIOSInfo.version = kDefaultMacProNehalemBIOSVersion;
defaultBIOSInfo.releaseDate = kDefaultMacProNehalemBIOSReleaseDate;
defaultSystemInfo.productName= kDefaultMacProNehalem;
defaultSystemInfo.family= kDefaultMacProFamily;
defaultSystemInfo.version = kDefaultMacProNahWestSystemVersion;
defaultSystemInfo.family = kDefaultMacProFamily;
defaultBaseBoard.product = kDefaultMacProNehalemBoardProduct;
defaultBaseBoard.boardType = kSMBBaseBoardProcessorMemoryModule;
defaultChassis.chassisType = kSMBchassisTower;
break;
case CPU_MODEL_WESTMERE:// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
case CPU_MODEL_JAKETOWN:// Intel Core i7, Xeon E5 LGA2011 (32nm)
case CPU_MODEL_IVYBRIDGE_XEON: // Intel Core i7, Xeon E5 v2 LGA2011 (22nm) MacMan moved to proper location
case CPU_MODEL_HASWELL_SVR: // Intel Core i7, Xeon E5 v3 LGA2011v3 (22nm)
defaultBIOSInfo.version= kDefaultMacProWestmereBIOSVersion;
defaultBIOSInfo.releaseDate= kDefaultMacProWestmereBIOSReleaseDate;
case CPU_MODEL_BROADWELL: // Intel Core i3, i5, i7 LGA1150 LGA2011v3 (14nm)
case CPU_MODEL_HASWELL_ULT:
case CPU_MODEL_CRYSTALWELL:
case CPU_MODEL_BRODWELL_SVR:
case CPU_MODEL_BRODWELL_MSVR:
defaultBIOSInfo.version = kDefaultMacProWestmereBIOSVersion;
defaultBIOSInfo.releaseDate = kDefaultMacProWestmereBIOSReleaseDate;
defaultSystemInfo.productName= kDefaultMacProWestmere;
defaultSystemInfo.family= kDefaultMacProFamily;
defaultSystemInfo.version = kDefaultMacProNahWestSystemVersion;
defaultSystemInfo.family = kDefaultMacProFamily;
defaultBaseBoard.product = kDefaultMacProWestmereBoardProduct;
defaultBaseBoard.boardType = kSMBBaseBoardProcessorMemoryModule;
defaultChassis.chassisType = kSMBchassisTower;
break;
default:
defaultBIOSInfo.version= kDefaultMacProBIOSVersion;
defaultBIOSInfo.releaseDate= kDefaultMacProBIOSReleaseDate;
defaultBIOSInfo.version = kDefaultMacProBIOSVersion;
defaultBIOSInfo.releaseDate = kDefaultMacProBIOSReleaseDate;
defaultSystemInfo.productName= kDefaultMacPro;
defaultSystemInfo.family= kDefaultMacProFamily;
defaultSystemInfo.family = kDefaultMacProFamily;
defaultBaseBoard.product = kDefaultMacProBoardProduct;
defaultBaseBoard.boardType = kSMBBaseBoardMotherboard;
defaultChassis.chassisType = kSMBchassisUnknown;
break;
}
default:
defaultBIOSInfo.version= kDefaultMacProBIOSVersion;
defaultBIOSInfo.releaseDate= kDefaultMacProBIOSReleaseDate;
defaultBIOSInfo.version = kDefaultMacProBIOSVersion;
defaultBIOSInfo.releaseDate = kDefaultMacProBIOSReleaseDate;
defaultSystemInfo.productName= kDefaultMacPro;
defaultSystemInfo.family= kDefaultMacProFamily;
defaultSystemInfo.family = kDefaultMacProFamily;
defaultBaseBoard.product = kDefaultMacProBoardProduct;
defaultBaseBoard.boardType = kSMBBaseBoardMotherboard;
defaultChassis.chassisType = kSMBchassisUnknown;
case kSMBByte:
case kSMBWord:
case kSMBDWord:
//case kSMBQWord:
case kSMBQWord:
if (SMBSetters[idx].keyString) {
parsed = getIntForKey(SMBSetters[idx].keyString, &val, SMBPlist);
if (!parsed)
case kSMBWord:
value->word = (uint16_t)val;
break;
//case kSMBQWord:
//value->qword = (uint64_t)val;
//break;
case kSMBQWord:
value->qword = (uint64_t)val;
break;
case kSMBDWord:
default:
value->dword = (uint32_t)val;
case kSMBWord:
value->word = *(uint16_t *)(SMBSetters[idx].defaultValue);
break;
//case kSMBQWord:
//value->qword = *(uint32_t *)(SMBSetters[idx].defaultValue);
//break;
case kSMBQWord:
value->qword = *(uint64_t *)(SMBSetters[idx].defaultValue);
break;
case kSMBDWord:
default:
value->dword = *(uint32_t *)(SMBSetters[idx].defaultValue);
case CPU_MODEL_IVYBRIDGE:// Intel Core i3, i5, i7 LGA1155 (22nm)
case CPU_MODEL_IVYBRIDGE_XEON:
case CPU_MODEL_JAKETOWN:// Intel Core i7, Xeon E5 LGA2011 (32nm)
case CPU_MODEL_HASWELL:
case CPU_MODEL_HASWELL: // Intel Core i3, i5, i7 LGA1150 LGA2011v3 (22nm)
case CPU_MODEL_HASWELL_SVR:
case CPU_MODEL_HASWELL_ULT:
case CPU_MODEL_CRYSTALWELL:
case CPU_MODEL_BROADWELL: // Intel Core i3, i5, i7 LGA1150 LGA2011v3 (14nm)
case CPU_MODEL_BRODWELL_SVR:
case CPU_MODEL_BRODWELL_MSVR:
break;
structSize = sizeof(SMBMemoryDevice);
break;
default:
structSize = structPtr->orig->length; // don't change if not to patch
structSize = structPtr->orig->length; // doesn't change a length for unpatched
break;
}
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};
static const char *SMBMemoryDeviceFormFactors[] = // Bungo: strings for form factor (Table Type 17 - Memory Device)
{
"Other", /* 01h */
"Unknown", /* 02h */
"SIMM", /* 03h */
"SIP", /* 04h */
"Chip", /* 05h */
"DIP", /* 06h */
"ZIP", /* 07h */
"Proprietary Card", /* 08h */
"DIMM", /* 09h */
"TSOP", /* 0Ah */
"Row of chips", /* 0Bh */
"RIMM", /* 0Ch */
"SODIMM", /* 0Dh */
"SRIMM", /* 0Eh */
"FB-DIMM" /* 0Fh */
};
/*=====
7.18.2
====*/
}
//-------------------------------------------------------------------------------------------------------------------------
// Memory Controller Information (Type 5)
//-------------------------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------------------------
// Memory Module Information (Type 6)
//-------------------------------------------------------------------------------------------------------------------------
//void decodeMemoryModule(SMBStructHeader *structHeader)
//}
//-------------------------------------------------------------------------------------------------------------------------
// Cache Information (Type 7)
//-------------------------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------------------------
// Port Connector Information (Type 8)
//-------------------------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------------------------
// System Slot Information (Type 9)
//-------------------------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------------------------
// On Board Device Information (Type 10)
//-------------------------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------------------------
// OEM Strings (Type 11)
//-------------------------------------------------------------------------------------------------------------------------
void decodeSMBOEMStrings(SMBStructHeader *structHeader)
}
DBG("\n");
}
//-------------------------------------------------------------------------------------------------------------------------
// System Configuration Options (Type 12)
//-------------------------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------------------------
// BIOS Language Information (Type 13)
//-------------------------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------------------------
// Physical Memory Array (Type 16)
//-------------------------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------------------------
// MemoryDevice (Type 17)
//-------------------------------------------------------------------------------------------------------------------------
void decodeMemoryDevice(SMBStructHeader *structHeader)
printHeader(structHeader);
DBG("Memory Device\n");
// Aray Handle
DBG("\tError Information Handle: 0x%x\n", ((SMBMemoryDevice *)structHeader)->errorHandle);
if (((SMBMemoryDevice *)structHeader)->errorHandle == 0xFFFF) {
DBG("\tError Information Handle: No Error\n");
} else {
DBG("\tError Information Handle: 0x%x\n", ((SMBMemoryDevice *)structHeader)->errorHandle);
}
// Total Width:
// Data Width:
// Size:
// Form Factor:
switch (((SMBMemoryDevice *)structHeader)->memorySize) {
case 0:
DBG("\tSize: No Module Installed\n");
break;
case 0x7FFF:
DBG("\tSize: 32GB or more\n");
break;
case 0xFFFF:
DBG("\tSize: Unknown\n");
break;
default:
DBG("\tSize: %d %s\n", ((SMBMemoryDevice *)structHeader)->memorySize & 0x7FFF, ((((SMBMemoryDevice *)structHeader)->memorySize & 0x8000) == 0x8000) ? "kB" : "MB");
break;
}
if ((((SMBMemoryDevice *)structHeader)->formFactor < 0x01) || (((SMBMemoryDevice *)structHeader)->formFactor > 0x0F)) {
DBG("\tForm Factor: %s\n", OutOfSpecStr);
} else {
DBG("\tForm Factor: %s\n", SMBMemoryDeviceFormFactors[((SMBMemoryDevice *)structHeader)->formFactor - 1]);
}
// Set:
DBG("\tLocator: %s\n", SMBStringForField(structHeader, ((SMBMemoryDevice *)structHeader)->deviceLocator, neverMask));
DBG("\tBank Locator: %s\n", SMBStringForField(structHeader, ((SMBMemoryDevice *)structHeader)->bankLocator, neverMask));
//}
//-------------------------------------------------------------------------------------------------------------------------
// Specific (Type 134)
// Specific (Type 134)
//-------------------------------------------------------------------------------------------------------------------------
//void decodeOem(SMBStructHeader *structHeader)
//{
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#define __LIBSAIO_SMBIOS_H
/* Based on System Management BIOS Reference Specification v2.5 */
// http://dmtf.org/sites/default/files/standards/documents/DSP0134_2.8.0.pdf
/* Based on System Management BIOS Reference Specification v2.4 */
// http://dmtf.org/standards/smbios
typedef uint8_t SMBString;
typedef uint8_t SMBByte;
#define SMB_ANCHOR_RESET(x)\
bzero(x, sizeof(typedef struct SMBAnchor));
/*
=======================
SMBIOS structure types.
======================= */
/* ======================= SMBIOS structure types. ======================= */
enum
{
kSMBTypeBIOSInformation= 0, // BIOS information (Type 0)
kSMBTypeSystemInformation= 1, // System Information (Type 1)
kSMBTypeBaseBoard= 2, // BaseBoard Information (Type 2)
kSMBTypeBaseBoard = 2, // BaseBoard Information (Type 2)
kSMBTypeSystemEnclosure= 3, // System Chassis Information (Type 3)
kSMBTypeProcessorInformation= 4, // Processor Information (Type 4)
kSMBTypeProcessorInformation= 4, // Processor Information (Type 4)
// Memory Controller Information (Type 5) Obsolete
kSMBTypeMemoryModule= 6, // Memory Module Information (Type 6) Obsolete
kSMBTypeCacheInformation= 7, // Cache Information (Type 7)
// Port Connector Information (Type 8)
kSMBTypeSystemSlot= 9, // System Slots (Type 9)
kSMBTypeSystemSlot = 9, // System Slots (Type 9)
// On Board Devices Information (Type 10) Obsolete
kSMBOEMStrings= 11 ,// OEM Strings (Type 11)
kSMBOEMStrings = 11 ,// OEM Strings (Type 11)
// System Configuration Options (Type 12)
// BIOS Language Information (Type 13)
// Group Associations (Type 14)
// Out-of-Band Remote Access (Type 30)
// Boot Integrity Service (BIS) Entry Point (Type 31)
// System Boot Information (Type 32)
kSMBType64BitMemoryErrorInfo= 33, // 64-Bit Memory Error Information (Type 33)
kSMBType64BitMemoryErrorInfo = 33, // 64-Bit Memory Error Information (Type 33)
// Managment Device (Type 34)
// Managment Device Component (Type 35)
// Management Device Threshold Data (Type 36)
// Management Controlle Host Interface (Type 42)
// Inactive (Type 126)
kSMBTypeEndOfTable= 127, // End-of-Table (Type 127)
kSMBTypeEndOfTable = 127, // End-of-Table (Type 127)
// Apple Specific Structures
kSMBTypeFirmwareVolume= 128, // FirmwareVolume (TYPE 128)
kSMBTypeMemorySPD= 130, // MemorySPD (TYPE 130)
kSMBTypeMemorySPD = 130, // MemorySPD (TYPE 130)
kSMBTypeOemProcessorType= 131, // Processor Type (Type 131)
kSMBTypeOemProcessorBusSpeed= 132 // Processor Bus Speed (Type 132)
//kSMBTypeOemPlatformFeature= 133 // Platform Feature (Type 133)
kSMBTypeOemProcessorBusSpeed = 132, // Processor Bus Speed (Type 132)
kSMBTypeOemPlatformFeature= 133 // Platform Feature (Type 133)
};
/* =======================
BIOS Information (Type 0)
========================= */
//----------------------------------------------------------------------------------------------------------
// Struct - BIOS Information (Type 0)
typedef struct SMBBIOSInformation
{
SMB_STRUCT_HEADER
SMBByte ECreleaseMinor; // Embedded Controller firmware release (minor)
} __attribute__((packed)) SMBBIOSInformation;
/* =========================
System Information (Type 1)
=========================== */
//----------------------------------------------------------------------------------------------------------
// Struct - System Information (Type 1)
typedef struct SMBSystemInformation
{
// 2.0+ spec (8 bytes)
SMBString family;
} __attribute__((packed)) SMBSystemInformation;
/* =========================================
Base Board (or Module) Information (Type 2)
=========================================== */
//----------------------------------------------------------------------------------------------------------
// Base Board (or Module) Information (Type 2)
// Base Board - Board Type.
// Values for SMBBaseBoard.boardType
typedef enum
{
kSMBBaseBoardUnknown = 0x01,// Unknow
kSMBBaseBoardOther = 0x02,// Other
kSMBBaseBoardServerBlade = 0x03,// Server Blade
kSMBBaseBoardConnectivitySwitch = 0x04,// Connectivity Switch
kSMBBaseBoardSystemMgmtModule = 0x05,// System Management Module
kSMBBaseBoardProcessorModule = 0x06,// Processor Module
kSMBBaseBoardIOModule = 0x07,// I/O Module
kSMBBaseBoardMemoryModule = 0x08,// Memory Module
kSMBBaseBoardDaughter = 0x09,// Daughter Board
kSMBBaseBoardMotherboard = 0x0A,// Motherboard (includes processor, memory, and I/O)
kSMBBaseBoardProcessorMemoryModule = 0x0B,// Processor/Memory Module
kSMBBaseBoardProcessorIOModule = 0x0C,// Processor/IO Module
kSMBBaseBoardInterconnect = 0x0D// Interconnect board
} BASE_BOARD_TYPE;
// Struct - Base Board (or Module) Information (Type 2)
typedef struct SMBBaseBoard
{
SMB_STRUCT_HEADER // Type 2
SMBByte featureFlags;// Collection of flag that identify features of this baseboard
SMBStringlocationInChassis;
SMBWord chassisHandle;
SMBByte boardType;// Type of board
SMBByte boardType;// Type of board, numeration value from BASE_BOARD_TYPE.
SMBByte numberOfContainedHandles;
//SMBWord containedObjectHandles[1];
// 0 - 255 contained handles go here but we do not include
// them in our structure. Be careful to use numberOfContainedHandles
// times sizeof(SMBWord) when computing the actual record size,
// if you need it.
SMBByte containedObjectHandles;
} __attribute__((packed)) SMBBaseBoard;
/* ====================================
Values for boardType in Type 2 records
====================================== */
enum
{
kSMBBaseBoardUnknown = 0x01,// Unknow
kSMBBaseBoardOther = 0x02,// Other
kSMBBaseBoardServerBlade = 0x03,// Server Blade
kSMBBaseBoardConnectivitySwitch = 0x04,// Connectivity Switch
kSMBBaseBoardSystemMgmtModule = 0x05,// System Management Module
kSMBBaseBoardProcessorModule = 0x06,// Processor Module
kSMBBaseBoardIOModule = 0x07,// I/O Module
kSMBBaseBoardMemoryModule = 0x08,// Memory Module
kSMBBaseBoardDaughter = 0x09,// Daughter Board
kSMBBaseBoardMotherboard = 0x0A,// Motherboard (includes processor, memory, and I/O)
kSMBBaseBoardProcessorMemoryModule = 0x0B,// Processor/Memory Module
kSMBBaseBoardProcessorIOModule = 0x0C,// Processor/IO Module
kSMBBaseBoardInterconnect = 0x0D// Interconnect board
};
//----------------------------------------------------------------------------------------------------------
// System Enclosure (Type 3)
/* =======================
System Enclosure (Type 3)
========================= */
typedef struct SMBSystemEnclosure
{
SMB_STRUCT_HEADER // Type 3
SMBString manufacturer;
SMBByte chassisType;// System Enclosure Indicator
SMBString version;// Board Number?
SMBString serialNumber;
SMBString assetTag;// Bungo: renamed from assetTagNumber folowing convention
SMBByte bootupState;// State of enclosure when when it was last booted
SMBByte powerSupplyState;// State of enclosure's power supply when last booted
SMBByte thermalState;// Thermal state of the enclosure when last booted
SMBByte securityStatus;// Physical security status of the enclosure when last booted
SMBDWord oemDefined;// OEM- or BIOS vendor-specific information
SMBByte height;// Height of the enclosure, in 'U's
SMBByte numberOfPowerCords;// Number of power cords associated with the enclosure or chassis
SMBByte containedElementCount;// Number of Contained Element record that follow, in the range 0 to 255
//SMBByte containedElementRecord;// Byte leght of each Contained Element record that follow, in the range 0 to 255
//SMBByte containedElements;// Elements, possibly defined by other SMBIOS structures present in chassis
//SMBString skuNumber;// Number of null-terminated string describing the chassis or enclosure SKU number (2.7+)
} __attribute__((packed)) SMBSystemEnclosure;
// Bungo: values for SMBSystemEnclosure.chassisType
enum {
typedef enum {
kSMBchassisOther = 0x01,
kSMBchassisUnknown = 0x02,
kSMBchassisDesktop = 0x03,
kSMBchassisLunchBox = 0x10,
// ... fill up if needed ;-)
kSMBchassisBladeEnclosing = 0x1D
};
} MISC_CHASSIS_TYPE;
/* ============================
Processor Information (Type 4)
============================== */
// System Enclosure or Chassis States.
// values for SMBSystemEnclosure.bootupState
// values for SMBSystemEnclosure.powerSupplyState
// values for SMBSystemEnclosure.thermalState
typedef enum {
kSMBChassisStateOther = 0x01,
kSMBChassisStateUnknown = 0x02,
kSMBChassisStateSafe = 0x03,
kSMBChassisStateWarning = 0x04,
kSMBChassisStateCritical = 0x05,
kSMBChassisStateNonRecoverable = 0x06
} MISC_CHASSIS_STATE;
// System Enclosure or Chassis Security Status.
// values for SMBSystemEnclosure.securityStatus
typedef enum {
kSMBChassisSecurityStatusOther = 0x01,
kSMBChassisSecurityStatusUnknown = 0x02,
kSMBChassisSecurityStatusNone = 0x03,
kSMBChassisSecurityStatusExternalInterfaceLockedOut = 0x04,
kSMBChassisSecurityStatusExternalInterfaceLockedEnabled = 0x05
} MISC_CHASSIS_SECURITY_STATE;
// Struct - System Enclosure (Type 3)
typedef struct SMBSystemEnclosure
{
SMB_STRUCT_HEADER // Type 3
SMBString manufacturer;
SMBByte chassisType;// System Enclosure Indicator
SMBString version;// Board Number?
SMBString serialNumber;
SMBString assetTag;// Bungo: renamed from assetTagNumber folowing convention
SMBByte bootupState;// State of enclosure when when it was last booted
SMBByte powerSupplyState;// State of enclosure's power supply when last booted
SMBByte thermalState;// Thermal state of the enclosure when last booted
SMBByte securityStatus;// Physical security status of the enclosure when last booted
SMBDWord oemDefined;// OEM- or BIOS vendor-specific information
SMBByte height;// Height of the enclosure, in 'U's
SMBByte numberOfPowerCords;// Number of power cords associated with the enclosure or chassis
SMBByte containedElementCount;// Number of Contained Element record that follow, in the range 0 to 255
//SMBByte containedElementRecord;// Byte leght of each Contained Element record that follow, in the range 0 to 255
//SMBByte containedElements;// Elements, possibly defined by other SMBIOS structures present in chassis
//SMBString skuNumber;// Number of null-terminated string describing the chassis or enclosure SKU number (2.7+)
} __attribute__((packed)) SMBSystemEnclosure;
//----------------------------------------------------------------------------------------------------------
// Processor Information (Type 4)
#define kSMBProcessorInformationMinSize 26
// Processor Information - Processor Type.
// Values for SMBProcessorInformation.processorType
typedef enum
{
kSMBprocessorTypeOther = 0x01,
kSMBprocessorTypeUnknown = 0x02,
kSMBprocessorTypeCPU = 0x03,
kSMBprocessorTypeMPU = 0x04,
kSMBprocessorTypeDSP = 0x05,
kSMBprocessorTypeGPU = 0x06
} PROCESSOR_TYPE_DATA;
// Processor Information - Processor Family.
// Values for SMBProcessorInformation.processorFamily
typedef enum {
kSMBprocessorFamilyOther = 0x01,
kSMBprocessorFamilyUnknown = 0x02,
kSMBprocessorFamily8086 = 0x03,
kSMBprocessorFamily80286 = 0x04,
kSMBprocessorFamilyIntel386 = 0x05,
kSMBprocessorFamilyIntel486 = 0x06,
kSMBprocessorFamily8087 = 0x07,
kSMBprocessorFamily80287 = 0x08,
kSMBprocessorFamily80387 = 0x09,
kSMBprocessorFamily80487 = 0x0A,
kSMBprocessorFamilyPentium = 0x0B,
kSMBprocessorFamilyPentiumPro = 0x0C,
kSMBprocessorFamilyPentiumII = 0x0D,
kSMBprocessorFamilyPentiumMMX = 0x0E,
kSMBprocessorFamilyCeleron = 0x0F,
kSMBprocessorFamilyPentiumIIXeon = 0x10,
kSMBprocessorFamilyPentiumIII = 0x11,
kSMBprocessorFamilyM1 = 0x12,
kSMBprocessorFamilyM2 = 0x13,
kSMBprocessorFamilyIntelCeleronM = 0x14,
kSMBprocessorFamilyIntelPentium4Ht = 0x15,
kSMBprocessorFamilyM1Reserved4 = 0x16,
kSMBprocessorFamilyM1Reserved5 = 0x17,
kSMBprocessorFamilyAmdDuron = 0x18,
kSMBprocessorFamilyK5 = 0x19,
kSMBprocessorFamilyK6 = 0x1A,
kSMBprocessorFamilyK6_2 = 0x1B,
kSMBprocessorFamilyK6_3 = 0x1C,
kSMBprocessorFamilyAmdAthlon = 0x1D,
kSMBprocessorFamilyAmd29000 = 0x1E,
kSMBprocessorFamilyK6_2Plus = 0x1F,
kSMBprocessorFamilyPowerPC = 0x20,
kSMBprocessorFamilyPowerPC601 = 0x21,
kSMBprocessorFamilyPowerPC603 = 0x22,
kSMBprocessorFamilyPowerPC603Plus = 0x23,
kSMBprocessorFamilyPowerPC604 = 0x24,
kSMBprocessorFamilyPowerPC620 = 0x25,
kSMBprocessorFamilyPowerPCx704 = 0x26,
kSMBprocessorFamilyPowerPC750 = 0x27,
kSMBprocessorFamilyIntelCoreDuo = 0x28,
kSMBprocessorFamilyIntelCoreDuoMobile = 0x29,
kSMBprocessorFamilyIntelCoreSoloMobile = 0x2A,
kSMBprocessorFamilyIntelAtom = 0x2B,
kSMBprocessorFamilyAlpha3 = 0x30,
kSMBprocessorFamilyAlpha21064 = 0x31,
kSMBprocessorFamilyAlpha21066 = 0x32,
kSMBprocessorFamilyAlpha21164 = 0x33,
kSMBprocessorFamilyAlpha21164PC = 0x34,
kSMBprocessorFamilyAlpha21164a = 0x35,
kSMBprocessorFamilyAlpha21264 = 0x36,
kSMBprocessorFamilyAlpha21364 = 0x37,
kSMBprocessorFamilyAmdTurionIIUltraDualCoreMobileM = 0x38,
kSMBprocessorFamilyAmdTurionIIDualCoreMobileM = 0x39,
kSMBprocessorFamilyAmdAthlonIIDualCoreM = 0x3A,
kSMBprocessorFamilyAmdOpteron6100Series = 0x3B,
kSMBprocessorFamilyAmdOpteron4100Series = 0x3C,
kSMBprocessorFamilyAmdOpteron6200Series = 0x3D,
kSMBprocessorFamilyAmdOpteron4200Series = 0x3E,
kSMBprocessorFamilyMips = 0x40,
kSMBprocessorFamilyMIPSR4000 = 0x41,
kSMBprocessorFamilyMIPSR4200 = 0x42,
kSMBprocessorFamilyMIPSR4400 = 0x43,
kSMBprocessorFamilyMIPSR4600 = 0x44,
kSMBprocessorFamilyMIPSR10000 = 0x45,
kSMBprocessorFamilyAmdCSeries = 0x46,
kSMBprocessorFamilyAmdESeries = 0x47,
kSMBprocessorFamilyAmdSSeries = 0x48,
kSMBprocessorFamilyAmdGSeries = 0x49,
kSMBprocessorFamilySparc = 0x50,
kSMBprocessorFamilySuperSparc = 0x51,
kSMBprocessorFamilymicroSparcII = 0x52,
kSMBprocessorFamilymicroSparcIIep = 0x53,
kSMBprocessorFamilyUltraSparc = 0x54,
kSMBprocessorFamilyUltraSparcII = 0x55,
kSMBprocessorFamilyUltraSparcIIi = 0x56,
kSMBprocessorFamilyUltraSparcIII = 0x57,
kSMBprocessorFamilyUltraSparcIIIi = 0x58,
kSMBprocessorFamily68040 = 0x60,
kSMBprocessorFamily68xxx = 0x61,
kSMBprocessorFamily68000 = 0x62,
kSMBprocessorFamily68010 = 0x63,
kSMBprocessorFamily68020 = 0x64,
kSMBprocessorFamily68030 = 0x65,
kSMBprocessorFamilyHobbit = 0x70,
kSMBprocessorFamilyCrusoeTM5000 = 0x78,
kSMBprocessorFamilyCrusoeTM3000 = 0x79,
kSMBprocessorFamilyEfficeonTM8000 = 0x7A,
kSMBprocessorFamilyWeitek = 0x80,
kSMBprocessorFamilyItanium = 0x82,
kSMBprocessorFamilyAmdAthlon64 = 0x83,
kSMBprocessorFamilyAmdOpteron = 0x84,
kSMBprocessorFamilyAmdSempron = 0x85,
kSMBprocessorFamilyAmdTurion64Mobile = 0x86,
kSMBprocessorFamilyDualCoreAmdOpteron = 0x87,
kSMBprocessorFamilyAmdAthlon64X2DualCore = 0x88,
kSMBprocessorFamilyAmdTurion64X2Mobile = 0x89,
kSMBprocessorFamilyQuadCoreAmdOpteron = 0x8A,
kSMBprocessorFamilyThirdGenerationAmdOpteron = 0x8B,
kSMBprocessorFamilyAmdPhenomFxQuadCore = 0x8C,
kSMBprocessorFamilyAmdPhenomX4QuadCore = 0x8D,
kSMBprocessorFamilyAmdPhenomX2DualCore = 0x8E,
kSMBprocessorFamilyAmdAthlonX2DualCore = 0x8F,
kSMBprocessorFamilyPARISC = 0x90,
kSMBprocessorFamilyPaRisc8500 = 0x91,
kSMBprocessorFamilyPaRisc8000 = 0x92,
kSMBprocessorFamilyPaRisc7300LC = 0x93,
kSMBprocessorFamilyPaRisc7200 = 0x94,
kSMBprocessorFamilyPaRisc7100LC = 0x95,
kSMBprocessorFamilyPaRisc7100 = 0x96,
kSMBprocessorFamilyV30 = 0xA0,
kSMBprocessorFamilyQuadCoreIntelXeon3200Series = 0xA1,
kSMBprocessorFamilyDualCoreIntelXeon3000Series = 0xA2,
kSMBprocessorFamilyQuadCoreIntelXeon5300Series = 0xA3,
kSMBprocessorFamilyDualCoreIntelXeon5100Series = 0xA4,
kSMBprocessorFamilyDualCoreIntelXeon5000Series = 0xA5,
kSMBprocessorFamilyDualCoreIntelXeonLV = 0xA6,
kSMBprocessorFamilyDualCoreIntelXeonULV = 0xA7,
kSMBprocessorFamilyDualCoreIntelXeon7100Series = 0xA8,
kSMBprocessorFamilyQuadCoreIntelXeon5400Series = 0xA9,
kSMBprocessorFamilyQuadCoreIntelXeon = 0xAA,
kSMBprocessorFamilyDualCoreIntelXeon5200Series = 0xAB,
kSMBprocessorFamilyDualCoreIntelXeon7200Series = 0xAC,
kSMBprocessorFamilyQuadCoreIntelXeon7300Series = 0xAD,
kSMBprocessorFamilyQuadCoreIntelXeon7400Series = 0xAE,
kSMBprocessorFamilyMultiCoreIntelXeon7400Series = 0xAF,
kSMBprocessorFamilyPentiumIIIXeon = 0xB0,
kSMBprocessorFamilyPentiumIIISpeedStep = 0xB1,
kSMBprocessorFamilyPentium4 = 0xB2,
kSMBprocessorFamilyIntelXeon = 0xB3,
kSMBprocessorFamilyAS400 = 0xB4,
kSMBprocessorFamilyIntelXeonMP = 0xB5,
kSMBprocessorFamilyAMDAthlonXP = 0xB6,
kSMBprocessorFamilyAMDAthlonMP = 0xB7,
kSMBprocessorFamilyIntelItanium2 = 0xB8,
kSMBprocessorFamilyIntelPentiumM = 0xB9,
kSMBprocessorFamilyIntelCeleronD = 0xBA,
kSMBprocessorFamilyIntelPentiumD = 0xBB,
kSMBprocessorFamilyIntelPentiumEx = 0xBC,
kSMBprocessorFamilyIntelCoreSolo = 0xBD, ///< SMBIOS spec 2.6 correct this value
kSMBprocessorFamilyReserved = 0xBE,
kSMBprocessorFamilyIntelCore2 = 0xBF,
kSMBprocessorFamilyIntelCore2Solo = 0xC0,
kSMBprocessorFamilyIntelCore2Extreme = 0xC1,
kSMBprocessorFamilyIntelCore2Quad = 0xC2,
kSMBprocessorFamilyIntelCore2ExtremeMobile = 0xC3,
kSMBprocessorFamilyIntelCore2DuoMobile = 0xC4,
kSMBprocessorFamilyIntelCore2SoloMobile = 0xC5,
kSMBprocessorFamilyIntelCoreI7 = 0xC6,
kSMBprocessorFamilyDualCoreIntelCeleron = 0xC7,
kSMBprocessorFamilyIBM390 = 0xC8,
kSMBprocessorFamilyG4 = 0xC9,
kSMBprocessorFamilyG5 = 0xCA,
kSMBprocessorFamilyG6 = 0xCB,
kSMBprocessorFamilyzArchitectur = 0xCC,
kSMBprocessorFamilyIntelCoreI5 = 0xCD,
kSMBprocessorFamilyIntelCoreI3 = 0xCE,
kSMBprocessorFamilyViaC7M = 0xD2,
kSMBprocessorFamilyViaC7D = 0xD3,
kSMBprocessorFamilyViaC7 = 0xD4,
kSMBprocessorFamilyViaEden = 0xD5,
kSMBprocessorFamilyMultiCoreIntelXeon = 0xD6,
kSMBprocessorFamilyDualCoreIntelXeon3Series = 0xD7,
kSMBprocessorFamilyQuadCoreIntelXeon3Series = 0xD8,
kSMBprocessorFamilyViaNano = 0xD9,
kSMBprocessorFamilyDualCoreIntelXeon5Series = 0xDA,
kSMBp