Chameleon

Chameleon Commit Details

Date:2015-04-29 15:04:07 (8 years 11 months ago)
Author:ErmaC
Commit:2665
Parents: 2664
Message:Update data for embedded HDA enabler.
Changes:
M/trunk/i386/libsaio/hda.h
M/trunk/i386/libsaio/hda.c

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trunk/i386/libsaio/hda.c
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␊
static hda_controller_devices know_hda_controller[] = {␊
␉//8086 Intel Corporation␊
␉{ HDA_INTEL_OAK,␉"Oaktrail"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_BAY,␉"BayTrail"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_HSW1,␉"Haswell"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_HSW2,␉"Haswell"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_HSW3,␉"Haswell"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_CPT,␉"Cougar Point"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_PATSBURG,␉"Patsburg"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_PPT1,␉"Panther Point"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_LPT1,␉"Lynx Point"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_LPT2,␉"Lynx Point"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_WCPT,␉"Wildcat Point"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_WELLS1,␉"Wellsburg"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_WELLS2,␉"Wellsburg"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_LPTLP1,␉"Lynx Point-LP"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_LPTLP2,␉"Lynx Point-LP"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801F,␉"82801F"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_63XXESB,␉"631x/632xESB"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801G,␉"82801G"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801H,␉"82801H"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801I,␉"82801I"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801JI,␉"82801JI"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801JD,␉"82801JD"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_PCH,␉"5 Series/3400 Series" /*, 0, 0 */ },␊
␉{ HDA_INTEL_PCH2,␉"5 Series/3400 Series" /*, 0, 0 */ },␊
␉{ HDA_INTEL_SCH,␉"SCH"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_OAK,␉"Oaktrail"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_BAY,␉"BayTrail"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_HSW1,␉"Haswell"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_HSW2,␉"Haswell"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_HSW3,␉"Haswell"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_BDW,␉"Broadwell"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_CPT,␉"Cougar Point"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_PATSBURG,␉"Patsburg"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_PPT1,␉"Panther Point"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_BRASWELL,␉"Braswell"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801F,␉"82801F"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_63XXESB,␉"631x/632xESB"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801G,␉"82801G"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801H,␉"82801H"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801I,␉"82801I"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_ICH9,␉"ICH9"␉␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801JI,␉"82801JI"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_82801JD,␉"82801JD"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_PCH,␉"5 Series/3400 Series"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_PCH2,␉"5 Series/3400 Series"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_SCH,␉"SCH"␉␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_LPT1,␉"Lynx Point"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_LPT2,␉"Lynx Point"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_WCPT,␉"Wildcat Point"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_WELLS1,␉"Wellsburg"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_WELLS2,␉"Wellsburg"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_WCPTLP,␉"Wildcat Point-LP"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_LPTLP1,␉"Lynx Point-LP"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_LPTLP2,␉"Lynx Point-LP"␉␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_SRSPLP,␉"Sunrise Point-LP"␉/*, 0, 0 */ },␊
␉{ HDA_INTEL_SRSP,␉"Sunrise Point"␉␉/*, 0, 0 */ },␊
␊
␉//10de NVIDIA Corporation␊
␉{ HDA_NVIDIA_MCP51,␉"MCP51" /*, 0, HDAC_QUIRK_MSI */ },␊
␉{ HDA_NVIDIA_MCP55,␉"MCP55" /*, 0, HDAC_QUIRK_MSI */ },␊
␉{ HDA_ATI_SB450,␉"SB4x0" /*, 0, 0 */ },␊
␉{ HDA_ATI_SB600,␉"SB600" /*, 0, 0 */ },␊
␉{ HDA_ATI_RS600,␉"RS600" /*, 0, 0 */ },␊
␉{ HDA_ATI_HUDSON,␉"Hudson" /*, 0, 0 */ },␊
␉{ HDA_ATI_RS690,␉"RS690" /*, 0, 0 */ },␊
␉{ HDA_ATI_RS780,␉"RS780" /*, 0, 0 */ },␊
␉{ HDA_ATI_RS880,␉"RS880" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV940,␉"RV940" /*, 0, 0 */ },␊
␉{ HDA_ATI_RV970,␉"RV970" /*, 0, 0 */ },␊
␉{ HDA_ATI_R1000,␉"R1000" /*, 0, 0 */ }, // HDMi␊
␉{ HDA_ATI_SI,␉␉"SI" /*, 0, 0 */ },␊
␉{ HDA_ATI_VERDE,␉"Cape Verde" /*, 0, ? */ }, // HDMi␊
␉//17f3 RDC Semiconductor, Inc.␊
␉{ HDA_RDC_M3010,␉"M3010" /*, 0, 0 */ },␊
␉{ HDA_CODEC_CS4206, 0, "Cirrus Logic CS4206" },␊
␉{ HDA_CODEC_CS4207, 0, "Cirrus Logic CS4207" },␊
␉{ HDA_CODEC_CS4210, 0, "Cirrus Logic CS4210" },␊
␊
␉{ HDA_CODEC_ALC221, 0, "Realtek ALC221" },␊
␉{ HDA_CODEC_ALC260, 0, "Realtek ALC260" },␊
␉{ HDA_CODEC_ALC262, 0, "Realtek ALC262" },␊
␉␉case HDA_INTEL_HSW1:␊
␉␉case HDA_INTEL_HSW2:␊
␉␉case HDA_INTEL_HSW3:␊
␉␉case HDA_INTEL_BDW:␊
␉␉case HDA_INTEL_CPT:␊
␉␉case HDA_INTEL_PATSBURG:␊
␉␉case HDA_INTEL_PPT1:␊
␉␉case HDA_INTEL_LPT1:␊
␉␉case HDA_INTEL_LPT2:␊
␉␉case HDA_INTEL_WCPT:␊
␉␉case HDA_INTEL_WELLS1:␊
␉␉case HDA_INTEL_WELLS2:␊
␉␉case HDA_INTEL_LPTLP1:␊
␉␉case HDA_INTEL_LPTLP2:␊
␉␉case HDA_INTEL_BRASWELL:␊
␉␉case HDA_INTEL_82801F:␊
␉␉case HDA_INTEL_63XXESB:␊
␉␉case HDA_INTEL_82801G:␊
␉␉case HDA_INTEL_82801H:␊
␉␉case HDA_INTEL_82801I:␊
␉␉case HDA_INTEL_ICH9:␊
␉␉case HDA_INTEL_82801JI:␊
␉␉case HDA_INTEL_82801JD:␊
␉␉case HDA_INTEL_PCH:␊
␉␉case HDA_INTEL_PCH2:␊
␉␉case HDA_INTEL_SCH:␊
␉␉case HDA_INTEL_LPT1:␊
␉␉case HDA_INTEL_LPT2:␊
␉␉case HDA_INTEL_WCPT:␊
␉␉case HDA_INTEL_WELLS1:␊
␉␉case HDA_INTEL_WELLS2:␊
␉␉case HDA_INTEL_WCPTLP:␊
␉␉case HDA_INTEL_LPTLP1:␊
␉␉case HDA_INTEL_LPTLP2:␊
␉␉case HDA_INTEL_SRSPLP:␊
␉␉case HDA_INTEL_SRSP:␊
␊
␉/* if the key value kHDEFLayoutID as a value set that value, if not will assign a default layout */␊
␉if (getValueForKey(kHDEFLayoutID, &value, &len, &bootInfo->chameleonConfig) && len == HDEF_LEN * 2)␊
␉*************************************************************************************************************/␊
␉case HDA_ATI_SB450:␊
␉case HDA_ATI_SB600:␊
␉case HDA_ATI_HUDSON:␊
␉case HDA_ATI_RS600:␊
␉case HDA_ATI_RS690:␊
␉case HDA_ATI_RS780:␊
␉case HDA_ATI_RV930:␊
␉case HDA_ATI_RV910:␊
␉case HDA_ATI_R1000:␊
␉case HDA_ATI_SI:␊
␉case HDA_ATI_VERDE:␊
␊
/* if the key value kHDAULayoutID as a value set that value, if not will assign a default layout */␊
trunk/i386/libsaio/hda.h
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␊
/* Intel */␊
#define INTEL_VENDORID␉␉0x8086␊
#define HDA_INTEL_OAK␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x080a) // NEW␊
#define HDA_INTEL_BAY␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0f04) // NEW␊
#define HDA_INTEL_OAK␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x080a)␊
#define HDA_INTEL_BAY␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0f04)␊
#define HDA_INTEL_HSW1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0a0c)␊
#define HDA_INTEL_HSW2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0c0c)␊
#define HDA_INTEL_HSW3␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0d0c)␊
#define HDA_INTEL_BDW␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x160c)␊
#define HDA_INTEL_CPT␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x1c20)␊
#define HDA_INTEL_PATSBURG␉HDA_MODEL_CONSTRUCT(INTEL, 0x1d20)␊
#define HDA_INTEL_PPT1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x1e20) // Macmini6,2␊
#define HDA_INTEL_BRASWELL ␉HDA_MODEL_CONSTRUCT(INTEL, 0x2284)␊
#define HDA_INTEL_82801F␉HDA_MODEL_CONSTRUCT(INTEL, 0x2668)␊
#define HDA_INTEL_63XXESB␉HDA_MODEL_CONSTRUCT(INTEL, 0x269a)␊
#define HDA_INTEL_82801G␉HDA_MODEL_CONSTRUCT(INTEL, 0x27d8)␊
#define HDA_INTEL_82801H␉HDA_MODEL_CONSTRUCT(INTEL, 0x284b)␊
#define HDA_INTEL_82801I␉HDA_MODEL_CONSTRUCT(INTEL, 0x293e)␊
#define HDA_INTEL_ICH9␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x293f)␊
#define HDA_INTEL_82801JI␉HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e)␊
#define HDA_INTEL_82801JD␉HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e)␊
#define HDA_INTEL_PCH␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x3b56)␊
#define HDA_INTEL_PCH2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x3b57)␊
#define HDA_INTEL_MACBOOKPRO92␉HDA_MODEL_CONSTRUCT(INTEL, 0x7270) // NEW␊
#define HDA_INTEL_MACBOOKPRO92␉HDA_MODEL_CONSTRUCT(INTEL, 0x7270)␊
#define HDA_INTEL_SCH␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x811b)␊
#define HDA_INTEL_LPT1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8c20) // NEW␊
#define HDA_INTEL_LPT2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8c21) // NEW␊
#define HDA_INTEL_LPT1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8c20)␊
#define HDA_INTEL_LPT2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8c21)␊
#define HDA_INTEL_WCPT␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8ca0)␊
#define HDA_INTEL_WELLS1␉HDA_MODEL_CONSTRUCT(INTEL, 0x8d20)␊
#define HDA_INTEL_WELLS2␉HDA_MODEL_CONSTRUCT(INTEL, 0x8d21)␊
#define HDA_INTEL_WCPTLP ␉HDA_MODEL_CONSTRUCT(INTEL, 0x9ca0)␊
#define HDA_INTEL_LPTLP1␉HDA_MODEL_CONSTRUCT(INTEL, 0x9c20)␊
#define HDA_INTEL_LPTLP2␉HDA_MODEL_CONSTRUCT(INTEL, 0x9c21)␊
#define HDA_INTEL_SRSPLP ␉HDA_MODEL_CONSTRUCT(INTEL, 0x9d70)␊
#define HDA_INTEL_SRSP␉␉HDA_MODEL_CONSTRUCT(INTEL, 0xa170)␊
#define HDA_INTEL_ALL␉␉HDA_MODEL_CONSTRUCT(INTEL, 0xffff)␊
␊
/* Nvidia */␊
#define ATI_VENDORID␉␉0x1002␊
#define HDA_ATI_SB450␉␉HDA_MODEL_CONSTRUCT(ATI, 0x437b)␊
#define HDA_ATI_SB600␉␉HDA_MODEL_CONSTRUCT(ATI, 0x4383)␊
#define HDA_ATI_HUDSON␉␉HDA_MODEL_CONSTRUCT(ATI, 0x780d)␊
#define HDA_ATI_RS600␉␉HDA_MODEL_CONSTRUCT(ATI, 0x793b)␊
#define HDA_ATI_RS690␉␉HDA_MODEL_CONSTRUCT(ATI, 0x7919)␊
#define HDA_ATI_RS780␉␉HDA_MODEL_CONSTRUCT(ATI, 0x960f)␊
#define HDA_ATI_RV930␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa90)␊
#define HDA_ATI_RV910␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa98)␊
#define HDA_ATI_R1000␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaaa0)␊
#define HDA_ATI_SI␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaaa8)␊
#define HDA_ATI_VERDE␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaab0)␊
#define HDA_ATI_ALL␉␉HDA_MODEL_CONSTRUCT(ATI, 0xffff)␊
␊

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Revision: 2665