Chameleon

Chameleon Commit Details

Date:2015-04-29 15:07:26 (4 years 2 months ago)
Author:ErmaC
Commit:2666
Parents: 2665
Message:Typo.
Changes:
M/trunk/i386/libsaio/spd.c
M/trunk/i386/libsaio/dram_controllers.c
M/trunk/i386/libsaio/platform.h
M/trunk/i386/libsaio/sys.c
M/trunk/i386/libsaio/hpet.c

File differences

trunk/i386/libsaio/spd.c
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static struct smbus_controllers_t smbus_controllers[] = {
{0x8086, 0x1C22, "P67", read_smb_intel }, // Z68, Q67
{0x8086, 0x1D22, "X79", read_smb_intel },
{0x8086, 0x1D70, "X79", read_smb_intel },
{0x8086, 0x1D71, "X79", read_smb_intel },
{0x8086, 0x1D72, "C608", read_smb_intel },
{0x8086, 0x1E22, "Z77", read_smb_intel }, // H77, Q77
{0x8086, 0x2330, "DH89xxCC", read_smb_intel },
{0x8086, 0x2413, "82801AA", read_smb_intel },
{0x8086, 0x2423, "BAM", read_smb_intel },
{0x8086, 0x2443, "BAM", read_smb_intel },
{0x8086, 0x2483, "CAM", read_smb_intel },
{0x8086, 0x24C3, "ICH4", read_smb_intel },
{0x8086, 0x24D3, "ICH5", read_smb_intel },
{0x8086, 0x25A4, "6300ESB", read_smb_intel },
{0x8086, 0x266A, "ICH6", read_smb_intel },
{0x8086, 0x269B, "ESB", read_smb_intel },
{0x8086, 0x27DA, "ICH7", read_smb_intel },
{0x8086, 0x283E, "ICH8", read_smb_intel },
{0x8086, 0x2930, "ICH9", read_smb_intel },
{0x8086, 0x3A30, "ICH10", read_smb_intel },
{0x8086, 0x3A60, "ICH10", read_smb_intel },
{0x8086, 0x3B30, "P55", read_smb_intel },
{0x8086, 0x5032, "EP80579", read_smb_intel },
{0x8086, 0x8119, "US15W", read_smb_intel },
{0x8086, 0x8C22, "HSW", read_smb_intel }, // Z87, H87, Q87, H81
{0x8086, 0x8CA2, "Z97/H97", read_smb_intel }, // new
{0x8086, 0x8D22, "X99", read_smb_intel }, // new
{0x8086, 0x9C22, "HSW-ULT", read_smb_intel }
// Intel
{0x8086, 0x1C22, "P67",read_smb_intel },
{0x8086, 0x1D22, "X79",read_smb_intel },
{0x8086, 0x1D70, "X79",read_smb_intel },
{0x8086, 0x1D71, "X79",read_smb_intel },
{0x8086, 0x1D72, "C608",read_smb_intel },
{0x8086, 0x1E22, "Z77",read_smb_intel },
{0x8086, 0x2330, "DH89xxCC",read_smb_intel },
{0x8086, 0x2413, "82801AA",read_smb_intel },
{0x8086, 0x2423, "BAM",read_smb_intel },
{0x8086, 0x2443, "BAM",read_smb_intel },
{0x8086, 0x2483, "CAM",read_smb_intel },
{0x8086, 0x24C3, "ICH4",read_smb_intel },
{0x8086, 0x24D3, "ICH5",read_smb_intel },
{0x8086, 0x25A4, "6300ESB",read_smb_intel },
{0x8086, 0x266A, "ICH6",read_smb_intel },
{0x8086, 0x269B, "ESB",read_smb_intel },
{0x8086, 0x27DA, "ICH7",read_smb_intel },
{0x8086, 0x283E, "ICH8",read_smb_intel },
{0x8086, 0x2930, "ICH9",read_smb_intel },
{0x8086, 0x3A30, "ICH10",read_smb_intel },
{0x8086, 0x3A60, "ICH10",read_smb_intel },
{0x8086, 0x3B30, "P55",read_smb_intel },
{0x8086, 0x5032, "EP80579",read_smb_intel },
{0x8086, 0x8119, "US15W",read_smb_intel },
{0x8086, 0x8C22, "HSW",read_smb_intel },
{0x8086, 0x8CA2, "Z97/H97",read_smb_intel },
{0x8086, 0x8D22, "X99",read_smb_intel },
{0x8086, 0x9C22, "HSW-ULT",read_smb_intel }
// AMD
//0x1002 0x4385 "AMD SB600/700"
//0x1022 0x780B "AMD SB800/900"
};
// initial call : pci_dt = root_pci_dev;
trunk/i386/libsaio/dram_controllers.c
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void scan_dram_controller(pci_dt_t *dram_dev)
{
int i;
for(i = 1; i < sizeof(dram_controllers) / sizeof(dram_controllers[0]); i++) {
for(i = 1; i < sizeof(dram_controllers) / sizeof(dram_controllers[0]); i++)
{
if ((dram_controllers[i].vendor == dram_dev->vendor_id) && (dram_controllers[i].device == dram_dev->device_id)) {
verbose("%s%s DRAM Controller [%4x:%4x] at %02x:%02x.%x\n",
(dram_dev->vendor_id == 0x8086) ? "Intel Corporation " : "" ,
(dram_dev->vendor_id == 0x8086) ? "Intel " : "" ,
dram_controllers[i].name, dram_dev->vendor_id, dram_dev->device_id,
dram_dev->dev.bits.bus, dram_dev->dev.bits.dev, dram_dev->dev.bits.func);
trunk/i386/libsaio/sys.c
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#endif
#ifndef DEBUG_SYS
#define DEBUG_SYS 0
#define DEBUG_SYS 0
#endif
#if DEBUG_SYS
#define DBG(x...)printf(x)
#define DBG(x...)printf(x)
#else
#define DBG(x...)msglog(x)
#define DBG(x...)msglog(x)
#endif
#ifndef DEBUG_FEATURE_LAST_BOOT
#define DEBUG_FEATURE_LAST_BOOT 0 // AllocateKernelMemory error with feature from 2562
#define DEBUG_FEATURE_LAST_BOOT 0 // AllocateKernelMemory error with feature from 2562
#endif
extern int multiboot_partition;
trunk/i386/libsaio/platform.h
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#define CPUID_EXTFEATURE_EM64Tbit(29)/* Extended Mem 64 Technology */
#define CPUID_EXTFEATURE_LAHFhbit(0)/* LAFH/SAHF instructions */
/*
#define MSR_CONFIG_TDP_CONTROL0x64B// write once to lock
#define MSR_TURBO_ACTIVATION_RATIO0x64C
//AMD
/* AMD Defined MSRs */
#define MSR_K6_EFER0xC0000080
#define MSR_K6_STAR0xC0000081
#define MSR_K6_WHCR0xC0000082
#define MSR_K6_UWCCR0xC0000085
#define MSR_K6_EPMR0xC0000086
#define MSR_K6_PSOR0xC0000087
#define MSR_K6_PFIR0xC0000088
#define MSR_K7_EVNTSEL00xC0010000
#define MSR_K7_PERFCTR00xC0010004
#define MSR_K7_HWCR0xC0010015
#define MSR_K7_CLK_CTL0xC001001b
#define MSR_K7_FID_VID_CTL0xC0010041
#define K8_FIDVID_STATUS0xC0010042
#define K10_COFVID_LIMIT0xC0010061// max enabled p-state (msr >> 4) & 7
#define K10_COFVID_CONTROL0xC0010062// switch to p-state
uint64_tFrequency;// Ram Frequency
uint32_tDivider;// Memory divider
uint8_tCAS;// CAS 1/2/2.5/3/4/5/6/7
uint8_tTRC;
uint8_tTRC;
uint8_tTRP;
uint8_tRAS;
uint8_tChannels;// Channel Configuration Single,Dual or Triple
uint8_tChannels;// Channel Configuration Single,Dual, Triple or Quad
uint8_tNoSlots;// Maximum no of slots available
uint8_tType;// Standard SMBIOS v2.5 Memory Type
RamSlotInfo_tDIMM[MAX_RAM_SLOTS];// Information about each slot
trunk/i386/libsaio/hpet.c
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/*
*
* Copyright (c) 2009 Evan Lojewski. All rights reserved.
*/
/*
* High Precision Event Timer (HPET)
*/
#include "libsaio.h"
#include "pci.h"
#include "hpet.h"

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Revision: 2666