Chameleon

Chameleon Commit Details

Date:2015-05-09 17:15:19 (8 years 11 months ago)
Author:ErmaC
Commit:2670
Parents: 2669
Message:Typo
Changes:
M/trunk/i386/libsaio/hda.h
M/trunk/i386/libsaio/gma.c
M/trunk/i386/libsaio/dram_controllers.c
M/trunk/i386/libsaio/gma.h
M/trunk/i386/libsaio/hda.c

File differences

trunk/i386/libsaio/gma.c
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#include "graphics.h"␊
␊
#ifndef DEBUG_GMA␊
#define DEBUG_GMA 0␊
␉#define DEBUG_GMA 0␊
#endif␊
␊
#ifndef DEBUG_BDW␊
trunk/i386/libsaio/gma.h
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#define IRIS_6100 "Iris Graphics 6100"␊
#define IRIS_6200 "Iris Pro Graphics 6200"␊
#define IRIS_6300 "Iris Pro Graphics P6300"␊
#define INTEL_VENDORID 0x8086␊
#define INTEL_VENDORID 0x8086␊
␊
/* http://cgit.freedesktop.org/xorg/driver/xf86-video-intel/tree/src/intel_driver.h */␊
/* http://people.redhat.com/agk/patches/linux/patches-3.6/git-update1.patch */␊
trunk/i386/libsaio/hda.c
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␉{ HDA_CODEC_ALC665, 0, "Realtek ALC665" },␊
␉{ HDA_CODEC_ALC670, 0, "Realtek ALC670" },␊
␉{ HDA_CODEC_ALC680, 0, "Realtek ALC680" },␊
␉{ HDA_CODEC_ALC861, 0x100340, "Realtek ALC660" },␊
␉{ HDA_CODEC_ALC861, 0x100340, "Realtek ALC660" },␊
␉{ HDA_CODEC_ALC861, 0, "Realtek ALC861" },␊
␉{ HDA_CODEC_ALC861VD, 0, "Realtek ALC861-VD" },␊
␉{ HDA_CODEC_ALC880, 0, "Realtek ALC880" },␊
␉{ HDA_CODEC_ALC882, 0, "Realtek ALC882" },␊
␉{ HDA_CODEC_ALC883, 0, "Realtek ALC883" },␊
␉{ HDA_CODEC_ALC885, 0x100101, "Realtek ALC889A" },␊
␉{ HDA_CODEC_ALC885, 0x100103, "Realtek ALC889A" },␊
␉{ HDA_CODEC_ALC885, 0x100101, "Realtek ALC889A" },␊
␉{ HDA_CODEC_ALC885, 0x100103, "Realtek ALC889A" },␊
␉{ HDA_CODEC_ALC885, 0, "Realtek ALC885" },␊
␉{ HDA_CODEC_ALC887, 0, "Realtek ALC887" },␊
␉{ HDA_CODEC_ALC888, 0x100101, "Realtek ALC1200" },␊
␉{ HDA_CODEC_ALC888, 0x100101, "Realtek ALC1200" },␊
␉{ HDA_CODEC_ALC888, 0, "Realtek ALC888" },␊
␉{ HDA_CODEC_ALC889, 0, "Realtek ALC889" },␊
␉{ HDA_CODEC_ALC892, 0, "Realtek ALC892" },␊
trunk/i386/libsaio/hda.h
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......
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* instead of their own, which is beyond my comprehension␊
* (see HDA_CODEC_STAC9221 below).␊
*/␊
#define APPLE_INTEL_MAC␉␉0x76808384␊
#define APPLE_MACBOOKPRO55␉0xcb7910de␊
#define APPLE_INTEL_MAC 0x76808384␊
#define APPLE_MACBOOKAIR31 0x0d9410de␊
#define APPLE_MACBOOKPRO55 0xcb7910de␊
#define APPLE_MACBOOKPRO71 0xcb8910de␊
␊
/* LG Electronics */␊
#define LG_VENDORID␉␉0x1854␊
#define HDA0_LEN ( sizeof(default_HDEF_layout_id) / sizeof(uint8_t) )␊
#define HDA1_LEN ( sizeof(default_HDAU_layout_id) / sizeof(uint8_t) )␊
␊
/* codec information */␊
/* =================== C O D E C I N F O R M A T I O N ===================== */␊
␊
#define HDA_CODEC_CONSTRUCT(vendor, id) (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff))␊
␊
/* Cirrus Logic */␊
#define HDA_CODEC_INTELIP2␉HDA_CODEC_CONSTRUCT(INTEL, 0x2804)␊
#define HDA_CODEC_INTELCPT␉HDA_CODEC_CONSTRUCT(INTEL, 0x2805)␊
#define HDA_CODEC_INTELPPT␉HDA_CODEC_CONSTRUCT(INTEL, 0x2806)␊
#define HDA_CODEC_INTELHSW␉HDA_CODEC_CONSTRUCT(INTEL, 0x2807)␊
#define HDA_CODEC_INTELLLP␉HDA_CODEC_CONSTRUCT(INTEL, 0x2807)␊
#define HDA_CODEC_INTELCL␉HDA_CODEC_CONSTRUCT(INTEL, 0x29fb)␊
#define HDA_CODEC_INTELXXXX␉HDA_CODEC_CONSTRUCT(INTEL, 0xffff)␊
␊
trunk/i386/libsaio/dram_controllers.c
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//␉{ 0x8086, 0x0BF6, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
//␉{ 0x8086, 0x0BF7, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
␊
//␉{ 0x8086, 0x0C00, "Haswell",␉NULL, NULL, NULL },␊
//␉{ 0x8086, 0x0C04, "Haswell",␉NULL, NULL, NULL },␊
//␉{ 0x8086, 0x0C08, "Haswell",␉NULL, NULL, NULL },␊
//␉{ 0x8086, 0x0C00, "Haswell",␉␉␉NULL, NULL, NULL },␊
//␉{ 0x8086, 0x0C04, "Haswell",␉␉␉NULL, NULL, NULL },␊
//␉{ 0x8086, 0x0C08, "Haswell",␉␉␉NULL, NULL, NULL },␊
␊
␉{ 0x8086, 0x7190, "VMWare",␉NULL, NULL, NULL },␊
␉{ 0x8086, 0x7190, "VMWare",␉␉␉NULL, NULL, NULL },␊
␊
␉{ 0x8086, 0x1A30, "82845 845 [Brookdale]",␉NULL, NULL, NULL },␊
␉␊
␉{ 0x8086, 0x2970, "82946GZ/PL/GL",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊
␉{ 0x8086, 0x2990, "82Q963/Q965",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊
␉{ 0x8086, 0x29A0, "P965/G965",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊
␉{ 0x8086, 0x29A0, "P965/G965",␉␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊
␊
␉{ 0x8086, 0x2A00, "GM965/GL960",␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
␉{ 0x8086, 0x2A10, "GME965/GLE960",␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
␉{ 0x8086, 0x2A40, "PM/GM45/47",␉␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
␉{ 0x8086, 0x2A00, "GM965/GL960",␉␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
␉{ 0x8086, 0x2A10, "GME965/GLE960",␉␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
␉{ 0x8086, 0x2A40, "PM/GM45/47",␉␉␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
␊
␉{ 0x8086, 0x29B0, "82Q35 Express",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x29C0, "82G33/G31/P35/P31",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x29D0, "82Q33 Express",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x29E0, "82X38/X48 Express",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x29B0, "Q35",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x29C0, "P35/G33",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x29D0, "Q33",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x29E0, "X38/X48",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x29F0, "3200/3210",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␊
␉{ 0x8086, 0x2E00, "Eaglelake",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x2E10, "Q45/Q43",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x2E20, "P45/G45",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x2E30, "G41",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
//␉{ 0x8086, 0x2E40, "4 Series Chipset",␉␉NULL, NULL, NULL },␊
//␉{ 0x8086, 0x2E90, "4 Series Chipset",␉␉NULL, NULL, NULL },␊
␉{ 0x8086, 0x2E00, "Eaglelake",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x2E10, "Q45/Q43",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x2E20, "P45/G45",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␉{ 0x8086, 0x2E30, "G41",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
␊
␉{ 0x8086, 0xD131, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0xD132, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0xD131, "NHM IMC",␉␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0xD132, "NHM IMC",␉␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3400, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3401, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3402, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3403, "5500",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3403, "5500",␉␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3404, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3405, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3406, "5520",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3406, "5520",␉␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
␉{ 0x8086, 0x3407, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
};␊
␊
static const char *memory_channel_types[] =␊
{␊
␉"Unknown", "Single", "Dual", "Triple"␊
␉"Unknown", "Single", "Dual", "Triple" /*, "Quad" */␊
};␊
␊
void scan_dram_controller(pci_dt_t *dram_dev)␊

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Revision: 2670