Chameleon

Chameleon Commit Details

Date:2010-07-28 04:57:57 (8 years 11 months ago)
Author:Rekursor
Commit:270
Parents: 269
Message:Created new dynamic detection function for SMbusspeed and now handles natively cLGA1156 core i5/i7! Need more Processor interconnect speed for other model and also other bus speed for older cpus
Changes:
M/trunk/i386/libsaio/smbios_patcher.c
M/trunk/i386/libsaio/platform.h

File differences

trunk/i386/libsaio/smbios_patcher.c
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return 0x0301; // Core 2 Duo
}
static int sm_get_cputype (const char *name, int table_num)
static int sm_get_bus_speed (const char *name, int table_num)
{
if (Platform.CPU.Vendor == 0x756E6547) // Intel
{
case 0x0F: // Intel Core (65nm)
case 0x17: // Intel Core (45nm)
case 0x1C: // Intel Atom (45nm)
return 0; // TODO: populate bus speed for these processors
case 0x1A: // Intel Core i7 LGA1366 (45nm)
case 0x1E: // Intel Core i5, i7 LGA1156 (45nm)
case 0x1F: // Intel Core i5, i7 LGA1156 (45nm) ???
return 4800; // GT/s
case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm)
return 0; // TODO: populate bus speed for these processors
case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core
case 0x2E: // Intel Core i7 LGA1366 (45nm) 6 Core ???
return 0; // TODO: populate bus speed for these processors
}
}
}
}
return 0;
}
static int sm_get_cputype (const char *name, int table_num)
{
if (Platform.CPU.Vendor == 0x756E6547) // Intel
{
verbose("CPU is Intel, family 0x%x, model 0x%x, ext.model 0x%x\n", Platform.CPU.Family, Platform.CPU.Model, Platform.CPU.ExtModel);
switch (Platform.CPU.Family)
{
case 0x06:
{
switch (Platform.CPU.Model)
{
case 0x0F: // Intel Core (65nm)
case 0x17: // Intel Core (45nm)
case 0x1C: // Intel Atom (45nm)
return sm_get_simplecputype();
case 0x1E: // Intel Core i5, i7 LGA1156 (45nm)
case 0x1A: // Intel Core i7 LGA1366 (45nm)
Platform.CPU.BusFrequency = 4800;
return 0x0701;
case 0x1F: // Intel Core i5, i7 LGA1156 (45nm) ???
case 0x1E: // Intel Core i5, i7 LGA1156 (45nm)
// get this opportunity to fill the known processor interconnect speed for cor i5/i7 in GT/s
Platform.CPU.BusFrequency = 4800;
return 0x0701;
case 0x1F: // Intel Core i5, i7 LGA1156 (45nm) ???
Platform.CPU.BusFrequency = 4800;
return 0x0601;
case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm)
return 0x0301;
{.name="SMmemserial",.table_type=17,.value_type=SMSTRING,.offset=0x18,.auto_str=sm_get_memserial},
{.name="SMmempart",.table_type=17,.value_type=SMSTRING,.offset=0x1A,.auto_str=sm_get_mempartno},
{.name="SMcputype",.table_type=131,.value_type=SMWORD,.offset=0x04,.auto_int=sm_get_cputype},
{.name="SMbusspeed",.table_type=132,.value_type=SMWORD,.offset=0x04,.auto_str=0}
{.name="SMbusspeed",.table_type=132,.value_type=SMWORD,.offset=0x04,.auto_int=sm_get_bus_speed}
};
struct smbios_table_description smbios_table_descriptions[]=
trunk/i386/libsaio/platform.h
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uint64_tTSCFrequency;// TSC Frequency Hz
uint64_tFSBFrequency;// FSB Frequency Hz
uint64_tCPUFrequency;// CPU Frequency Hz
uint64_tBusFrequency;// Bus Frequency Hz
uint32_tBrandString[16];// 48 Byte Branding String
uint32_tCPUID[CPUID_MAX][4];// CPUID 0..4, 80..81 Raw Values
} CPU;

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Revision: 270