Chameleon

Chameleon Commit Details

Date:2015-11-02 16:14:21 (4 years 18 days ago)
Author:ErmaC
Commit:2789
Parents: 2788
Message:Workaround for Xeon Harpertown, and typo.
Changes:
M/branches/ErmaC/Enoch/i386/libsaio/cpu.c
M/branches/ErmaC/Enoch/i386/libsaio/bootstruct.c
M/branches/ErmaC/Enoch/i386/libsaio/platform.h

File differences

branches/ErmaC/Enoch/i386/libsaio/bootstruct.c
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}
DT__FlattenDeviceTree((void **)&addr, &size);
if (!size)
{
stop("Couldn't get flatten device tree\n");
return;
}
bootArgs->deviceTreeP = (uint32_t)addr;
bootArgs->deviceTreeLength = size;
branches/ErmaC/Enoch/i386/libsaio/cpu.c
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p->CPU.NoCores= 4;
p->CPU.NoThreads= 4;
}
//workaround for Xeon Harpertown
if ( strstr(p->CPU.BrandString, "E5405") )
{
p->CPU.NoCores= 4;
p->CPU.NoThreads= 4;
}
}
break;
branches/ErmaC/Enoch/i386/libsaio/platform.h
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#define CPUID_MODEL_JAKETOWN0x2D// Sandy Bridge-E, Sandy Bridge-EP
#define CPUID_MODEL_NEHALEM_EX0x2E// Nehalem-EX Xeon - Beckton
#define CPUID_MODEL_WESTMERE_EX0x2F// Westmere-EX Xeon - Eagleton
#define CPUID_MODEL_CLOVERVIEW 0x35// Atom Family Bonnell, cloverview
#define CPUID_MODEL_CLOVERVIEW0x35// Atom Family Bonnell, cloverview
#define CPUID_MODEL_ATOM_20000x36// Cedarview / Saltwell
#define CPUID_MODEL_ATOM_37000x37// Atom E3000, Z3000 Atom Silvermont **BYT
#define CPUID_MODEL_IVYBRIDGE0x3A// Ivy Bridge
// Sandy Bridge (SNB) adds support for additional MSRs
#define MSR_PKG_C7_RESIDENCY0x3FA
#define MSR_CORE_C7_RESIDENCY 0x3FE
#define MSR_CORE_C7_RESIDENCY0x3FE
#define MSR_PKG_C2_RESIDENCY0x60D// same as TSC but in C2 only
#define MSR_PKG_RAPL_POWER_LIMIT0x610//MSR 00000610 0000-A580-0000-8960
// Sandy Bridge IA (Core) domain MSR's.
#define MSR_PP0_POWER_LIMIT0x638
#define MSR_PP0_ENERGY_STATUS0x639
#define MSR_PP0_ENERGY_STATUS0x639
#define MSR_PP0_POLICY0x63A
#define MSR_PP0_PERF_STATUS0x63B

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Revision: 2789