Chameleon

Chameleon Commit Details

Date:2016-04-26 22:26:34 (7 years 11 months ago)
Author:ErmaC
Commit:2804
Parents: 2803
Message:Bronya C1E fix for AMD
Changes:
M/trunk/i386/libsaio/cpu.c
M/trunk/i386/libsaio/bootstruct.c
M/trunk/i386/libsaio/platform.h
M/trunk/i386/libsaio/smbios_getters.c
M/trunk/i386/libsaio/cpu.h
M/trunk/i386/libsaio/stringTable.c

File differences

trunk/i386/libsaio/bootstruct.c
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␉if (memoryMapCount == 0)␊
␉{␊
␉␉// XXX could make a two-part map here␊
␉␉stop("Unable to convert memory map into proper format\n");␊
␉␉stop("No memory map found!\n");␊
␉␉return;␊
␉}␊
␊
␉// convert memory map to boot_args memory map␊
␉memoryMap = (EfiMemoryRange *)AllocateKernelMemory(sizeof(EfiMemoryRange) * memoryMapCount);␊
␉if (memoryMap == NULL)␊
␉{␊
␉␉stop("Unable to allocate kernel space for the memory map!\n");␊
␉␉return;␊
␉}␊
␊
␉bootArgs->MemoryMap␉␉␉= (uint32_t)memoryMap;␊
␉bootArgs->MemoryMapSize␉␉␉= sizeof(EfiMemoryRange) * memoryMapCount;␊
␉{␊
␉␉range = &bootInfo->memoryMap[i];␊
␊
␉␉if (!range || !memoryMap)␊
␉␉{␊
␉␉␉stop("Error while computing kernel memory map\n");␊
␉␉␉return;␊
␉␉}␊
␊
␉␉switch(range->type)␊
␉␉{␊
␉␉␉case kMemoryRangeACPI:␊
␉if (addr == 0)␊
␉{␊
␉␉stop("Couldn't allocate device tree\n");␊
␉␉return;␊
␉}␊
␊
␉DT__FlattenDeviceTree((void **)&addr, &size);␊
trunk/i386/libsaio/cpu.c
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␉return(rtc_cyc_per_sec);␊
}␊
␊
// Bronya C1E fix␊
void post_startup_cpu_fixups(void)␊
{␊
␉/*␊
␉ * Some AMD processors support C1E state. Entering this state will␊
␉ * cause the local APIC timer to stop, which we can't deal with at␊
␉ * this time.␊
␉ */␊
␊
␉uint64_t reg;␊
␉verbose("\tLooking to disable C1E if is already enabled by the BIOS:\n");␊
␉reg = rdmsr64(MSR_AMD_INT_PENDING_CMP_HALT);␊
␉/* Disable C1E state if it is enabled by the BIOS */␊
␉if ((reg >> AMD_ACTONCMPHALT_SHIFT) & AMD_ACTONCMPHALT_MASK)␊
␉{␊
␉␉reg &= ~(AMD_ACTONCMPHALT_MASK << AMD_ACTONCMPHALT_SHIFT);␊
␉␉wrmsr64(MSR_AMD_INT_PENDING_CMP_HALT, reg);␊
␉␉verbose("\tC1E disabled!\n");␊
␉}␊
}␊
␊
/*␊
* Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
* - multi. is read from a specific MSR. In the case of Intel, there is:␊
␊
␉␉␉switch (p->CPU.Model)␊
␉␉␉{␊
␉␉␉␉case CPUID_MODEL_NEHALEM:␊
␉␉␉␉case CPUID_MODEL_FIELDS:␊
␉␉␉␉case CPUID_MODEL_CLARKDALE:␊
␉␉␉␉case CPUID_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm)␊
␉␉␉␉case CPUID_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm)␊
␉␉␉␉case CPUID_MODEL_CLARKDALE: // Intel Core i3, i5, i7 LGA1156 (32nm)␊
␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊
␉␉␉␉case CPUID_MODEL_BROADWELL_HQ:␊
␉␉␉␉case CPUID_MODEL_BRODWELL_SVR:␊
␉␉␉␉case CPUID_MODEL_SKYLAKE_S:␊
␉␉␉␉//case CPUID_MODEL_:␊
␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT); // 0x35␊
␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
␉␉␉␉␉break;␊
␉␉␉␉case CPUID_MODEL_ATOM_3700:␊
␉␉␉␉␉p->CPU.NoCores␉␉= 4;␊
␉␉␉␉␉p->CPU.NoThreads␉= 4;␊
␉␉␉␉case CPUID_MODEL_ATOM:␊
␉␉␉␉␉p->CPU.NoCores␉␉= 2;␊
␉␉␉␉␉p->CPU.NoThreads␉= 2;␊
␉␉␉␉␉break;␊
␉␉␉␉default:␊
␉␉␉␉␉p->CPU.NoCores␉␉= 0;␊
␉␉␉␉␉break;␊
␉␉␉}␊
␊
␉␉␉if (p->CPU.NoCores == 0)␊
␉␉␉}␊
␊
␉␉␉// MSR is *NOT* available on the Intel Atom CPU␊
␉␉␉//workaround for N270. I don't know why it detected wrong␊
␉␉␉// workaround for N270. I don't know why it detected wrong␊
␉␉␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊
␉␉␉{␊
␉␉␉␉p->CPU.NoCores␉␉= 1;␊
␉␉␉␉p->CPU.NoThreads␉= 2;␊
␉␉␉}␊
␊
␉␉␉//workaround for Quad␊
␉␉␉if ( strstr(p->CPU.BrandString, "Quad") )␊
␊
␉␉␉// workaround for Xeon Harpertown and Yorkfield␊
␉␉␉if ((p->CPU.Model == CPUID_MODEL_PENRYN) &&␊
␉␉␉␉(p->CPU.NoCores␉== 0))␊
␉␉␉{␊
␉␉␉␉p->CPU.NoCores␉␉= 4;␊
␉␉␉␉p->CPU.NoThreads␉= 4;␊
␉␉␉␉if ((strstr(p->CPU.BrandString, "X54")) ||␊
␉␉␉␉␉(strstr(p->CPU.BrandString, "E54")) ||␊
␉␉␉␉␉(strstr(p->CPU.BrandString, "W35")) ||␊
␉␉␉␉␉(strstr(p->CPU.BrandString, "X34")) ||␊
␉␉␉␉␉(strstr(p->CPU.BrandString, "X33")) ||␊
␉␉␉␉␉(strstr(p->CPU.BrandString, "L33")) ||␊
␉␉␉␉␉(strstr(p->CPU.BrandString, "X32")) ||␊
␉␉␉␉␉(strstr(p->CPU.BrandString, "L3426")) ||␊
␉␉␉␉␉(strstr(p->CPU.BrandString, "L54")))␊
␉␉␉␉{␊
␉␉␉␉␉p->CPU.NoCores␉␉= 4;␊
␉␉␉␉␉p->CPU.NoThreads␉= 4;␊
␉␉␉␉} else if (strstr(p->CPU.BrandString, "W36")) {␊
␉␉␉␉␉p->CPU.NoCores␉␉= 6;␊
␉␉␉␉␉p->CPU.NoThreads␉= 6;␊
␉␉␉␉} else { //other Penryn and Wolfdale␊
␉␉␉␉␉p->CPU.NoCores␉␉= 0;␊
␉␉␉␉␉p->CPU.NoThreads␉= 0;␊
␉␉␉␉}␊
␉␉␉}␊
␊
␉␉␉//workaround for Xeon Harpertown␊
␊
␉␉␉if ( strstr(p->CPU.BrandString, "E5405") )␊
␉␉␉// workaround for Quad␊
␉␉␉if ( strstr(p->CPU.BrandString, "Quad") )␊
␉␉␉{␊
␉␉␉␉p->CPU.NoCores␉␉= 4;␊
␉␉␉␉p->CPU.NoThreads␉= 4;␊
␊
␉␉case CPUID_VENDOR_AMD:␊
␉␉{␊
␊
␉␉␉post_startup_cpu_fixups();␊
␉␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_88][ecx], 7, 0) + 1;␊
␉␉␉threads_per_core = cores_per_package;␊
␊
trunk/i386/libsaio/platform.h
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#define CPUID_MODEL_AVOTON␉␉0x4D␉␉␉// Silvermont/Avoton Atom C2000 **AVN␊
#define CPUID_MODEL_SKYLAKE␉␉0x4E␉␉␉// Future Core **SKL␊
#define CPUID_MODEL_BRODWELL_SVR␉0x4F␉␉␉// Broadwell Server **BDX␊
#define CPUID_MODEL_SKYLAKE_AVX␉␉0x55␉␉␉// Skylake with AVX-512 support.␊
#define CPUID_MODEL_BRODWELL_MSVR␉0x56␉␉␉// Broadwell Micro Server, Future Xeon **BDX-DE␊
//#define CPUID_MODEL_KNIGHT␉␉0x57␊
#define CPUID_MODEL_ANNIDALE␉␉0x5A␉␉␉// Silvermont, Future Atom E3000, Z3000 (Annidale)␊
trunk/i386/libsaio/cpu.h
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#define CALIBRATE_TIME_MSEC␉30␉␉/* 30 msecs */␊
#define CALIBRATE_LATCH␉␉((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)␊
␊
#define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055␊
#define AMD_ACTONCMPHALT_SHIFT 27␊
#define AMD_ACTONCMPHALT_MASK 3␊
␊
/*␊
* Control register 0␊
*/␊
␊
typedef struct _cr0 {␊
unsigned int␉pe␉:1,␊
␉␉␉mp␉:1,␊
␉␉␉em␉:1,␊
␉␉␉ts␉:1,␊
␉␉␉␉:1,␊
␉␉␉ne␉:1,␊
␉␉␉␉:10,␊
␉␉␉wp␉:1,␊
␉␉␉␉:1,␊
␉␉␉am␉:1,␊
␉␉␉␉:10,␊
␉␉␉nw␉:1,␊
␉␉␉cd␉:1,␊
␉␉␉pg␉:1;␊
} cr0_t;␊
␊
/*␊
* Debugging register 6␊
*/␊
␊
typedef struct _dr6 {␊
unsigned int␉b0␉:1,␊
␉␉␉b1␉:1,␊
␉␉␉b2␉:1,␊
␉␉␉b3␉:1,␊
␉␉␉␉:9,␊
␉␉␉bd␉:1,␊
␉␉␉bs␉:1,␊
␉␉␉bt␉:1,␊
␉␉␉␉:16;␊
} dr6_t;␊
␊
static inline uint64_t rdtsc64(void)␊
{␊
␉uint64_t ret;␊
trunk/i386/libsaio/stringTable.c
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*/␊
int loadSystemConfig(config_file_t *config)␊
{␊
␉// Micky1979, the order is important␊
␉char *dirspec[] = {␊
␉␉"/com.apple.recovery.boot/com.apple.Boot.plist",␉␉␉// OS X Recovery␊
␉␉"/OS X Install Data/com.apple.Boot.plist",␉␉␉␉// OS X Upgrade (10.8+)␊
trunk/i386/libsaio/smbios_getters.c
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␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
␉␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␉␉␉// 0x46 -␊
␉␉␉␉␉case CPUID_MODEL_BROADWELL_HQ:␉␉␉// 0x47␊
␉␉␉␉␉case CPUID_MODEL_SKYLAKE:␊
␉␉␉␉␉case CPUID_MODEL_SKYLAKE_AVX:␊
␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊
␉␉␉␉␉␉{␊

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Revision: 2804