␊ |
/* Intel */␊ |
#define INTEL_VENDORID␉␉PCI_VENDOR_ID_INTEL␊ |
#define HDA_INTEL_OAK␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x080a)␊ |
#define HDA_INTEL_BAY␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0f04)␊ |
#define HDA_INTEL_HSW1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0a0c)␊ |
#define HDA_INTEL_HSW2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0c0c)␊ |
#define HDA_INTEL_HSW3␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0d0c)␊ |
#define HDA_INTEL_BDW␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x160c)␊ |
#define HDA_INTEL_CPT␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x1c20)␊ |
#define HDA_INTEL_PATSBURG␉HDA_MODEL_CONSTRUCT(INTEL, 0x1d20)␊ |
#define HDA_INTEL_PPT1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x1e20) // Macmini6,2␊ |
#define HDA_INTEL_BRASWELL ␉HDA_MODEL_CONSTRUCT(INTEL, 0x2284)␊ |
#define HDA_INTEL_82801F␉HDA_MODEL_CONSTRUCT(INTEL, 0x2668)␊ |
#define HDA_INTEL_63XXESB␉HDA_MODEL_CONSTRUCT(INTEL, 0x269a)␊ |
#define HDA_INTEL_82801G␉HDA_MODEL_CONSTRUCT(INTEL, 0x27d8)␊ |
#define HDA_INTEL_82801H␉HDA_MODEL_CONSTRUCT(INTEL, 0x284b)␊ |
#define HDA_INTEL_82801I␉HDA_MODEL_CONSTRUCT(INTEL, 0x293e)␊ |
#define HDA_INTEL_ICH9␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x293f)␊ |
#define HDA_INTEL_82801JI␉HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e)␊ |
#define HDA_INTEL_82801JD␉HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e)␊ |
#define HDA_INTEL_PCH␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x3b56)␊ |
#define HDA_INTEL_PCH2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x3b57)␊ |
#define HDA_INTEL_OAK␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x080a) /* Oaktrail */␊ |
#define HDA_INTEL_BAY␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0f04) /* BayTrail */␊ |
#define HDA_INTEL_HSW1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0a0c) /* Haswell */␊ |
#define HDA_INTEL_HSW2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0c0c) /* Haswell */␊ |
#define HDA_INTEL_HSW3␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0d0c) /* Haswell */␊ |
#define HDA_INTEL_BDW␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x160c) /* Broadwell */␊ |
#define HDA_INTEL_BROXTON_T␉HDA_MODEL_CONSTRUCT(INTEL, 0x1a98) /* Broxton-T */␊ |
#define HDA_INTEL_CPT␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x1c20) /* CPT */␊ |
#define HDA_INTEL_PATSBURG␉HDA_MODEL_CONSTRUCT(INTEL, 0x1d20) /* PBG */␊ |
#define HDA_INTEL_PPT1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x1e20) /* Panther Point */␊ |
#define HDA_INTEL_BRASWELL ␉HDA_MODEL_CONSTRUCT(INTEL, 0x2284) /* Braswell */␊ |
#define HDA_INTEL_82801F␉HDA_MODEL_CONSTRUCT(INTEL, 0x2668) /* ICH6 */␊ |
#define HDA_INTEL_63XXESB␉HDA_MODEL_CONSTRUCT(INTEL, 0x269a) /* ESB2 */␊ |
#define HDA_INTEL_82801G␉HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) /* ICH7 */␊ |
#define HDA_INTEL_82801H␉HDA_MODEL_CONSTRUCT(INTEL, 0x284b) /* ICH8 */␊ |
#define HDA_INTEL_82801I␉HDA_MODEL_CONSTRUCT(INTEL, 0x293e) /* ICH9 */␊ |
#define HDA_INTEL_ICH9␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x293f) /* ICH9 */␊ |
#define HDA_INTEL_82801JI␉HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) /* ICH10 */␊ |
#define HDA_INTEL_82801JD␉HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e) /* ICH10 */␊ |
#define HDA_INTEL_PCH␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) /* 5 Series/3400 */␊ |
#define HDA_INTEL_PCH2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x3b57) /* 5 Series/3400 */␊ |
#define HDA_INTEL_BROXTON_P␉HDA_MODEL_CONSTRUCT(INTEL, 0x5a98) /* Broxton-P(Apollolake) */␊ |
#define HDA_INTEL_MACBOOKPRO92␉HDA_MODEL_CONSTRUCT(INTEL, 0x7270)␊ |
#define HDA_INTEL_SCH␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x811b)␊ |
#define HDA_INTEL_LPT1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8c20)␊ |
#define HDA_INTEL_LPT2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8c21)␊ |
#define HDA_INTEL_WCPT␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8ca0)␊ |
#define HDA_INTEL_WELLS1␉HDA_MODEL_CONSTRUCT(INTEL, 0x8d20)␊ |
#define HDA_INTEL_WELLS2␉HDA_MODEL_CONSTRUCT(INTEL, 0x8d21)␊ |
#define HDA_INTEL_WCPTLP ␉HDA_MODEL_CONSTRUCT(INTEL, 0x9ca0)␊ |
#define HDA_INTEL_LPTLP1␉HDA_MODEL_CONSTRUCT(INTEL, 0x9c20)␊ |
#define HDA_INTEL_LPTLP2␉HDA_MODEL_CONSTRUCT(INTEL, 0x9c21)␊ |
#define HDA_INTEL_SRSPLP ␉HDA_MODEL_CONSTRUCT(INTEL, 0x9d70)␊ |
#define HDA_INTEL_SRSP␉␉HDA_MODEL_CONSTRUCT(INTEL, 0xa170)␊ |
#define HDA_INTEL_SCH␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x811b) /* Poulsbo */␊ |
#define HDA_INTEL_LPT1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8c20) /* Lynx Point */␊ |
#define HDA_INTEL_LPT2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8c21) /* Lynx Point */␊ |
#define HDA_INTEL_WCPT␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8ca0) /* 9 Series */␊ |
#define HDA_INTEL_WELLS1␉HDA_MODEL_CONSTRUCT(INTEL, 0x8d20) /* Wellsburg */␊ |
#define HDA_INTEL_WELLS2␉HDA_MODEL_CONSTRUCT(INTEL, 0x8d21) /* Wellsburg */␊ |
#define HDA_INTEL_WCPTLP ␉HDA_MODEL_CONSTRUCT(INTEL, 0x9ca0) /* Wildcat Point-LP */␊ |
#define HDA_INTEL_LPTLP1␉HDA_MODEL_CONSTRUCT(INTEL, 0x9c20) /* Lynx Point-LP */␊ |
#define HDA_INTEL_LPTLP2␉HDA_MODEL_CONSTRUCT(INTEL, 0x9c21) /* Lynx Point-LP */␊ |
#define HDA_INTEL_SRSPLP ␉HDA_MODEL_CONSTRUCT(INTEL, 0x9d70) /* Sunrise Point-LP */␊ |
#define HDA_INTEL_KABYLAKE_LP␉HDA_MODEL_CONSTRUCT(INTEL, 0x9d71) /* Kabylake-LP */␊ |
#define HDA_INTEL_SRSP␉␉HDA_MODEL_CONSTRUCT(INTEL, 0xa170) /* Sunrise Point */␊ |
#define HDA_INTEL_KABYLAKE␉HDA_MODEL_CONSTRUCT(INTEL, 0xa171) /* Kabylake */␊ |
#define HDA_INTEL_LEWISBURG1␉HDA_MODEL_CONSTRUCT(INTEL, 0xa1f0) /* Lewisburg */␊ |
#define HDA_INTEL_LEWISBURG2␉HDA_MODEL_CONSTRUCT(INTEL, 0xa270) /* Lewisburg */␊ |
#define HDA_INTEL_UNPT␉␉HDA_MODEL_CONSTRUCT(INTEL, 0xa2f0) /* Kabylake-H */␊ |
#define HDA_INTEL_ALL␉␉HDA_MODEL_CONSTRUCT(INTEL, 0xffff)␊ |
␊ |
/* Nvidia */␊ |
#define NVIDIA_VENDORID␉␉PCI_VENDOR_ID_NVIDIA␊ |
// AppleHDA binary contain 0a00de10 (10de000a)␊ |
// AppleHDAController binary contain de10ea0b (10de0bea)␊ |
#define HDA_NVIDIA_MCP51␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c)␊ |
#define HDA_NVIDIA_MCP55␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371)␊ |
#define HDA_NVIDIA_MCP61_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4)␊ |
|
#define HDA_NVIDIA_0BE4␉␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be4) // [GeForge GT 240] HDACodec 10de000d (0d00de10)␊ |
#define HDA_NVIDIA_GT100␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be5) // [GeForge GTX 470] HDACodec 10de0010 (1000de10)␊ |
#define HDA_NVIDIA_GT106␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be9)␊ |
#define HDA_NVIDIA_GT108␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0bea) // HDACodec ␊ |
#define HDA_NVIDIA_GT108␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0bea) // HDACodec␊ |
#define HDA_NVIDIA_GT104␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0beb)␊ |
#define HDA_NVIDIA_GT116␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0bee)␊ |
#define HDA_NVIDIA_MCP89_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94)␊ |
|
␊ |
/* ATI */␊ |
#define ATI_VENDORID␉␉PCI_VENDOR_ID_ATI␊ |
#define HDA_ATI_SB450␉␉HDA_MODEL_CONSTRUCT(ATI, 0x437b)␊ |
#define HDA_ATI_SB600␉␉HDA_MODEL_CONSTRUCT(ATI, 0x4383)␊ |
#define HDA_ATI_HUDSON␉␉HDA_MODEL_CONSTRUCT(ATI, 0x780d)␊ |
#define HDA_ATI_RS600␉␉HDA_MODEL_CONSTRUCT(ATI, 0x793b)␊ |
#define HDA_ATI_RS690␉␉HDA_MODEL_CONSTRUCT(ATI, 0x7919)␊ |
//#define HDA_ATI_0002␉␉HDA_MODEL_CONSTRUCT(ATI, 0x0002) /* ATI HDMI */␊ |
//#define HDA_ATI_1308␉␉HDA_MODEL_CONSTRUCT(ATI, 0x1308) /* ATI HDMI */␊ |
//#define HDA_ATI_177A␉␉HDA_MODEL_CONSTRUCT(ATI, 0x157a) /* ATI HDMI */␊ |
//#define HDA_ATI_15B3␉␉HDA_MODEL_CONSTRUCT(ATI, 0x15b3) /* ATI HDMI */␊ |
#define HDA_ATI_SB450␉␉HDA_MODEL_CONSTRUCT(ATI, 0x437b) /* ATI SB 450/600/700/800/900 */␊ |
#define HDA_ATI_SB600␉␉HDA_MODEL_CONSTRUCT(ATI, 0x4383) /* ATI SB 450/600/700/800/900 */␊ |
#define HDA_ATI_HUDSON␉␉HDA_MODEL_CONSTRUCT(ATI, 0x780d) /* PCI_DEVICE(0x1022, 0x780d) */␊ |
#define HDA_ATI_RS600␉␉HDA_MODEL_CONSTRUCT(ATI, 0x793b) /* ATI HDMI */␊ |
#define HDA_ATI_RS690␉␉HDA_MODEL_CONSTRUCT(ATI, 0x7919) /* ATI HDMI */␊ |
#define HDA_ATI_RS780␉␉HDA_MODEL_CONSTRUCT(ATI, 0x960f)␊ |
#define HDA_ATI_RS880␉␉HDA_MODEL_CONSTRUCT(ATI, 0x970f)␊ |
#define HDA_ATI_TRINITY␉␉HDA_MODEL_CONSTRUCT(ATI, 0x9902)␊ |
#define HDA_ATI_R600␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa00)␊ |
#define HDA_ATI_RV630␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa08)␊ |
#define HDA_ATI_RV610␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa10)␊ |
#define HDA_ATI_RV670␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa18)␊ |
#define HDA_ATI_RV635␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa20)␊ |
#define HDA_ATI_RV620␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa28)␊ |
#define HDA_ATI_RV770␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa30)␊ |
#define HDA_ATI_RV730␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa38)␊ |
#define HDA_ATI_RV710␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa40)␊ |
#define HDA_ATI_RV740␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa48)␊ |
#define HDA_ATI_RV870␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa50)␊ |
#define HDA_ATI_RV840␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa58) // Codec 021001aa (1002aa01)␊ |
#define HDA_ATI_RV830␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa60)␊ |
#define HDA_ATI_RV810␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa68)␊ |
#define HDA_ATI_RV970␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa80)␊ |
#define HDA_ATI_RV940␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa88)␊ |
#define HDA_ATI_RV930␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa90)␊ |
#define HDA_ATI_RV910␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa98)␊ |
#define HDA_ATI_R1000␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaaa0)␊ |
#define HDA_ATI_SI␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaaa8)␊ |
#define HDA_ATI_VERDE␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaab0)␊ |
#define HDA_ATI_RS880␉␉HDA_MODEL_CONSTRUCT(ATI, 0x970f) /* ATI HDMI */␊ |
//#define HDA_ATI_9840␉␉HDA_MODEL_CONSTRUCT(ATI, 0x9840) /* ATI HDMI */␊ |
#define HDA_ATI_TRINITY␉␉HDA_MODEL_CONSTRUCT(ATI, 0x9902) /* ATI HDMI */␊ |
#define HDA_ATI_R600␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa00) /* ATI HDMI */␊ |
#define HDA_ATI_RV630␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa08) /* ATI HDMI */␊ |
#define HDA_ATI_RV610␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa10) /* ATI HDMI */␊ |
#define HDA_ATI_RV670␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa18) /* ATI HDMI */␊ |
#define HDA_ATI_RV635␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa20) /* ATI HDMI */␊ |
#define HDA_ATI_RV620␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa28) /* ATI HDMI */␊ |
#define HDA_ATI_RV770␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa30) /* ATI HDMI */␊ |
#define HDA_ATI_RV730␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa38) /* ATI HDMI */␊ |
#define HDA_ATI_RV710␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa40) /* ATI HDMI */␊ |
#define HDA_ATI_RV740␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa48) /* ATI HDMI */␊ |
#define HDA_ATI_RV870␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa50) /* ATI HDMI */␊ |
#define HDA_ATI_RV840␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa58) /* ATI HDMI */␊ |
#define HDA_ATI_RV830␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa60) /* ATI HDMI */␊ |
#define HDA_ATI_RV810␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa68) /* ATI HDMI */␊ |
#define HDA_ATI_RV970␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa80) /* ATI HDMI */␊ |
#define HDA_ATI_RV940␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa88) /* ATI HDMI */␊ |
#define HDA_ATI_RV930␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa90) /* ATI HDMI */␊ |
#define HDA_ATI_RV910␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa98) /* ATI HDMI */␊ |
#define HDA_ATI_R1000␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaaa0) /* ATI HDMI */␊ |
#define HDA_ATI_SI␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaaa8) /* ATI HDMI */␊ |
#define HDA_ATI_VERDE␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaab0) /* ATI HDMI */␊ |
//#define HDA_ATI_AAC0␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaac0) /* ATI HDMI */␊ |
//#define HDA_ATI_AAC8␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaac8) /* ATI HDMI */␊ |
//#define HDA_ATI_AAD8␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaad8) /* ATI HDMI */␊ |
//#define HDA_ATI_AAE8␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaae8) /* ATI HDMI */␊ |
//#define HDA_ATI_AAE0␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaae0) /* ATI HDMI */␊ |
//#define HDA_ATI_AAF0␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaaf0) /* ATI HDMI */␊ |
#define HDA_ATI_ALL␉␉HDA_MODEL_CONSTRUCT(ATI, 0xffff)␊ |
␊ |
/* RDC */␊ |
#define RDC_VENDORID␉␉0x17f3␊ |
#define HDA_RDC_M3010␉␉HDA_MODEL_CONSTRUCT(RDC, 0x3010)␊ |
#define HDA_RDC_M3010␉␉HDA_MODEL_CONSTRUCT(RDC, 0x3010) /* Vortex86MX */␊ |
␊ |
/* VIA */␊ |
#define VIA_VENDORID␉␉0x1106␊ |
#define HDA_VIA_VT82XX␉␉HDA_MODEL_CONSTRUCT(VIA, 0x3288)␊ |
#define HDA_VIA_VT82XX␉␉HDA_MODEL_CONSTRUCT(VIA, 0x3288) /* VIA VT8251/VT8237A */␊ |
//#define HDA_VIA_VT71XX␉HDA_MODEL_CONSTRUCT(VIA, 0x9170) /* VIA GFX VT7122/VX900 */␊ |
//#define HDA_VIA_VT61XX␉HDA_MODEL_CONSTRUCT(VIA, 0x9140) /* VIA GFX VT6122/VX11 */␊ |
#define HDA_VIA_ALL␉␉HDA_MODEL_CONSTRUCT(VIA, 0xffff)␊ |
␊ |
/* SiS */␊ |
#define SIS_VENDORID␉␉0x1039␊ |
#define HDA_SIS_966␉␉HDA_MODEL_CONSTRUCT(SIS, 0x7502)␊ |
#define HDA_SIS_966␉␉HDA_MODEL_CONSTRUCT(SIS, 0x7502) /* SIS966 */␊ |
#define HDA_SIS_ALL␉␉HDA_MODEL_CONSTRUCT(SIS, 0xffff)␊ |
␊ |
/* ULI */␊ |
#define ULI_VENDORID␉␉0x10b9␊ |
#define HDA_ULI_M5461␉␉HDA_MODEL_CONSTRUCT(ULI, 0x5461)␊ |
#define HDA_ULI_M5461␉␉HDA_MODEL_CONSTRUCT(ULI, 0x5461) /* ULI M5461 */␊ |
#define HDA_ULI_ALL␉␉HDA_MODEL_CONSTRUCT(ULI, 0xffff)␊ |
␊ |
/* OEM/subvendors */␊ |
/* Teradici */␊ |
//{ PCI_DEVICE(0x6549, 0x1200),␊ |
//{ PCI_DEVICE(0x6549, 0x2200}␊ |
␊ |
/* Intel */␊ |
#define INTEL_D101GGC_SUBVENDOR␉HDA_MODEL_CONSTRUCT(INTEL, 0xd600)␊ |
/* CTHDA chips */␊ |
//{ PCI_DEVICE(0x1102, 0x0010),␊ |
//{ PCI_DEVICE(0x1102, 0x0012),␊ |
␊ |
/* HP/Compaq */␊ |
#define HP_VENDORID␉␉0x103c␊ |
#define HP_V3000_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x30b5)␊ |
#define HP_NX7400_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x30a2)␊ |
#define HP_NX6310_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x30aa)␊ |
#define HP_NX6325_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x30b0)␊ |
#define HP_XW4300_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x3013)␊ |
#define HP_3010_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x3010)␊ |
#define HP_DV5000_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x30a5)␊ |
#define HP_DC7700S_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x2801)␊ |
#define HP_DC7700_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x2802)␊ |
#define HP_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0xffff)␊ |
/* What is wrong with XN 2563 anyway? (Got the picture ?) */␊ |
#define HP_NX6325_SUBVENDORX␉0x103c30b0␊ |
/* this entry seems still valid -- i.e. without emu20kx chip */␊ |
//{ PCI_DEVICE(0x1102, 0x0009␊ |
␊ |
/* Dell */␊ |
#define DELL_VENDORID␉␉0x1028␊ |
#define DELL_D630_SUBVENDOR␉HDA_MODEL_CONSTRUCT(DELL, 0x01f9)␊ |
#define DELL_D820_SUBVENDOR␉HDA_MODEL_CONSTRUCT(DELL, 0x01cc)␊ |
#define DELL_V1400_SUBVENDOR␉HDA_MODEL_CONSTRUCT(DELL, 0x0227)␊ |
#define DELL_V1500_SUBVENDOR␉HDA_MODEL_CONSTRUCT(DELL, 0x0228)␊ |
#define DELL_I1300_SUBVENDOR␉HDA_MODEL_CONSTRUCT(DELL, 0x01c9)␊ |
#define DELL_XPSM1210_SUBVENDOR␉HDA_MODEL_CONSTRUCT(DELL, 0x01d7)␊ |
#define DELL_OPLX745_SUBVENDOR␉HDA_MODEL_CONSTRUCT(DELL, 0x01da)␊ |
#define DELL_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(DELL, 0xffff)␊ |
/* CM8888 */␊ |
//{ PCI_DEVICE(0x13f6, 0x5011),␊ |
␊ |
/* Clevo */␊ |
#define CLEVO_VENDORID␉␉0x1558␊ |
#define CLEVO_D900T_SUBVENDOR␉HDA_MODEL_CONSTRUCT(CLEVO, 0x0900)␊ |
#define CLEVO_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(CLEVO, 0xffff)␊ |
/* VMware HDAudio */␊ |
//{ PCI_DEVICE(0x15ad, 0x1977),␊ |
␊ |
/* Acer */␊ |
#define ACER_VENDORID␉␉0x1025␊ |
#define ACER_A5050_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ACER, 0x010f)␊ |
#define ACER_A4520_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ACER, 0x0127)␊ |
#define ACER_A4710_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ACER, 0x012f)␊ |
#define ACER_A4715_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ACER, 0x0133)␊ |
#define ACER_3681WXM_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ACER, 0x0110)␊ |
#define ACER_T6292_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ACER, 0x011b)␊ |
#define ACER_T5320_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ACER, 0x011f)␊ |
#define ACER_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ACER, 0xffff)␊ |
␊ |
/* Asus */␊ |
#define ASUS_VENDORID␉␉0x1043␊ |
#define ASUS_A8X_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x1153)␊ |
#define ASUS_U5F_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x1263)␊ |
#define ASUS_W6F_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x1263)␊ |
#define ASUS_A7M_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x1323)␊ |
#define ASUS_F3JC_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x1338)␊ |
#define ASUS_G2K_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x1339)␊ |
#define ASUS_A7T_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x13c2)␊ |
#define ASUS_W2J_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x1971)␊ |
#define ASUS_M5200_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x1993)␊ |
#define ASUS_P5PL2_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x817f)␊ |
#define ASUS_P1AH2_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)␊ |
#define ASUS_M2NPVMX_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)␊ |
#define ASUS_M2V_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x81e7)␊ |
#define ASUS_P5BWD_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x81ec)␊ |
#define ASUS_M2N_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x8234)␊ |
#define ASUS_A8NVMCSM_SUBVENDOR␉HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84)␊ |
#define ASUS_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0xffff)␊ |
␊ |
/* IBM / Lenovo */␊ |
#define IBM_VENDORID␉␉0x1014␊ |
#define IBM_M52_SUBVENDOR␉HDA_MODEL_CONSTRUCT(IBM, 0x02f6)␊ |
#define IBM_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(IBM, 0xffff)␊ |
␊ |
/* Lenovo */␊ |
#define LENOVO_VENDORID␉␉0x17aa␊ |
#define LENOVO_3KN100_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x2066)␊ |
#define LENOVO_3KN200_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x384e)␊ |
#define LENOVO_B450_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x3a0d)␊ |
#define LENOVO_TCA55_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x1015)␊ |
#define LENOVO_X300_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x20ac)␊ |
#define LENOVO_X1_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x21e8)␊ |
#define LENOVO_X1CRBN_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x21f9)␊ |
#define LENOVO_X220_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x21da)␊ |
#define LENOVO_T420_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x21ce)␊ |
#define LENOVO_T430_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x21f3)␊ |
#define LENOVO_T430S_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x21fb)␊ |
#define LENOVO_T520_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x21cf)␊ |
#define LENOVO_T530_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x21f6)␊ |
#define LENOVO_ALL_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0xffff)␊ |
␊ |
/* Samsung */␊ |
#define SAMSUNG_VENDORID␉0x144d␊ |
#define SAMSUNG_Q1_SUBVENDOR␉HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027)␊ |
#define SAMSUNG_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff)␊ |
␊ |
/* Medion ? */␊ |
#define MEDION_VENDORID␉␉␉0x161f␊ |
#define MEDION_MD95257_SUBVENDOR␉HDA_MODEL_CONSTRUCT(MEDION, 0x203d)␊ |
#define MEDION_ALL_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(MEDION, 0xffff)␊ |
␊ |
/* Apple Computer Inc. */␊ |
#define APPLE_VENDORID␉␉PCI_VENDOR_ID_APPLE␊ |
#define APPLE_MB3_SUBVENDOR␉HDA_MODEL_CONSTRUCT(APPLE, 0x00a1)␊ |
␊ |
/* Sony */␊ |
#define SONY_VENDORID␉␉0x104d␊ |
#define SONY_S5_SUBVENDOR␉HDA_MODEL_CONSTRUCT(SONY, 0x81cc)␊ |
#define SONY_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(SONY, 0xffff)␊ |
␊ |
/*␊ |
* Apple Intel MacXXXX seems using Sigmatel codec/vendor id␊ |
* instead of their own, which is beyond my comprehension␊ |
* (see HDA_CODEC_STAC9221 below).␊ |
*/␊ |
#define APPLE_INTEL_MAC 0x76808384␊ |
#define APPLE_MACBOOKAIR31 0x0d9410de␊ |
#define APPLE_MACBOOKPRO55 0xcb7910de␊ |
#define APPLE_MACBOOKPRO71 0xcb8910de␊ |
␊ |
/* LG Electronics */␊ |
#define LG_VENDORID␉␉0x1854␊ |
#define LG_LW20_SUBVENDOR␉HDA_MODEL_CONSTRUCT(LG, 0x0018)␊ |
#define LG_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(LG, 0xffff)␊ |
␊ |
/* Fujitsu Siemens */␊ |
#define FS_VENDORID␉␉0x1734␊ |
#define FS_PA1510_SUBVENDOR␉HDA_MODEL_CONSTRUCT(FS, 0x10b8)␊ |
#define FS_SI1848_SUBVENDOR␉HDA_MODEL_CONSTRUCT(FS, 0x10cd)␊ |
#define FS_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(FS, 0xffff)␊ |
␊ |
/* Fujitsu Limited */␊ |
#define FL_VENDORID␉␉0x10cf␊ |
#define FL_S7020D_SUBVENDOR␉HDA_MODEL_CONSTRUCT(FL, 0x1326)␊ |
#define FL_U1010_SUBVENDOR␉HDA_MODEL_CONSTRUCT(FL, 0x142d)␊ |
#define FL_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(FL, 0xffff)␊ |
␊ |
/* Toshiba */␊ |
#define TOSHIBA_VENDORID␉0x1179␊ |
#define TOSHIBA_U200_SUBVENDOR␉HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001)␊ |
#define TOSHIBA_A135_SUBVENDOR␉HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01)␊ |
#define TOSHIBA_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff)␊ |
␊ |
/* Micro-Star International (MSI) */␊ |
#define MSI_VENDORID␉␉0x1462␊ |
#define MSI_MS1034_SUBVENDOR␉HDA_MODEL_CONSTRUCT(MSI, 0x0349)␊ |
#define MSI_MS034A_SUBVENDOR␉HDA_MODEL_CONSTRUCT(MSI, 0x034a)␊ |
#define MSI_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(MSI, 0xffff)␊ |
␊ |
/* Giga-Byte Technology */␊ |
#define GB_VENDORID␉␉0x1458␊ |
#define GB_G33S2H_SUBVENDOR␉HDA_MODEL_CONSTRUCT(GB, 0xa022)␊ |
#define GP_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(GB, 0xffff)␊ |
␊ |
/* Uniwill ? */␊ |
#define UNIWILL_VENDORID␉0x1584␊ |
#define UNIWILL_9075_SUBVENDOR␉HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075)␊ |
#define UNIWILL_9080_SUBVENDOR␉HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080)␊ |
␊ |
//#define HDEF_PATH "PciRoot(0x0)/Pci(0x1b,0x0)"␊ |
//#define PINCONF_LEN ( sizeof(default_PinConfiguration) / sizeof(uint8_t) )␊ |
#define HDA0_LEN ( sizeof(default_HDEF_layout_id) / sizeof(uint8_t) )␊ |
|
//#define HDA_CODEC_ALC898 HDA_CODEC_CONSTRUCT(REALTEK, 0x0898)␊ |
//#define HDA_CODEC_ALC899 HDA_CODEC_CONSTRUCT(REALTEK, 0x0899)␊ |
#define HDA_CODEC_ALC900 HDA_CODEC_CONSTRUCT(REALTEK, 0x0900)␊ |
#define HDA_CODEC_ALCS1220A␉HDA_CODEC_CONSTRUCT(REALTEK, 0x1168)␊ |
#define HDA_CODEC_ALC1220 HDA_CODEC_CONSTRUCT(REALTEK, 0x1220)␊ |
#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff)␊ |
␊ |
|
#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x9880)␊ |
#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff)␊ |
␊ |
/* CMedia */␊ |
#define CMEDIA2_VENDORID 0x434d␊ |
#define HDA_CODEC_CMI98802 HDA_CODEC_CONSTRUCT(CMEDIA2, 0x4980)␊ |
#define HDA_CODEC_CMIXXXX2 HDA_CODEC_CONSTRUCT(CMEDIA2, 0xffff)␊ |
|
#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392)␊ |
#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff)␊ |
␊ |
/* Lucent/Agere */␊ |
/* LSI - Lucent/Agere */␊ |
#define AGERE_VENDORID 0x11c1␊ |
#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff)␊ |
␊ |
|
#define CHRONTEL_VENDORID 0x17e8␊ |
#define HDA_CODEC_CHXXXX HDA_CODEC_CONSTRUCT(CHRONTEL, 0xffff)␊ |
␊ |
/* LG */␊ |
#define LG_VENDORID 0x1854␊ |
#define HDA_CODEC_LGXXXX HDA_CODEC_CONSTRUCT(LG, 0xffff)␊ |
␊ |
/* Wolfson Microelectronics */␊ |
#define WOLFSON_VENDORID 0x14ec␊ |
#define HDA_CODEC_WMXXXX HDA_CODEC_CONSTRUCT(WOLFSON, 0xffff)␊ |
␊ |
/* QEMU */␊ |
#define QEMU_VENDORID 0x1af4␊ |
#define HDA_CODEC_QEMUXXXX HDA_CODEC_CONSTRUCT(QEMU, 0xffff)␊ |
␊ |
/* INTEL */␊ |
#define HDA_CODEC_INTELIP␉HDA_CODEC_CONSTRUCT(INTEL, 0x0054)␊ |
#define HDA_CODEC_INTELBL␉HDA_CODEC_CONSTRUCT(INTEL, 0x2801)␊ |
|
#define HDA_CODEC_INTELLLP␉HDA_CODEC_CONSTRUCT(INTEL, 0x2807) // Haswell HDMI␊ |
#define HDA_CODEC_INTELBRW␉HDA_CODEC_CONSTRUCT(INTEL, 0x2808) // Broadwell HDMI␊ |
#define HDA_CODEC_INTELSKL␉HDA_CODEC_CONSTRUCT(INTEL, 0x2809) // Skylake HDMI␊ |
#define HDA_CODEC_INTELBRO␉HDA_CODEC_CONSTRUCT(INTEL, 0x280a) // Broxton HDMI␊ |
#define HDA_CODEC_INTELKAB␉HDA_CODEC_CONSTRUCT(INTEL, 0x280b) // Kabylake HDMI␊ |
#define HDA_CODEC_INTELCDT␉HDA_CODEC_CONSTRUCT(INTEL, 0x2880) // CedarTrail HDMI␊ |
#define HDA_CODEC_INTELVLV␉HDA_CODEC_CONSTRUCT(INTEL, 0x2882) // Valleyview2 HDMI␊ |
#define HDA_CODEC_INTELBSW␉HDA_CODEC_CONSTRUCT(INTEL, 0x2883) // Braswell HDMI␊ |