Chameleon

Chameleon Commit Details

Date:2010-08-07 05:39:56 (8 years 11 months ago)
Author:Azimutz
Commit:323
Parents: 322
Message:Matching trunk rev 317... ... and restoring some more eye candy.
Changes:
M/branches/azimutz/CleanCut/i386/libsaio/acpi_patcher.c
M/branches/azimutz/CleanCut/i386/libsaio/smbios_patcher.c
M/branches/azimutz/CleanCut/i386/libsaio/cpu.c
M/branches/azimutz/CleanCut/i386/libsaio/platform.h
M/branches/azimutz/CleanCut/i386/libsaio/cpu.h

File differences

branches/azimutz/CleanCut/i386/libsaio/acpi_patcher.c
362362
363363
364364
365
365
366366
367367
368368
......
386386
387387
388388
389
390
389
391390
392391
393392
......
397396
398397
399398
400
401
402
399
400
401
402
403
403404
404405
405406
......
515516
516517
517518
518
519
520
521
522
523
519
520
521
522
523
524
524525
525526
526527
......
529530
530531
531532
532
533533
534534
535535
}
struct acpi_2_ssdt *generate_pss_ssdt(struct acpi_2_dsdt* dsdt)
{
{
char ssdt_header[] =
{
0x53, 0x53, 0x44, 0x54, 0x7E, 0x00, 0x00, 0x00, /* SSDT.... */
get_acpi_cpu_names((void*)dsdt, dsdt->Length);
if (acpi_cpu_count > 0)
{
{
struct p_state initial, maximum, minimum, p_states[32];
uint8_t p_states_count = 0;
{
switch (Platform.CPU.Model)
{
case 0x0F: // Intel Core (65nm)
case 0x17: // Intel Core (45nm)
case 0x1C: // Intel Atom (45nm)
case 0x0D: // ?
case CPU_MODEL_YONAH: // Yonah
case CPU_MODEL_MEROM: // Merom
case CPU_MODEL_PENRYN: // Penryn
case CPU_MODEL_ATOM: // Intel Atom (45nm)
{
bool cpu_dynamic_fsb = false;
p_states_count -= invalid;
}
} break;
case 0x1A: // Intel Core i7 LGA1366 (45nm)
case 0x1E: // Intel Core i5, i7 LGA1156 (45nm)
case 0x1F:
case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm)
case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core
case 0x2F:
case CPU_MODEL_FIELDS:
case CPU_MODEL_NEHALEM:
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM:
case CPU_MODEL_WESTMERE:
case CPU_MODEL_WESTMERE_EX:
default:
verbose ("Unsupported CPU: P-States not generated !!!\n");
break;
}
// Generating SSDT
if (p_states_count > 0)
{
int i;
branches/azimutz/CleanCut/i386/libsaio/smbios_patcher.c
1010
1111
1212
13
1314
1415
1516
......
2829
2930
3031
31
32
33
34
35
36
37
38
39
40
32
33
34
35
36
37
38
39
40
41
4142
4243
4344
4445
4546
46
47
48
49
50
51
52
53
54
55
47
48
49
50
51
52
53
54
55
56
5657
5758
5859
5960
6061
61
62
63
64
65
66
67
68
69
70
62
63
64
65
66
67
68
69
70
71
7172
7273
7374
7475
7576
76
77
78
79
80
81
82
83
84
85
77
78
79
80
81
82
83
84
85
86
8687
8788
8889
8990
9091
91
92
93
94
95
96
97
98
99
100
92
93
94
95
96
97
98
99
100
101
101102
102103
103104
104
105
106
107
108
109
110
111
112
113
114
115
105
106
107
108
109
110
111
112
113
114
115
116
116117
117118
118119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
119135
120136
121137
......
144160
145161
146162
147
148
149
150
163
164
165
166
167
151168
169
170
171
172
173
174
152175
153176
154177
......
200223
201224
202225
203
226
204227
205228
206229
......
210233
211234
212235
213
214
215
236
237
238
239
240
216241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
217259
218
219
220
221
222
223
224
225
226
227
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
228295
229296
230297
......
239306
240307
241308
242
309
243310
244311
245312
......
249316
250317
251318
252
253
254
319
320
321
322
323
255324
256
257
258
259
260
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
261350
262
263
264
265
266
267
268
351
269352
270353
271354
......
354437
355438
356439
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
379462
380463
381464
#include "fake_efi.h"
#include "platform.h"
#include "smbios_patcher.h"
#include "pci.h"
#ifndef DEBUG_SMBIOS
#define DEBUG_SMBIOS 0
// defaults for a MacBook
static const SMStrEntryPair const sm_macbook_defaults[]={
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","MB41.88Z.0073.B00.0809221748"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","MacBook4,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","MacBook"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F42D89C8"},
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","MB41.88Z.0073.B00.0809221748"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","MacBook4,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","MacBook"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F42D89C8"},
{ "",""}
};
// defaults for a MacBook Pro
static const SMStrEntryPair const sm_macbookpro_defaults[]={
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","MBP41.88Z.0073.B00.0809221748"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","MacBookPro4,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","MacBookPro"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F42D89C8"},
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","MBP41.88Z.0073.B00.0809221748"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","MacBookPro4,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","MacBookPro"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F42D89C8"},
{ "",""}
};
// defaults for a Mac mini
static const SMStrEntryPair const sm_macmini_defaults[]={
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","MM21.88Z.009A.B00.0706281359"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","Macmini2,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","Napa Mac"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F4208EAA"},
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","MM21.88Z.009A.B00.0706281359"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","Macmini2,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","Napa Mac"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F4208EAA"},
{ "",""}
};
// defaults for an iMac
static const SMStrEntryPair const sm_imac_defaults[]={
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","IM81.88Z.00C1.B00.0802091538"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","iMac8,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","Mac"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F227BEC8"},
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","IM81.88Z.00C1.B00.0802091538"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","iMac8,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","Mac"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F227BEC8"},
{ "",""}
};
// defaults for a Mac Pro
static const SMStrEntryPair const sm_macpro_defaults[]={
{"SMbiosvendor","Apple Computer, Inc."},
{"SMbiosversion","MP31.88Z.006C.B05.0802291410"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Computer, Inc."},
{"SMproductname","MacPro3,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","MacPro"},
{"SMboardmanufacter","Apple Computer, Inc."},
{"SMboardproduct","Mac-F4208DC8"},
{"SMbiosvendor","Apple Computer, Inc."},
{"SMbiosversion","MP31.88Z.006C.B05.0802291410"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Computer, Inc."},
{"SMproductname","MacPro3,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","MacPro"},
{"SMboardmanufacter","Apple Computer, Inc."},
{"SMboardproduct","Mac-F4208DC8"},
{ "",""}
};
// defaults for an iMac11,1 core i5/i7
static const SMStrEntryPair const sm_imacCore_i5_i7_defaults[]={
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","IM111.0034.B00"},
{"SMbiosdate","06/01/2009"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","iMac11,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","iMac"},
{"SMboardmanufacter","Apple Computer, Inc."},
{"SMboardproduct","Mac-F2268DAE"},
// defaults for an iMac11,1 core i3/i5/i7
static const SMStrEntryPair const sm_imac_core_defaults[]={
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","IM111.88Z.0034.B00.0802091538"},
{"SMbiosdate","06/01/2009"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","iMac11,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","iMac"},
{"SMboardmanufacter","Apple Computer, Inc."},
{"SMboardproduct","Mac-F2268DAE"},
{ "",""}
};
// defaults for a Mac Pro 4,1 core i7/Xeon
static const SMStrEntryPair const sm_macpro_core_defaults[]={
{"SMbiosvendor","Apple Computer, Inc."},
{"SMbiosversion","MP41.88Z.0081.B04.0903051113"},
{"SMbiosdate","11/06/2009"},
{"SMmanufacter","Apple Computer, Inc."},
{"SMproductname","MacPro4,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","MacPro"},
{"SMboardmanufacter","Apple Computer, Inc."},
{"SMboardproduct","Mac-F4208DC8"},
{ "",""}
};
static const char* sm_get_defstr(const char * key, int table_num)
{
inti;
{
switch (Platform.CPU.Model)
{
case 0x19: // Intel Core i5 650
case 0x1E: // Intel Core i7 LGA1156 (45nm)
case 0x1F: // Intel Core i5 LGA1156 (45nm)
sm_defaults=sm_imacCore_i5_i7_defaults;
case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm)
case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ???
case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)
case 0x19: // Intel Core i5 650 @3.20 Ghz
sm_defaults=sm_imac_core_defaults;
break;
case CPU_MODEL_NEHALEM:
case CPU_MODEL_NEHALEM_EX:
case CPU_MODEL_WESTMERE:
case CPU_MODEL_WESTMERE_EX:
sm_defaults=sm_macpro_core_defaults;
break;
default:
sm_defaults=sm_macpro_defaults;
break;
return 0x0301; // Core 2 Duo
}
static int sm_get_bus_speed (const char *name, int table_num)
static int sm_get_bus_speed(const char *name, int table_num)
{
if (Platform.CPU.Vendor == 0x756E6547) // Intel
{
{
switch (Platform.CPU.Model)
{
case 0x0F: // Intel Core (65nm)
case 0x17: // Intel Core (45nm)
case 0x1C: // Intel Atom (45nm)
case 0x0D: // ?
case CPU_MODEL_YONAH:// Yonah0x0E
case CPU_MODEL_MEROM:// Merom0x0F
case CPU_MODEL_PENRYN:// Penryn0x17
case CPU_MODEL_ATOM:// Atom 45nm0x1C
return 0; // TODO: populate bus speed for these processors
//case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm)
//if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))
//return 2500; // Core i5
//return 4800; // Core i7
//case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm)
//case CPU_MODEL_NEHALEM_EX:
//case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ???
//return 4800; // GT/s / 1000
//
case CPU_MODEL_WESTMERE_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ???
return 0; // TODO: populate bus speed for these processors
//case 0x19: // Intel Core i5 650 @3.20 Ghz
//return 2500; // why? Intel spec says 2.5GT/s
case 0x19: // Intel Core i5 650 @3.20 Ghz
return 3600; // GT/s / 1000
case 0x1A: // Intel Core i7 LGA1366 (45nm)
case 0x1E: // Intel Core i5, i7 LGA1156 (45nm)
case 0x1F: // Intel Core i5, i7 LGA1156 (45nm) ???
return 4800; // GT/s / 1000
case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm)
return 0; // TODO: populate bus speed for these processors
case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core
case 0x2E: // Intel Core i7 LGA1366 (45nm) 6 Core ???
return 0; // TODO: populate bus speed for these processors
case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm)
case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm)
case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ???
case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm)
case CPU_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core
case CPU_MODEL_NEHALEM_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ???
{ // thanks to dgobe for i3/i5/i7 bus speed detection
int nhm_bus = 0x3F;
static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};
unsigned long did, vid;
int i;
// Nehalem supports Scrubbing
// First, locate the PCI bus where the MCH is located
for(i = 0; i < sizeof(possible_nhm_bus); i++)
{
vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);
did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);
vid &= 0xFFFF;
did &= 0xFF00;
if(vid == 0x8086 && did >= 0x2C00)
nhm_bus = possible_nhm_bus[i];
}
unsigned long qpimult, qpibusspeed;
qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);
qpimult &= 0x7F;
DBG("qpimult %d\n", qpimult);
qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));
// Rek: rounding decimals to match original mac profile info
if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;
DBG("qpibusspeed %d\n", qpibusspeed);
return qpibusspeed;
}
}
}
}
if (Platform.CPU.Vendor == 0x756E6547) // Intel
{
if (!done) {
verbose("CPU is Intel, family 0x%x, model 0x%x, ext.model 0x%x\n", Platform.CPU.Family, Platform.CPU.Model, Platform.CPU.ExtModel);
verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);
done = true;
}
{
switch (Platform.CPU.Model)
{
case 0x0F: // Intel Core (65nm)
case 0x17: // Intel Core (45nm)
case 0x1C: // Intel Atom (45nm)
case 0x0D: // ?
case CPU_MODEL_YONAH: // Yonah
case CPU_MODEL_MEROM: // Merom
case CPU_MODEL_PENRYN: // Penryn
case CPU_MODEL_ATOM: // Intel Atom (45nm)
return sm_get_simplecputype();
case 0x1A: // Intel Core i7 LGA1366 (45nm)
return 0x0701;
case 0x1E: // Intel Core i5, i7 LGA1156 (45nm)
// get this opportunity to fill the known processor interconnect speed for cor i5/i7 in GT/s
return 0x0701;
case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm)
return 0x0701; // Core i7
case CPU_MODEL_FIELDS: // Lynnfield, Clarksfield, Jasper
if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))
return 0x601; // Core i5
return 0x701; // Core i7
case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)
if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))
return 0x601; // Core i5
return 0x0701; // Core i7
case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)
if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))
return 0x301; // Core i3
if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))
return 0x601; // Core i5
return 0x0701; // Core i7
case CPU_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS)
case CPU_MODEL_WESTMERE_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ???
return 0x0701; // Core i7
case 0x19: // Intel Core i5 650 @3.20 Ghz
case 0x1F: // Intel Core i5, i7 LGA1156 (45nm) ???
return 0x0601;
case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm)
return 0x0301;
case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core
case 0x2E: // Intel Core i7 LGA1366 (45nm) 6 Core ???
return 0x0601;
return 0x601; // Core i5
}
}
}
struct smbios_property smbios_properties[]=
{
{.name="SMbiosvendor",.table_type= 0,.value_type=SMSTRING,.offset=0x04,.auto_str=sm_get_defstr},
{.name="SMbiosversion",.table_type= 0,.value_type=SMSTRING,.offset=0x05,.auto_str=sm_get_defstr},
{.name="SMbiosdate",.table_type= 0,.value_type=SMSTRING,.offset=0x08,.auto_str=sm_get_defstr},
{.name="SMmanufacter",.table_type= 1,.value_type=SMSTRING,.offset=0x04,.auto_str=sm_get_defstr},
{.name="SMproductname",.table_type= 1,.value_type=SMSTRING,.offset=0x05,.auto_str=sm_get_defstr},
{.name="SMsystemversion",.table_type= 1,.value_type=SMSTRING,.offset=0x06,.auto_str=sm_get_defstr},
{.name="SMserial",.table_type= 1,.value_type=SMSTRING,.offset=0x07,.auto_str=sm_get_defstr},
{.name="SMUUID",.table_type= 1, .value_type=SMOWORD,.offset=0x08,.auto_oword=0},
{.name="SMfamily",.table_type= 1,.value_type=SMSTRING,.offset=0x1a,.auto_str=sm_get_defstr},
{.name="SMboardmanufacter",.table_type= 2, .value_type=SMSTRING,.offset=0x04,.auto_str=sm_get_defstr},
{.name="SMboardproduct",.table_type= 2, .value_type=SMSTRING,.offset=0x05,.auto_str=sm_get_defstr},
{.name="SMexternalclock",.table_type= 4,.value_type=SMWORD,.offset=0x12,.auto_int=sm_get_fsb},
{.name="SMmaximalclock",.table_type= 4,.value_type=SMWORD,.offset=0x14,.auto_int=sm_get_cpu},
{.name="SMmemdevloc",.table_type=17,.value_type=SMSTRING,.offset=0x10,.auto_str=0},
{.name="SMmembankloc",.table_type=17,.value_type=SMSTRING,.offset=0x11,.auto_str=0},
{.name="SMmemtype",.table_type=17,.value_type=SMBYTE,.offset=0x12,.auto_int=sm_get_memtype},
{.name="SMmemspeed",.table_type=17,.value_type=SMWORD,.offset=0x15,.auto_int=sm_get_memspeed},
{.name="SMmemmanufacter",.table_type=17,.value_type=SMSTRING,.offset=0x17,.auto_str=sm_get_memvendor},
{.name="SMmemserial",.table_type=17,.value_type=SMSTRING,.offset=0x18,.auto_str=sm_get_memserial},
{.name="SMmempart",.table_type=17,.value_type=SMSTRING,.offset=0x1A,.auto_str=sm_get_mempartno},
{.name="SMcputype",.table_type=131,.value_type=SMWORD,.offset=0x04,.auto_int=sm_get_cputype},
{.name="SMbusspeed",.table_type=132,.value_type=SMWORD,.offset=0x04,.auto_int=sm_get_bus_speed}
{.name="SMbiosvendor",.table_type= 0,.value_type=SMSTRING,.offset=0x04,.auto_str=sm_get_defstr},
{.name="SMbiosversion",.table_type= 0,.value_type=SMSTRING,.offset=0x05,.auto_str=sm_get_defstr},
{.name="SMbiosdate",.table_type= 0,.value_type=SMSTRING,.offset=0x08,.auto_str=sm_get_defstr},
{.name="SMmanufacter",.table_type= 1,.value_type=SMSTRING,.offset=0x04,.auto_str=sm_get_defstr},
{.name="SMproductname",.table_type= 1,.value_type=SMSTRING,.offset=0x05,.auto_str=sm_get_defstr},
{.name="SMsystemversion",.table_type= 1,.value_type=SMSTRING,.offset=0x06,.auto_str=sm_get_defstr},
{.name="SMserial",.table_type= 1,.value_type=SMSTRING,.offset=0x07,.auto_str=sm_get_defstr},
{.name="SMUUID",.table_type= 1, .value_type=SMOWORD,.offset=0x08,.auto_oword=0},
{.name="SMfamily",.table_type= 1,.value_type=SMSTRING,.offset=0x1a,.auto_str=sm_get_defstr},
{.name="SMboardmanufacter",.table_type= 2, .value_type=SMSTRING,.offset=0x04,.auto_str=sm_get_defstr},
{.name="SMboardproduct",.table_type= 2, .value_type=SMSTRING,.offset=0x05,.auto_str=sm_get_defstr},
{.name="SMexternalclock",.table_type= 4,.value_type=SMWORD,.offset=0x12,.auto_int=sm_get_fsb},
{.name="SMmaximalclock",.table_type= 4,.value_type=SMWORD,.offset=0x14,.auto_int=sm_get_cpu},
{.name="SMmemdevloc",.table_type=17,.value_type=SMSTRING,.offset=0x10,.auto_str=0},
{.name="SMmembankloc",.table_type=17,.value_type=SMSTRING,.offset=0x11,.auto_str=0},
{.name="SMmemtype",.table_type=17,.value_type=SMBYTE,.offset=0x12,.auto_int=sm_get_memtype},
{.name="SMmemspeed",.table_type=17,.value_type=SMWORD,.offset=0x15,.auto_int=sm_get_memspeed},
{.name="SMmemmanufacter",.table_type=17,.value_type=SMSTRING,.offset=0x17,.auto_str=sm_get_memvendor},
{.name="SMmemserial",.table_type=17,.value_type=SMSTRING,.offset=0x18,.auto_str=sm_get_memserial},
{.name="SMmempart",.table_type=17,.value_type=SMSTRING,.offset=0x1A,.auto_str=sm_get_mempartno},
{.name="SMcputype",.table_type=131,.value_type=SMWORD,.offset=0x04,.auto_int=sm_get_cputype},
{.name="SMbusspeed",.table_type=132,.value_type=SMWORD,.offset=0x04,.auto_int=sm_get_bus_speed}
};
struct smbios_table_description smbios_table_descriptions[]=
branches/azimutz/CleanCut/i386/libsaio/cpu.c
120120
121121
122122
123
124
123125
124126
125127
......
128130
129131
130132
131
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
132164
133165
134166
}
#endif
p->CPU.Vendor= p->CPU.CPUID[CPUID_0][1];
p->CPU.Signature= p->CPU.CPUID[CPUID_1][0];
p->CPU.Stepping= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);
p->CPU.Model= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);
p->CPU.Family= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);
p->CPU.ExtModel= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);
p->CPU.NoCores= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;
p->CPU.Model += (p->CPU.ExtModel << 4);
/* get brand string (if supported) */
/* Copyright: from Apple's XNU cpuid.c */
if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {
uint32_treg[4];
char str[128], *s;
/*
* The brand string 48 bytes (max), guaranteed to
* be NUL terminated.
*/
do_cpuid(0x80000002, reg);
bcopy((char *)reg, &str[0], 16);
do_cpuid(0x80000003, reg);
bcopy((char *)reg, &str[16], 16);
do_cpuid(0x80000004, reg);
bcopy((char *)reg, &str[32], 16);
for (s = str; *s != '\0'; s++) {
if (*s != ' ') break;
}
strlcpy(p->CPU.BrandString,s, sizeof(p->CPU.BrandString));
if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, min(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {
/*
* This string means we have a firmware-programmable brand string,
* and the firmware couldn't figure out what sort of CPU we have.
*/
p->CPU.BrandString[0] = '\0';
}
}
/* setup features */
if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {
p->CPU.Features |= CPU_FEATURE_MMX;
branches/azimutz/CleanCut/i386/libsaio/platform.h
1414
1515
1616
17
18
19
20
21
22
23
24
17
18
19
20
21
22
23
24
2525
26
27
28
29
30
31
32
33
34
35
36
37
2638
27
28
29
30
31
32
33
34
35
36
39
40
41
42
43
44
45
46
47
48
3749
3850
39
51
4052
41
53
4254
4355
4456
......
5769
5870
5971
60
72
6173
6274
63
64
65
66
75
76
77
78
6779
6880
6981
......
7385
7486
7587
76
88
7789
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
90102
91103
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
111127
112128
113
114
115
116
117
118
119
120
121
122
123
129
130
131
132
133
134
135
136
137
138
139
140
124141
125142
126
127
128
129
130
143
144
145
146
147
148
131149
132
150
133151
134152
135153
extern void dumpPhysAddr(const char * title, void * a, int len);
/* CPUID index into cpuid_raw */
#define CPUID_00
#define CPUID_11
#define CPUID_22
#define CPUID_33
#define CPUID_44
#define CPUID_805
#define CPUID_816
#define CPUID_MAX7
#define CPUID_00
#define CPUID_11
#define CPUID_22
#define CPUID_33
#define CPUID_44
#define CPUID_805
#define CPUID_816
#define CPUID_MAX7
#define CPU_MODEL_YONAH0x0E
#define CPU_MODEL_MEROM0x0F
#define CPU_MODEL_PENRYN0x17
#define CPU_MODEL_NEHALEM0x1A
#define CPU_MODEL_ATOM0x1C
#define CPU_MODEL_FIELDS0x1E// Lynnfield, Clarksfield, Jasper
#define CPU_MODEL_DALES0x1F// Havendale, Auburndale
#define CPU_MODEL_DALES_32NM0x25// Clarkdale, Arrandale
#define CPU_MODEL_WESTMERE0x2C// Gulftown, Westmere-EP, Westmere-WS
#define CPU_MODEL_NEHALEM_EX0x2E
#define CPU_MODEL_WESTMERE_EX0x2F
/* CPU Features */
#define CPU_FEATURE_MMX0x00000001// MMX Instruction Set
#define CPU_FEATURE_SSE0x00000002// SSE Instruction Set
#define CPU_FEATURE_SSE20x00000004// SSE2 Instruction Set
#define CPU_FEATURE_SSE30x00000008// SSE3 Instruction Set
#define CPU_FEATURE_SSE410x00000010// SSE41 Instruction Set
#define CPU_FEATURE_SSE420x00000020// SSE42 Instruction Set
#define CPU_FEATURE_EM64T0x00000040// 64Bit Support
#define CPU_FEATURE_HTT0x00000080// HyperThreading
#define CPU_FEATURE_MOBILE0x00000100// Mobile CPU
#define CPU_FEATURE_MSR0x00000200// MSR Support
#define CPU_FEATURE_MMX0x00000001// MMX Instruction Set
#define CPU_FEATURE_SSE0x00000002// SSE Instruction Set
#define CPU_FEATURE_SSE20x00000004// SSE2 Instruction Set
#define CPU_FEATURE_SSE30x00000008// SSE3 Instruction Set
#define CPU_FEATURE_SSE410x00000010// SSE41 Instruction Set
#define CPU_FEATURE_SSE420x00000020// SSE42 Instruction Set
#define CPU_FEATURE_EM64T0x00000040// 64Bit Support
#define CPU_FEATURE_HTT0x00000080// HyperThreading
#define CPU_FEATURE_MOBILE0x00000100// Mobile CPU
#define CPU_FEATURE_MSR0x00000200// MSR Support
/* SMBIOS Memory Types */
#define SMB_MEM_TYPE_UNDEFINED0
#define SMB_MEM_TYPE_UNDEFINED0
#define SMB_MEM_TYPE_OTHER1
#define SMB_MEM_TYPE_UNKNOWN2
#define SMB_MEM_TYPE_UNKNOWN2
#define SMB_MEM_TYPE_DRAM3
#define SMB_MEM_TYPE_EDRAM4
#define SMB_MEM_TYPE_VRAM5
#define SMB_MEM_TYPE_DDR18
#define SMB_MEM_TYPE_DDR219
#define SMB_MEM_TYPE_FBDIMM20
#define SMB_MEM_TYPE_DDR324// Supported in 10.5.6+ AppleSMBIOS
#define SMB_MEM_TYPE_DDR324// Supported in 10.5.6+ AppleSMBIOS
/* Memory Configuration Types */
#define SMB_MEM_CHANNEL_UNKNOWN0
#define SMB_MEM_CHANNEL_SINGLE1
#define SMB_MEM_CHANNEL_DUAL2
#define SMB_MEM_CHANNEL_TRIPLE3
#define SMB_MEM_CHANNEL_UNKNOWN0
#define SMB_MEM_CHANNEL_SINGLE1
#define SMB_MEM_CHANNEL_DUAL2
#define SMB_MEM_CHANNEL_TRIPLE3
/* Maximum number of ram slots */
#define MAX_RAM_SLOTS8
#define MAX_SPD_SIZE256
/* Size of SMBIOS UUID in bytes */
#define UUID_LEN16
#define UUID_LEN16
typedef struct _RamSlotInfo_t {
uint32_tModuleSize;// Size of Module in MB
uint32_tFrequency; // in Mhz
const char*Vendor;
const char*PartNo;
const char*SerialNo;
char*spd;// SPD Dump
boolInUse;
uint8_tType;
uint8_tBankConnections; // table type 6, see (3.3.7)
uint8_tBankConnCnt;
typedef struct _RamSlotInfo_t
{
uint32_tModuleSize;// Size of Module in MB
uint32_tFrequency;// in Mhz
const char*Vendor;
const char*PartNo;
const char*SerialNo;
char*spd;// SPD Dump
boolInUse;
uint8_tType;
uint8_tBankConnections;// table type 6, see (3.3.7)
uint8_tBankConnCnt;
} RamSlotInfo_t;
typedef struct _PlatformInfo_t {
struct CPU {
uint32_tFeatures;// CPU Features like MMX, SSE2, VT, MobileCPU
uint32_tVendor;// Vendor
uint32_tModel;// Model
uint32_tExtModel;// Extended Model
uint32_tFamily;// Family
uint32_tExtFamily;// Extended Family
uint32_tNoCores;// No Cores per Package
uint32_tNoThreads;// Threads per Package
uint8_tMaxCoef;// Max Multiplier
uint8_tMaxDiv;
uint8_tCurrCoef;// Current Multiplier
uint8_tCurrDiv;
uint64_tTSCFrequency;// TSC Frequency Hz
uint64_tFSBFrequency;// FSB Frequency Hz
uint64_tCPUFrequency;// CPU Frequency Hz
uint32_tBrandString[16];// 48 Byte Branding String
uint32_tCPUID[CPUID_MAX][4];// CPUID 0..4, 80..81 Raw Values
typedef struct _PlatformInfo_t
{
struct CPU
{
uint32_tFeatures;// CPU Features like MMX, SSE2, VT, MobileCPU
uint32_tVendor;// Vendor
uint32_tSignature;// Signature
uint32_tStepping;// Stepping
uint32_tModel;// Model
uint32_tExtModel;// Extended Model
uint32_tFamily;// Family
uint32_tExtFamily;// Extended Family
uint32_tNoCores;// No Cores per Package
uint32_tNoThreads;// Threads per Package
uint8_tMaxCoef;// Max Multiplier
uint8_tMaxDiv;
uint8_tCurrCoef;// Current Multiplier
uint8_tCurrDiv;
uint64_tTSCFrequency;// TSC Frequency Hz
uint64_tFSBFrequency;// FSB Frequency Hz
uint64_tCPUFrequency;// CPU Frequency Hz
charBrandString[48];// 48 Byte Branding String
uint32_tCPUID[CPUID_MAX][4];// CPUID 0..4, 80..81 Raw Values
} CPU;
struct RAM {
uint64_tFrequency;// Ram Frequency
uint32_tDivider;// Memory divider
uint8_tCAS;// CAS 1/2/2.5/3/4/5/6/7
uint8_tTRC;
uint8_tTRP;
uint8_tRAS;
uint8_tChannels;// Channel Configuration Single,Dual or Triple
uint8_tNoSlots;// Maximum no of slots available
uint8_tType;// Standard SMBIOS v2.5 Memory Type
RamSlotInfo_tDIMM[MAX_RAM_SLOTS];// Information about each slot
struct RAM
{
uint64_tFrequency;// Ram Frequency
uint32_tDivider;// Memory divider
uint8_tCAS;// CAS 1/2/2.5/3/4/5/6/7
uint8_tTRC;
uint8_tTRP;
uint8_tRAS;
uint8_tChannels;// Channel Configuration Single,Dual or Triple
uint8_tNoSlots;// Maximum no of slots available
uint8_tType;// Standard SMBIOS v2.5 Memory Type
RamSlotInfo_tDIMM[MAX_RAM_SLOTS];// Information about each slot
} RAM;
struct DMI {
intMaxMemorySlots;// number of memory slots polulated by SMBIOS
intCntMemorySlots;// number of memory slots counted
intMemoryModules;// number of memory modules installed
intDIMM[MAX_RAM_SLOTS];// Information and SPD mapping for each slot
struct DMI
{
intMaxMemorySlots;// number of memory slots polulated by SMBIOS
intCntMemorySlots;// number of memory slots counted
intMemoryModules;// number of memory modules installed
intDIMM[MAX_RAM_SLOTS];// Information and SPD mapping for each slot
} DMI;
uint8_tType;// System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)
uint8_tType;// System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)
} PlatformInfo_t;
extern PlatformInfo_t Platform;
branches/azimutz/CleanCut/i386/libsaio/cpu.h
1414
1515
1616
17
18
1719
1820
1921
#define bitmask(h,l)((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
#define bitfield(x,h,l)(((x) & bitmask(h,l)) >> l)
#define CPU_STRING_UNKNOWN"Unknown CPU Type"
#defineMSR_IA32_PERF_STATUS0x198
#define MSR_IA32_PERF_CONTROL0x199
#define MSR_IA32_EXT_CONFIG0x00EE

Archive Download the corresponding diff file

Revision: 323