Chameleon

Chameleon Commit Details

Date:2010-09-13 04:07:37 (9 years 1 month ago)
Author:Rekursor
Commit:517
Parents: 516
Message:Fixed bad previous nhm mem reg reassignment, trp was 0 and ras was in fact CAS ...
Changes:
M/trunk/i386/libsaio/dram_controllers.c

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trunk/i386/libsaio/dram_controllers.c
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// RAS-To-CAS (tRCD)
Platform.RAM.TRC = (mc_channel_bank_timing >> 9) & 0xF;
// RAS Active to precharge (tRAS)
Platform.RAM.RAS = (mc_channel_bank_timing >> 4) & 0x1F;
// RAS Precharge (tRP)
Platform.RAM.CAS = (mc_channel_bank_timing >> 4) & 0x1F;
Platform.RAM.TRP = mc_channel_bank_timing & 0xF;
// RAS Active to precharge (tRAS)
Platform.RAM.RAS = mc_channel_bank_timing & 0xF;
// Single , Dual or Triple Channels
if (mc_control == 1 || mc_control == 2 || mc_control == 4 )
Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;
if (dram_controllers[i].poll_speed != NULL)
dram_controllers[i].poll_speed(dram_dev);
verbose("Frequency detected: %d MHz (%d) %s Channel %d-%d-%d-%d\n",
verbose("Frequency detected: %d MHz (%d) %s Channel \n\tCAS:%d tRC:%d tRP:%d RAS:%d (%d-%d-%d-%d)\n",
(uint32_t)Platform.RAM.Frequency / 1000000,
(uint32_t)Platform.RAM.Frequency / 500000,
memory_channel_types[Platform.RAM.Channels],
Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS
memory_channel_types[Platform.RAM.Channels]
,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS
,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS
);
/* getc();
*/
}
}

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Revision: 517