Chameleon

Chameleon Commit Details

Date:2010-09-13 19:42:04 (8 years 10 months ago)
Author:Evan Lojewski
Commit:519
Parents: 518
Message:Moved GraphicsEnabler into a module. Untested
Changes:
D/branches/meklort/i386/libsaio/nvidia.c
D/branches/meklort/i386/libsaio/ati.c
D/branches/meklort/i386/libsaio/nvidia.h
D/branches/meklort/i386/libsaio/ati.h
A/branches/meklort/i386/modules/GraphicsEnabler/GraphicsEnabler.c
A/branches/meklort/i386/modules/GraphicsEnabler/Makefile
A/branches/meklort/i386/modules/GraphicsEnabler/nvidia.c
A/branches/meklort/i386/modules/GraphicsEnabler/ati.c
A/branches/meklort/i386/modules/GraphicsEnabler/nvidia.h
A/branches/meklort/i386/modules/GraphicsEnabler
A/branches/meklort/i386/modules/GraphicsEnabler/ati.h
M/branches/meklort/i386/modules/KextPatcher/Makefile
M/branches/meklort/i386/modules/KernelPatcher/Makefile
M/branches/meklort/i386/Makefile
M/branches/meklort/i386/modules/Symbols/Makefile
M/branches/meklort/i386/boot2/boot.h
M/branches/meklort/Makefile
M/branches/meklort/i386/modules/Makefile
M/branches/meklort/i386/cdboot/Makefile
M/branches/meklort/i386/util/Makefile
M/branches/meklort/i386/libsaio/pci_setup.c
M/branches/meklort/i386/libsaio/Makefile
M/branches/meklort/i386/modules/HelloWorld/Makefile

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branches/meklort/i386/libsaio/nvidia.c
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/*
* NVidia injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi
*
* NVidia injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* NVidia driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
/*
* DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
*
*
* Copyright 2005-2006 Erik Waling
* Copyright 2006 Stephane Marchesin
* Copyright 2007-2009 Stuart Bennett
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "libsaio.h"
#include "boot.h"
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#include "device_inject.h"
#include "nvidia.h"
#ifndef DEBUG_NVIDIA
#define DEBUG_NVIDIA 0
#endif
#if DEBUG_NVIDIA
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
#define NVIDIA_ROM_SIZE 0x10000
#define PATCH_ROM_SUCCESS 1
#define PATCH_ROM_SUCCESS_HAS_LVDS 2
#define PATCH_ROM_FAILED 0
#define MAX_NUM_DCB_ENTRIES 16
#define TYPE_GROUPED 0xff
extern uint32_t devices_number;
const char *nvidia_compatible_0[]={ "@0,compatible","NVDA,NVMac" };
const char *nvidia_compatible_1[]={ "@1,compatible","NVDA,NVMac" };
const char *nvidia_device_type_0[]={ "@0,device_type","display" };
const char *nvidia_device_type_1[]={ "@1,device_type","display" };
const char *nvidia_device_type[]={ "device_type","NVDA,Parent" };
const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
const char *nvidia_slot_name[]={ "AAPL,slot-name","Slot-1" };
static uint8_t default_NVCAP[]= {
0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
0x00, 0x00, 0x00, 0x00
};
#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )
static struct nv_chipsets_t NVKnownChipsets[] = {
{ 0x00000000, "Unknown" },
{ 0x10DE0040, "GeForce 6800 Ultra" },
{ 0x10DE0041, "GeForce 6800" },
{ 0x10DE0042, "GeForce 6800 LE" },
{ 0x10DE0043, "GeForce 6800 XE" },
{ 0x10DE0044, "GeForce 6800 XT" },
{ 0x10DE0045, "GeForce 6800 GT" },
{ 0x10DE0046, "GeForce 6800 GT" },
{ 0x10DE0047, "GeForce 6800 GS" },
{ 0x10DE0048, "GeForce 6800 XT" },
{ 0x10DE004E, "Quadro FX 4000" },
{ 0x10DE0090, "GeForce 7800 GTX" },
{ 0x10DE0091, "GeForce 7800 GTX" },
{ 0x10DE0092, "GeForce 7800 GT" },
{ 0x10DE0093, "GeForce 7800 GS" },
{ 0x10DE0095, "GeForce 7800 SLI" },
{ 0x10DE0098, "GeForce Go 7800" },
{ 0x10DE0099, "GeForce Go 7800 GTX" },
{ 0x10DE009D, "Quadro FX 4500" },
{ 0x10DE00C0, "GeForce 6800 GS" },
{ 0x10DE00C1, "GeForce 6800" },
{ 0x10DE00C2, "GeForce 6800 LE" },
{ 0x10DE00C3, "GeForce 6800 XT" },
{ 0x10DE00C8, "GeForce Go 6800" },
{ 0x10DE00C9, "GeForce Go 6800 Ultra" },
{ 0x10DE00CC, "Quadro FX Go1400" },
{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },
{ 0x10DE00CE, "Quadro FX 1400" },
{ 0x10DE0140, "GeForce 6600 GT" },
{ 0x10DE0141, "GeForce 6600" },
{ 0x10DE0142, "GeForce 6600 LE" },
{ 0x10DE0143, "GeForce 6600 VE" },
{ 0x10DE0144, "GeForce Go 6600" },
{ 0x10DE0145, "GeForce 6610 XL" },
{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },
{ 0x10DE0147, "GeForce 6700 XL" },
{ 0x10DE0148, "GeForce Go 6600" },
{ 0x10DE0149, "GeForce Go 6600 GT" },
{ 0x10DE014C, "Quadro FX 550" },
{ 0x10DE014D, "Quadro FX 550" },
{ 0x10DE014E, "Quadro FX 540" },
{ 0x10DE014F, "GeForce 6200" },
{ 0x10DE0160, "GeForce 6500" },
{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },
{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },
{ 0x10DE0163, "GeForce 6200 LE" },
{ 0x10DE0164, "GeForce Go 6200" },
{ 0x10DE0165, "Quadro NVS 285" },
{ 0x10DE0166, "GeForce Go 6400" },
{ 0x10DE0167, "GeForce Go 6200" },
{ 0x10DE0168, "GeForce Go 6400" },
{ 0x10DE0169, "GeForce 6250" },
{ 0x10DE016A, "GeForce 7100 GS" },
{ 0x10DE0191, "GeForce 8800 GTX" },
{ 0x10DE0193, "GeForce 8800 GTS" },
{ 0x10DE0194, "GeForce 8800 Ultra" },
{ 0x10DE019D, "Quadro FX 5600" },
{ 0x10DE019E, "Quadro FX 4600" },
{ 0x10DE01D1, "GeForce 7300 LE" },
{ 0x10DE01D3, "GeForce 7300 SE" },
{ 0x10DE01D6, "GeForce Go 7200" },
{ 0x10DE01D7, "GeForce Go 7300" },
{ 0x10DE01D8, "GeForce Go 7400" },
{ 0x10DE01D9, "GeForce Go 7400 GS" },
{ 0x10DE01DA, "Quadro NVS 110M" },
{ 0x10DE01DB, "Quadro NVS 120M" },
{ 0x10DE01DC, "Quadro FX 350M" },
{ 0x10DE01DD, "GeForce 7500 LE" },
{ 0x10DE01DE, "Quadro FX 350" },
{ 0x10DE01DF, "GeForce 7300 GS" },
{ 0x10DE0211, "GeForce 6800" },
{ 0x10DE0212, "GeForce 6800 LE" },
{ 0x10DE0215, "GeForce 6800 GT" },
{ 0x10DE0218, "GeForce 6800 XT" },
{ 0x10DE0221, "GeForce 6200" },
{ 0x10DE0222, "GeForce 6200 A-LE" },
{ 0x10DE0240, "GeForce 6150" },
{ 0x10DE0241, "GeForce 6150 LE" },
{ 0x10DE0242, "GeForce 6100" },
{ 0x10DE0244, "GeForce Go 6150" },
{ 0x10DE0247, "GeForce Go 6100" },
{ 0x10DE0290, "GeForce 7900 GTX" },
{ 0x10DE0291, "GeForce 7900 GT" },
{ 0x10DE0292, "GeForce 7900 GS" },
{ 0x10DE0298, "GeForce Go 7900 GS" },
{ 0x10DE0299, "GeForce Go 7900 GTX" },
{ 0x10DE029A, "Quadro FX 2500M" },
{ 0x10DE029B, "Quadro FX 1500M" },
{ 0x10DE029C, "Quadro FX 5500" },
{ 0x10DE029D, "Quadro FX 3500" },
{ 0x10DE029E, "Quadro FX 1500" },
{ 0x10DE029F, "Quadro FX 4500 X2" },
{ 0x10DE0301, "GeForce FX 5800 Ultra" },
{ 0x10DE0302, "GeForce FX 5800" },
{ 0x10DE0308, "Quadro FX 2000" },
{ 0x10DE0309, "Quadro FX 1000" },
{ 0x10DE0311, "GeForce FX 5600 Ultra" },
{ 0x10DE0312, "GeForce FX 5600" },
{ 0x10DE0314, "GeForce FX 5600XT" },
{ 0x10DE031A, "GeForce FX Go5600" },
{ 0x10DE031B, "GeForce FX Go5650" },
{ 0x10DE031C, "Quadro FX Go700" },
{ 0x10DE0324, "GeForce FX Go5200" },
{ 0x10DE0325, "GeForce FX Go5250" },
{ 0x10DE0326, "GeForce FX 5500" },
{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },
{ 0x10DE032A, "Quadro NVS 55/280 PCI" },
{ 0x10DE032B, "Quadro FX 500/600 PCI" },
{ 0x10DE032C, "GeForce FX Go53xx Series" },
{ 0x10DE032D, "GeForce FX Go5100" },
{ 0x10DE0330, "GeForce FX 5900 Ultra" },
{ 0x10DE0331, "GeForce FX 5900" },
{ 0x10DE0332, "GeForce FX 5900XT" },
{ 0x10DE0333, "GeForce FX 5950 Ultra" },
{ 0x10DE0334, "GeForce FX 5900ZT" },
{ 0x10DE0338, "Quadro FX 3000" },
{ 0x10DE033F, "Quadro FX 700" },
{ 0x10DE0341, "GeForce FX 5700 Ultra" },
{ 0x10DE0342, "GeForce FX 5700" },
{ 0x10DE0343, "GeForce FX 5700LE" },
{ 0x10DE0344, "GeForce FX 5700VE" },
{ 0x10DE0347, "GeForce FX Go5700" },
{ 0x10DE0348, "GeForce FX Go5700" },
{ 0x10DE034C, "Quadro FX Go1000" },
{ 0x10DE034E, "Quadro FX 1100" },
{ 0x10DE0391, "GeForce 7600 GT" },
{ 0x10DE0392, "GeForce 7600 GS" },
{ 0x10DE0393, "GeForce 7300 GT" },
{ 0x10DE0394, "GeForce 7600 LE" },
{ 0x10DE0395, "GeForce 7300 GT" },
{ 0x10DE0397, "GeForce Go 7700" },
{ 0x10DE0398, "GeForce Go 7600" },
{ 0x10DE0399, "GeForce Go 7600 GT"},
{ 0x10DE039A, "Quadro NVS 300M" },
{ 0x10DE039B, "GeForce Go 7900 SE" },
{ 0x10DE039C, "Quadro FX 550M" },
{ 0x10DE039E, "Quadro FX 560" },
{ 0x10DE0400, "GeForce 8600 GTS" },
{ 0x10DE0401, "GeForce 8600 GT" },
{ 0x10DE0402, "GeForce 8600 GT" },
{ 0x10DE0403, "GeForce 8600 GS" },
{ 0x10DE0404, "GeForce 8400 GS" },
{ 0x10DE0405, "GeForce 9500M GS" },
{ 0x10DE0407, "GeForce 8600M GT" },
{ 0x10DE0408, "GeForce 9650M GS" },
{ 0x10DE0409, "GeForce 8700M GT" },
{ 0x10DE040A, "Quadro FX 370" },
{ 0x10DE040B, "Quadro NVS 320M" },
{ 0x10DE040C, "Quadro FX 570M" },
{ 0x10DE040D, "Quadro FX 1600M" },
{ 0x10DE040E, "Quadro FX 570" },
{ 0x10DE040F, "Quadro FX 1700" },
{ 0x10DE0420, "GeForce 8400 SE" },
{ 0x10DE0421, "GeForce 8500 GT" },
{ 0x10DE0422, "GeForce 8400 GS" },
{ 0x10DE0423, "GeForce 8300 GS" },
{ 0x10DE0424, "GeForce 8400 GS" },
{ 0x10DE0425, "GeForce 8600M GS" },
{ 0x10DE0426, "GeForce 8400M GT" },
{ 0x10DE0427, "GeForce 8400M GS" },
{ 0x10DE0428, "GeForce 8400M G" },
{ 0x10DE0429, "Quadro NVS 140M" },
{ 0x10DE042A, "Quadro NVS 130M" },
{ 0x10DE042B, "Quadro NVS 135M" },
{ 0x10DE042C, "GeForce 9400 GT" },
{ 0x10DE042D, "Quadro FX 360M" },
{ 0x10DE042E, "GeForce 9300M G" },
{ 0x10DE042F, "Quadro NVS 290" },
{ 0x10DE05E0, "GeForce GTX 295" },
{ 0x10DE05E1, "GeForce GTX 280" },
{ 0x10DE05E2, "GeForce GTX 260" },
{ 0x10DE05E3, "GeForce GTX 285" },
{ 0x10DE05E6, "GeForce GTX 275" },
{ 0x10DE05EA, "GeForce GTX 260" },
{ 0x10DE05EB, "GeForce GTX 295" },
{ 0x10DE05F9, "Quadro CX" },
{ 0x10DE05FD, "Quadro FX 5800" },
{ 0x10DE05FE, "Quadro FX 4800" },
{ 0x10DE0600, "GeForce 8800 GTS 512" },
{ 0x10DE0602, "GeForce 8800 GT" },
{ 0x10DE0604, "GeForce 9800 GX2" },
{ 0x10DE0605, "GeForce 9800 GT" },
{ 0x10DE0606, "GeForce 8800 GS" },
{ 0x10DE0607, "GeForce GTS 240" },
{ 0x10DE0608, "GeForce 9800M GTX" },
{ 0x10DE0609, "GeForce 8800M GTS" },
{ 0x10DE060A, "GeForce GTX 280M" },
{ 0x10DE060B, "GeForce 9800M GT" },
{ 0x10DE060C, "GeForce 8800M GTX" },
{ 0x10DE060D, "GeForce 8800 GS" },
{ 0x10DE0610, "GeForce 9600 GSO" },
{ 0x10DE0611, "GeForce 8800 GT" },
{ 0x10DE0612, "GeForce 9800 GTX" },
{ 0x10DE0613, "GeForce 9800 GTX+" },
{ 0x10DE0614, "GeForce 9800 GT" },
{ 0x10DE0615, "GeForce GTS 250" },
{ 0x10DE0617, "GeForce 9800M GTX" },
{ 0x10DE0618, "GeForce GTX 260M" },
{ 0x10DE061A, "Quadro FX 3700" },
{ 0x10DE061C, "Quadro FX 3600M" },
{ 0x10DE061D, "Quadro FX 2800M" },
{ 0x10DE061F, "Quadro FX 3800M" },
{ 0x10DE0622, "GeForce 9600 GT" },
{ 0x10DE0623, "GeForce 9600 GS" },
{ 0x10DE0625, "GeForce 9600 GSO 512"},
{ 0x10DE0626, "GeForce GT 130" },
{ 0x10DE0627, "GeForce GT 140" },
{ 0x10DE0628, "GeForce 9800M GTS" },
{ 0x10DE062A, "GeForce 9700M GTS" },
{ 0x10DE062C, "GeForce 9800M GTS" },
{ 0x10DE0640, "GeForce 9500 GT" },
{ 0x10DE0641, "GeForce 9400 GT" },
{ 0x10DE0642, "GeForce 8400 GS" },
{ 0x10DE0643, "GeForce 9500 GT" },
{ 0x10DE0644, "GeForce 9500 GS" },
{ 0x10DE0645, "GeForce 9500 GS" },
{ 0x10DE0646, "GeForce GT 120" },
{ 0x10DE0647, "GeForce 9600M GT" },
{ 0x10DE0648, "GeForce 9600M GS" },
{ 0x10DE0649, "GeForce 9600M GT" },
{ 0x10DE064A, "GeForce 9700M GT" },
{ 0x10DE064B, "GeForce 9500M G" },
{ 0x10DE064C, "GeForce 9650M GT" },
{ 0x10DE0652, "GeForce GT 130M" },
{ 0x10DE0658, "Quadro FX 380" },
{ 0x10DE0659, "Quadro FX 580" },
{ 0x10DE065A, "Quadro FX 1700M" },
{ 0x10DE065B, "GeForce 9400 GT" },
{ 0x10DE065C, "Quadro FX 770M" },
{ 0x10DE06C0, "GeForce GTX 480" },
{ 0x10DE06C4, "GeForce GTX 465" },
{ 0x10DE06CA, "GeForce GTX 480M" },
{ 0x10DE06CD, "GeForce GTX 470" },
{ 0x10DE06E0, "GeForce 9300 GE" },
{ 0x10DE06E1, "GeForce 9300 GS" },
{ 0x10DE06E4, "GeForce 8400 GS" },
{ 0x10DE06E5, "GeForce 9300M GS" },
{ 0x10DE06E8, "GeForce 9200M GS" },
{ 0x10DE06E9, "GeForce 9300M GS" },
{ 0x10DE06EA, "Quadro NVS 150M" },
{ 0x10DE06EB, "Quadro NVS 160M" },
{ 0x10DE06EC, "GeForce G 105M" },
{ 0x10DE06EF, "GeForce G 103M" },
{ 0x10DE06F8, "Quadro NVS 420" },
{ 0x10DE06F9, "Quadro FX 370 LP" },
{ 0x10DE06FA, "Quadro NVS 450" },
{ 0x10DE06FD, "Quadro NVS 295" },
{ 0x10DE086C, "GeForce 9300/nForce 730i" },
{ 0x10DE087D, "ION 9400M" },
{ 0x10DE087E, "ION LE" },
{ 0x10DE0A20, "GeForce GT220" },
{ 0x10DE0A23, "GeForce 210" },
{ 0x10DE0A28, "GeForce GT 230M" },
{ 0x10DE0A2A, "GeForce GT 230M" },
{ 0x10DE0A34, "GeForce GT 240M" },
{ 0x10DE0A60, "GeForce G210" },
{ 0x10DE0A62, "GeForce 205" },
{ 0x10DE0A63, "GeForce 310" },
{ 0x10DE0A65, "GeForce 210" },
{ 0x10DE0A66, "GeForce 310" },
{ 0x10DE0A74, "GeForce G210M" },
{ 0x10DE0A78, "Quadro FX 380 LP" },
{ 0x10DE0CA3, "GeForce GT 240" },
{ 0x10DE0CA8, "GeForce GTS 260M" },
{ 0x10DE0CA9, "GeForce GTS 250M" },
{ 0x10DE0CA3, "GeForce GT240" },
{ 0x10DE0E22, "GeForce GTX 460" },
{ 0x10DE0E24, "GeForce GTX 460" },
{ 0x10DE06D1, "Tesla C2050" },// TODO: sub-device id: 0x0771
{ 0x10DE06D1, "Tesla C2070" },// TODO: sub-device id: 0x0772
{ 0x10DE06DE, "Tesla M2050" },// TODO: sub-device id: 0x0846
{ 0x10DE06DE, "Tesla M2070" }// TODO: sub-device id: ?
};
static uint16_t swap16(uint16_t x)
{
return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));
}
static uint16_t read16(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[2];
ret[0] = ptr[offset+1];
ret[1] = ptr[offset];
return *((uint16_t*)&ret);
}
#if 0
static uint32_t swap32(uint32_t x)
{
return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);
}
static uint8_t read8(uint8_t *ptr, uint16_t offset)
{
return ptr[offset];
}
static uint32_t read32(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[4];
ret[0] = ptr[offset+3];
ret[1] = ptr[offset+2];
ret[2] = ptr[offset+1];
ret[3] = ptr[offset];
return *((uint32_t*)&ret);
}
#endif
static int patch_nvidia_rom(uint8_t *rom)
{
if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {
printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);
return PATCH_ROM_FAILED;
}
uint16_t dcbptr = swap16(read16(rom, 0x36));
if(!dcbptr) {
printf("no dcb table found\n");
return PATCH_ROM_FAILED;
}/* else
printf("dcb table at offset 0x%04x\n", dcbptr);
*/
uint8_t *dcbtable = &rom[dcbptr];
uint8_t dcbtable_version = dcbtable[0];
uint8_t headerlength = 0;
uint8_t recordlength = 0;
uint8_t numentries = 0;
if(dcbtable_version >= 0x20) {
uint32_t sig;
if(dcbtable_version >= 0x30) {
headerlength = dcbtable[1];
numentries = dcbtable[2];
recordlength = dcbtable[3];
sig = *(uint32_t *)&dcbtable[6];
} else {
sig = *(uint32_t *)&dcbtable[4];
headerlength = 8;
}
if (sig != 0x4edcbdcb) {
printf("bad display config block signature (0x%8x)\n", sig);
return PATCH_ROM_FAILED;
}
} else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */
char sig[8] = { 0 };
strncpy(sig, (char *)&dcbtable[-7], 7);
recordlength = 10;
if (strcmp(sig, "DEV_REC")) {
printf("Bad Display Configuration Block signature (%s)\n", sig);
return PATCH_ROM_FAILED;
}
} else {
return PATCH_ROM_FAILED;
}
if(numentries >= MAX_NUM_DCB_ENTRIES)
numentries = MAX_NUM_DCB_ENTRIES;
uint8_t num_outputs = 0, i=0;
struct dcbentry {
uint8_t type;
uint8_t index;
uint8_t *heads;
} entries[numentries];
for (i = 0; i < numentries; i++) {
uint32_t connection;
connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];
/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
continue;
if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */
continue;
if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */
continue;
entries[num_outputs].type = connection & 0xf;
entries[num_outputs].index = num_outputs;
entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);
}
int has_lvds = false;
uint8_t channel1 = 0, channel2 = 0;
for(i=0; i<num_outputs; i++) {
if(entries[i].type == 3) {
has_lvds = true;
//printf("found LVDS\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
}
// if we have a LVDS output, we group the rest to the second channel
if(has_lvds) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
continue;
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
} else {
//
int x;
// we loop twice as we need to generate two channels
for(x=0; x<=1; x++) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
continue;
// if type is TMDS, the prior output is ANALOG
// we always group ANALOG and TMDS
// if there is a TV output after TMDS, we group it to that channel as well
if(i && entries[i].type == 0x2) {
switch (x) {
case 0:
//printf("group channel 1\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if((entries[i-1].type == 0x0)) {
channel1 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
//printf("group tv1\n");
channel1 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
case 1:
//printf("group channel 2 : %d\n", i);
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if((entries[i-1].type == 0x0)) {
channel2 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
//printf("group tv2\n");
channel2 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
}
break;
}
}
}
}
// if we have left ungrouped outputs merge them to the empty channel
uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);
togroup = &channel2;
for(i=0; i<num_outputs;i++)
if(entries[i].type != TYPE_GROUPED) {
//printf("%d not grouped\n", i);
if(togroup)
*togroup |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
if(channel1 > channel2) {
uint8_t buff = channel1;
channel1 = channel2;
channel2 = buff;
}
default_NVCAP[6] = channel1;
default_NVCAP[8] = channel2;
// patching HEADS
for(i=0; i<num_outputs;i++) {
if(channel1 & (1 << i))
*entries[i].heads = 1;
else if(channel2 & (1 << i))
*entries[i].heads = 2;
}
return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);
}
static char *get_nvidia_model(uint32_t id) {
inti;
for (i=1; i< (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {
if (NVKnownChipsets[i].device == id) {
return NVKnownChipsets[i].name;
}
}
return NVKnownChipsets[0].name;
}
static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)
{
intfd;
intsize;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {
return 0;
}
size = file_size(fd);
if (size > bufsize) {
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);
size = bufsize;
}
size = read(fd, (char *)buf, size);
close(fd);
return size > 0 ? size : 0;
}
static int devprop_add_nvidia_template(struct DevPropDevice *device)
{
chartmp[16];
if(!device)
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_name_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_name_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type))
return 0;
// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!
// len = sprintf(tmp, "Slot-%x", devices_number);
sprintf(tmp, "Slot-%x",devices_number);
devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));
devices_number++;
return 1;
}
int hex2bin(const char *hex, uint8_t *bin, int len)
{
char*p;
inti;
charbuf[3];
if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {
printf("[ERROR] bin2hex input error\n");
return -1;
}
buf[2] = '\0';
p = (char *) hex;
for (i=0; i<len; i++) {
if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {
printf("[ERROR] bin2hex '%s' syntax error\n", hex);
return -2;
}
buf[0] = *p++;
buf[1] = *p++;
bin[i] = (unsigned char) strtoul(buf, NULL, 16);
}
return 0;
}
unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)
{
unsigned long long vram_size = 0;
if (nvCardType < NV_ARCH_50) {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
}
else if (nvCardType >= NV_ARCH_C0) {
vram_size = REG32(NVC0_MEM_CTRLR_COUNT);
vram_size *= REG32(NVC0_MEM_CTRLR_RAM_AMOUNT);
vram_size <<= 20;
}
else {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size |= (vram_size & 0xff) << 32;
vram_size &= 0xffffffff00ll;
}
return vram_size;
}
bool setup_nvidia_devprop(pci_dt_t *nvda_dev)
{
struct DevPropDevice*device;
char*devicepath;
struct pci_rom_pci_header_t*rom_pci_header;
volatile uint8_t*regs;
uint8_t*rom;
uint8_t*nvRom;
uint8_tnvCardType;
unsigned long longvideoRam;
uint32_tnvBiosOveride;
uint32_tbar[7];
uint32_tboot_display;
intnvPatch;
intlen;
charbiosVersion[32];
charnvFilename[32];
charkNVCAP[12];
char*model;
const char*value;
booldoit;
devicepath = get_pci_dev_path(nvda_dev);
bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );
regs = (uint8_t *) (bar[0] & ~0x0f);
delay(50);
// get card type
nvCardType = (REG32(0) >> 20) & 0x1ff;
// Amount of VRAM in kilobytes
videoRam = mem_detect(regs, nvCardType, nvda_dev);
model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);
verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",
model, (uint32_t)(videoRam / 1024 / 1024),
(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,
devicepath);
rom = malloc(NVIDIA_ROM_SIZE);
sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id);
if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit) {
verbose("Looking for nvidia video bios file %s\n", nvFilename);
nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);
if (nvBiosOveride > 0) {
verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);
DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);
} else {
printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);
return false;
}
} else {
// Otherwise read bios from card
nvBiosOveride = 0;
// TODO: we should really check for the signature before copying the rom, i think.
// PRAMIN first
nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];
bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
// PROM next
// Enable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;
nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];
bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// disable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
// 0xC0000 last
bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
printf("ERROR: Unable to locate nVidia Video BIOS\n");
return false;
} else {
DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
} else {
DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
} else {
DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
}
if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {
printf("ERROR: nVidia ROM Patching Failed!\n");
return false;
}
rom_pci_header = (struct pci_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);
// check for 'PCIR' sig
if (rom_pci_header->signature == 0x50434952) {
if (rom_pci_header->device != nvda_dev->device_id) {
// Get Model from the OpROM
model = get_nvidia_model((rom_pci_header->vendor << 16) | rom_pci_header->device);
} else {
printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);
}
}
if (!string) {
string = devprop_create_string();
}
device = devprop_add_device(string, devicepath);
/* FIXME: for primary graphics card only */
boot_display = 1;
devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
if(nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {
uint8_t built_in = 0x01;
devprop_add_value(device, "@0,built-in", &built_in, 1);
}
// get bios version
const int MAX_BIOS_VERSION_LENGTH = 32;
char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);
memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);
int i, version_start;
int crlf_count = 0;
// only search the first 384 bytes
for(i = 0; i < 0x180; i++) {
if(rom[i] == 0x0D && rom[i+1] == 0x0A) {
crlf_count++;
// second 0x0D0A was found, extract bios version
if(crlf_count == 2) {
if(rom[i-1] == 0x20) i--; // strip last " "
for(version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--) {
// find start
if(rom[version_start] == 0x00) {
version_start++;
// strip "Version "
if(strncmp((const char*)rom+version_start, "Version ", 8) == 0) {
version_start += 8;
}
strncpy(version_str, (const char*)rom+version_start, i-version_start);
break;
}
}
break;
}
}
}
sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);
sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);
if (getValueForKey(kNVCAP, &value, &len, &bootInfo->bootConfig) && len == NVCAP_LEN * 2) {
uint8_tnew_NVCAP[NVCAP_LEN];
if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) {
verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);
memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);
}
}
#if DEBUG_NVCAP
printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",
default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],
default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],
default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],
default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],
default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);
#endif
devprop_add_nvidia_template(device);
devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);
devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);
devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);
if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit) {
devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));
}
stringdata = malloc(sizeof(uint8_t) * string->length);
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
branches/meklort/i386/libsaio/ati.c
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/*
* ATI injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas
*
* ATI injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ATI driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with ATI injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
#include "libsaio.h"
#include "boot.h"
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#include "device_inject.h"
#include "ati.h"
#ifndef DEBUG_ATI
#define DEBUG_ATI 0
#endif
#if DEBUG_ATI
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
#define MAX_NUM_DCB_ENTRIES 16
#define TYPE_GROUPED 0xff
extern uint32_t devices_number;
const char *ati_compatible_0[]= { "@0,compatible", "ATY,%s" };
const char *ati_compatible_1[]= { "@1,compatible", "ATY,%s" };
const char *ati_device_type_0[]= { "@0,device_type", "display" };
const char *ati_device_type_1[]= { "@1,device_type", "display" };
const char *ati_device_type[]= { "device_type", "ATY,%sParent" };
const char *ati_name_0[]= { "@0,name", "ATY,%s" };
const char *ati_name_1[]= { "@1,name", "ATY,%s" };
const char *ati_name[]= { "name", "ATY,%sParent" };
const char *ati_efidisplay_0[]= { "@0,ATY,EFIDisplay", "TMDSB" };
struct ati_data_key ati_connector_type_0= { 0x04, "@0,connector-type", {0x00, 0x04, 0x00, 0x00} };
struct ati_data_key ati_connector_type_1= { 0x04, "@1,connector-type", {0x04, 0x00, 0x00, 0x00} };
struct ati_data_key ati_display_con_fl_type_0= { 0x04, "@0,display-connect-flags", {0x00, 0x00, 0x04, 0x00} };
const char *ati_display_type_0[]= { "@0,display-type", "LCD" };
const char *ati_display_type_1[]= { "@1,display-type", "NONE" };
struct ati_data_key ati_aux_power_conn= { 0x04, "AAPL,aux-power-connected", {0x01, 0x00, 0x00, 0x00} };
struct ati_data_key ati_backlight_ctrl= { 0x04, "AAPL,backlight-control", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl01_coher= { 0x04, "AAPL01,Coherency", {0x01, 0x00, 0x00, 0x00} };
const char *ati_card_no[]= { "ATY,Card#", "109-B77101-00" };
const char *ati_copyright[]= { "ATY,Copyright", "Copyright AMD Inc. All Rights Reserved. 2005-2009" };
const char *ati_efi_compile_d[]= { "ATY,EFICompileDate", "Jan 26 2009" };
struct ati_data_key ati_efi_disp_conf= { 0x08, "ATY,EFIDispConfig", {0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} };
struct ati_data_key ati_efi_drv_type= { 0x01, "ATY,EFIDriverType", {0x02} };
struct ati_data_key ati_efi_enbl_mode= { 0x01, "ATY,EFIEnabledMode", {0x01} };
struct ati_data_key ati_efi_init_stat= { 0x04, "ATY,EFIHWInitStatus", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_efi_orientation= { 0x02, "ATY,EFIOrientation", {0x02, 0x00} };
const char *ati_efi_version[]= { "ATY,EFIVersion", "01.00.318" };
const char *ati_efi_versionB[]= { "ATY,EFIVersionB", "113-SBSJ1G04-00R-02" };
const char *ati_efi_versionE[]= { "ATY,EFIVersionE", "113-B7710A-318" };
struct ati_data_key ati_mclk= { 0x04, "ATY,MCLK", {0x70, 0x2e, 0x11, 0x00} };
struct ati_data_key ati_mem_rev_id= { 0x02, "ATY,MemRevisionID", {0x03, 0x00} };
struct ati_data_key ati_mem_vend_id= { 0x02, "ATY,MemVendorID", {0x02, 0x00} };
const char *ati_mrt[]= { "ATY,MRT", " " };
const char *ati_romno[]= { "ATY,Rom#", "113-B7710C-176" };
struct ati_data_key ati_sclk= { 0x04, "ATY,SCLK", {0x28, 0xdb, 0x0b, 0x00} };
struct ati_data_key ati_vendor_id= { 0x02, "ATY,VendorID", {0x02, 0x10} };
struct ati_data_key ati_platform_info= { 0x80, "ATY,PlatformInfo", {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_mvad= { 0x40, "MVAD", {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, 0x92, 0x20, 0x00, 0x03} };
struct ati_data_key ati_saved_config= { 0x100, "saved-config", {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, 0x92, 0x20, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xee, 0x02, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
///non 48xx keys
const char *ati_efidisplay_0_n4[]= { "@0,ATY,EFIDisplay", "TMDSA" };
struct ati_data_key ati_connector_type_0_n4= { 0x04, "@0,connector-type", {0x04, 0x00, 0x00, 0x00} };
struct ati_data_key ati_connector_type_1_n4= { 0x04, "@1,connector-type", {0x00, 0x02, 0x00, 0x00} };
struct ati_data_key ati_aapl_emc_disp_list_n4= { 0x40, "AAPL,EMC-Display-List", {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x1b, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x1c, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x21, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_fb_offset_n4= { 0x08, "ATY,FrameBufferOffset", {0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00} };
struct ati_data_key ati_hwgpio_n4= { 0x04, "ATY,HWGPIO", {0x23, 0xa8, 0x48, 0x00} };
struct ati_data_key ati_iospace_offset_n4= { 0x08, "ATY,IOSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00} };
struct ati_data_key ati_mclk_n4= { 0x04, "ATY,MCLK", {0x00, 0x35, 0x0c, 0x00} };
struct ati_data_key ati_sclk_n4= { 0x04, "ATY,SCLK", {0x60, 0xae, 0x0a, 0x00} };
struct ati_data_key ati_refclk_n4= { 0x04, "ATY,RefCLK", {0x8c, 0x0a, 0x00, 0x00} };
struct ati_data_key ati_regspace_offset_n4= { 0x08, "ATY,RegisterSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x90, 0xa2, 0x00, 0x00} };
struct ati_data_key ati_vram_memsize_0= { 0x08, "@0,VRAM,memsize", {0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_vram_memsize_1= { 0x08, "@1,VRAM,memsize", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl_blackscr_prefs_0_n4= { 0x04, "AAPL00,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl_blackscr_prefs_1_n4= { 0x04, "AAPL01,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_swgpio_info_n4= { 0x04, "ATY,SWGPIO Info", {0x00, 0x48, 0xa8, 0x23} };
struct ati_data_key ati_efi_orientation_n4= { 0x01, "ATY,EFIOrientation", {0x08} };
struct ati_data_key ati_mvad_n4= { 0x100, "MVAD", {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_saved_config_n4= { 0x100, "saved-config", {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct pcir_s {
uint32_t signature;
uint16_t vid;
uint16_t devid;
};
// Known cards as of 2008/08/26
static struct ati_chipsets_t ATIKnownChipsets[] = {
{ 0x00000000, "Unknown" } ,
{ 0x10029589, "ATI Radeon 2600 Series"} ,
{ 0x10029588, "ATI Radeon 2600 Series"} ,
{ 0x100294C3, "ATI Radeon 2400 Series"} ,
{ 0x100294C4, "ATI Radeon 2400 Series"} ,
{ 0x100294C6, "ATI Radeon 2400 Series"} ,
{ 0x10029400, "ATI Radeon 2900 Series"} ,
{ 0x10029405, "ATI Radeon 2900GT Series"} ,
{ 0x10029581, "ATI Radeon 2600 Series"} ,
{ 0x10029583, "ATI Radeon 2600 Series"} ,
{ 0x10029586, "ATI Radeon 2600 Series"} ,
{ 0x10029587, "ATI Radeon 2600 Series"} ,
{ 0x100294C9, "ATI Radeon 2400 Series"} ,
{ 0x10029501, "ATI Radeon 3800 Series"} ,
{ 0x10029505, "ATI Radeon 3800 Series"} ,
{ 0x10029515, "ATI Radeon 3800 Series"} ,
{ 0x10029507, "ATI Radeon 3800 Series"} ,
{ 0x10029500, "ATI Radeon 3800 Series"} ,
{ 0x1002950F, "ATI Radeon 3800X2 Series"} ,
{ 0x100295C5, "ATI Radeon 3400 Series"} ,
{ 0x100295C7, "ATI Radeon 3400 Series"} ,
{ 0x100295C0, "ATI Radeon 3400 Series"} ,
{ 0x10029596, "ATI Radeon 3600 Series"} ,
{ 0x10029590, "ATI Radeon 3600 Series"} ,
{ 0x10029599, "ATI Radeon 3600 Series"} ,
{ 0x10029597, "ATI Radeon 3600 Series"} ,
{ 0x10029598, "ATI Radeon 3600 Series"} ,
{ 0x10029442, "ATI Radeon 4850 Series"} ,
{ 0x10029440, "ATI Radeon 4870 Series"} ,
{ 0x1002944C, "ATI Radeon 4830 Series"} ,
{ 0x10029460, "ATI Radeon 4890 Series"} ,
{ 0x10029462, "ATI Radeon 4890 Series"} ,
{ 0x10029441, "ATI Radeon 4870X2 Series"} ,
{ 0x10029443, "ATI Radeon 4850X2 Series"} ,
{ 0x10029444, "ATI Radeon 4800 Series"} ,
{ 0x10029446, "ATI Radeon 4800 Series"} ,
{ 0x1002944E, "ATI Radeon 4730 Series"} ,
{ 0x10029450, "ATI Radeon 4800 Series"} ,
{ 0x10029452, "ATI Radeon 4800 Series"} ,
{ 0x10029456, "ATI Radeon 4800 Series"} ,
{ 0x1002944A, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002945A, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002945B, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002944B, "ATI Radeon 4800 Mobility Series"} ,
{ 0x10029490, "ATI Radeon 4670 Series"} ,
{ 0x10029498, "ATI Radeon 4650 Series"} ,
{ 0x10029490, "ATI Radeon 4600 Series"} ,
{ 0x10029498, "ATI Radeon 4600 Series"} ,
{ 0x1002949E, "ATI Radeon 4600 Series"} ,
{ 0x10029480, "ATI Radeon 4600 Series"} ,
{ 0x10029488, "ATI Radeon 4600 Series"} ,
{ 0x10029540, "ATI Radeon 4500 Series"} ,
{ 0x10029541, "ATI Radeon 4500 Series"} ,
{ 0x1002954E, "ATI Radeon 4500 Series"} ,
{ 0x10029552, "ATI Radeon 4300 Mobility Series"} ,
{ 0x10029553, "ATI Radeon 4500 Mobility Series"} ,
{ 0x1002954F, "ATI Radeon 4300 Series"} ,
{ 0x100294B3, "ATI Radeon 4770 Series"} ,
{ 0x100294B5, "ATI Radeon 4770 Series"} ,
{ 0x100268B8, "ATI Radeon 5700 Series"} ,
{ 0x100268BE, "ATI Radeon 5700 Series"} ,
{ 0x10026898, "ATI Radeon 5800 Series"} ,
{ 0x10026899, "ATI Radeon 5800 Series"}
};
static struct ati_chipsets_t ATIKnownFramebuffers[] = {
{ 0x00000000, "Megalodon" },
{ 0x10029589, "Lamna"} ,
{ 0x10029588, "Lamna"} ,
{ 0x100294C3, "Iago"} ,
{ 0x100294C4, "Iago"} ,
{ 0x100294C6, "Iago"} ,
{ 0x10029400, "Franklin"} ,
{ 0x10029405, "Franklin"} ,
{ 0x10029581, "Hypoprion"} ,
{ 0x10029583, "Hypoprion"} ,
{ 0x10029586, "Hypoprion"} ,
{ 0x10029587, "Hypoprion"} ,
{ 0x100294C9, "Iago"} ,
{ 0x10029501, "Megalodon"} ,
{ 0x10029505, "Megalodon"} ,
{ 0x10029515, "Megalodon"} ,
{ 0x10029507, "Megalodon"} ,
{ 0x10029500, "Megalodon"} ,
{ 0x1002950F, "Triakis"} ,
{ 0x100295C5, "Iago"} ,
{ 0x100295C7, "Iago"} ,
{ 0x100295C0, "Iago"} ,
{ 0x10029596, "Megalodon"} ,
{ 0x10029590, "Megalodon"} ,
{ 0x10029599, "Megalodon"} ,
{ 0x10029597, "Megalodon"} ,
{ 0x10029598, "Megalodon"} ,
{ 0x10029442, "Motmot"} ,
{ 0x10029440, "Motmot"} ,
{ 0x1002944C, "Motmot"} ,
{ 0x10029460, "Motmot"} ,
{ 0x10029462, "Motmot"} ,
{ 0x10029441, "Motmot"} ,
{ 0x10029443, "Motmot"} ,
{ 0x10029444, "Motmot"} ,
{ 0x10029446, "Motmot"} ,
{ 0x1002944E, "Motmot"} ,
{ 0x10029450, "Motmot"} ,
{ 0x10029452, "Motmot"} ,
{ 0x10029456, "Motmot"} ,
{ 0x1002944A, "Motmot"} ,
{ 0x1002945A, "Motmot"} ,
{ 0x1002945B, "Motmot"} ,
{ 0x1002944B, "Motmot"} ,
{ 0x10029490, "Peregrine"} ,
{ 0x10029498, "Peregrine"} ,
{ 0x1002949E, "Peregrine"} ,
{ 0x10029480, "Peregrine"} ,
{ 0x10029488, "Peregrine"} ,
{ 0x10029540, "Peregrine"} ,
{ 0x10029541, "Peregrine"} ,
{ 0x1002954E, "Peregrine"} ,
{ 0x10029552, "Peregrine"} ,
{ 0x10029553, "Peregrine"} ,
{ 0x1002954F, "Peregrine"} ,
{ 0x100294B3, "Peregrine"},
{ 0x100294B5, "Peregrine"},
{ 0x100268B8, "Motmot"},
{ 0x100268BE, "Motmot"},
{ 0x10026898, "Motmot"},
{ 0x10026899, "Motmot"}
};
static uint32_t accessROM(pci_dt_t *ati_dev, unsigned int mode)
{
uint32_tbar[7];
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (uint32_t *) (bar[2] & ~0x0f);
if (mode) {
if (mode != 1) {
return 0xe00002c7;
}
REG32W(0x179c, 0x00080000);
REG32W(0x1798, 0x00080721);
REG32W(0x17a0, 0x00080621);
REG32W(0x1600, 0x14030300);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
REG32W(0x17a0, 0x21);
REG32W(0x1798, 0x21);
REG32W(0x1798, 0x21);
} else {
REG32W(0x1600, 0x14030302);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00080000);
REG32W(0x17a0, 0x00080621);
REG32W(0x1798, 0x00080721);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
REG32W(0x1604, 0x0400e9fc);
REG32W(0x161c, 0x00);
REG32W(0x1620, 0x9f);
REG32W(0x1618, 0x00040004);
REG32W(0x161c, 0x00);
REG32W(0x1604, 0xe9fc);
REG32W(0x179c, 0x00080000);
REG32W(0x1798, 0x00080721);
REG32W(0x17a0, 0x00080621);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
}
return 0;
}
static uint8_t *readAtomBIOS(pci_dt_t *ati_dev)
{
uint32_tbar[7];
uint32_t*BIOSBase;
uint32_tcounter;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (volatile uint32_t *) (bar[2] & ~0x0f);
accessROM(ati_dev, 0);
REG32W(0xa8, 0);
REG32R(0xac);
REG32W(0xa8, 0);
REG32R(0xac);
BIOSBase = malloc(0x10000);
REG32W(0xa8, 0);
BIOSBase[0] = REG32R(0xac);
counter = 4;
do {
REG32W(0xa8, counter);
BIOSBase[counter/4] = REG32R(0xac);
counter +=4;
} while (counter != 0x10000);
accessROM((pci_dt_t *)regs, 1);
if (*(uint16_t *)BIOSBase != 0xAA55) {
printf("Wrong BIOS signature: %04x\n", *(uint16_t *)BIOSBase);
return 0;
}
return (uint8_t *)BIOSBase;
}
#define R5XX_CONFIG_MEMSIZE0x00F8
#define R6XX_CONFIG_MEMSIZE0x5428
uint32_t getvramsizekb(pci_dt_t *ati_dev)
{
uint32_tbar[7];
uint32_tsize;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (uint32_t *) (bar[2] & ~0x0f);
if (ati_dev->device_id < 0x9400) {
size = (REG32R(R5XX_CONFIG_MEMSIZE)) >> 10;
} else {
size = (REG32R(R6XX_CONFIG_MEMSIZE)) >> 10;
}
return size;
}
#define AVIVO_D1CRTC_CONTROL0x6080
#define AVIVO_CRTC_EN(1<<0)
#define AVIVO_D2CRTC_CONTROL0x6880
static bool radeon_card_posted(pci_dt_t *ati_dev)
{
// if devid matches biosimage(from legacy) devid - posted card, fails with X2/crossfire cards.
/*char *biosimage = 0xC0000;
if ((uint8_t)biosimage[0] == 0x55 && (uint8_t)biosimage[1] == 0xaa)
{
struct pci_rom_pci_header_t *rom_pci_header;
rom_pci_header = (struct pci_rom_pci_header_t*)(biosimage + (uint8_t)biosimage[24] + (uint8_t)biosimage[25]*256);
if (rom_pci_header->signature == 0x52494350)
{
if (rom_pci_header->device == ati_dev->device_id)
{
return true;
printf("Card was POSTed\n");
}
}
}
return false;
printf("Card was not POSTed\n");
*/
//fails yet
uint32_tbar[7];
uint32_tval;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18);
regs = (uint32_t *) (bar[2] & ~0x0f);
val = REG32R(AVIVO_D1CRTC_CONTROL) | REG32R(AVIVO_D2CRTC_CONTROL);
if (val & AVIVO_CRTC_EN) {
return true;
} else {
return false;
}
}
static uint32_t load_ati_bios_file(const char *filename, uint8_t *buf, int bufsize)
{
intfd;
intsize;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {
return 0;
}
size = file_size(fd);
if (size > bufsize) {
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);
size = bufsize;
}
size = read(fd, (char *)buf, size);
close(fd);
return size > 0 ? size : 0;
}
static char *get_ati_model(uint32_t id)
{
inti;
for (i=0; i< (sizeof(ATIKnownChipsets) / sizeof(ATIKnownChipsets[0])); i++) {
if (ATIKnownChipsets[i].device == id) {
return ATIKnownChipsets[i].name;
}
}
return ATIKnownChipsets[0].name;
}
static char *get_ati_fb(uint32_t id)
{
inti;
for (i=0; i< (sizeof(ATIKnownFramebuffers) / sizeof(ATIKnownFramebuffers[0])); i++) {
if (ATIKnownFramebuffers[i].device == id) {
return ATIKnownFramebuffers[i].name;
}
}
return ATIKnownFramebuffers[0].name;
}
static int devprop_add_iopciconfigspace(struct DevPropDevice *device, pci_dt_t *ati_dev)
{
inti;
uint8_t*config_space;
if (!device || !ati_dev) {
return 0;
}
printf("dumping pci config space, 256 bytes\n");
config_space = malloc(256);
for (i=0; i<=255; i++) {
config_space[i] = pci_config_read8( ati_dev->dev.addr, i);
}
devprop_add_value(device, "ATY,PCIConfigSpace", config_space, 256);
free (config_space);
return 1;
}
static int devprop_add_ati_template_4xxx(struct DevPropDevice *device)
{
if(!device)
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_compatible_0))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_compatible_1))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_1))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_device_type))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name_0))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name_1))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_display_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_display_type_1))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_slot_name))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_card_no))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_copyright))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_version))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_mrt))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_romno))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_name_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_display_con_fl_type_0))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_disp_conf))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_init_stat))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config))
return 0;
return 1;
}
static int devprop_add_ati_template(struct DevPropDevice *device)
{
if(!device)
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0_n4))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_slot_name_n4))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_card_no))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_copyright))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_version))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_mrt))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_romno))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_name_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_emc_disp_list_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_fb_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_hwgpio_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_iospace_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_refclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_regspace_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_0_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_1_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_swgpio_info_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config_n4))
return 0;
return 1;
}
bool setup_ati_devprop(pci_dt_t *ati_dev)
{
struct DevPropDevice*device;
char*devicepath;
char*model;
char*framebuffer;
chartmp[64];
uint8_t*rom = NULL;
uint32_trom_size = 0;
uint8_t*bios;
uint32_tbios_size;
uint32_tvram_size;
uint32_tboot_display;
uint8_tcmd;
booldoit;
booltoFree;
devicepath = get_pci_dev_path(ati_dev);
cmd = pci_config_read8(ati_dev->dev.addr, 4);
verbose("old pci command - %x\n", cmd);
if (cmd == 0) {
pci_config_write8(ati_dev->dev.addr, 4, 6);
cmd = pci_config_read8(ati_dev->dev.addr, 4);
verbose("new pci command - %x\n", cmd);
}
model = get_ati_model((ati_dev->vendor_id << 16) | ati_dev->device_id);
framebuffer = get_ati_fb((ati_dev->vendor_id << 16) | ati_dev->device_id);
if (!string) {
string = devprop_create_string();
}
device = devprop_add_device(string, devicepath);
if (!device) {
printf("Failed initializing dev-prop string dev-entry, press any key...\n");
getc();
return false;
}
/* FIXME: for primary graphics card only */
if (radeon_card_posted(ati_dev)) {
boot_display = 1;
} else {
boot_display = 0;
}
verbose("boot display - %x\n", boot_display);
devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
if((framebuffer[0] == 'M' && framebuffer[1] == 'o' && framebuffer[2] == 't') ||
(framebuffer[0] == 'S' && framebuffer[1] == 'h' && framebuffer[2] == 'r') ||
(framebuffer[0] == 'P' && framebuffer[1] == 'e' && framebuffer[2] == 'r')) //faster than strcmp ;)
devprop_add_ati_template_4xxx(device);
else {
devprop_add_ati_template(device);
vram_size = getvramsizekb(ati_dev) * 1024;
if ((vram_size > 0x80000000) || (vram_size == 0)) {
vram_size = 0x10000000;//vram reported wrong, defaulting to 256 mb
}
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&vram_size, 4);
ati_vram_memsize_0.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway
ati_vram_memsize_0.data[7] = (vram_size >> 24) & 0xFF;
ati_vram_memsize_1.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway
ati_vram_memsize_1.data[7] = (vram_size >> 24) & 0xFF;
DP_ADD_TEMP_VAL_DATA(device, ati_vram_memsize_0);
DP_ADD_TEMP_VAL_DATA(device, ati_vram_memsize_1);
devprop_add_iopciconfigspace(device, ati_dev);
}
devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1));
devprop_add_value(device, "ATY,DeviceID", (uint8_t*)&ati_dev->device_id, 2);
//fb setup
sprintf(tmp, "Slot-%x",devices_number);
devprop_add_value(device, "AAPL,slot-name", (uint8_t*)tmp, strlen(tmp) + 1);
devices_number++;
sprintf(tmp, ati_compatible_0[1], framebuffer);
devprop_add_value(device, (char *) ati_compatible_0[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_compatible_1[1], framebuffer);
devprop_add_value(device, (char *) ati_compatible_1[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_device_type[1], framebuffer);
devprop_add_value(device, (char *) ati_device_type[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name[1], framebuffer);
devprop_add_value(device, (char *) ati_name[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name_0[1], framebuffer);
devprop_add_value(device, (char *) ati_name_0[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name_1[1], framebuffer);
devprop_add_value(device, (char *) ati_name_1[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, "/Extra/%04x_%04x.rom", (uint16_t)ati_dev->vendor_id, (uint16_t)ati_dev->device_id);
if (getBoolForKey(kUseAtiROM, &doit, &bootInfo->bootConfig) && doit) {
verbose("looking for ati video bios file %s\n", tmp);
rom = malloc(0x20000);
rom_size = load_ati_bios_file(tmp, rom, 0x20000);
if (rom_size > 0) {
verbose("Using ATI Video BIOS File %s (%d Bytes)\n", tmp, rom_size);
if (rom_size > 0x10000) {
rom_size = 0x10000; //we dont need rest anyway;
}
} else {
printf("ERROR: unable to open ATI Video BIOS File %s\n", tmp);
}
}
if (rom_size == 0) {
if (boot_display) {// no custom rom
bios = NULL;// try to dump from legacy space, otherwise can result in 100% fan speed
} else {
// readAtomBios result in bug on some cards (100% fan speed and black screen),
// not using it for posted card, rading from legacy space instead
bios = readAtomBIOS(ati_dev);
}
} else {
bios = rom;//going custom rom way
verbose("Using rom %s\n", tmp);
}
if (bios == NULL) {
bios = (uint8_t *)0x000C0000;
toFree = false;
verbose("Not going to use bios image file\n");
} else {
toFree = true;
}
if (bios[0] == 0x55 && bios[1] == 0xaa) {
printf("Found bios image\n");
bios_size = bios[2] * 512;
struct pci_rom_pci_header_t *rom_pci_header;
rom_pci_header = (struct pci_rom_pci_header_t*)(bios + bios[24] + bios[25]*256);
if (rom_pci_header->signature == 0x52494350) {
if (rom_pci_header->device != ati_dev->device_id) {
verbose("Bios image (%x) doesnt match card (%x), ignoring\n", rom_pci_header->device, ati_dev->device_id);
} else {
if (toFree) {
verbose("Adding binimage to card %x from mmio space with size %x\n", ati_dev->device_id, bios_size);
} else {
verbose("Adding binimage to card %x from legacy space with size %x\n", ati_dev->device_id, bios_size);
}
devprop_add_value(device, "ATY,bin_image", bios, bios_size);
}
} else {
verbose("Wrong pci header signature %x\n", rom_pci_header->signature);
}
} else {
verbose("Bios image not found at %x, content %x %x\n", bios, bios[0], bios[1]);
}
if (toFree) {
free(bios);
}
stringdata = malloc(sizeof(uint8_t) * string->length);
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
branches/meklort/i386/libsaio/nvidia.h
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/*
* NVidia injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi
*
* NVidia injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* NVidia driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
/*
* DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
*
*
* Copyright 2005-2006 Erik Waling
* Copyright 2006 Stephane Marchesin
* Copyright 2007-2009 Stuart Bennett
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __LIBSAIO_NVIDIA_H
#define __LIBSAIO_NVIDIA_H
bool setup_nvidia_devprop(pci_dt_t *nvda_dev);
struct nv_chipsets_t {
unsigned device;
char *name;
};
#define DCB_MAX_NUM_ENTRIES 16
#define DCB_MAX_NUM_I2C_ENTRIES 16
#define DCB_LOC_ON_CHIP 0
struct bios {
uint16_tsignature;/* 0x55AA */
uint8_tsize;/* Size in multiples of 512 */
};
#define NV_PROM_OFFSET0x300000
#define NV_PROM_SIZE0x0000ffff
#define NV_PRAMIN_OFFSET0x00700000
#define NV_PRAMIN_SIZE0x00100000
#define NV04_PFB_FIFO_DATA0x0010020c
#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK0xfff00000
#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT20
#define NVC0_MEM_CTRLR_COUNT0x00121c74
#define NVC0_MEM_CTRLR_RAM_AMOUNT0x0010f20c
#define NV_PBUS_PCI_NV_200x00001850
#define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED(0 << 0)
#define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED(1 << 0)
#define REG8(reg) ((volatile uint8_t *)regs)[(reg)]
#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1]
#define REG32(reg) ((volatile uint32_t *)regs)[(reg) >> 2]
#define NV_ARCH_03 0x03
#define NV_ARCH_04 0x04
#define NV_ARCH_10 0x10
#define NV_ARCH_20 0x20
#define NV_ARCH_30 0x30
#define NV_ARCH_40 0x40
#define NV_ARCH_50 0x50
#define NV_ARCH_C0 0xC0
#define CHIPSET_NV03 0x0010
#define CHIPSET_NV04 0x0020
#define CHIPSET_NV10 0x0100
#define CHIPSET_NV11 0x0110
#define CHIPSET_NV15 0x0150
#define CHIPSET_NV17 0x0170
#define CHIPSET_NV18 0x0180
#define CHIPSET_NFORCE 0x01A0
#define CHIPSET_NFORCE2 0x01F0
#define CHIPSET_NV20 0x0200
#define CHIPSET_NV25 0x0250
#define CHIPSET_NV28 0x0280
#define CHIPSET_NV30 0x0300
#define CHIPSET_NV31 0x0310
#define CHIPSET_NV34 0x0320
#define CHIPSET_NV35 0x0330
#define CHIPSET_NV36 0x0340
#define CHIPSET_NV40 0x0040
#define CHIPSET_NV41 0x00C0
#define CHIPSET_NV43 0x0140
#define CHIPSET_NV44 0x0160
#define CHIPSET_NV44A 0x0220
#define CHIPSET_NV45 0x0210
#define CHIPSET_NV50 0x0190
#define CHIPSET_NV84 0x0400
#define CHIPSET_MISC_BRIDGED 0x00F0
#define CHIPSET_G70 0x0090
#define CHIPSET_G71 0x0290
#define CHIPSET_G72 0x01D0
#define CHIPSET_G73 0x0390
// integrated GeForces (6100, 6150)
#define CHIPSET_C51 0x0240
// variant of C51, seems based on a G70 design
#define CHIPSET_C512 0x03D0
#define CHIPSET_G73_BRIDGED 0x02E0
#endif /* !__LIBSAIO_NVIDIA_H */
branches/meklort/i386/libsaio/ati.h
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/*
* ATI injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas
*
* ATI injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ATI driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with ATI injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
#ifndef __LIBSAIO_ATI_H
#define __LIBSAIO_ATI_H
bool setup_ati_devprop(pci_dt_t *ati_dev);
struct ati_chipsets_t {
unsigned device;
char *name;
};
struct ati_data_key {
uint32_t size;
char *name;
uint8_t data[];
};
#define REG8(reg) ((volatile uint8_t *)regs)[(reg)]
#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1]
#define REG32R(reg) ((volatile uint32_t *)regs)[(reg) >> 2]
#define REG32W(reg, val) ((volatile uint32_t *)regs)[(reg) >> 2] = (val)
#endif /* !__LIBSAIO_ATI_H */
branches/meklort/i386/libsaio/Makefile
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cpu.o platform.o acpi_patcher.o \
smbios_patcher.o fake_efi.o ext2fs.o \
hpet.o dram_controllers.o spd.o usb.o pci_setup.o \
device_inject.o nvidia.o ati.o pci_root.o \
device_inject.o pci_root.o \
convert.o mem.o aml_generator.o resolution.o edid.o
branches/meklort/i386/libsaio/pci_setup.c
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#include "boot.h"
#include "bootstruct.h"
#include "pci.h"
#include "nvidia.h"
#include "ati.h"
#include "modules.h"
extern void set_eth_builtin(pci_dt_t *eth_dev);
extern void notify_usb_dev(pci_dt_t *pci_dev);
void setup_pci_devs(pci_dt_t *pci_dt)
{
char *devicepath;
bool do_eth_devprop, do_gfx_devprop, do_enable_hpet;
bool do_eth_devprop, do_enable_hpet;
pci_dt_t *current = pci_dt;
do_eth_devprop = do_gfx_devprop = do_enable_hpet = false;
do_eth_devprop = do_enable_hpet = false;
getBoolForKey(kEthernetBuiltIn, &do_eth_devprop, &bootInfo->bootConfig);
getBoolForKey(kGraphicsEnabler, &do_gfx_devprop, &bootInfo->bootConfig);
getBoolForKey(kForceHPET, &do_enable_hpet, &bootInfo->bootConfig);
while (current)
{
devicepath = get_pci_dev_path(current);
switch (current->class_id)
{
case PCI_CLASS_BRIDGE_HOST:
break;
case PCI_CLASS_DISPLAY_VGA:
if (do_gfx_devprop)
switch (current->vendor_id)
{
case PCI_VENDOR_ID_ATI:
verbose("ATI VGA Controller [%04x:%04x] :: %s \n",
current->vendor_id, current->device_id, devicepath);
setup_ati_devprop(current);
break;
case PCI_VENDOR_ID_INTEL:
/* message to be removed once support for these cards is added */
verbose("Intel VGA Controller [%04x:%04x] :: %s (currently NOT SUPPORTED)\n",
current->vendor_id, current->device_id, devicepath);
break;
case PCI_VENDOR_ID_NVIDIA:
setup_nvidia_devprop(current);
break;
}
execute_hook("GraphicsEnabler", current, NULL, NULL, NULL);
break;
case PCI_CLASS_SERIAL_USB:
branches/meklort/i386/boot2/boot.h
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#define kVBIOS"VBIOS"/* nvidia.c */
#define kPCIRootUID"PCIRootUID"/* pci_root.c */
#define kEthernetBuiltIn"EthernetBuiltIn"/* pci_setup.c */
#define kGraphicsEnabler"GraphicsEnabler"/* pci_setup.c */
#define kForceHPET"ForceHPET"/* pci_setup.c */
#define kUseMemDetect"UseMemDetect" /* platform.c */
#define kSMBIOSdefaults"SMBIOSdefaults"/* smbios_patcher.c */
branches/meklort/i386/modules/KextPatcher/Makefile
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$(HFILES) $(OTHERFILES)
DIRS_NEEDED = $(OBJROOT) $(SYMROOT)
all embedtheme: ${OBJS} dylib
all embedtheme optionrom: ${OBJS} dylib
dylib: ${OBJS}
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$(HFILES) $(OTHERFILES)
DIRS_NEEDED = $(OBJROOT) $(SYMROOT)
all embedtheme: ${OBJS} dylib
all embedtheme optionrom: ${OBJS} dylib
dylib: ${OBJS}
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$(HFILES) $(OTHERFILES)
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all embedtheme: dylib
all embedtheme optionrom: dylib
dylib: $(OBJS)
branches/meklort/i386/modules/GraphicsEnabler/nvidia.h
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/*
* NVidia injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi
*
* NVidia injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* NVidia driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
/*
* DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
*
*
* Copyright 2005-2006 Erik Waling
* Copyright 2006 Stephane Marchesin
* Copyright 2007-2009 Stuart Bennett
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __LIBSAIO_NVIDIA_H
#define __LIBSAIO_NVIDIA_H
bool setup_nvidia_devprop(pci_dt_t *nvda_dev);
struct nv_chipsets_t {
unsigned device;
char *name;
};
#define DCB_MAX_NUM_ENTRIES 16
#define DCB_MAX_NUM_I2C_ENTRIES 16
#define DCB_LOC_ON_CHIP 0
struct bios {
uint16_tsignature;/* 0x55AA */
uint8_tsize;/* Size in multiples of 512 */
};
#define NV_PROM_OFFSET0x300000
#define NV_PROM_SIZE0x0000ffff
#define NV_PRAMIN_OFFSET0x00700000
#define NV_PRAMIN_SIZE0x00100000
#define NV04_PFB_FIFO_DATA0x0010020c
#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK0xfff00000
#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT20
#define NVC0_MEM_CTRLR_COUNT0x00121c74
#define NVC0_MEM_CTRLR_RAM_AMOUNT0x0010f20c
#define NV_PBUS_PCI_NV_200x00001850
#define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED(0 << 0)
#define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED(1 << 0)
#define REG8(reg) ((volatile uint8_t *)regs)[(reg)]
#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1]
#define REG32(reg) ((volatile uint32_t *)regs)[(reg) >> 2]
#define NV_ARCH_03 0x03
#define NV_ARCH_04 0x04
#define NV_ARCH_10 0x10
#define NV_ARCH_20 0x20
#define NV_ARCH_30 0x30
#define NV_ARCH_40 0x40
#define NV_ARCH_50 0x50
#define NV_ARCH_C0 0xC0
#define CHIPSET_NV03 0x0010
#define CHIPSET_NV04 0x0020
#define CHIPSET_NV10 0x0100
#define CHIPSET_NV11 0x0110
#define CHIPSET_NV15 0x0150
#define CHIPSET_NV17 0x0170
#define CHIPSET_NV18 0x0180
#define CHIPSET_NFORCE 0x01A0
#define CHIPSET_NFORCE2 0x01F0
#define CHIPSET_NV20 0x0200
#define CHIPSET_NV25 0x0250
#define CHIPSET_NV28 0x0280
#define CHIPSET_NV30 0x0300
#define CHIPSET_NV31 0x0310
#define CHIPSET_NV34 0x0320
#define CHIPSET_NV35 0x0330
#define CHIPSET_NV36 0x0340
#define CHIPSET_NV40 0x0040
#define CHIPSET_NV41 0x00C0
#define CHIPSET_NV43 0x0140
#define CHIPSET_NV44 0x0160
#define CHIPSET_NV44A 0x0220
#define CHIPSET_NV45 0x0210
#define CHIPSET_NV50 0x0190
#define CHIPSET_NV84 0x0400
#define CHIPSET_MISC_BRIDGED 0x00F0
#define CHIPSET_G70 0x0090
#define CHIPSET_G71 0x0290
#define CHIPSET_G72 0x01D0
#define CHIPSET_G73 0x0390
// integrated GeForces (6100, 6150)
#define CHIPSET_C51 0x0240
// variant of C51, seems based on a G70 design
#define CHIPSET_C512 0x03D0
#define CHIPSET_G73_BRIDGED 0x02E0
#endif /* !__LIBSAIO_NVIDIA_H */
branches/meklort/i386/modules/GraphicsEnabler/ati.h
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/*
* ATI injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas
*
* ATI injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ATI driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with ATI injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
#ifndef __LIBSAIO_ATI_H
#define __LIBSAIO_ATI_H
bool setup_ati_devprop(pci_dt_t *ati_dev);
struct ati_chipsets_t {
unsigned device;
char *name;
};
struct ati_data_key {
uint32_t size;
char *name;
uint8_t data[];
};
#define REG8(reg) ((volatile uint8_t *)regs)[(reg)]
#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1]
#define REG32R(reg) ((volatile uint32_t *)regs)[(reg) >> 2]
#define REG32W(reg, val) ((volatile uint32_t *)regs)[(reg) >> 2] = (val)
#endif /* !__LIBSAIO_ATI_H */
branches/meklort/i386/modules/GraphicsEnabler/GraphicsEnabler.c
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/*
* GraphicsEnabler Module
*Enabled many nvidia and ati cards to be used out of the box in
*OS X. This was converted from boot2 code to a boot2 module.
*
*/
#include "libsaio.h"
#include "pci.h"
#include "bootstruct.h"
#include "nvidia.h"
#include "ati.h"
#include "modules.h"
#define kGraphicsEnabler"GraphicsEnabler"
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4);
void GraphicsEnabler_start()
{
register_hook_callback(kGraphicsEnabler, &GraphicsEnabler_hook);
}
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4)
{
pci_dt_t* current = arg1;
char *devicepath = get_pci_dev_path(current);
bool do_gfx_devprop = false;
getBoolForKey(kGraphicsEnabler, &do_gfx_devprop, &bootInfo->bootConfig);
if (do_gfx_devprop)
switch (current->vendor_id)
{
case PCI_VENDOR_ID_ATI:
verbose("ATI VGA Controller [%04x:%04x] :: %s \n",
current->vendor_id, current->device_id, devicepath);
setup_ati_devprop(current);
break;
case PCI_VENDOR_ID_INTEL:
/* message to be removed once support for these cards is added */
verbose("Intel VGA Controller [%04x:%04x] :: %s (currently NOT SUPPORTED)\n",
current->vendor_id, current->device_id, devicepath);
break;
case PCI_VENDOR_ID_NVIDIA:
setup_nvidia_devprop(current);
break;
}
}
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/*
* NVidia injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi
*
* NVidia injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* NVidia driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
/*
* DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
*
*
* Copyright 2005-2006 Erik Waling
* Copyright 2006 Stephane Marchesin
* Copyright 2007-2009 Stuart Bennett
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "libsaio.h"
#include "boot.h"
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#include "device_inject.h"
#include "nvidia.h"
#ifndef DEBUG_NVIDIA
#define DEBUG_NVIDIA 0
#endif
#if DEBUG_NVIDIA
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
#define NVIDIA_ROM_SIZE 0x10000
#define PATCH_ROM_SUCCESS 1
#define PATCH_ROM_SUCCESS_HAS_LVDS 2
#define PATCH_ROM_FAILED 0
#define MAX_NUM_DCB_ENTRIES 16
#define TYPE_GROUPED 0xff
extern uint32_t devices_number;
const char *nvidia_compatible_0[]={ "@0,compatible","NVDA,NVMac" };
const char *nvidia_compatible_1[]={ "@1,compatible","NVDA,NVMac" };
const char *nvidia_device_type_0[]={ "@0,device_type","display" };
const char *nvidia_device_type_1[]={ "@1,device_type","display" };
const char *nvidia_device_type[]={ "device_type","NVDA,Parent" };
const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
const char *nvidia_slot_name[]={ "AAPL,slot-name","Slot-1" };
static uint8_t default_NVCAP[]= {
0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
0x00, 0x00, 0x00, 0x00
};
#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )
static struct nv_chipsets_t NVKnownChipsets[] = {
{ 0x00000000, "Unknown" },
{ 0x10DE0040, "GeForce 6800 Ultra" },
{ 0x10DE0041, "GeForce 6800" },
{ 0x10DE0042, "GeForce 6800 LE" },
{ 0x10DE0043, "GeForce 6800 XE" },
{ 0x10DE0044, "GeForce 6800 XT" },
{ 0x10DE0045, "GeForce 6800 GT" },
{ 0x10DE0046, "GeForce 6800 GT" },
{ 0x10DE0047, "GeForce 6800 GS" },
{ 0x10DE0048, "GeForce 6800 XT" },
{ 0x10DE004E, "Quadro FX 4000" },
{ 0x10DE0090, "GeForce 7800 GTX" },
{ 0x10DE0091, "GeForce 7800 GTX" },
{ 0x10DE0092, "GeForce 7800 GT" },
{ 0x10DE0093, "GeForce 7800 GS" },
{ 0x10DE0095, "GeForce 7800 SLI" },
{ 0x10DE0098, "GeForce Go 7800" },
{ 0x10DE0099, "GeForce Go 7800 GTX" },
{ 0x10DE009D, "Quadro FX 4500" },
{ 0x10DE00C0, "GeForce 6800 GS" },
{ 0x10DE00C1, "GeForce 6800" },
{ 0x10DE00C2, "GeForce 6800 LE" },
{ 0x10DE00C3, "GeForce 6800 XT" },
{ 0x10DE00C8, "GeForce Go 6800" },
{ 0x10DE00C9, "GeForce Go 6800 Ultra" },
{ 0x10DE00CC, "Quadro FX Go1400" },
{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },
{ 0x10DE00CE, "Quadro FX 1400" },
{ 0x10DE0140, "GeForce 6600 GT" },
{ 0x10DE0141, "GeForce 6600" },
{ 0x10DE0142, "GeForce 6600 LE" },
{ 0x10DE0143, "GeForce 6600 VE" },
{ 0x10DE0144, "GeForce Go 6600" },
{ 0x10DE0145, "GeForce 6610 XL" },
{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },
{ 0x10DE0147, "GeForce 6700 XL" },
{ 0x10DE0148, "GeForce Go 6600" },
{ 0x10DE0149, "GeForce Go 6600 GT" },
{ 0x10DE014C, "Quadro FX 550" },
{ 0x10DE014D, "Quadro FX 550" },
{ 0x10DE014E, "Quadro FX 540" },
{ 0x10DE014F, "GeForce 6200" },
{ 0x10DE0160, "GeForce 6500" },
{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },
{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },
{ 0x10DE0163, "GeForce 6200 LE" },
{ 0x10DE0164, "GeForce Go 6200" },
{ 0x10DE0165, "Quadro NVS 285" },
{ 0x10DE0166, "GeForce Go 6400" },
{ 0x10DE0167, "GeForce Go 6200" },
{ 0x10DE0168, "GeForce Go 6400" },
{ 0x10DE0169, "GeForce 6250" },
{ 0x10DE016A, "GeForce 7100 GS" },
{ 0x10DE0191, "GeForce 8800 GTX" },
{ 0x10DE0193, "GeForce 8800 GTS" },
{ 0x10DE0194, "GeForce 8800 Ultra" },
{ 0x10DE019D, "Quadro FX 5600" },
{ 0x10DE019E, "Quadro FX 4600" },
{ 0x10DE01D1, "GeForce 7300 LE" },
{ 0x10DE01D3, "GeForce 7300 SE" },
{ 0x10DE01D6, "GeForce Go 7200" },
{ 0x10DE01D7, "GeForce Go 7300" },
{ 0x10DE01D8, "GeForce Go 7400" },
{ 0x10DE01D9, "GeForce Go 7400 GS" },
{ 0x10DE01DA, "Quadro NVS 110M" },
{ 0x10DE01DB, "Quadro NVS 120M" },
{ 0x10DE01DC, "Quadro FX 350M" },
{ 0x10DE01DD, "GeForce 7500 LE" },
{ 0x10DE01DE, "Quadro FX 350" },
{ 0x10DE01DF, "GeForce 7300 GS" },
{ 0x10DE0211, "GeForce 6800" },
{ 0x10DE0212, "GeForce 6800 LE" },
{ 0x10DE0215, "GeForce 6800 GT" },
{ 0x10DE0218, "GeForce 6800 XT" },
{ 0x10DE0221, "GeForce 6200" },
{ 0x10DE0222, "GeForce 6200 A-LE" },
{ 0x10DE0240, "GeForce 6150" },
{ 0x10DE0241, "GeForce 6150 LE" },
{ 0x10DE0242, "GeForce 6100" },
{ 0x10DE0244, "GeForce Go 6150" },
{ 0x10DE0247, "GeForce Go 6100" },
{ 0x10DE0290, "GeForce 7900 GTX" },
{ 0x10DE0291, "GeForce 7900 GT" },
{ 0x10DE0292, "GeForce 7900 GS" },
{ 0x10DE0298, "GeForce Go 7900 GS" },
{ 0x10DE0299, "GeForce Go 7900 GTX" },
{ 0x10DE029A, "Quadro FX 2500M" },
{ 0x10DE029B, "Quadro FX 1500M" },
{ 0x10DE029C, "Quadro FX 5500" },
{ 0x10DE029D, "Quadro FX 3500" },
{ 0x10DE029E, "Quadro FX 1500" },
{ 0x10DE029F, "Quadro FX 4500 X2" },
{ 0x10DE0301, "GeForce FX 5800 Ultra" },
{ 0x10DE0302, "GeForce FX 5800" },
{ 0x10DE0308, "Quadro FX 2000" },
{ 0x10DE0309, "Quadro FX 1000" },
{ 0x10DE0311, "GeForce FX 5600 Ultra" },
{ 0x10DE0312, "GeForce FX 5600" },
{ 0x10DE0314, "GeForce FX 5600XT" },
{ 0x10DE031A, "GeForce FX Go5600" },
{ 0x10DE031B, "GeForce FX Go5650" },
{ 0x10DE031C, "Quadro FX Go700" },
{ 0x10DE0324, "GeForce FX Go5200" },
{ 0x10DE0325, "GeForce FX Go5250" },
{ 0x10DE0326, "GeForce FX 5500" },
{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },
{ 0x10DE032A, "Quadro NVS 55/280 PCI" },
{ 0x10DE032B, "Quadro FX 500/600 PCI" },
{ 0x10DE032C, "GeForce FX Go53xx Series" },
{ 0x10DE032D, "GeForce FX Go5100" },
{ 0x10DE0330, "GeForce FX 5900 Ultra" },
{ 0x10DE0331, "GeForce FX 5900" },
{ 0x10DE0332, "GeForce FX 5900XT" },
{ 0x10DE0333, "GeForce FX 5950 Ultra" },
{ 0x10DE0334, "GeForce FX 5900ZT" },
{ 0x10DE0338, "Quadro FX 3000" },
{ 0x10DE033F, "Quadro FX 700" },
{ 0x10DE0341, "GeForce FX 5700 Ultra" },
{ 0x10DE0342, "GeForce FX 5700" },
{ 0x10DE0343, "GeForce FX 5700LE" },
{ 0x10DE0344, "GeForce FX 5700VE" },
{ 0x10DE0347, "GeForce FX Go5700" },
{ 0x10DE0348, "GeForce FX Go5700" },
{ 0x10DE034C, "Quadro FX Go1000" },
{ 0x10DE034E, "Quadro FX 1100" },
{ 0x10DE0391, "GeForce 7600 GT" },
{ 0x10DE0392, "GeForce 7600 GS" },
{ 0x10DE0393, "GeForce 7300 GT" },
{ 0x10DE0394, "GeForce 7600 LE" },
{ 0x10DE0395, "GeForce 7300 GT" },
{ 0x10DE0397, "GeForce Go 7700" },
{ 0x10DE0398, "GeForce Go 7600" },
{ 0x10DE0399, "GeForce Go 7600 GT"},
{ 0x10DE039A, "Quadro NVS 300M" },
{ 0x10DE039B, "GeForce Go 7900 SE" },
{ 0x10DE039C, "Quadro FX 550M" },
{ 0x10DE039E, "Quadro FX 560" },
{ 0x10DE0400, "GeForce 8600 GTS" },
{ 0x10DE0401, "GeForce 8600 GT" },
{ 0x10DE0402, "GeForce 8600 GT" },
{ 0x10DE0403, "GeForce 8600 GS" },
{ 0x10DE0404, "GeForce 8400 GS" },
{ 0x10DE0405, "GeForce 9500M GS" },
{ 0x10DE0407, "GeForce 8600M GT" },
{ 0x10DE0408, "GeForce 9650M GS" },
{ 0x10DE0409, "GeForce 8700M GT" },
{ 0x10DE040A, "Quadro FX 370" },
{ 0x10DE040B, "Quadro NVS 320M" },
{ 0x10DE040C, "Quadro FX 570M" },
{ 0x10DE040D, "Quadro FX 1600M" },
{ 0x10DE040E, "Quadro FX 570" },
{ 0x10DE040F, "Quadro FX 1700" },
{ 0x10DE0420, "GeForce 8400 SE" },
{ 0x10DE0421, "GeForce 8500 GT" },
{ 0x10DE0422, "GeForce 8400 GS" },
{ 0x10DE0423, "GeForce 8300 GS" },
{ 0x10DE0424, "GeForce 8400 GS" },
{ 0x10DE0425, "GeForce 8600M GS" },
{ 0x10DE0426, "GeForce 8400M GT" },
{ 0x10DE0427, "GeForce 8400M GS" },
{ 0x10DE0428, "GeForce 8400M G" },
{ 0x10DE0429, "Quadro NVS 140M" },
{ 0x10DE042A, "Quadro NVS 130M" },
{ 0x10DE042B, "Quadro NVS 135M" },
{ 0x10DE042C, "GeForce 9400 GT" },
{ 0x10DE042D, "Quadro FX 360M" },
{ 0x10DE042E, "GeForce 9300M G" },
{ 0x10DE042F, "Quadro NVS 290" },
{ 0x10DE05E0, "GeForce GTX 295" },
{ 0x10DE05E1, "GeForce GTX 280" },
{ 0x10DE05E2, "GeForce GTX 260" },
{ 0x10DE05E3, "GeForce GTX 285" },
{ 0x10DE05E6, "GeForce GTX 275" },
{ 0x10DE05EA, "GeForce GTX 260" },
{ 0x10DE05EB, "GeForce GTX 295" },
{ 0x10DE05F9, "Quadro CX" },
{ 0x10DE05FD, "Quadro FX 5800" },
{ 0x10DE05FE, "Quadro FX 4800" },
{ 0x10DE0600, "GeForce 8800 GTS 512" },
{ 0x10DE0602, "GeForce 8800 GT" },
{ 0x10DE0604, "GeForce 9800 GX2" },
{ 0x10DE0605, "GeForce 9800 GT" },
{ 0x10DE0606, "GeForce 8800 GS" },
{ 0x10DE0607, "GeForce GTS 240" },
{ 0x10DE0608, "GeForce 9800M GTX" },
{ 0x10DE0609, "GeForce 8800M GTS" },
{ 0x10DE060A, "GeForce GTX 280M" },
{ 0x10DE060B, "GeForce 9800M GT" },
{ 0x10DE060C, "GeForce 8800M GTX" },
{ 0x10DE060D, "GeForce 8800 GS" },
{ 0x10DE0610, "GeForce 9600 GSO" },
{ 0x10DE0611, "GeForce 8800 GT" },
{ 0x10DE0612, "GeForce 9800 GTX" },
{ 0x10DE0613, "GeForce 9800 GTX+" },
{ 0x10DE0614, "GeForce 9800 GT" },
{ 0x10DE0615, "GeForce GTS 250" },
{ 0x10DE0617, "GeForce 9800M GTX" },
{ 0x10DE0618, "GeForce GTX 260M" },
{ 0x10DE061A, "Quadro FX 3700" },
{ 0x10DE061C, "Quadro FX 3600M" },
{ 0x10DE061D, "Quadro FX 2800M" },
{ 0x10DE061F, "Quadro FX 3800M" },
{ 0x10DE0622, "GeForce 9600 GT" },
{ 0x10DE0623, "GeForce 9600 GS" },
{ 0x10DE0625, "GeForce 9600 GSO 512"},
{ 0x10DE0626, "GeForce GT 130" },
{ 0x10DE0627, "GeForce GT 140" },
{ 0x10DE0628, "GeForce 9800M GTS" },
{ 0x10DE062A, "GeForce 9700M GTS" },
{ 0x10DE062C, "GeForce 9800M GTS" },
{ 0x10DE0640, "GeForce 9500 GT" },
{ 0x10DE0641, "GeForce 9400 GT" },
{ 0x10DE0642, "GeForce 8400 GS" },
{ 0x10DE0643, "GeForce 9500 GT" },
{ 0x10DE0644, "GeForce 9500 GS" },
{ 0x10DE0645, "GeForce 9500 GS" },
{ 0x10DE0646, "GeForce GT 120" },
{ 0x10DE0647, "GeForce 9600M GT" },
{ 0x10DE0648, "GeForce 9600M GS" },
{ 0x10DE0649, "GeForce 9600M GT" },
{ 0x10DE064A, "GeForce 9700M GT" },
{ 0x10DE064B, "GeForce 9500M G" },
{ 0x10DE064C, "GeForce 9650M GT" },
{ 0x10DE0652, "GeForce GT 130M" },
{ 0x10DE0658, "Quadro FX 380" },
{ 0x10DE0659, "Quadro FX 580" },
{ 0x10DE065A, "Quadro FX 1700M" },
{ 0x10DE065B, "GeForce 9400 GT" },
{ 0x10DE065C, "Quadro FX 770M" },
{ 0x10DE06C0, "GeForce GTX 480" },
{ 0x10DE06C4, "GeForce GTX 465" },
{ 0x10DE06CA, "GeForce GTX 480M" },
{ 0x10DE06CD, "GeForce GTX 470" },
{ 0x10DE06E0, "GeForce 9300 GE" },
{ 0x10DE06E1, "GeForce 9300 GS" },
{ 0x10DE06E4, "GeForce 8400 GS" },
{ 0x10DE06E5, "GeForce 9300M GS" },
{ 0x10DE06E8, "GeForce 9200M GS" },
{ 0x10DE06E9, "GeForce 9300M GS" },
{ 0x10DE06EA, "Quadro NVS 150M" },
{ 0x10DE06EB, "Quadro NVS 160M" },
{ 0x10DE06EC, "GeForce G 105M" },
{ 0x10DE06EF, "GeForce G 103M" },
{ 0x10DE06F8, "Quadro NVS 420" },
{ 0x10DE06F9, "Quadro FX 370 LP" },
{ 0x10DE06FA, "Quadro NVS 450" },
{ 0x10DE06FD, "Quadro NVS 295" },
{ 0x10DE086C, "GeForce 9300/nForce 730i" },
{ 0x10DE087D, "ION 9400M" },
{ 0x10DE087E, "ION LE" },
{ 0x10DE0A20, "GeForce GT220" },
{ 0x10DE0A23, "GeForce 210" },
{ 0x10DE0A28, "GeForce GT 230M" },
{ 0x10DE0A2A, "GeForce GT 230M" },
{ 0x10DE0A34, "GeForce GT 240M" },
{ 0x10DE0A60, "GeForce G210" },
{ 0x10DE0A62, "GeForce 205" },
{ 0x10DE0A63, "GeForce 310" },
{ 0x10DE0A65, "GeForce 210" },
{ 0x10DE0A66, "GeForce 310" },
{ 0x10DE0A74, "GeForce G210M" },
{ 0x10DE0A78, "Quadro FX 380 LP" },
{ 0x10DE0CA3, "GeForce GT 240" },
{ 0x10DE0CA8, "GeForce GTS 260M" },
{ 0x10DE0CA9, "GeForce GTS 250M" },
{ 0x10DE0CA3, "GeForce GT240" },
{ 0x10DE0E22, "GeForce GTX 460" },
{ 0x10DE0E24, "GeForce GTX 460" },
{ 0x10DE06D1, "Tesla C2050" },// TODO: sub-device id: 0x0771
{ 0x10DE06D1, "Tesla C2070" },// TODO: sub-device id: 0x0772
{ 0x10DE06DE, "Tesla M2050" },// TODO: sub-device id: 0x0846
{ 0x10DE06DE, "Tesla M2070" }// TODO: sub-device id: ?
};
static uint16_t swap16(uint16_t x)
{
return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));
}
static uint16_t read16(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[2];
ret[0] = ptr[offset+1];
ret[1] = ptr[offset];
return *((uint16_t*)&ret);
}
#if 0
static uint32_t swap32(uint32_t x)
{
return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);
}
static uint8_t read8(uint8_t *ptr, uint16_t offset)
{
return ptr[offset];
}
static uint32_t read32(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[4];
ret[0] = ptr[offset+3];
ret[1] = ptr[offset+2];
ret[2] = ptr[offset+1];
ret[3] = ptr[offset];
return *((uint32_t*)&ret);
}
#endif
static int patch_nvidia_rom(uint8_t *rom)
{
if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {
printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);
return PATCH_ROM_FAILED;
}
uint16_t dcbptr = swap16(read16(rom, 0x36));
if(!dcbptr) {
printf("no dcb table found\n");
return PATCH_ROM_FAILED;
}/* else
printf("dcb table at offset 0x%04x\n", dcbptr);
*/
uint8_t *dcbtable = &rom[dcbptr];
uint8_t dcbtable_version = dcbtable[0];
uint8_t headerlength = 0;
uint8_t recordlength = 0;
uint8_t numentries = 0;
if(dcbtable_version >= 0x20) {
uint32_t sig;
if(dcbtable_version >= 0x30) {
headerlength = dcbtable[1];
numentries = dcbtable[2];
recordlength = dcbtable[3];
sig = *(uint32_t *)&dcbtable[6];
} else {
sig = *(uint32_t *)&dcbtable[4];
headerlength = 8;
}
if (sig != 0x4edcbdcb) {
printf("bad display config block signature (0x%8x)\n", sig);
return PATCH_ROM_FAILED;
}
} else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */
char sig[8] = { 0 };
strncpy(sig, (char *)&dcbtable[-7], 7);
recordlength = 10;
if (strcmp(sig, "DEV_REC")) {
printf("Bad Display Configuration Block signature (%s)\n", sig);
return PATCH_ROM_FAILED;
}
} else {
return PATCH_ROM_FAILED;
}
if(numentries >= MAX_NUM_DCB_ENTRIES)
numentries = MAX_NUM_DCB_ENTRIES;
uint8_t num_outputs = 0, i=0;
struct dcbentry {
uint8_t type;
uint8_t index;
uint8_t *heads;
} entries[numentries];
for (i = 0; i < numentries; i++) {
uint32_t connection;
connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];
/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
continue;
if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */
continue;
if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */
continue;
entries[num_outputs].type = connection & 0xf;
entries[num_outputs].index = num_outputs;
entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);
}
int has_lvds = false;
uint8_t channel1 = 0, channel2 = 0;
for(i=0; i<num_outputs; i++) {
if(entries[i].type == 3) {
has_lvds = true;
//printf("found LVDS\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
}
// if we have a LVDS output, we group the rest to the second channel
if(has_lvds) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
continue;
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
} else {
//
int x;
// we loop twice as we need to generate two channels
for(x=0; x<=1; x++) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
continue;
// if type is TMDS, the prior output is ANALOG
// we always group ANALOG and TMDS
// if there is a TV output after TMDS, we group it to that channel as well
if(i && entries[i].type == 0x2) {
switch (x) {
case 0:
//printf("group channel 1\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if((entries[i-1].type == 0x0)) {
channel1 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
//printf("group tv1\n");
channel1 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
case 1:
//printf("group channel 2 : %d\n", i);
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if((entries[i-1].type == 0x0)) {
channel2 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
//printf("group tv2\n");
channel2 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
}
break;
}
}
}
}
// if we have left ungrouped outputs merge them to the empty channel
uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);
togroup = &channel2;
for(i=0; i<num_outputs;i++)
if(entries[i].type != TYPE_GROUPED) {
//printf("%d not grouped\n", i);
if(togroup)
*togroup |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
if(channel1 > channel2) {
uint8_t buff = channel1;
channel1 = channel2;
channel2 = buff;
}
default_NVCAP[6] = channel1;
default_NVCAP[8] = channel2;
// patching HEADS
for(i=0; i<num_outputs;i++) {
if(channel1 & (1 << i))
*entries[i].heads = 1;
else if(channel2 & (1 << i))
*entries[i].heads = 2;
}
return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);
}
static char *get_nvidia_model(uint32_t id) {
inti;
for (i=1; i< (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {
if (NVKnownChipsets[i].device == id) {
return NVKnownChipsets[i].name;
}
}
return NVKnownChipsets[0].name;
}
static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)
{
intfd;
intsize;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {
return 0;
}
size = file_size(fd);
if (size > bufsize) {
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);
size = bufsize;
}
size = read(fd, (char *)buf, size);
close(fd);
return size > 0 ? size : 0;
}
static int devprop_add_nvidia_template(struct DevPropDevice *device)
{
chartmp[16];
if(!device)
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_name_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_name_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type))
return 0;
// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!
// len = sprintf(tmp, "Slot-%x", devices_number);
sprintf(tmp, "Slot-%x",devices_number);
devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));
devices_number++;
return 1;
}
int hex2bin(const char *hex, uint8_t *bin, int len)
{
char*p;
inti;
charbuf[3];
if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {
printf("[ERROR] bin2hex input error\n");
return -1;
}
buf[2] = '\0';
p = (char *) hex;
for (i=0; i<len; i++) {
if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {
printf("[ERROR] bin2hex '%s' syntax error\n", hex);
return -2;
}
buf[0] = *p++;
buf[1] = *p++;
bin[i] = (unsigned char) strtoul(buf, NULL, 16);
}
return 0;
}
unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)
{
unsigned long long vram_size = 0;
if (nvCardType < NV_ARCH_50) {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
}
else if (nvCardType >= NV_ARCH_C0) {
vram_size = REG32(NVC0_MEM_CTRLR_COUNT);
vram_size *= REG32(NVC0_MEM_CTRLR_RAM_AMOUNT);
vram_size <<= 20;
}
else {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size |= (vram_size & 0xff) << 32;
vram_size &= 0xffffffff00ll;
}
return vram_size;
}
bool setup_nvidia_devprop(pci_dt_t *nvda_dev)
{
struct DevPropDevice*device;
char*devicepath;
struct pci_rom_pci_header_t*rom_pci_header;
volatile uint8_t*regs;
uint8_t*rom;
uint8_t*nvRom;
uint8_tnvCardType;
unsigned long longvideoRam;
uint32_tnvBiosOveride;
uint32_tbar[7];
uint32_tboot_display;
intnvPatch;
intlen;
charbiosVersion[32];
charnvFilename[32];
charkNVCAP[12];
char*model;
const char*value;
booldoit;
devicepath = get_pci_dev_path(nvda_dev);
bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );
regs = (uint8_t *) (bar[0] & ~0x0f);
delay(50);
// get card type
nvCardType = (REG32(0) >> 20) & 0x1ff;
// Amount of VRAM in kilobytes
videoRam = mem_detect(regs, nvCardType, nvda_dev);
model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);
verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",
model, (uint32_t)(videoRam / 1024 / 1024),
(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,
devicepath);
rom = malloc(NVIDIA_ROM_SIZE);
sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id);
if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit) {
verbose("Looking for nvidia video bios file %s\n", nvFilename);
nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);
if (nvBiosOveride > 0) {
verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);
DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);
} else {
printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);
return false;
}
} else {
// Otherwise read bios from card
nvBiosOveride = 0;
// TODO: we should really check for the signature before copying the rom, i think.
// PRAMIN first
nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];
bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
// PROM next
// Enable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;
nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];
bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// disable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
// 0xC0000 last
bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
printf("ERROR: Unable to locate nVidia Video BIOS\n");
return false;
} else {
DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
} else {
DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
} else {
DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
}
if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {
printf("ERROR: nVidia ROM Patching Failed!\n");
return false;
}
rom_pci_header = (struct pci_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);
// check for 'PCIR' sig
if (rom_pci_header->signature == 0x50434952) {
if (rom_pci_header->device != nvda_dev->device_id) {
// Get Model from the OpROM
model = get_nvidia_model((rom_pci_header->vendor << 16) | rom_pci_header->device);
} else {
printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);
}
}
if (!string) {
string = devprop_create_string();
}
device = devprop_add_device(string, devicepath);
/* FIXME: for primary graphics card only */
boot_display = 1;
devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
if(nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {
uint8_t built_in = 0x01;
devprop_add_value(device, "@0,built-in", &built_in, 1);
}
// get bios version
const int MAX_BIOS_VERSION_LENGTH = 32;
char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);
memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);
int i, version_start;
int crlf_count = 0;
// only search the first 384 bytes
for(i = 0; i < 0x180; i++) {
if(rom[i] == 0x0D && rom[i+1] == 0x0A) {
crlf_count++;
// second 0x0D0A was found, extract bios version
if(crlf_count == 2) {
if(rom[i-1] == 0x20) i--; // strip last " "
for(version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--) {
// find start
if(rom[version_start] == 0x00) {
version_start++;
// strip "Version "
if(strncmp((const char*)rom+version_start, "Version ", 8) == 0) {
version_start += 8;
}
strncpy(version_str, (const char*)rom+version_start, i-version_start);
break;
}
}
break;
}
}
}
sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);
sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);
if (getValueForKey(kNVCAP, &value, &len, &bootInfo->bootConfig) && len == NVCAP_LEN * 2) {
uint8_tnew_NVCAP[NVCAP_LEN];
if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) {
verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);
memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);
}
}
#if DEBUG_NVCAP
printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",
default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],
default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],
default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],
default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],
default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);
#endif
devprop_add_nvidia_template(device);
devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);
devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);
devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);
if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit) {
devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));
}
stringdata = malloc(sizeof(uint8_t) * string->length);
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
branches/meklort/i386/modules/GraphicsEnabler/Makefile
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MODULE_NAME = GraphicsEnabler
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = _$(MODULE_NAME)_start
MODULE_DEPENDENCIES =
DIR = HelloWorld
include ../../MakePaths.dir
OBJROOT=../../../obj/i386/modules/$(DIR)
SYMROOT=../../../sym/i386/modules/
DSTROOT=../../../dst/i386/modules/
UTILDIR = ../../util
LIBSADIR = ../../libsa
LIBSAIODIR = ../../libsaio
BOOT2DIR = ../../boot2
INSTALLDIR = $(DSTROOT)/System/Library/Frameworks/System.framework/Versions/B/PrivateHeaders/standalone
OPTIM = -Os -Oz
DEBUG = -DNOTHING
#DEBUG = -DDEBUG_HELLO_WORLD=1
CFLAGS= $(RC_CFLAGS) $(OPTIM) $(MORECPP) -arch i386 -g -Wmost \
-D__ARCHITECTURE__=\"i386\" -DSAIO_INTERNAL_USER \
-DRCZ_COMPRESSED_FILE_SUPPORT $(DEBUG) \
-fno-builtin $(OMIT_FRAME_POINTER_CFLAG) \
-mpreferred-stack-boundary=2 -fno-align-functions -fno-stack-protector \
-march=pentium4 -msse2 -mfpmath=sse -msoft-float -fno-common -mdynamic-no-pic
DEFINES=
CONFIG = hd
INC = -I. -I.. -I$(SYMROOT) -I$(UTILDIR) -I$(LIBSADIR) -I$(LIBSAIODIR) -I$(BOOT2DIR)
ifneq "" "$(wildcard /bin/mkdirs)"
MKDIRS = /bin/mkdirs
else
MKDIRS = /bin/mkdir -p
endif
AS = as
LD = ld
# LIBS= -lc_static
LIBS=
VPATH = $(OBJROOT):$(SYMROOT)
GRAPHICS_ENABLER_OBJS = nvidia.o ati.o GraphicsEnabler.o
SFILES =
CFILES =
HFILES =
EXPORTED_HFILES =
INSTALLED_HFILES =
OTHERFILES = Makefile
ALLSRC = $(SFILES) $(CFILES) \
$(HFILES) $(OTHERFILES)
DIRS_NEEDED = $(OBJROOT) $(SYMROOT)
all embedtheme optionrom: ${GRAPHICS_ENABLER_OBJS} dylib
dylib: ${GRAPHICS_ENABLER_OBJS}
ld -flat_namespace -arch i386 \
-undefined suppress \
-alias $(MODULE_START) start \
-dylib -read_only_relocs suppress \
-S -x -Z -dead_strip_dylibs \
-no_uuid \
-current_version $(MODULE_VERSION) -compatibility_version $(MODULE_COMPAT_VERSION) \
-final_output $(MODULE_NAME) \
$(OBJROOT)/ati.o \
$(OBJROOT)/nvidia.o \
$(OBJROOT)/GraphicsEnabler.o \
-o $(SYMROOT)/$(MODULE_NAME).dylib
GraphicsEnabler.o:
$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c "GraphicsEnabler.c" $(INC) -o "$(OBJROOT)/GraphicsEnabler.o"
ati.o:
$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c "ati.c" $(INC) -o "$(OBJROOT)/ati.o"
nvidia.o:
$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c "nvidia.c" $(INC) -o "$(OBJROOT)/nvidia.o"
include ../../MakeInc.dir
# dependencies
-include $(OBJROOT)/Makedep
branches/meklort/i386/modules/GraphicsEnabler/ati.c
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/*
* ATI injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas
*
* ATI injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ATI driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with ATI injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
#include "libsaio.h"
#include "boot.h"
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#include "device_inject.h"
#include "ati.h"
#ifndef DEBUG_ATI
#define DEBUG_ATI 0
#endif
#if DEBUG_ATI
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
#define MAX_NUM_DCB_ENTRIES 16
#define TYPE_GROUPED 0xff
extern uint32_t devices_number;
const char *ati_compatible_0[]= { "@0,compatible", "ATY,%s" };
const char *ati_compatible_1[]= { "@1,compatible", "ATY,%s" };
const char *ati_device_type_0[]= { "@0,device_type", "display" };
const char *ati_device_type_1[]= { "@1,device_type", "display" };
const char *ati_device_type[]= { "device_type", "ATY,%sParent" };
const char *ati_name_0[]= { "@0,name", "ATY,%s" };
const char *ati_name_1[]= { "@1,name", "ATY,%s" };
const char *ati_name[]= { "name", "ATY,%sParent" };
const char *ati_efidisplay_0[]= { "@0,ATY,EFIDisplay", "TMDSB" };
struct ati_data_key ati_connector_type_0= { 0x04, "@0,connector-type", {0x00, 0x04, 0x00, 0x00} };
struct ati_data_key ati_connector_type_1= { 0x04, "@1,connector-type", {0x04, 0x00, 0x00, 0x00} };
struct ati_data_key ati_display_con_fl_type_0= { 0x04, "@0,display-connect-flags", {0x00, 0x00, 0x04, 0x00} };
const char *ati_display_type_0[]= { "@0,display-type", "LCD" };
const char *ati_display_type_1[]= { "@1,display-type", "NONE" };
struct ati_data_key ati_aux_power_conn= { 0x04, "AAPL,aux-power-connected", {0x01, 0x00, 0x00, 0x00} };
struct ati_data_key ati_backlight_ctrl= { 0x04, "AAPL,backlight-control", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl01_coher= { 0x04, "AAPL01,Coherency", {0x01, 0x00, 0x00, 0x00} };
const char *ati_card_no[]= { "ATY,Card#", "109-B77101-00" };
const char *ati_copyright[]= { "ATY,Copyright", "Copyright AMD Inc. All Rights Reserved. 2005-2009" };
const char *ati_efi_compile_d[]= { "ATY,EFICompileDate", "Jan 26 2009" };
struct ati_data_key ati_efi_disp_conf= { 0x08, "ATY,EFIDispConfig", {0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} };
struct ati_data_key ati_efi_drv_type= { 0x01, "ATY,EFIDriverType", {0x02} };
struct ati_data_key ati_efi_enbl_mode= { 0x01, "ATY,EFIEnabledMode", {0x01} };
struct ati_data_key ati_efi_init_stat= { 0x04, "ATY,EFIHWInitStatus", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_efi_orientation= { 0x02, "ATY,EFIOrientation", {0x02, 0x00} };
const char *ati_efi_version[]= { "ATY,EFIVersion", "01.00.318" };
const char *ati_efi_versionB[]= { "ATY,EFIVersionB", "113-SBSJ1G04-00R-02" };
const char *ati_efi_versionE[]= { "ATY,EFIVersionE", "113-B7710A-318" };
struct ati_data_key ati_mclk= { 0x04, "ATY,MCLK", {0x70, 0x2e, 0x11, 0x00} };
struct ati_data_key ati_mem_rev_id= { 0x02, "ATY,MemRevisionID", {0x03, 0x00} };
struct ati_data_key ati_mem_vend_id= { 0x02, "ATY,MemVendorID", {0x02, 0x00} };
const char *ati_mrt[]= { "ATY,MRT", " " };
const char *ati_romno[]= { "ATY,Rom#", "113-B7710C-176" };
struct ati_data_key ati_sclk= { 0x04, "ATY,SCLK", {0x28, 0xdb, 0x0b, 0x00} };
struct ati_data_key ati_vendor_id= { 0x02, "ATY,VendorID", {0x02, 0x10} };
struct ati_data_key ati_platform_info= { 0x80, "ATY,PlatformInfo", {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_mvad= { 0x40, "MVAD", {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, 0x92, 0x20, 0x00, 0x03} };
struct ati_data_key ati_saved_config= { 0x100, "saved-config", {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, 0x92, 0x20, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xee, 0x02, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
///non 48xx keys
const char *ati_efidisplay_0_n4[]= { "@0,ATY,EFIDisplay", "TMDSA" };
struct ati_data_key ati_connector_type_0_n4= { 0x04, "@0,connector-type", {0x04, 0x00, 0x00, 0x00} };
struct ati_data_key ati_connector_type_1_n4= { 0x04, "@1,connector-type", {0x00, 0x02, 0x00, 0x00} };
struct ati_data_key ati_aapl_emc_disp_list_n4= { 0x40, "AAPL,EMC-Display-List", {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x1b, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x1c, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x21, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_fb_offset_n4= { 0x08, "ATY,FrameBufferOffset", {0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00} };
struct ati_data_key ati_hwgpio_n4= { 0x04, "ATY,HWGPIO", {0x23, 0xa8, 0x48, 0x00} };
struct ati_data_key ati_iospace_offset_n4= { 0x08, "ATY,IOSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00} };
struct ati_data_key ati_mclk_n4= { 0x04, "ATY,MCLK", {0x00, 0x35, 0x0c, 0x00} };
struct ati_data_key ati_sclk_n4= { 0x04, "ATY,SCLK", {0x60, 0xae, 0x0a, 0x00} };
struct ati_data_key ati_refclk_n4= { 0x04, "ATY,RefCLK", {0x8c, 0x0a, 0x00, 0x00} };
struct ati_data_key ati_regspace_offset_n4= { 0x08, "ATY,RegisterSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x90, 0xa2, 0x00, 0x00} };
struct ati_data_key ati_vram_memsize_0= { 0x08, "@0,VRAM,memsize", {0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_vram_memsize_1= { 0x08, "@1,VRAM,memsize", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl_blackscr_prefs_0_n4= { 0x04, "AAPL00,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl_blackscr_prefs_1_n4= { 0x04, "AAPL01,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_swgpio_info_n4= { 0x04, "ATY,SWGPIO Info", {0x00, 0x48, 0xa8, 0x23} };
struct ati_data_key ati_efi_orientation_n4= { 0x01, "ATY,EFIOrientation", {0x08} };
struct ati_data_key ati_mvad_n4= { 0x100, "MVAD", {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_saved_config_n4= { 0x100, "saved-config", {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct pcir_s {
uint32_t signature;
uint16_t vid;
uint16_t devid;
};
// Known cards as of 2008/08/26
static struct ati_chipsets_t ATIKnownChipsets[] = {
{ 0x00000000, "Unknown" } ,
{ 0x10029589, "ATI Radeon 2600 Series"} ,
{ 0x10029588, "ATI Radeon 2600 Series"} ,
{ 0x100294C3, "ATI Radeon 2400 Series"} ,
{ 0x100294C4, "ATI Radeon 2400 Series"} ,
{ 0x100294C6, "ATI Radeon 2400 Series"} ,
{ 0x10029400, "ATI Radeon 2900 Series"} ,
{ 0x10029405, "ATI Radeon 2900GT Series"} ,
{ 0x10029581, "ATI Radeon 2600 Series"} ,
{ 0x10029583, "ATI Radeon 2600 Series"} ,
{ 0x10029586, "ATI Radeon 2600 Series"} ,
{ 0x10029587, "ATI Radeon 2600 Series"} ,
{ 0x100294C9, "ATI Radeon 2400 Series"} ,
{ 0x10029501, "ATI Radeon 3800 Series"} ,
{ 0x10029505, "ATI Radeon 3800 Series"} ,
{ 0x10029515, "ATI Radeon 3800 Series"} ,
{ 0x10029507, "ATI Radeon 3800 Series"} ,
{ 0x10029500, "ATI Radeon 3800 Series"} ,
{ 0x1002950F, "ATI Radeon 3800X2 Series"} ,
{ 0x100295C5, "ATI Radeon 3400 Series"} ,
{ 0x100295C7, "ATI Radeon 3400 Series"} ,
{ 0x100295C0, "ATI Radeon 3400 Series"} ,
{ 0x10029596, "ATI Radeon 3600 Series"} ,
{ 0x10029590, "ATI Radeon 3600 Series"} ,
{ 0x10029599, "ATI Radeon 3600 Series"} ,
{ 0x10029597, "ATI Radeon 3600 Series"} ,
{ 0x10029598, "ATI Radeon 3600 Series"} ,
{ 0x10029442, "ATI Radeon 4850 Series"} ,
{ 0x10029440, "ATI Radeon 4870 Series"} ,
{ 0x1002944C, "ATI Radeon 4830 Series"} ,
{ 0x10029460, "ATI Radeon 4890 Series"} ,
{ 0x10029462, "ATI Radeon 4890 Series"} ,
{ 0x10029441, "ATI Radeon 4870X2 Series"} ,
{ 0x10029443, "ATI Radeon 4850X2 Series"} ,
{ 0x10029444, "ATI Radeon 4800 Series"} ,
{ 0x10029446, "ATI Radeon 4800 Series"} ,
{ 0x1002944E, "ATI Radeon 4730 Series"} ,
{ 0x10029450, "ATI Radeon 4800 Series"} ,
{ 0x10029452, "ATI Radeon 4800 Series"} ,
{ 0x10029456, "ATI Radeon 4800 Series"} ,
{ 0x1002944A, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002945A, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002945B, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002944B, "ATI Radeon 4800 Mobility Series"} ,
{ 0x10029490, "ATI Radeon 4670 Series"} ,
{ 0x10029498, "ATI Radeon 4650 Series"} ,
{ 0x10029490, "ATI Radeon 4600 Series"} ,
{ 0x10029498, "ATI Radeon 4600 Series"} ,
{ 0x1002949E, "ATI Radeon 4600 Series"} ,
{ 0x10029480, "ATI Radeon 4600 Series"} ,
{ 0x10029488, "ATI Radeon 4600 Series"} ,
{ 0x10029540, "ATI Radeon 4500 Series"} ,
{ 0x10029541, "ATI Radeon 4500 Series"} ,
{ 0x1002954E, "ATI Radeon 4500 Series"} ,
{ 0x10029552, "ATI Radeon 4300 Mobility Series"} ,
{ 0x10029553, "ATI Radeon 4500 Mobility Series"} ,
{ 0x1002954F, "ATI Radeon 4300 Series"} ,
{ 0x100294B3, "ATI Radeon 4770 Series"} ,
{ 0x100294B5, "ATI Radeon 4770 Series"} ,
{ 0x100268B8, "ATI Radeon 5700 Series"} ,
{ 0x100268BE, "ATI Radeon 5700 Series"} ,
{ 0x10026898, "ATI Radeon 5800 Series"} ,
{ 0x10026899, "ATI Radeon 5800 Series"}
};
static struct ati_chipsets_t ATIKnownFramebuffers[] = {
{ 0x00000000, "Megalodon" },
{ 0x10029589, "Lamna"} ,
{ 0x10029588, "Lamna"} ,
{ 0x100294C3, "Iago"} ,
{ 0x100294C4, "Iago"} ,
{ 0x100294C6, "Iago"} ,
{ 0x10029400, "Franklin"} ,
{ 0x10029405, "Franklin"} ,
{ 0x10029581, "Hypoprion"} ,
{ 0x10029583, "Hypoprion"} ,
{ 0x10029586, "Hypoprion"} ,
{ 0x10029587, "Hypoprion"} ,
{ 0x100294C9, "Iago"} ,
{ 0x10029501, "Megalodon"} ,
{ 0x10029505, "Megalodon"} ,
{ 0x10029515, "Megalodon"} ,
{ 0x10029507, "Megalodon"} ,
{ 0x10029500, "Megalodon"} ,
{ 0x1002950F, "Triakis"} ,
{ 0x100295C5, "Iago"} ,
{ 0x100295C7, "Iago"} ,
{ 0x100295C0, "Iago"} ,
{ 0x10029596, "Megalodon"} ,
{ 0x10029590, "Megalodon"} ,
{ 0x10029599, "Megalodon"} ,
{ 0x10029597, "Megalodon"} ,
{ 0x10029598, "Megalodon"} ,
{ 0x10029442, "Motmot"} ,
{ 0x10029440, "Motmot"} ,
{ 0x1002944C, "Motmot"} ,
{ 0x10029460, "Motmot"} ,
{ 0x10029462, "Motmot"} ,
{ 0x10029441, "Motmot"} ,
{ 0x10029443, "Motmot"} ,
{ 0x10029444, "Motmot"} ,
{ 0x10029446, "Motmot"} ,
{ 0x1002944E, "Motmot"} ,
{ 0x10029450, "Motmot"} ,
{ 0x10029452, "Motmot"} ,
{ 0x10029456, "Motmot"} ,
{ 0x1002944A, "Motmot"} ,
{ 0x1002945A, "Motmot"} ,
{ 0x1002945B, "Motmot"} ,
{ 0x1002944B, "Motmot"} ,
{ 0x10029490, "Peregrine"} ,
{ 0x10029498, "Peregrine"} ,
{ 0x1002949E, "Peregrine"} ,
{ 0x10029480, "Peregrine"} ,
{ 0x10029488, "Peregrine"} ,
{ 0x10029540, "Peregrine"} ,
{ 0x10029541, "Peregrine"} ,
{ 0x1002954E, "Peregrine"} ,
{ 0x10029552, "Peregrine"} ,
{ 0x10029553, "Peregrine"} ,
{ 0x1002954F, "Peregrine"} ,
{ 0x100294B3, "Peregrine"},
{ 0x100294B5, "Peregrine"},
{ 0x100268B8, "Motmot"},
{ 0x100268BE, "Motmot"},
{ 0x10026898, "Motmot"},
{ 0x10026899, "Motmot"}
};
static uint32_t accessROM(pci_dt_t *ati_dev, unsigned int mode)
{
uint32_tbar[7];
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (uint32_t *) (bar[2] & ~0x0f);
if (mode) {
if (mode != 1) {
return 0xe00002c7;
}
REG32W(0x179c, 0x00080000);
REG32W(0x1798, 0x00080721);
REG32W(0x17a0, 0x00080621);
REG32W(0x1600, 0x14030300);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
REG32W(0x17a0, 0x21);
REG32W(0x1798, 0x21);
REG32W(0x1798, 0x21);
} else {
REG32W(0x1600, 0x14030302);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00080000);
REG32W(0x17a0, 0x00080621);
REG32W(0x1798, 0x00080721);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
REG32W(0x1604, 0x0400e9fc);
REG32W(0x161c, 0x00);
REG32W(0x1620, 0x9f);
REG32W(0x1618, 0x00040004);
REG32W(0x161c, 0x00);
REG32W(0x1604, 0xe9fc);
REG32W(0x179c, 0x00080000);
REG32W(0x1798, 0x00080721);
REG32W(0x17a0, 0x00080621);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
}
return 0;
}
static uint8_t *readAtomBIOS(pci_dt_t *ati_dev)
{
uint32_tbar[7];
uint32_t*BIOSBase;
uint32_tcounter;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (volatile uint32_t *) (bar[2] & ~0x0f);
accessROM(ati_dev, 0);
REG32W(0xa8, 0);
REG32R(0xac);
REG32W(0xa8, 0);
REG32R(0xac);
BIOSBase = malloc(0x10000);
REG32W(0xa8, 0);
BIOSBase[0] = REG32R(0xac);
counter = 4;
do {
REG32W(0xa8, counter);
BIOSBase[counter/4] = REG32R(0xac);
counter +=4;
} while (counter != 0x10000);
accessROM((pci_dt_t *)regs, 1);
if (*(uint16_t *)BIOSBase != 0xAA55) {
printf("Wrong BIOS signature: %04x\n", *(uint16_t *)BIOSBase);
return 0;
}
return (uint8_t *)BIOSBase;
}
#define R5XX_CONFIG_MEMSIZE0x00F8
#define R6XX_CONFIG_MEMSIZE0x5428
uint32_t getvramsizekb(pci_dt_t *ati_dev)
{
uint32_tbar[7];
uint32_tsize;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (uint32_t *) (bar[2] & ~0x0f);
if (ati_dev->device_id < 0x9400) {
size = (REG32R(R5XX_CONFIG_MEMSIZE)) >> 10;
} else {
size = (REG32R(R6XX_CONFIG_MEMSIZE)) >> 10;
}
return size;
}
#define AVIVO_D1CRTC_CONTROL0x6080
#define AVIVO_CRTC_EN(1<<0)
#define AVIVO_D2CRTC_CONTROL0x6880
static bool radeon_card_posted(pci_dt_t *ati_dev)
{
// if devid matches biosimage(from legacy) devid - posted card, fails with X2/crossfire cards.
/*char *biosimage = 0xC0000;
if ((uint8_t)biosimage[0] == 0x55 && (uint8_t)biosimage[1] == 0xaa)
{
struct pci_rom_pci_header_t *rom_pci_header;
rom_pci_header = (struct pci_rom_pci_header_t*)(biosimage + (uint8_t)biosimage[24] + (uint8_t)biosimage[25]*256);
if (rom_pci_header->signature == 0x52494350)
{
if (rom_pci_header->device == ati_dev->device_id)
{
return true;
printf("Card was POSTed\n");
}
}
}
return false;
printf("Card was not POSTed\n");
*/
//fails yet
uint32_tbar[7];
uint32_tval;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18);
regs = (uint32_t *) (bar[2] & ~0x0f);
val = REG32R(AVIVO_D1CRTC_CONTROL) | REG32R(AVIVO_D2CRTC_CONTROL);
if (val & AVIVO_CRTC_EN) {
return true;
} else {
return false;
}
}
static uint32_t load_ati_bios_file(const char *filename, uint8_t *buf, int bufsize)
{
intfd;
intsize;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {
return 0;
}
size = file_size(fd);
if (size > bufsize) {
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);
size = bufsize;
}
size = read(fd, (char *)buf, size);
close(fd);
return size > 0 ? size : 0;
}
static char *get_ati_model(uint32_t id)
{
inti;
for (i=0; i< (sizeof(ATIKnownChipsets) / sizeof(ATIKnownChipsets[0])); i++) {
if (ATIKnownChipsets[i].device == id) {
return ATIKnownChipsets[i].name;
}
}
return ATIKnownChipsets[0].name;
}
static char *get_ati_fb(uint32_t id)
{
inti;
for (i=0; i< (sizeof(ATIKnownFramebuffers) / sizeof(ATIKnownFramebuffers[0])); i++) {
if (ATIKnownFramebuffers[i].device == id) {
return ATIKnownFramebuffers[i].name;
}
}
return ATIKnownFramebuffers[0].name;
}
static int devprop_add_iopciconfigspace(struct DevPropDevice *device, pci_dt_t *ati_dev)
{
inti;
uint8_t*config_space;
if (!device || !ati_dev) {
return 0;
}
printf("dumping pci config space, 256 bytes\n");
config_space = malloc(256);
for (i=0; i<=255; i++) {
config_space[i] = pci_config_read8( ati_dev->dev.addr, i);
}
devprop_add_value(device, "ATY,PCIConfigSpace", config_space, 256);
free (config_space);
return 1;
}
static int devprop_add_ati_template_4xxx(struct DevPropDevice *device)
{
if(!device)
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_compatible_0))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_compatible_1))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_1))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_device_type))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name_0))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name_1))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_display_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_display_type_1))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_slot_name))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_card_no))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_copyright))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_version))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_mrt))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_romno))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_name_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_display_con_fl_type_0))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_disp_conf))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_init_stat))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config))
return 0;
return 1;
}
static int devprop_add_ati_template(struct DevPropDevice *device)
{
if(!device)
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0_n4))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_slot_name_n4))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_card_no))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_copyright))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_version))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_mrt))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_romno))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_name_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_emc_disp_list_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_fb_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_hwgpio_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_iospace_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_refclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_regspace_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_0_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_1_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_swgpio_info_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config_n4))
return 0;
return 1;
}
bool setup_ati_devprop(pci_dt_t *ati_dev)
{
struct DevPropDevice*device;
char*devicepath;
char*model;
char*framebuffer;
chartmp[64];
uint8_t*rom = NULL;
uint32_trom_size = 0;
uint8_t*bios;
uint32_tbios_size;
uint32_tvram_size;
uint32_tboot_display;
uint8_tcmd;
booldoit;
booltoFree;
devicepath = get_pci_dev_path(ati_dev);
cmd = pci_config_read8(ati_dev->dev.addr, 4);
verbose("old pci command - %x\n", cmd);
if (cmd == 0) {
pci_config_write8(ati_dev->dev.addr, 4, 6);
cmd = pci_config_read8(ati_dev->dev.addr, 4);
verbose("new pci command - %x\n", cmd);
}
model = get_ati_model((ati_dev->vendor_id << 16) | ati_dev->device_id);
framebuffer = get_ati_fb((ati_dev->vendor_id << 16) | ati_dev->device_id);
if (!string) {
string = devprop_create_string();
}
device = devprop_add_device(string, devicepath);
if (!device) {
printf("Failed initializing dev-prop string dev-entry, press any key...\n");
getc();
return false;
}
/* FIXME: for primary graphics card only */
if (radeon_card_posted(ati_dev)) {
boot_display = 1;
} else {
boot_display = 0;
}
verbose("boot display - %x\n", boot_display);
devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
if((framebuffer[0] == 'M' && framebuffer[1] == 'o' && framebuffer[2] == 't') ||
(framebuffer[0] == 'S' && framebuffer[1] == 'h' && framebuffer[2] == 'r') ||
(framebuffer[0] == 'P' && framebuffer[1] == 'e' && framebuffer[2] == 'r')) //faster than strcmp ;)
devprop_add_ati_template_4xxx(device);
else {
devprop_add_ati_template(device);
vram_size = getvramsizekb(ati_dev) * 1024;
if ((vram_size > 0x80000000) || (vram_size == 0)) {
vram_size = 0x10000000;//vram reported wrong, defaulting to 256 mb
}
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&vram_size, 4);
ati_vram_memsize_0.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway
ati_vram_memsize_0.data[7] = (vram_size >> 24) & 0xFF;
ati_vram_memsize_1.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway
ati_vram_memsize_1.data[7] = (vram_size >> 24) & 0xFF;
DP_ADD_TEMP_VAL_DATA(device, ati_vram_memsize_0);
DP_ADD_TEMP_VAL_DATA(device, ati_vram_memsize_1);
devprop_add_iopciconfigspace(device, ati_dev);
}
devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1));
devprop_add_value(device, "ATY,DeviceID", (uint8_t*)&ati_dev->device_id, 2);
//fb setup
sprintf(tmp, "Slot-%x",devices_number);
devprop_add_value(device, "AAPL,slot-name", (uint8_t*)tmp, strlen(tmp) + 1);
devices_number++;
sprintf(tmp, ati_compatible_0[1], framebuffer);
devprop_add_value(device, (char *) ati_compatible_0[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_compatible_1[1], framebuffer);
devprop_add_value(device, (char *) ati_compatible_1[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_device_type[1], framebuffer);
devprop_add_value(device, (char *) ati_device_type[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name[1], framebuffer);
devprop_add_value(device, (char *) ati_name[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name_0[1], framebuffer);
devprop_add_value(device, (char *) ati_name_0[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name_1[1], framebuffer);
devprop_add_value(device, (char *) ati_name_1[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, "/Extra/%04x_%04x.rom", (uint16_t)ati_dev->vendor_id, (uint16_t)ati_dev->device_id);
if (getBoolForKey(kUseAtiROM, &doit, &bootInfo->bootConfig) && doit) {
verbose("looking for ati video bios file %s\n", tmp);
rom = malloc(0x20000);
rom_size = load_ati_bios_file(tmp, rom, 0x20000);
if (rom_size > 0) {
verbose("Using ATI Video BIOS File %s (%d Bytes)\n", tmp, rom_size);
if (rom_size > 0x10000) {
rom_size = 0x10000; //we dont need rest anyway;
}
} else {
printf("ERROR: unable to open ATI Video BIOS File %s\n", tmp);
}
}
if (rom_size == 0) {
if (boot_display) {// no custom rom
bios = NULL;// try to dump from legacy space, otherwise can result in 100% fan speed
} else {
// readAtomBios result in bug on some cards (100% fan speed and black screen),
// not using it for posted card, rading from legacy space instead
bios = readAtomBIOS(ati_dev);
}
} else {
bios = rom;//going custom rom way
verbose("Using rom %s\n", tmp);
}
if (bios == NULL) {
bios = (uint8_t *)0x000C0000;
toFree = false;
verbose("Not going to use bios image file\n");
} else {
toFree = true;
}
if (bios[0] == 0x55 && bios[1] == 0xaa) {
printf("Found bios image\n");
bios_size = bios[2] * 512;
struct pci_rom_pci_header_t *rom_pci_header;
rom_pci_header = (struct pci_rom_pci_header_t*)(bios + bios[24] + bios[25]*256);
if (rom_pci_header->signature == 0x52494350) {
if (rom_pci_header->device != ati_dev->device_id) {
verbose("Bios image (%x) doesnt match card (%x), ignoring\n", rom_pci_header->device, ati_dev->device_id);
} else {
if (toFree) {
verbose("Adding binimage to card %x from mmio space with size %x\n", ati_dev->device_id, bios_size);
} else {
verbose("Adding binimage to card %x from legacy space with size %x\n", ati_dev->device_id, bios_size);
}
devprop_add_value(device, "ATY,bin_image", bios, bios_size);
}
} else {
verbose("Wrong pci header signature %x\n", rom_pci_header->signature);
}
} else {
verbose("Bios image not found at %x, content %x %x\n", bios, bios[0], bios[1]);
}
if (toFree) {
free(bios);