Chameleon

Chameleon Commit Details

Date:2010-09-23 06:05:45 (13 years 7 months ago)
Author:Evan Lojewski
Commit:542
Parents: 541
Message:Removed some uneccisary if staements. saved a few hundred bytes.
Changes:
M/branches/meklort/i386/libsaio/platform.c
M/branches/meklort/i386/libsaio/cpu.c
M/branches/meklort/i386/libsaio/platform.h

File differences

branches/meklort/i386/libsaio/platform.c
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#define DBG(x...)␊
#endif␊
␊
PlatformInfo_t Platform;␊
pci_dt_t * dram_controller_dev = NULL;␊
PlatformInfo_t* Platform;␊
␊
/** Return if a CPU feature specified by feature is activated (true) or not (false) */␊
bool platformCPUFeature(uint32_t feature)␊
inline bool platformCPUFeature(uint32_t feature)␊
{␊
␉if (Platform.CPU.Features & feature) {␊
␉␉return true;␊
␉} else {␊
␉␉return false;␊
␉}␊
␉return (Platform->CPU.Features & feature);␊
}␊
␊
/** scan mem for memory autodection purpose */␊
_before_ bootConfig xml parsing settings are loaded␊
*/␊
void scan_platform(void)␊
{␊
{␉␊
␉Platform = malloc(sizeof(Platform));␊
␉memset(&Platform, 0, sizeof(Platform));␊
␉build_pci_dt();␊
␉scan_cpu(&Platform);␊
branches/meklort/i386/libsaio/cpu.c
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␉}␊
␉␊
␉/* setup features */␊
␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
␉}␊
␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
␉}␊
␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
␉}␊
␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
␉}␊
␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
␉}␊
␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
␉}␊
␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {␊
␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
␉}␊
␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
␉}␊
␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
␉p->CPU.Features |= (CPU_FEATURE_MMX | CPU_FEATURE_SSE | CPU_FEATURE_SSE2 | CPU_FEATURE_MSR) & p->CPU.CPUID[CPUID_1][3];␊
␉p->CPU.Features |= (CPU_FEATURE_SSE3 | CPU_FEATURE_SSE41 | CPU_FEATURE_SSE42) & p->CPU.CPUID[CPUID_1][2];␉␊
␉p->CPU.Features |= (CPU_FEATURE_EM64T) & p->CPU.CPUID[CPUID_81][3];␊
␊
␊
␉//if ((CPU_FEATURE_HTT & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
␉}␊
␉ ␊
␊
␉tscFrequency = measure_tsc_frequency();␊
␉fsbFrequency = 0;␊
branches/meklort/i386/libsaio/platform.h
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extern void scan_platform(void);␊
extern void dumpPhysAddr(const char * title, void * a, int len);␊
␊
#define bit(n)␉␉␉(1UL << (n))␊
#define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊
#define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊
␊
␊
/* CPUID index into cpuid_raw */␊
#define CPUID_0␉␉␉␉0␊
#define CPUID_1␉␉␉␉1␊
#define CPU_MODEL_WESTMERE_EX␉0x2F␊
␊
/* CPU Features */␊
#define CPU_FEATURE_MMX␉␉␉0x00000001␉␉// MMX Instruction Set␊
#define CPU_FEATURE_SSE␉␉␉0x00000002␉␉// SSE Instruction Set␊
#define CPU_FEATURE_SSE2␉␉0x00000004␉␉// SSE2 Instruction Set␊
#define CPU_FEATURE_SSE3␉␉0x00000008␉␉// SSE3 Instruction Set␊
#define CPU_FEATURE_SSE41␉␉0x00000010␉␉// SSE41 Instruction Set␊
#define CPU_FEATURE_SSE42␉␉0x00000020␉␉// SSE42 Instruction Set␊
#define CPU_FEATURE_EM64T␉␉0x00000040␉␉// 64Bit Support␊
#define CPU_FEATURE_HTT␉␉␉0x00000080␉␉// HyperThreading␊
#define CPU_FEATURE_MOBILE␉␉0x00000100␉␉// Mobile CPU␊
#define CPU_FEATURE_MSR␉␉␉0x00000200␉␉// MSR Support␊
// NOTE: Theses are currently mapped to the actual bit in the cpuid value␊
#define CPU_FEATURE_MMX␉␉␉bit(23)␉␉// MMX Instruction Set␊
#define CPU_FEATURE_SSE␉␉␉bit(25)␉␉// SSE Instruction Set␊
#define CPU_FEATURE_SSE2␉␉bit(26)␉␉// SSE2 Instruction Set␊
#define CPU_FEATURE_SSE3␉␉bit(0)␉␉// SSE3 Instruction Set␊
#define CPU_FEATURE_SSE41␉␉bit(19)␉␉// SSE41 Instruction Set␊
#define CPU_FEATURE_SSE42␉␉bit(20)␉␉// SSE42 Instruction Set␊
#define CPU_FEATURE_EM64T␉␉bit(29)␉␉// 64Bit Support␊
#define CPU_FEATURE_HTT␉␉␉bit(28)␉␉// HyperThreading␊
#define CPU_FEATURE_MSR␉␉␉bit(5)␉␉// MSR Support␊
// NOTE: Determine correc tbit for bellow␊
#define CPU_FEATURE_MOBILE␉␉bit(1)␉␉// Mobile CPU␊
␊
␊
/* SMBIOS Memory Types */ ␊
#define SMB_MEM_TYPE_UNDEFINED␉0␊
#define SMB_MEM_TYPE_OTHER␉␉1␊
␉uint8_t␉␉␉␉Type;␉␉␉// System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)␊
} PlatformInfo_t;␊
␊
extern PlatformInfo_t Platform;␊
extern PlatformInfo_t* Platform;␊
␊
#endif /* !__LIBSAIO_PLATFORM_H */␊

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Revision: 542