Chameleon

Chameleon Commit Details

Date:2010-09-23 15:15:34 (9 years 1 month ago)
Author:Evan Lojewski
Commit:546
Parents: 545
Message:More code shrinkage
Changes:
M/branches/meklort/i386/libsaio/cpu.c
M/branches/meklort/i386/libsaio/platform.h
M/branches/meklort/i386/libsaio/pci.c

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branches/meklort/i386/libsaio/cpu.c
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void scan_cpu(PlatformInfo_t *p)
{
int i = 0;
uint64_ttscFrequency, fsbFrequency, cpuFrequency;
uint64_tmsr, flex_ratio;
uint8_tmaxcoef, maxdiv, currcoef, currdiv;
maxcoef = maxdiv = currcoef = currdiv = 0;
/* get cpuid values */
do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);
do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);
do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);
do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);
for( ; i < 3; i++)
{
do_cpuid(i, p->CPU.CPUID[i]);
}
do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);
do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);
if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {
fsbFrequency = 0;
cpuFrequency = 0;
if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {
if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {
if ((p->CPU.Vendor == 0x756E6547 /* Intel */) &&
((p->CPU.Family == 0x06) ||
(p->CPU.Family == 0x0f)))
{
if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) ||
(p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))
{
/* Nehalem CPU model */
if (p->CPU.Family == 0x06 && (p->CPU.Model == 0x1a || p->CPU.Model == 0x1e
|| p->CPU.Model == 0x1f || p->CPU.Model == 0x25 || p->CPU.Model == 0x2c)) {
if (p->CPU.Family == 0x06 && (p->CPU.Model == 0x1a || p->CPU.Model == 0x1e ||
p->CPU.Model == 0x1f || p->CPU.Model == 0x25 ||
p->CPU.Model == 0x2c))
{
msr = rdmsr64(MSR_PLATFORM_INFO);
DBG("msr(%d): platform_info %08x\n", __LINE__, msr & 0xffffffff);
currcoef = (msr >> 8) & 0xff;
msr = rdmsr64(MSR_FLEX_RATIO);
DBG("msr(%d): flex_ratio %08x\n", __LINE__, msr & 0xffffffff);
if ((msr >> 16) & 0x01) {
if ((msr >> 16) & 0x01)
{
flex_ratio = (msr >> 8) & 0xff;
if (currcoef > flex_ratio) {
if (currcoef > flex_ratio)
{
currcoef = flex_ratio;
}
}
fsbFrequency = (tscFrequency / currcoef);
}
cpuFrequency = tscFrequency;
} else {
}
else
{
msr = rdmsr64(MSR_IA32_PERF_STATUS);
DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, msr & 0xffffffff);
currcoef = (msr >> 8) & 0x1f;
/* Non-integer bus ratio for the current-multi (undocumented)*/
currdiv = (msr >> 14) & 0x01;
if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) // This will always be model >= 3
if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) ||
(p->CPU.Family == 0x0f)) // This will always be model >= 3
{
/* On these models, maxcoef defines TSC freq */
maxcoef = (msr >> 40) & 0x1f;
} else {
}
else
{
/* On lower models, currcoef defines TSC freq */
/* XXX */
maxcoef = currcoef;
}
if (maxcoef) {
if (maxdiv) {
if (maxcoef)
{
if (maxdiv)
{
fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));
} else {
}
else
{
fsbFrequency = (tscFrequency / maxcoef);
}
if (currdiv) {
if (currdiv)
{
cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);
} else {
}
else
{
cpuFrequency = (fsbFrequency * currcoef);
}
DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");
}
}
/* Mobile CPU ? */
if (rdmsr64(0x17) & (1<<28)) {
if (rdmsr64(0x17) & (1<<28))
{
p->CPU.Features |= CPU_FEATURE_MOBILE;
}
}
#if 0
else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f)) {
if(p->CPU.ExtFamily == 0x00 /* K8 */) {
else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f))
{
if(p->CPU.ExtFamily == 0x00 /* K8 */)
{
msr = rdmsr64(K8_FIDVID_STATUS);
currcoef = (msr & 0x3f) / 2 + 4;
currdiv = (msr & 0x01) * 2;
} else if(p->CPU.ExtFamily >= 0x01 /* K10+ */) {
}
else if(p->CPU.ExtFamily >= 0x01 /* K10+ */)
{
msr = rdmsr64(K10_COFVID_STATUS);
if(p->CPU.ExtFamily == 0x01 /* K10 */)
currcoef = (msr & 0x3f) + 0x10;
currdiv = (2 << ((msr >> 6) & 0x07));
}
if (currcoef) {
if (currdiv) {
if (currcoef)
{
if (currdiv)
{
fsbFrequency = ((tscFrequency * currdiv) / currcoef);
DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);
} else {
}
else
{
fsbFrequency = (tscFrequency / currcoef);
DBG("%d\n", currcoef);
}
}
}
if (!fsbFrequency) {
if (!fsbFrequency)
{
fsbFrequency = (DEFAULT_FSB * 1000);
cpuFrequency = tscFrequency;
DBG("0 ! using the default value for FSB !\n");
branches/meklort/i386/libsaio/platform.h
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#define CPU_FEATURE_EM64Tbit(29)// 64Bit Support
#define CPU_FEATURE_HTTbit(28)// HyperThreading
#define CPU_FEATURE_MSRbit(5)// MSR Support
// NOTE: Determine correc tbit for bellow
// NOTE: Determine correct bit for bellow (28 is already in use)
#define CPU_FEATURE_MOBILEbit(1)// Mobile CPU
branches/meklort/i386/libsaio/pci.c
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#endif
pci_dt_t*root_pci_dev;
static char* dev_path;
uint8_t pci_config_read8(uint32_t pci_addr, uint8_t reg)
uint8_tfunc;
uint8_tsecondary_bus;
uint8_theader_type;
for (dev = 0; dev < 32; dev++) {
for (func = 0; func < 8; func++) {
for (dev = 0; dev < 32; dev++)
{
for (func = 0; func < 8; func++)
{
pci_addr = PCIADDR(bus, dev, func);
id = pci_config_read32(pci_addr, PCI_VENDOR_ID);
if (!id || id == 0xffffffff) {
if (!id || id == 0xffffffff)
{
continue;
}
new = (pci_dt_t*)malloc(sizeof(pci_dt_t));
new->device_id= (id >> 16) & 0xffff;
new->class_id= pci_config_read16(pci_addr, PCI_CLASS_DEVICE);
new->parent= start;
header_type = pci_config_read8(pci_addr, PCI_HEADER_TYPE);
switch (header_type & 0x7f) {
case PCI_HEADER_TYPE_BRIDGE:
case PCI_HEADER_TYPE_CARDBUS:
secondary_bus = pci_config_read8(pci_addr, PCI_SECONDARY_BUS);
if (secondary_bus != 0) {
scan_pci_bus(new, secondary_bus);
}
break;
switch (header_type & 0x7f)
{
case PCI_HEADER_TYPE_BRIDGE:
case PCI_HEADER_TYPE_CARDBUS:
secondary_bus = pci_config_read8(pci_addr, PCI_SECONDARY_BUS);
if (secondary_bus != 0)
{
scan_pci_bus(new, secondary_bus);
}
break;
}
*current = new;
current = &new->next;
if ((func == 0) && ((header_type & 0x80) == 0)) {
if ((func == 0) && ((header_type & 0x80) == 0))
{
break;
}
}
{
uint16_t id;
uint32_t rcba, *fd;
id = pci_config_read16(PCIADDR(0, 0x00, 0), 0x00);
/* make sure we're on Intel chipset */
if (id != 0x8086)
void build_pci_dt(void)
{
dev_path = malloc(sizeof(char) * 256);
root_pci_dev = malloc(sizeof(pci_dt_t));
bzero(root_pci_dev, sizeof(pci_dt_t));
enable_pci_devs();
#endif
}
static char dev_path[256];
char *get_pci_dev_path(pci_dt_t *pci_dt)
{
pci_dt_t*current;
pci_dt_t*end;
chartmp[64];
dev_path[0] = 0;
end = root_pci_dev;
if (current->parent == root_pci_dev)
{
sprintf(tmp, "PciRoot(0x%x)/Pci(0x%x,0x%x)", uid,
current->dev.bits.dev, current->dev.bits.func);
} else {
current->dev.bits.dev, current->dev.bits.func);
}
else
{
sprintf(tmp, "/Pci(0x%x,0x%x)",
current->dev.bits.dev, current->dev.bits.func);
current->dev.bits.dev, current->dev.bits.func);
}
strcat(dev_path, tmp);
}
return dev_path;
}
#if DEBUG_PCI
void dump_pci_dt(pci_dt_t *pci_dt)
{
pci_dt_t*current;
current = pci_dt;
while (current) {
while (current)
{
printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n",
current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func,
current->class_id, current->vendor_id, current->device_id,
get_pci_dev_path(current));
current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func,
current->class_id, current->vendor_id, current->device_id,
get_pci_dev_path(current));
dump_pci_dt(current->children);
current = current->next;
}
}
#endif

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Revision: 546