Chameleon

Chameleon Commit Details

Date:2010-12-16 09:23:37 (9 years 6 months ago)
Author:Kabyl
Commit:672
Parents: 671
Message:Added new ATi/AMD Graphics Card Enabler
Changes:
A/branches/Kabyl/i386/libsaio/ati_reg.h
M/branches/Kabyl/i386/libsaio/ati.c
M/branches/Kabyl/i386/libsaio/pci.h
M/branches/Kabyl/i386/libsaio/memvendors.h
M/branches/Kabyl/i386/libsaio/spd.c
M/branches/Kabyl/i386/libsaio/platform.h
M/branches/Kabyl/i386/libsaio/nvidia.c
M/branches/Kabyl/i386/boot2/boot.h
M/branches/Kabyl/i386/libsaio/pci_setup.c

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branches/Kabyl/i386/libsaio/spd.c
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#define SMBHSTADD 4␊
#define SMBHSTDAT 5␊
#define SBMBLKDAT 7␊
#if 0␊
/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
{␊
int l1, h1, l2, h2;␊
unsigned long long t;␊
␉␊
#define Reg32(reg)␉␉␉␉␉(*(volatile uint32_t *)(base + reg))␊
#define RegRead32(reg)␉␉␉␉(Reg32(reg))␊
#define RegWrite32(reg, value)␉␉(Reg32(reg) = value)␊
␊
RegWrite32(SMBHSTSTS, 0x1f);␉␉␉␉␉// reset SMBus Controller␊
RegWrite32(SMBHSTDAT, 0xff);␊
␉␊
while(RegRead32(SMBHSTSTS) & 0x01);␉␉␉// wait until ready␊
␉␊
RegWrite32(SMBHSTCMD, cmd);␊
RegWrite32(SMBHSTADD, (adr << 1) | 0x01 );␊
RegWrite32(SMBHSTCNT, 0x48 );␊
␉␊
rdtsc(l1, h1);␊
␉␊
␉while (!( RegRead32(SMBHSTSTS) & 0x02))␉␉// wait til command finished␊
␉{␉␊
␉␉rdtsc(l2, h2);␊
␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
␉␉if (t > 5)␊
␉␉␉break;␉␉␉␉␉␉␉␉␉// break after 5ms␊
}␊
return RegRead32(SMBHSTDAT);␊
}␊
#endif␊
//#if 0␊
/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
{␊
}␊
return inb(base + SMBHSTDAT);␊
}␊
//#endif␊
␊
/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊
#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊
{ ␊
int i, speed;␊
uint8_t spd_size, spd_type;␊
uint32_t base;␊
uint32_t base, mmio, hostc;␊
bool dump = false;␊
RamSlotInfo_t* slot;␊
␊
␉uint16_t cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);␊
␉DBG("SMBus CmdReg: 0x%x\n", cmd);␊
␉pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);␊
␊
␉mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;␊
base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
DBG("Scanning smbus_dev <%04x, %04x> ...\n",smbus_dev->vendor_id, smbus_dev->device_id);␊
␉hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);␊
verbose("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n", ␊
␉␉smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);␊
␊
getBoolForKey("DumpSPD", &dump, &bootInfo->bootConfig);␊
bool fullBanks = // needed at least for laptops␊
␉␉Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots;␊
␉// needed at least for laptops␊
bool fullBanks = Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots;␊
␊
␉char spdbuf[MAX_SPD_SIZE];␊
// Search MAX_RAM_SLOTS slots␊
for (i = 0; i < MAX_RAM_SLOTS; i++){␊
slot = &Platform.RAM.DIMM[i];␊
spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
␉␉DBG("SPD[0] (size): %d @0x%x\n", spd_size, 0x50 + i);␊
// Check spd is present␊
if (spd_size && (spd_size != 0xff) ) {␊
if (spd_size && (spd_size != 0xff))␊
{␊
␊
␉␉␉slot->spd = spdbuf;␊
slot->InUse = true;␊
␊
␉␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
init_spd(slot->spd, base, i);␊
␉␉␉␊
␉␉␊
switch (slot->spd[SPD_MEMORY_TYPE]) {␊
case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
␊
␉␉␉␉}␊
␉␉␉␉slot->Frequency = freq;␊
␉␉␉}␊
␉␉␉␊
␊
␉␉␉verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n", ␊
i, ␊
(int)slot->Type,␊
slot->Vendor,␊
slot->PartNo,␊
slot->SerialNo); ␊
␊
#if DEBUG_SPD␊
dumpPhysAddr("spd content: ",slot->spd, spd_size);␊
dumpPhysAddr("spd content: ", slot->spd, spd_size);␊
getc();␊
#endif␊
}␊
{␊
find_and_read_smbus_controller(root_pci_dev);␊
}␊
␊
branches/Kabyl/i386/libsaio/memvendors.h
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} VenIdName;␊
␊
VenIdName vendorMap[] = {␊
{ 0, 0x01, "AMD"},␊
␉␉{ 0, 0x01, "AMD"},␊
␉␉{ 0, 0x02, "AMI"},␊
␉␉{ 0, 0x83, "Fairchild"},␊
␉␉{ 0, 0x04, "Fujitsu"},␊
branches/Kabyl/i386/libsaio/nvidia.c
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{␊
␉struct DevPropDevice␉␉*device;␊
␉char␉␉␉␉␉␉*devicepath;␊
␉struct pci_rom_pci_header_t␉*rom_pci_header;␉␊
␉option_rom_pci_header_t␉␉*rom_pci_header;␉␊
␉volatile uint8_t␉*regs;␊
␉uint8_t␉␉␉␉*rom;␊
␉uint8_t␉␉␉␉*nvRom;␊
␉␉}␊
␉}␊
␊
␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
/*␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
␉␉return false;␊
␉}␊
*/␊
␉rom_pci_header = (option_rom_pci_header_t *)(rom + *(uint16_t *)&rom[24]);␊
␊
␉rom_pci_header = (struct pci_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
␊
␉// check for 'PCIR' sig␊
␉if (rom_pci_header->signature == 0x50434952) {␊
␉␉if (rom_pci_header->device != nvda_dev->device_id) {␊
␉if (rom_pci_header->signature == 0x53454550)//0x52494350)␊
␉␉if (rom_pci_header->device_id != nvda_dev->device_id)␊
␉␉␉// Get Model from the OpROM␊
␉␉␉model = get_nvidia_model((rom_pci_header->vendor << 16) | rom_pci_header->device);␊
␉␉} else {␊
␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
␉␉}␊
␉}␊
␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊
␉else␊
␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
␊
␉if (!string) {␊
␉if (!string)␊
␉␉string = devprop_create_string();␊
␉}␊
␊
␉device = devprop_add_device(string, devicepath);␊
␊
␉/* FIXME: for primary graphics card only */␊
␉␉}␊
␉}␊
␊
#if DEBUG_NVCAP␊
#if DEBUG_NVCAP␊
printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
␉␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
␉␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
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/*␊
* ATI injector␊
* ATI Graphics Card Enabler, part of the Chameleon Boot Loader Project␊
*␊
* Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas␊
* Copyright 2010 by Islam M. Ahmed Zaid. All rights reserved.␊
*␊
* ATI injector is free software: you can redistribute it and/or modify␊
* it under the terms of the GNU General Public License as published by␊
* the Free Software Foundation, either version 3 of the License, or␊
* (at your option) any later version.␊
*␊
* ATI driver and injector is distributed in the hope that it will be useful,␊
* but WITHOUT ANY WARRANTY; without even the implied warranty of␊
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
* GNU General Public License for more details.␊
*␊
* You should have received a copy of the GNU General Public License␊
* along with ATI injector. If not, see <http://www.gnu.org/licenses/>.␊
*/ ␊
/*␊
* Alternatively you can choose to comply with APSL␊
*/␊
␊
␊
␊
␊
#include "libsaio.h"␊
#include "boot.h"␊
#include "bootstruct.h"␊
#include "pci.h"␊
#include "platform.h"␊
#include "device_inject.h"␊
#include "ati.h"␊
␊
#ifndef DEBUG_ATI␊
#define DEBUG_ATI 0␊
#endif␊
#include "ati_reg.h"␊
␊
#if DEBUG_ATI␊
#define DBG(x...)␉printf(x)␊
#else␊
#define DBG(x...)␊
#endif␊
#define Reg32(reg)␉␉␉␉␉(*(volatile uint32_t *)(card->mmio + reg))␊
#define RegRead32(reg)␉␉␉␉(Reg32(reg))␊
#define RegWrite32(reg, value)␉␉(Reg32(reg) = value)␊
␊
#define MAX_NUM_DCB_ENTRIES 16␊
typedef enum {␊
␉kNul,␊
␉kStr,␊
␉kPtr,␊
␉kCst␊
} type_t;␊
␊
#define TYPE_GROUPED 0xff␊
typedef enum {␊
␉CHIP_FAMILY_UNKNOW,␊
␉CHIP_FAMILY_RS600,␊
␉CHIP_FAMILY_RS690,␊
␉CHIP_FAMILY_RS740,␊
␉CHIP_FAMILY_R600,␉/* r600 */␊
␉CHIP_FAMILY_RV610,␊
␉CHIP_FAMILY_RV630,␊
␉CHIP_FAMILY_RV670,␊
␉CHIP_FAMILY_RV620,␊
␉CHIP_FAMILY_RV635,␊
␉CHIP_FAMILY_RS780,␊
␉CHIP_FAMILY_RS880,␊
␉CHIP_FAMILY_RV770, /* r700 */␊
␉CHIP_FAMILY_RV730,␊
␉CHIP_FAMILY_RV710,␊
␉CHIP_FAMILY_RV740,␊
␉CHIP_FAMILY_CEDAR, /* evergreen */␊
␉CHIP_FAMILY_REDWOOD,␊
␉CHIP_FAMILY_JUNIPER,␊
␉CHIP_FAMILY_CYPRESS,␊
␉CHIP_FAMILY_HEMLOCK,␊
␉CHIP_FAMILY_LAST␊
} chip_family_t;␊
␊
extern uint32_t devices_number;␊
static const char *chip_family_name[] = {␊
␉"UNKNOW",␊
␉"RS600",␊
␉"RS690",␊
␉"RS740",␊
␉/* r600 */␊
␉"R600",␊
␉"RV610",␊
␉"RV630",␊
␉"RV670",␊
␉"RV620",␊
␉"RV635",␊
␉"RS780",␊
␉"RS880",␊
␉/* r700 */␊
␉"RV770",␊
␉"RV730",␊
␉"RV710",␊
␉"RV740",␊
␉/* evergreen */␊
␉"Cedar",␉// RV810␊
␉"Redwood",␉// RV830␊
␉"Juniper",␉// RV840␊
␉"Cypress",␉// RV870␊
␉"Hemlock",␉␊
};␊
␊
const char *ati_compatible_0[]␉␉␉= { "@0,compatible", "ATY,%s" };␊
const char *ati_compatible_1[]␉␉␉= { "@1,compatible", "ATY,%s" };␊
const char *ati_device_type_0[]␉␉␉= { "@0,device_type", "display" };␊
const char *ati_device_type_1[]␉␉␉= { "@1,device_type", "display" };␊
const char *ati_device_type[]␉␉␉= { "device_type", "ATY,%sParent" };␊
const char *ati_name_0[]␉␉␉= { "@0,name", "ATY,%s" };␊
const char *ati_name_1[]␉␉␉= { "@1,name", "ATY,%s" };␊
const char *ati_name[]␉␉␉␉= { "name", "ATY,%sParent" };␊
const char *ati_efidisplay_0[]␉␉␉= { "@0,ATY,EFIDisplay", "TMDSB" };␊
struct ati_data_key ati_connector_type_0␉= { 0x04, "@0,connector-type", {0x00, 0x04, 0x00, 0x00} };␊
struct ati_data_key ati_connector_type_1␉= { 0x04, "@1,connector-type", {0x04, 0x00, 0x00, 0x00} };␊
struct ati_data_key ati_display_con_fl_type_0␉= { 0x04, "@0,display-connect-flags", {0x00, 0x00, 0x04, 0x00} };␊
const char *ati_display_type_0[]␉␉= { "@0,display-type", "LCD" };␊
const char *ati_display_type_1[]␉␉= { "@1,display-type", "NONE" };␊
struct ati_data_key ati_aux_power_conn␉␉= { 0x04, "AAPL,aux-power-connected", {0x01, 0x00, 0x00, 0x00} };␊
struct ati_data_key ati_backlight_ctrl␉␉= { 0x04, "AAPL,backlight-control", {0x00, 0x00, 0x00, 0x00} };␊
struct ati_data_key ati_aapl01_coher␉␉= { 0x04, "AAPL01,Coherency", {0x01, 0x00, 0x00, 0x00} };␊
const char *ati_card_no[]␉␉␉= { "ATY,Card#", "109-B77101-00" };␊
const char *ati_copyright[]␉␉␉= { "ATY,Copyright", "Copyright AMD Inc. All Rights Reserved. 2005-2009" };␊
const char *ati_efi_compile_d[]␉␉␉= { "ATY,EFICompileDate", "Jan 26 2009" };␊
struct ati_data_key ati_efi_disp_conf␉␉= { 0x08, "ATY,EFIDispConfig", {0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} };␊
struct ati_data_key ati_efi_drv_type␉␉= { 0x01, "ATY,EFIDriverType", {0x02} };␊
struct ati_data_key ati_efi_enbl_mode␉␉= { 0x01, "ATY,EFIEnabledMode", {0x01} };␊
struct ati_data_key ati_efi_init_stat␉␉= { 0x04, "ATY,EFIHWInitStatus", {0x00, 0x00, 0x00, 0x00} };␊
struct ati_data_key ati_efi_orientation␉␉= { 0x02, "ATY,EFIOrientation", {0x02, 0x00} };␊
const char *ati_efi_version[]␉␉␉= { "ATY,EFIVersion", "01.00.318" };␊
const char *ati_efi_versionB[]␉␉␉= { "ATY,EFIVersionB", "113-SBSJ1G04-00R-02" };␊
const char *ati_efi_versionE[]␉␉␉= { "ATY,EFIVersionE", "113-B7710A-318" };␊
struct ati_data_key ati_mclk␉␉␉= { 0x04, "ATY,MCLK", {0x70, 0x2e, 0x11, 0x00} };␊
struct ati_data_key ati_mem_rev_id␉␉= { 0x02, "ATY,MemRevisionID", {0x03, 0x00} };␊
struct ati_data_key ati_mem_vend_id␉␉= { 0x02, "ATY,MemVendorID", {0x02, 0x00} };␊
const char *ati_mrt[]␉␉␉␉= { "ATY,MRT", " " };␊
const char *ati_romno[]␉␉␉␉= { "ATY,Rom#", "113-B7710C-176" };␊
struct ati_data_key ati_sclk␉␉␉= { 0x04, "ATY,SCLK", {0x28, 0xdb, 0x0b, 0x00} };␊
struct ati_data_key ati_vendor_id␉␉= { 0x02, "ATY,VendorID", {0x02, 0x10} };␊
struct ati_data_key ati_platform_info␉␉= { 0x80, "ATY,PlatformInfo", {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };␊
struct ati_data_key ati_mvad␉␉␉= { 0x40, "MVAD", {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, 0x92, 0x20, 0x00, 0x03} };␊
struct ati_data_key ati_saved_config␉␉= { 0x100, "saved-config", {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, 0x92, 0x20, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xee, 0x02, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };␊
///non 48xx keys␊
const char *ati_efidisplay_0_n4[]␉␉= { "@0,ATY,EFIDisplay", "TMDSA" };␊
struct ati_data_key ati_connector_type_0_n4␉= { 0x04, "@0,connector-type", {0x04, 0x00, 0x00, 0x00} };␊
struct ati_data_key ati_connector_type_1_n4␉= { 0x04, "@1,connector-type", {0x00, 0x02, 0x00, 0x00} };␊
struct ati_data_key ati_aapl_emc_disp_list_n4␉= { 0x40, "AAPL,EMC-Display-List", {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x1b, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x1c, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x21, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };␊
struct ati_data_key ati_fb_offset_n4␉␉= { 0x08, "ATY,FrameBufferOffset", {0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00} };␊
struct ati_data_key ati_hwgpio_n4␉␉= { 0x04, "ATY,HWGPIO", {0x23, 0xa8, 0x48, 0x00} };␊
struct ati_data_key ati_iospace_offset_n4␉= { 0x08, "ATY,IOSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00} };␊
struct ati_data_key ati_mclk_n4␉␉␉= { 0x04, "ATY,MCLK", {0x00, 0x35, 0x0c, 0x00} };␊
struct ati_data_key ati_sclk_n4␉␉␉= { 0x04, "ATY,SCLK", {0x60, 0xae, 0x0a, 0x00} };␊
struct ati_data_key ati_refclk_n4␉␉= { 0x04, "ATY,RefCLK", {0x8c, 0x0a, 0x00, 0x00} };␊
struct ati_data_key ati_regspace_offset_n4␉= { 0x08, "ATY,RegisterSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x90, 0xa2, 0x00, 0x00} };␊
struct ati_data_key ati_vram_memsize_0␉␉= { 0x08, "@0,VRAM,memsize", {0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00} };␊
struct ati_data_key ati_vram_memsize_1␉␉= { 0x08, "@1,VRAM,memsize", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };␊
struct ati_data_key ati_aapl_blackscr_prefs_0_n4= { 0x04, "AAPL00,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} };␊
struct ati_data_key ati_aapl_blackscr_prefs_1_n4= { 0x04, "AAPL01,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} };␊
struct ati_data_key ati_swgpio_info_n4␉␉= { 0x04, "ATY,SWGPIO Info", {0x00, 0x48, 0xa8, 0x23} };␊
struct ati_data_key ati_efi_orientation_n4␉= { 0x01, "ATY,EFIOrientation", {0x08} };␊
struct ati_data_key ati_mvad_n4␉␉␉= { 0x100, "MVAD", {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };␊
struct ati_data_key ati_saved_config_n4␉␉= { 0x100, "saved-config", {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };␊
typedef struct {␊
␉const char␉␉*name;␊
␉uint8_t␉␉␉ports;␊
} card_config_t;␊
␊
struct pcir_s {␊
␉uint32_t signature;␊
␉uint16_t vid;␊
␉uint16_t devid;␊
static card_config_t card_configs[] = {␊
␉{NULL,␉␉␉0},␊
␉{"Alopias",␉␉2},␊
␉{"Alouatta",␉4},␊
␉{"Baboon",␉␉3},␊
␉{"Cardinal",␉2},␊
␉{"Caretta",␉␉1},␊
␉{"Colobus",␉␉2},␊
␉{"Douc",␉␉2},␊
␉{"Eulemur",␉␉3},␊
␉{"Flicker",␉␉3},␊
␉{"Galago",␉␉2},␊
␉{"Gliff",␉␉3},␊
␉{"Hoolock",␉␉3},␊
␉{"Hypoprion",␉2},␊
␉{"Iago",␉␉2},␊
␉{"Kakapo",␉␉3},␊
␉{"Kipunji",␉␉4},␊
␉{"Lamna",␉␉2},␊
␉{"Langur",␉␉3},␊
␉{"Megalodon",␉3},␊
␉{"Motmot",␉␉2},␊
␉{"Peregrine",␉2},␊
␉{"Quail",␉␉3},␊
␉{"Raven",␉␉3},␊
␉{"Shrike",␉␉3},␊
␉{"Sphyrna",␉␉1},␊
␉{"Triakis",␉␉2},␊
␉{"Uakari",␉␉4},␊
␉{"Vervet",␉␉4},␊
␉{"Zonalis",␉␉6}␊
};␊
␊
// Known cards as of 2008/08/26␊
static struct ati_chipsets_t ATIKnownChipsets[] = {␊
␉{ 0x00000000, "Unknown" } ,␊
␉{ 0x10029589, "ATI Radeon 2600 Series"} ,␊
␉{ 0x10029588, "ATI Radeon 2600 Series"} ,␊
␉{ 0x100294C3, "ATI Radeon 2400 Series"} ,␊
␉{ 0x100294C4, "ATI Radeon 2400 Series"} ,␊
␉{ 0x100294C6, "ATI Radeon 2400 Series"} ,␊
␉{ 0x10029400, "ATI Radeon 2900 Series"} ,␊
␉{ 0x10029405, "ATI Radeon 2900GT Series"} ,␊
␉{ 0x10029581, "ATI Radeon 2600 Series"} ,␊
␉{ 0x10029583, "ATI Radeon 2600 Series"} ,␊
␉{ 0x10029586, "ATI Radeon 2600 Series"} ,␊
␉{ 0x10029587, "ATI Radeon 2600 Series"} ,␊
␉{ 0x100294C9, "ATI Radeon 2400 Series"} ,␊
␉{ 0x10029501, "ATI Radeon 3800 Series"} ,␊
␉{ 0x10029505, "ATI Radeon 3800 Series"} ,␊
␉{ 0x10029515, "ATI Radeon 3800 Series"} ,␊
␉{ 0x10029507, "ATI Radeon 3800 Series"} ,␊
␉{ 0x10029500, "ATI Radeon 3800 Series"} ,␊
␉{ 0x1002950F, "ATI Radeon 3800X2 Series"} ,␊
␉{ 0x100295C5, "ATI Radeon 3400 Series"} ,␊
␉{ 0x100295C7, "ATI Radeon 3400 Series"} ,␊
␉{ 0x100295C0, "ATI Radeon 3400 Series"} ,␊
␉{ 0x10029596, "ATI Radeon 3600 Series"} ,␊
␉{ 0x10029590, "ATI Radeon 3600 Series"} ,␊
␉{ 0x10029599, "ATI Radeon 3600 Series"} ,␊
␉{ 0x10029597, "ATI Radeon 3600 Series"} ,␊
␉{ 0x10029598, "ATI Radeon 3600 Series"} ,␊
␉{ 0x10029442, "ATI Radeon 4850 Series"} ,␊
␉{ 0x10029440, "ATI Radeon 4870 Series"} ,␊
␉{ 0x1002944C, "ATI Radeon 4830 Series"} ,␊
␉{ 0x10029460, "ATI Radeon 4890 Series"} ,␊
␉{ 0x10029462, "ATI Radeon 4890 Series"} ,␊
␉{ 0x10029441, "ATI Radeon 4870X2 Series"} ,␊
␉{ 0x10029443, "ATI Radeon 4850X2 Series"} ,␊
␉{ 0x10029444, "ATI Radeon 4800 Series"} ,␊
␉{ 0x10029446, "ATI Radeon 4800 Series"} ,␊
␉{ 0x1002944E, "ATI Radeon 4730 Series"} ,␊
␉{ 0x10029450, "ATI Radeon 4800 Series"} ,␊
␉{ 0x10029452, "ATI Radeon 4800 Series"} ,␉␉␊
␉{ 0x10029456, "ATI Radeon 4800 Series"} ,␉␉␊
␉{ 0x1002944A, "ATI Radeon 4800 Mobility Series"} ,␊
␉{ 0x1002945A, "ATI Radeon 4800 Mobility Series"} ,␊
␉{ 0x1002945B, "ATI Radeon 4800 Mobility Series"} ,␊
␉{ 0x1002944B, "ATI Radeon 4800 Mobility Series"} ,␊
{ 0x10029490, "ATI Radeon 4670 Series"} ,␊
{ 0x10029498, "ATI Radeon 4650 Series"} ,␊
␉{ 0x10029490, "ATI Radeon 4600 Series"} ,␊
␉{ 0x10029498, "ATI Radeon 4600 Series"} ,␊
␉{ 0x1002949E, "ATI Radeon 4600 Series"} ,␊
␉{ 0x10029480, "ATI Radeon 4600 Series"} ,␊
␉{ 0x10029488, "ATI Radeon 4600 Series"} ,␊
␉{ 0x10029540, "ATI Radeon 4500 Series"} ,␊
␉{ 0x10029541, "ATI Radeon 4500 Series"} ,␊
␉{ 0x1002954E, "ATI Radeon 4500 Series"} ,␊
␉{ 0x10029552, "ATI Radeon 4300 Mobility Series"} ,␊
␉{ 0x10029553, "ATI Radeon 4500 Mobility Series"} ,␊
␉{ 0x1002954F, "ATI Radeon 4300 Series"} ,␊
{ 0x100294B3, "ATI Radeon 4770 Series"} ,␊
{ 0x100294B5, "ATI Radeon 4770 Series"} ,␊
{ 0x100268B8, "ATI Radeon 5700 Series"} ,␊
{ 0x100268BE, "ATI Radeon 5700 Series"} ,␊
{ 0x10026898, "ATI Radeon 5800 Series"} ,␊
{ 0x10026899, "ATI Radeon 5800 Series"}␊
typedef enum {␊
␉kNull,␊
␉kAlopias,␊
␉kAlouatta,␊
␉kBaboon,␊
␉kCardinal,␊
␉kCaretta,␊
␉kColobus,␊
␉kDouc,␊
␉kEulemur,␊
␉kFlicker,␊
␉kGalago,␊
␉kGliff,␊
␉kHoolock,␊
␉kHypoprion,␊
␉kIago,␊
␉kKakapo,␊
␉kKipunji,␊
␉kLamna,␊
␉kLangur,␊
␉kMegalodon,␊
␉kMotmot,␊
␉kPeregrine,␊
␉kQuail,␊
␉kRaven,␊
␉kShrike,␊
␉kSphyrna,␊
␉kTriakis,␊
␉kUakari,␊
␉kVervet,␊
␉kZonalis,␊
␉kCfgEnd␊
} config_name_t;␊
␊
typedef struct {␊
␉uint16_t␉␉device_id;␊
␉uint32_t␉␉subsys_id;␊
␉chip_family_t␉chip_family;␊
␉const char␉␉*model_name;␊
␉config_name_t␉cfg_name;␊
} radeon_card_info_t;␊
␊
static radeon_card_info_t radeon_cards[] = {␊
␉/* Earlier cards are not supported */␊
␉{ 0x9400,␉0x30001002,␉CHIP_FAMILY_R600,␉␉"ATI Radeon HD 2900 PRO",␉␉␉kNull␉␉},␊
␉{ 0x9400,␉0x25521002,␉CHIP_FAMILY_R600,␉␉"ATI Radeon HD 2900 XT",␉␉␉kNull␉␉},␊
␊
␉{ 0x9440,␉0x24401682,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4870",␉␉␉␉kMotmot␉␉},␊
␉{ 0x9440,␉0x24411682,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4870",␉␉␉␉kMotmot␉␉},␊
␉{ 0x9440,␉0x24441682,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4870",␉␉␉␉kMotmot␉␉},␊
␉{ 0x9440,␉0x24451682,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4870",␉␉␉␉kMotmot␉␉},␊
␊
␉{ 0x9441,␉0x24401682,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4870 X2",␉␉␉kMotmot␉␉},␊
␊
␉{ 0x9442,␉0x24701682,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4850",␉␉␉␉kMotmot␉␉},␊
␉{ 0x9442,␉0x24711682,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4850",␉␉␉␉kMotmot␉␉},␊
␉{ 0x9442,␉0x080110B0,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4850",␉␉␉␉kMotmot␉␉},␊
␉{ 0x9442,␉0xE104174B,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4850",␉␉␉␉kMotmot␉␉},␊
␊
␉{ 0x944A,␉0x30001682,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4800 Series",␉␉kMotmot␉␉},␊
␉{ 0x944A,␉0x30001043,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4800 Series",␉␉kMotmot␉␉},␊
␉{ 0x944A,␉0x30001458,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4800 Series",␉␉kMotmot␉␉},␊
␉{ 0x944A,␉0x30001462,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4800 Series",␉␉kMotmot␉␉},␊
␉{ 0x944A,␉0x30001545,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4800 Series",␉␉kMotmot␉␉},␊
␉{ 0x944A,␉0x30001787,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4800 Series",␉␉kMotmot␉␉},␊
␉{ 0x944A,␉0x3000174B,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4800 Series",␉␉kMotmot␉␉},␊
␉{ 0x944A,␉0x300017AF,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4800 Series",␉␉kMotmot␉␉},␊
␊
␉{ 0x944C,␉0x24801682,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4830",␉␉␉␉kMotmot␉␉},␊
␉{ 0x944C,␉0x24811682,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4830",␉␉␉␉kMotmot␉␉},␊
␊
␉{ 0x944E,␉0x3260174B,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4810 Series",␉␉kMotmot␉␉},␊
␉{ 0x944E,␉0x3261174B,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4810 series",␉␉kMotmot␉␉},␊
␉{ 0x944E,␉0x30001787,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4730 Series",␉␉kMotmot␉␉},␊
␉{ 0x944E,␉0x30101787,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4810 Series",␉␉kMotmot␉␉},␊
␉{ 0x944E,␉0x31001787,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4820",␉␉␉␉kMotmot␉␉},␊
␊
␉{ 0x9490,␉0x30501787,␉CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4710",␉␉␉␉kNull␉␉},␊
␉{ 0x9490,␉0x4710174B,␉CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4710",␉␉␉␉kNull␉␉},␊
␉{ 0x9490,␉0x300017AF,␉CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4710",␉␉␉␉kNull␉␉},␊
␊
␉{ 0x9498,␉0x30501787,␉CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4700",␉␉␉␉kNull␉␉},␊
␉{ 0x9498,␉0x31001787,␉CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4720",␉␉␉␉kNull␉␉},␊
␉{ 0x9498,␉0x24511682,␉CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4650",␉␉␉␉kNull␉␉},␊
␉{ 0x9498,␉0x24521682,␉CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4650",␉␉␉␉kNull␉␉},␊
␉{ 0x9498,␉0x24541682,␉CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4650",␉␉␉␉kNull␉␉},␊
␉{ 0x9498,␉0x29331682,␉CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4670",␉␉␉␉kNull␉␉},␊
␉{ 0x9498,␉0x29341682,␉CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4670",␉␉␉␉kNull␉␉},␊
␉{ 0x9498,␉0x21CF1458,␉CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4600 Series",␉␉kNull␉␉},␊
␊
␉{ 0x94B3,␉0x29001682,␉CHIP_FAMILY_RV740,␉␉"ATI Radeon HD 4770",␉␉␉␉kFlicker␉},␊
␉{ 0x94B3,␉0x1170174B,␉CHIP_FAMILY_RV740,␉␉"ATI Radeon HD 4770",␉␉␉␉kFlicker␉},␊
␉{ 0x94B3,␉0x10020D00,␉CHIP_FAMILY_RV740,␉␉"ATI Radeon HD 4770",␉␉␉␉kFlicker␉},␊
␊
␉{ 0x94C1,␉0x10021002,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 Pro",␉␉␉kNull␉␉},␊
␉{ 0x94C1,␉0x0D021002,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 XT",␉␉␉kNull␉␉},␊
␉{ 0x94C1,␉0x0D021028,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 Pro",␉␉␉kNull␉␉},␊
␉{ 0x94C1,␉0x0D021028,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 XT",␉␉␉kNull␉␉},␊
␉{ 0x94C1,␉0x21741458,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 XT",␉␉␉kNull␉␉},␊
␉{ 0x94C1,␉0x10401462,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 XT",␉␉␉kNull␉␉},␊
␉{ 0x94C1,␉0x10331462,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 XT",␉␉␉kNull␉␉},␊
␉{ 0x94C1,␉0x10331462,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 XT",␉␉␉kNull␉␉},␊
␉{ 0x94C1,␉0x11101462,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 XT",␉␉␉kNull␉␉},␊
␊
␉{ 0x94C3,␉0x37161642,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 PRO",␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x30001642,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 3410",␉␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x03421002,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 PRO",␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x30001025,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2350 Series",␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x04021028,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400",␉␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x03021028,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 PRO",␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x04021028,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 PRO",␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x216A1458,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 PRO",␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x21721458,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 PRO",␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x30001458,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 3410",␉␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x11041462,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400",␉␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x10411462,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400",␉␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x11051462,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400",␉␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x10321462,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 PRO",␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x30001462,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 3410",␉␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x3000148C,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2350 Series",␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x2247148C,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 LE",␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x3000174B,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2350 Series",␉␉kNull␉␉},␊
␉{ 0x94C3,␉0xE400174B,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 PRO",␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0xE370174B,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 PRO",␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0xE400174B,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 PRO",␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0xE370174B,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 PRO",␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0xE400174B,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 PRO",␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x203817AF,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400",␉␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x30001787,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2350 Series",␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x22471787,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 LE",␉␉␉kNull␉␉},␊
␉{ 0x94C3,␉0x01011A93,␉CHIP_FAMILY_RV610,␉␉"Qimonda Radeon HD 2400 PRO",␉␉kNull␉␉},␊
␊
␊
␉{ 0x9501,␉0x30001002,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 3690",␉␉␉␉kNull␉␉},␊
␉{ 0x9501,␉0x25421002,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 3870",␉␉␉␉kNull␉␉},␊
␉{ 0x9501,␉0x4750174B,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 4750",␉␉␉␉kNull␉␉},␊
␉{ 0x9501,␉0x3000174B,␉CHIP_FAMILY_RV670,␉␉"Sapphire Radeon HD 3690",␉␉␉kNull␉␉},␊
␉{ 0x9501,␉0x30001787,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 3690",␉␉␉␉kNull␉␉},␊
␊
␉{ 0x9505,␉0x30001002,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 3690",␉␉␉␉kNull␉␉},␊
␉{ 0x9505,␉0x25421002,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 3850",␉␉␉␉kNull␉␉},␊
␉{ 0x9505,␉0x30011043,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 4730",␉␉␉␉kNull␉␉},␊
␉{ 0x9505,␉0x3000148C,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 3850",␉␉␉␉kNull␉␉},␊
␉{ 0x9505,␉0x3002148C,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 4730",␉␉␉␉kNull␉␉},␊
␉{ 0x9505,␉0x3001148C,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 4730",␉␉␉␉kNull␉␉},␊
␉{ 0x9505,␉0x3003148C,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 4750",␉␉␉␉kNull␉␉},␊
␉{ 0x9505,␉0x3004148C,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 4750",␉␉␉␉kNull␉␉},␊
␉{ 0x9505,␉0x4730174B,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 4730",␉␉␉␉kNull␉␉},␊
␉{ 0x9505,␉0x3010174B,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 4750",␉␉␉␉kNull␉␉},␊
␉{ 0x9505,␉0x3001174B,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 4750",␉␉␉␉kNull␉␉},␊
␉{ 0x9505,␉0x3000174B,␉CHIP_FAMILY_RV670,␉␉"Sapphire Radeon HD 3690",␉␉␉kNull␉␉},␊
␉{ 0x9505,␉0x30001787,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 3690",␉␉␉␉kNull␉␉},␊
␉{ 0x9505,␉0x301017AF,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 4750",␉␉␉␉kNull␉␉},␊
␊
␉{ 0x9540,␉0x4590174B,␉CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4590",␉␉␉␉kNull␉␉},␊
␉{ 0x9540,␉0x30501787,␉CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4590",␉␉␉␉kNull␉␉},␊
␊
␉{ 0x954F,␉0x29201682,␉CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4550",␉␉␉␉kNull␉␉},␊
␉{ 0x954F,␉0x29211682,␉CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4550",␉␉␉␉kNull␉␉},␊
␉{ 0x954F,␉0x30901682,␉CHIP_FAMILY_RV710,␉␉"XFX Radeon HD 4570",␉␉␉␉kNull␉␉},␊
␉{ 0x954F,␉0x4450174B,␉CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4450",␉␉␉␉kNull␉␉},␊
␉{ 0x954F,␉0x3000174B,␉CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4520",␉␉␉␉kNull␉␉},␊
␉{ 0x954F,␉0x30501787,␉CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4450",␉␉␉␉kNull␉␉},␊
␉{ 0x954F,␉0x31001787,␉CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4520",␉␉␉␉kNull␉␉},␊
␉{ 0x954F,␉0x4570174B,␉CHIP_FAMILY_RV710,␉␉"Sapphire Radeon HD4570",␉␉␉kNull␉␉},␊
␉{ 0x954F,␉0x301017AF,␉CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4450",␉␉␉␉kNull␉␉},␊
␊
␉{ 0x9552,␉0x3000148C,␉CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4300/4500 Series",␉kNull␉␉},␊
␉{ 0x9552,␉0x3000174B,␉CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4300/4500 Series",␉kNull␉␉},␊
␉{ 0x9552,␉0x30001787,␉CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4300/4500 Series",␉kNull␉␉},␊
␉{ 0x9552,␉0x300017AF,␉CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4300/4500 Series",␉kNull␉␉},␊
␊
␉{ 0x9581,␉0x95811002,␉CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 3600 Series",␉␉kNull␉␉},␊
␉{ 0x9581,␉0x3000148C,␉CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 3600 Series",␉␉kNull␉␉},␊
␊
␉{ 0x9583,␉0x3000148C,␉CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 3600 Series",␉␉kNull␉␉},␊
␉{ 0x9588,␉0x01021A93,␉CHIP_FAMILY_RV630,␉␉"Qimonda Radeon HD 2600 XT",␉␉kNull␉␉},␊
␊
␉{ 0x9589,␉0x30001462,␉CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 3610",␉␉␉␉kNull␉␉},␊
␉{ 0x9589,␉0x30001642,␉CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 3610",␉␉␉␉kNull␉␉},␊
␉{ 0x9589,␉0x0E41174B,␉CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 3600 Series",␉␉kNull␉␉},␊
␉{ 0x9589,␉0x30001787,␉CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 3600 Series",␉␉kNull␉␉},␊
␉{ 0x9589,␉0x01001A93,␉CHIP_FAMILY_RV630,␉␉"Qimonda Radeon HD 2600 PRO",␉␉kNull␉␉},␊
␊
␉{ 0x9591,␉0x2303148C,␉CHIP_FAMILY_RV635,␉␉"ATI Radeon HD 3600 Series",␉␉kNull␉␉},␊
␊
␉{ 0x9598,␉0xB3831002,␉CHIP_FAMILY_RV635,␉␉"ATI All-in-Wonder HD",␉␉␉␉kNull␉␉},␊
␉{ 0x9598,␉0x30011043,␉CHIP_FAMILY_RV635,␉␉"ATI Radeon HD 4570",␉␉␉␉kNull␉␉},␊
␉{ 0x9598,␉0x30001043,␉CHIP_FAMILY_RV635,␉␉"HD3730",␉␉␉␉␉␉␉kNull␉␉},␊
␉{ 0x9598,␉0x3000148C,␉CHIP_FAMILY_RV635,␉␉"ATI Radeon HD 3730",␉␉␉␉kNull␉␉},␊
␉{ 0x9598,␉0x3031148C,␉CHIP_FAMILY_RV635,␉␉"ATI Radeon HD 4570",␉␉␉␉kNull␉␉},␊
␉{ 0x9598,␉0x3001148C,␉CHIP_FAMILY_RV635,␉␉"ATI Radeon HD 4580",␉␉␉␉kNull␉␉},␊
␉{ 0x9598,␉0x30011545,␉CHIP_FAMILY_RV635,␉␉"VisionTek Radeon HD 2600 Pro",␉␉kNull␉␉},␊
␉{ 0x9598,␉0x30001545,␉CHIP_FAMILY_RV635,␉␉"VisionTek Radeon HD 2600 XT",␉␉kNull␉␉},␊
␉{ 0x9598,␉0x4570174B,␉CHIP_FAMILY_RV635,␉␉"ATI Radeon HD 4570",␉␉␉␉kNull␉␉},␊
␉{ 0x9598,␉0x4580174B,␉CHIP_FAMILY_RV635,␉␉"ATI Radeon HD 4580",␉␉␉␉kNull␉␉},␊
␉{ 0x9598,␉0x4610174B,␉CHIP_FAMILY_RV635,␉␉"ATI Radeon HD 4610",␉␉␉␉kNull␉␉},␊
␉{ 0x9598,␉0x3000174B,␉CHIP_FAMILY_RV635,␉␉"Sapphire Radeon HD 3730",␉␉␉kNull␉␉},␊
␉{ 0x9598,␉0x3001174B,␉CHIP_FAMILY_RV635,␉␉"Sapphire Radeon HD 3750",␉␉␉kNull␉␉},␊
␉{ 0x9598,␉0x301017AF,␉CHIP_FAMILY_RV635,␉␉"ATI Radeon HD 4570",␉␉␉␉kNull␉␉},␊
␉{ 0x9598,␉0x301117AF,␉CHIP_FAMILY_RV635,␉␉"ATI Radeon HD 4580",␉␉␉␉kNull␉␉},␊
␉{ 0x9598,␉0x300117AF,␉CHIP_FAMILY_RV635,␉␉"ATI Radeon HD3750",␉␉␉␉kNull␉␉},␊
␉{ 0x9598,␉0x30501787,␉CHIP_FAMILY_RV635,␉␉"ATI Radeon HD 4610",␉␉␉␉kNull␉␉},␊
␊
␉{ 0x95C0,␉0x3000148C,␉CHIP_FAMILY_RV620,␉␉"ATI Radeon HD 3550",␉␉␉␉kNull␉␉},␊
␉{ 0x95C0,␉0xE3901745,␉CHIP_FAMILY_RV620,␉␉"ATI Radeon HD 3550",␉␉␉␉kNull␉␉},␊
␉{ 0x95C0,␉0x3002174B,␉CHIP_FAMILY_RV620,␉␉"ATI Radeon HD 3570",␉␉␉␉kNull␉␉},␊
␉{ 0x95C0,␉0x3020174B,␉CHIP_FAMILY_RV620,␉␉"ATI Radeon HD 4250",␉␉␉␉kNull␉␉},␊
␉{ 0x95C0,␉0x3000174B,␉CHIP_FAMILY_RV620,␉␉"Sapphire Radeon HD 3550",␉␉␉kNull␉␉},␊
␊
␉{ 0x95C5,␉0x3000148C,␉CHIP_FAMILY_RV620,␉␉"ATI Radeon HD 3450",␉␉␉␉kNull␉␉},␊
␉{ 0x95C5,␉0x3001148C,␉CHIP_FAMILY_RV620,␉␉"ATI Radeon HD 3550",␉␉␉␉kNull␉␉},␊
␉{ 0x95C5,␉0x3002148C,␉CHIP_FAMILY_RV620,␉␉"ATI Radeon HD 4230",␉␉␉␉kNull␉␉},␊
␉{ 0x95C5,␉0x3033148C,␉CHIP_FAMILY_RV620,␉␉"ATI Radeon HD 4230",␉␉␉␉kNull␉␉},␊
␉{ 0x95C5,␉0x3003148C,␉CHIP_FAMILY_RV620,␉␉"ATI Radeon HD 4250",␉␉␉␉kNull␉␉},␊
␉{ 0x95C5,␉0x3032148C,␉CHIP_FAMILY_RV620,␉␉"ATI Radeon HD 4250",␉␉␉␉kNull␉␉},␊
␉{ 0x95C5,␉0x3010174B,␉CHIP_FAMILY_RV620,␉␉"ATI Radeon HD 4250",␉␉␉␉kNull␉␉},␊
␉{ 0x95C5,␉0x4250174B,␉CHIP_FAMILY_RV620,␉␉"ATI Radeon HD 4250",␉␉␉␉kNull␉␉},␊
␉{ 0x95C5,␉0x30501787,␉CHIP_FAMILY_RV620,␉␉"ATI Radeon HD 4250",␉␉␉␉kNull␉␉},␊
␉{ 0x95C5,␉0x301017AF,␉CHIP_FAMILY_RV620,␉␉"ATI Radeon HD 4230",␉␉␉␉kNull␉␉},␊
␉{ 0x95C5,␉0x01051A93,␉CHIP_FAMILY_RV620,␉␉"Qimonda Radeon HD 3450",␉␉␉kNull␉␉},␊
␉{ 0x95C5,␉0x01041A93,␉CHIP_FAMILY_RV620,␉␉"Qimonda Radeon HD 3450",␉␉␉kNull␉␉},␊
␊
␉/* Evergreen */␊
␉{ 0x6898,␉0x032E1043,␉CHIP_FAMILY_CYPRESS,␉"ATI Radeon HD 5870",␉␉␉␉kUakari␉␉},␊
␉{ 0x6898,␉0xE140174B,␉CHIP_FAMILY_CYPRESS,␉"ATI Radeon HD 5870",␉␉␉␉kUakari␉␉},␊
␉{ 0x6898,␉0x0B001002,␉CHIP_FAMILY_CYPRESS,␉"ATI Radeon HD 5870",␉␉␉␉kZonalis␉},␊
␊
␉{ 0x6899,␉0x21E41458,␉CHIP_FAMILY_CYPRESS,␉"ATI Radeon HD 5850",␉␉␉␉kUakari␉␉},␊
␉{ 0x6899,␉0x200A1787,␉CHIP_FAMILY_CYPRESS,␉"ATI Radeon HD 5850",␉␉␉␉kUakari␉␉},␊
␉{ 0x6899,␉0x22901787,␉CHIP_FAMILY_CYPRESS,␉"ATI Radeon HD 5850",␉␉␉␉kUakari␉␉},␊
␉{ 0x6899,␉0xE140174B,␉CHIP_FAMILY_CYPRESS,␉"ATI Radeon HD 5850",␉␉␉␉kUakari␉␉},␊
␊
␉{ 0x689C,␉0x03521043,␉CHIP_FAMILY_HEMLOCK,␉"ASUS ARES",␉␉␉␉␉␉kUakari␉␉},␊
␉{ 0x689C,␉0x039E1043,␉CHIP_FAMILY_HEMLOCK,␉"ASUS EAH5870 Series",␉␉␉␉kUakari␉␉},␊
␉{ 0x689C,␉0x30201682,␉CHIP_FAMILY_HEMLOCK,␉"ATI Radeon HD 5970",␉␉␉␉kUakari␉␉},␊
␊
␉{ 0x68B8,␉0xE147174B,␉CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5770",␉␉␉␉kVervet␉␉},␊
␉{ 0x68B8,␉0x21D71458,␉CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5770",␉␉␉␉kVervet␉␉},␊
␉{ 0x68B8,␉0x1482174B,␉CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5770",␉␉␉␉kVervet␉␉},␊
␉{ 0x68B8,␉0x29901682,␉CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5770",␉␉␉␉kVervet␉␉},␊
␉{ 0x68B8,␉0x29911682,␉CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5770",␉␉␉␉kVervet␉␉},␊
␉{ 0x68B8,␉0x200B1787,␉CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5770",␉␉␉␉kVervet␉␉},␊
␉{ 0x68B8,␉0x22881787,␉CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5770",␉␉␉␉kVervet␉␉},␊
␊
␉{ 0x68D8,␉0x301117AF,␉CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5690",␉␉␉␉kNull␉␉},␊
␉{ 0x68D8,␉0x301017AF,␉CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5730",␉␉␉␉kNull␉␉},␊
␉{ 0x68D8,␉0x30001787,␉CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5730",␉␉␉␉kNull␉␉},␊
␉{ 0x68D8,␉0x5690174B,␉CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5690",␉␉␉␉kNull␉␉},␊
␉{ 0x68D8,␉0x5730174B,␉CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5730",␉␉␉␉kNull␉␉},␊
␉{ 0x68D8,␉0x21D91458,␉CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5670",␉␉␉␉kBaboon␉␉},␊
␉{ 0x68D8,␉0x03561043,␉CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5670",␉␉␉␉kBaboon␉␉},␊
␉{ 0x68D9,␉0x301017AF,␉CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5630",␉␉␉␉kNull␉␉},␊
␉{ 0x68DA,␉0x301017AF,␉CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5630",␉␉␉␉kNull␉␉},␊
␉{ 0x68DA,␉0x30001787,␉CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5630",␉␉␉␉kNull␉␉},␊
␉{ 0x68DA,␉0x5630174B,␉CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5630",␉␉␉␉kNull␉␉},␊
␊
␉{ 0x68F9,␉0x301317AF,␉CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5470",␉␉␉␉kNull␉␉},␊
␉{ 0x68F9,␉0x301117AF,␉CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5470",␉␉␉␉kNull␉␉},␊
␉{ 0x68F9,␉0x301217AF,␉CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5490",␉␉␉␉kNull␉␉},␊
␉{ 0x68F9,␉0x30001787,␉CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5470",␉␉␉␉kNull␉␉},␊
␉{ 0x68F9,␉0x30021787,␉CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5490",␉␉␉␉kNull␉␉},␊
␉{ 0x68F9,␉0x30011787,␉CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5530",␉␉␉␉kNull␉␉},␊
␉{ 0x68F9,␉0x5470174B,␉CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5470",␉␉␉␉kNull␉␉},␊
␉{ 0x68F9,␉0x5490174B,␉CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5490",␉␉␉␉kNull␉␉},␊
␉{ 0x68F9,␉0x5530174B,␉CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5530",␉␉␉␉kNull␉␉},␊
␊
␉/* standard/default models */␊
␉{ 0x9400,␉0x00000000,␉CHIP_FAMILY_R600,␉␉"ATI Radeon HD 2900 XT",␉␉␉kNull␉␉},␊
␉{ 0x9405,␉0x00000000,␉CHIP_FAMILY_R600,␉␉"ATI Radeon HD 2900 GT",␉␉␉kNull␉␉},␊
␉{ 0x9440,␉0x00000000,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4800 Series",␉␉kMotmot␉␉},␊
␉{ 0x9441,␉0x00000000,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4870 X2",␉␉␉kMotmot␉␉},␊
␉{ 0x9442,␉0x00000000,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4800 Series",␉␉kMotmot␉␉},␊
␉{ 0x9443,␉0x00000000,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4850 X2",␉␉␉kMotmot␉␉},␊
␉{ 0x944C,␉0x00000000,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4800 Series",␉␉kMotmot␉␉},␊
␉{ 0x944E,␉0x00000000,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4700 Series",␉␉kMotmot␉␉},␊
␉{ 0x944E,␉0x00000000,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4700 Series",␉␉kMotmot␉␉},␊
␉{ 0x9450,␉0x00000000,␉CHIP_FAMILY_RV770,␉␉"AMD FireStream 9270",␉␉␉␉kMotmot␉␉},␊
␉{ 0x9452,␉0x00000000,␉CHIP_FAMILY_RV770,␉␉"AMD FireStream 9250",␉␉␉␉kMotmot␉␉},␊
␉{ 0x9460,␉0x00000000,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4800 Series",␉␉kMotmot␉␉},␊
␉{ 0x9462,␉0x00000000,␉CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4800 Series",␉␉kMotmot␉␉},␊
␉{ 0x9490,␉0x00000000,␉CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4600 Series",␉␉kFlicker␉},␊
␉{ 0x9498,␉0x00000000,␉CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4600 Series",␉␉kFlicker␉},␊
␉{ 0x94B3,␉0x00000000,␉CHIP_FAMILY_RV740,␉␉"ATI Radeon HD 4770",␉␉␉␉kFlicker␉},␊
␉{ 0x94B4,␉0x00000000,␉CHIP_FAMILY_RV740,␉␉"ATI Radeon HD 4700 Series",␉␉kFlicker␉},␊
␉{ 0x94B5,␉0x00000000,␉CHIP_FAMILY_RV740,␉␉"ATI Radeon HD 4770",␉␉␉␉kFlicker␉},␊
␉{ 0x94C1,␉0x00000000,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 Series",␉␉kIago␉␉},␊
␉{ 0x94C3,␉0x00000000,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 Series",␉␉kIago␉␉},␊
␉{ 0x94C7,␉0x00000000,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2350",␉␉␉␉kIago␉␉},␊
␉{ 0x94CC,␉0x00000000,␉CHIP_FAMILY_RV610,␉␉"ATI Radeon HD 2400 Series",␉␉kIago␉␉},␊
␊
␉{ 0x9501,␉0x00000000,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 3800 Series",␉␉kMegalodon␉},␊
␉{ 0x9505,␉0x00000000,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 3800 Series",␉␉kMegalodon␉},␊
␉{ 0x9507,␉0x00000000,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 3830",␉␉␉␉kMegalodon␉},␊
␉{ 0x950F,␉0x00000000,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 3870 X2",␉␉␉kMegalodon␉},␊
␉{ 0x9513,␉0x00000000,␉CHIP_FAMILY_RV670,␉␉"ATI Radeon HD 3850 X2",␉␉␉kMegalodon␉},␊
␉{ 0x9519,␉0x00000000,␉CHIP_FAMILY_RV670,␉␉"AMD FireStream 9170",␉␉␉␉kMegalodon␉},␊
␉{ 0x9540,␉0x00000000,␉CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4550",␉␉␉␉kNull␉␉},␊
␉{ 0x954F,␉0x00000000,␉CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4300/4500 Series",␉kNull␉␉},␊
␉{ 0x9588,␉0x00000000,␉CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 2600 XT",␉␉␉kLamna␉␉},␊
␉{ 0x9589,␉0x00000000,␉CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 2600 PRO",␉␉␉kLamna␉␉},␊
␉{ 0x958A,␉0x00000000,␉CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 2600 X2 Series",␉␉kLamna␉␉},␊
␉{ 0x9598,␉0x00000000,␉CHIP_FAMILY_RV635,␉␉"ATI Radeon HD 3600 Series",␉␉kMegalodon␉},␊
␉{ 0x95C0,␉0x00000000,␉CHIP_FAMILY_RV620,␉␉"ATI Radeon HD 3400 Series",␉␉kIago␉␉},␊
␉{ 0x95C5,␉0x00000000,␉CHIP_FAMILY_RV620,␉␉"ATI Radeon HD 3400 Series",␉␉kIago␉␉},␊
␊
␉{ 0x9610,␉0x00000000,␉CHIP_FAMILY_RS780,␉␉"ATI Radeon HD 3200 Graphics",␉␉kNull␉␉},␊
␉{ 0x9611,␉0x00000000,␉CHIP_FAMILY_RS780,␉␉"ATI Radeon 3100 Graphics",␉␉␉kNull␉␉},␊
␉{ 0x9614,␉0x00000000,␉CHIP_FAMILY_RS780,␉␉"ATI Radeon HD 3300 Graphics",␉␉kNull␉␉},␊
␉{ 0x9616,␉0x00000000,␉CHIP_FAMILY_RS780,␉␉"AMD 760G",␉␉␉␉␉␉␉kNull␉␉},␊
␊
␉{ 0x9710,␉0x00000000,␉CHIP_FAMILY_RS880,␉␉"ATI Radeon HD 4200",␉␉␉␉kNull␉␉},␊
␉{ 0x9715,␉0x00000000,␉CHIP_FAMILY_RS880,␉␉"ATI Radeon HD 4250",␉␉␉␉kNull␉␉},␊
␉{ 0x9714,␉0x00000000,␉CHIP_FAMILY_RS880,␉␉"ATI Radeon HD 4290",␉␉␉␉kNull␉␉},␊
␊
␊
␉{ 0x688D,␉0x00000000,␉CHIP_FAMILY_CYPRESS,␉"AMD FireStream 9350",␉␉␉␉kUakari␉␉},␊
␊
␉{ 0x6898,␉0x00000000,␉CHIP_FAMILY_CYPRESS,␉"ATI Radeon HD 5800 Series",␉␉kUakari␉␉},␊
␉{ 0x6899,␉0x00000000,␉CHIP_FAMILY_CYPRESS,␉"ATI Radeon HD 5800 Series",␉␉kUakari␉␉},␊
␉{ 0x689E,␉0x00000000,␉CHIP_FAMILY_CYPRESS,␉"ATI Radeon HD 5800 Series",␉␉kUakari␉␉},␊
␉{ 0x689C,␉0x00000000,␉CHIP_FAMILY_HEMLOCK,␉"ATI Radeon HD 5900 Series",␉␉kUakari␉␉},␊
␊
␉{ 0x68B9,␉0x00000000,␉CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5600 Series",␉␉kVervet␉␉},␊
␉{ 0x68B8,␉0x00000000,␉CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5700 Series",␉␉kVervet␉␉},␊
␉{ 0x68BE,␉0x00000000,␉CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5700 Series",␉␉kVervet␉␉},␊
␊
␉{ 0x68D8,␉0x00000000,␉CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5600 Series",␉␉kBaboon␉␉},␊
␉{ 0x68D9,␉0x00000000,␉CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5500 Series",␉␉kBaboon␉␉},␊
␉{ 0x68DA,␉0x00000000,␉CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5500 Series",␉␉kBaboon␉␉},␊
␊
␉{ 0x68F9,␉0x00000000,␉CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 5400 Series",␉␉kNull␉␉},␊
␊
␉{ 0x0000,␉0x00000000,␉CHIP_FAMILY_UNKNOW,␉␉NULL,␉␉␉␉␉␉␉␉kNull␉␉}␊
};␊
␊
static struct ati_chipsets_t ATIKnownFramebuffers[] = {␊
␉{ 0x00000000, "Megalodon" },␊
␉{ 0x10029589, "Lamna"} ,␊
␉{ 0x10029588, "Lamna"} ,␊
␉{ 0x100294C3, "Iago"} ,␊
␉{ 0x100294C4, "Iago"} ,␊
␉{ 0x100294C6, "Iago"} ,␊
␉{ 0x10029400, "Franklin"} ,␊
␉{ 0x10029405, "Franklin"} ,␊
␉{ 0x10029581, "Hypoprion"} ,␊
␉{ 0x10029583, "Hypoprion"} ,␊
␉{ 0x10029586, "Hypoprion"} ,␊
␉{ 0x10029587, "Hypoprion"} ,␊
␉{ 0x100294C9, "Iago"} ,␊
␉{ 0x10029501, "Megalodon"} ,␊
␉{ 0x10029505, "Megalodon"} ,␊
␉{ 0x10029515, "Megalodon"} ,␊
␉{ 0x10029507, "Megalodon"} ,␊
␉{ 0x10029500, "Megalodon"} ,␊
␉{ 0x1002950F, "Triakis"} ,␊
␉{ 0x100295C5, "Iago"} ,␊
␉{ 0x100295C7, "Iago"} ,␊
␉{ 0x100295C0, "Iago"} ,␊
␉{ 0x10029596, "Megalodon"} ,␊
␉{ 0x10029590, "Megalodon"} ,␊
␉{ 0x10029599, "Megalodon"} ,␊
␉{ 0x10029597, "Megalodon"} ,␊
␉{ 0x10029598, "Megalodon"} ,␊
␉{ 0x10029442, "Motmot"} ,␊
␉{ 0x10029440, "Motmot"} ,␊
␉{ 0x1002944C, "Motmot"} ,␊
␉{ 0x10029460, "Motmot"} ,␊
␉{ 0x10029462, "Motmot"} ,␊
␉{ 0x10029441, "Motmot"} ,␊
␉{ 0x10029443, "Motmot"} ,␊
␉{ 0x10029444, "Motmot"} ,␊
␉{ 0x10029446, "Motmot"} ,␊
␉{ 0x1002944E, "Motmot"} ,␊
␉{ 0x10029450, "Motmot"} ,␊
␉{ 0x10029452, "Motmot"} ,␉␉␊
␉{ 0x10029456, "Motmot"} ,␉␉␊
␉{ 0x1002944A, "Motmot"} ,␊
␉{ 0x1002945A, "Motmot"} ,␊
␉{ 0x1002945B, "Motmot"} ,␊
␉{ 0x1002944B, "Motmot"} ,␊
{ 0x10029490, "Peregrine"} ,␊
{ 0x10029498, "Peregrine"} ,␊
{ 0x1002949E, "Peregrine"} ,␊
{ 0x10029480, "Peregrine"} ,␊
{ 0x10029488, "Peregrine"} ,␊
{ 0x10029540, "Peregrine"} ,␊
{ 0x10029541, "Peregrine"} ,␊
{ 0x1002954E, "Peregrine"} ,␊
{ 0x10029552, "Peregrine"} ,␊
{ 0x10029553, "Peregrine"} ,␊
{ 0x1002954F, "Peregrine"} ,␊
{ 0x100294B3, "Peregrine"},␊
{ 0x100294B5, "Peregrine"},␊
{ 0x100268B8, "Motmot"},␊
{ 0x100268BE, "Motmot"},␊
{ 0x10026898, "Motmot"},␊
{ 0x10026899, "Motmot"}␊
␊
typedef struct {␊
␉struct DevPropDevice␉*device;␊
␉radeon_card_info_t␉␉*info;␊
␉pci_dt_t ␉␉␉␉*pci_dev;␊
␉uint8_t␉␉␉␉␉*fb;␊
␉uint8_t␉␉␉␉␉*mmio;␊
␉uint8_t␉␉␉␉␉*io;␊
␉uint8_t␉␉␉␉␉*rom;␊
␉uint32_t␉␉␉␉rom_size;␊
␉uint32_t␉␉␉␉vram_size;␊
␉uint8_t␉␉␉␉␉ports;␊
␉uint32_t␉␉␉␉flags;␊
␉bool␉␉␉␉␉posted;␊
} card_t;␊
card_t *card;␊
␊
/* Flags */␊
#define MKFLAG(n)␉␉(1 << n)␊
#define FLAGTRUE␉␉MKFLAG(0)␊
#define EVERGREEN␉␉MKFLAG(1)␊
␊
static uint8_t atN = 0;␊
␊
typedef struct {␊
␉type_t␉␉type;␊
␉uint32_t␉size;␊
␉uint8_t␉␉*data;␊
} value_t;␊
␊
static value_t aty_name;␊
static value_t aty_nameparent;␊
//static value_t aty_model;␊
␊
#define DATVAL(x)␉␉{kPtr, sizeof(x), (uint8_t *)x}␊
#define STRVAL(x)␉␉{kStr, sizeof(x), (uint8_t *)x}␊
#define BYTVAL(x)␉␉{kCst, 1, (uint8_t *)x}␊
#define WRDVAL(x)␉␉{kCst, 2, (uint8_t *)x}␊
#define DWRVAL(x)␉␉{kCst, 4, (uint8_t *)x}␊
#define QWRVAL(x)␉␉{kCst, 8, (uint8_t *)x}␊
#define NULVAL␉␉␉{kNul, 0, (uint8_t *)NULL}␊
␊
bool get_bootdisplay_val(value_t *val);␊
bool get_vrammemory_val(value_t *val);␊
bool get_name_val(value_t *val);␊
bool get_nameparent_val(value_t *val);␊
bool get_model_val(value_t *val);␊
bool get_conntype_val(value_t *val);␊
bool get_vrammemsize_val(value_t *val);␊
bool get_binimage_val(value_t *val);␊
bool get_deviceid_val(value_t *val);␊
bool get_mclk_val(value_t *val);␊
bool get_sclk_val(value_t *val);␊
bool get_refclk_val(value_t *val);␊
bool get_platforminfo_val(value_t *val);␊
bool get_vramtotalsize_val(value_t *val);␊
␊
typedef struct {␊
␉uint32_t␉flags;␊
␉bool␉␉all_ports;␊
␉char␉␉*name;␊
␉bool␉␉(*get_value)(value_t *val);␊
␉value_t␉␉default_val;␊
} dev_prop_t;␊
␊
dev_prop_t ati_devprop_list[] = {␊
␉{FLAGTRUE,␉false,␉"@0,AAPL,boot-display",␉␉get_bootdisplay_val,␉NULVAL␉␉␉␉␉␉␉},␊
//␉{FLAGTRUE,␉false,␉"@0,ATY,EFIDisplay",␉␉NULL,␉␉␉␉␉STRVAL("TMDSA")␉␉␉␉␉},␊
␊
//␉{FLAGTRUE,␉true,␉"@0,AAPL,vram-memory",␉␉get_vrammemory_val,␉␉NULVAL␉␉␉␉␉␉␉},␊
//␉{FLAGTRUE,␉true,␉"@0,compatible",␉␉␉get_name_val,␉␉␉NULVAL␉␉␉␉␉␉␉},␊
//␉{FLAGTRUE,␉true,␉"@0,connector-type",␉␉get_conntype_val,␉␉NULVAL␉␉␉␉␉␉␉},␊
//␉{FLAGTRUE,␉true,␉"@0,device_type",␉␉␉NULL,␉␉␉␉␉STRVAL("display")␉␉␉␉},␊
//␉{FLAGTRUE,␉false,␉"@0,display-connect-flags",␉NULL,␉␉␉␉␉DWRVAL((uint32_t)0)␉␉␉␉},␊
//␉{FLAGTRUE,␉true,␉"@0,display-type",␉␉␉NULL,␉␉␉␉␉STRVAL("NONE")␉␉␉␉␉},␊
␉{FLAGTRUE,␉true,␉"@0,name",␉␉␉␉␉get_name_val,␉␉␉NULVAL␉␉␉␉␉␉␉},␊
//␉{FLAGTRUE,␉true,␉"@0,VRAM,memsize",␉␉␉get_vrammemsize_val,␉NULVAL␉␉␉␉␉␉␉},␊
␊
//␉{FLAGTRUE,␉false,␉"AAPL,aux-power-connected",␉NULL,␉␉␉␉␉DWRVAL((uint32_t)1)␉␉␉␉},␊
//␉{FLAGTRUE,␉false,␉"AAPL,backlight-control",␉NULL,␉␉␉␉␉DWRVAL((uint32_t)0)␉␉␉␉},␊
␉{FLAGTRUE,␉false,␉"ATY,bin_image",␉␉␉get_binimage_val,␉␉NULVAL␉␉␉␉␉␉␉},␊
␉{FLAGTRUE,␉false,␉"ATY,Copyright",␉␉␉NULL,␉STRVAL("Copyright AMD Inc. All Rights Reserved. 2005-2010")␉},␊
␉{FLAGTRUE,␉false,␉"ATY,VendorID",␉␉␉␉NULL,␉␉␉␉␉WRDVAL((uint16_t)0x1002)␉␉},␊
␉{FLAGTRUE,␉false,␉"ATY,DeviceID",␉␉␉␉get_deviceid_val,␉␉NULVAL␉␉␉␉␉␉␉},␊
␊
//␉{FLAGTRUE,␉false,␉"ATY,MCLK",␉␉␉␉␉get_mclk_val,␉␉␉NULVAL␉␉␉␉␉␉␉},␊
//␉{FLAGTRUE,␉false,␉"ATY,SCLK",␉␉␉␉␉get_sclk_val,␉␉␉NULVAL␉␉␉␉␉␉␉},␊
//␉{FLAGTRUE,␉false,␉"ATY,RefCLK",␉␉␉␉get_refclk_val,␉␉␉DWRVAL((uint32_t)0x0a8c)␉␉},␊
␊
//␉{FLAGTRUE,␉false,␉"ATY,PlatformInfo",␉␉␉get_platforminfo_val,␉NULVAL␉␉␉␉␉␉␉},␊
␊
␉{FLAGTRUE,␉false,␉"name",␉␉␉␉␉␉get_nameparent_val,␉␉NULVAL␉␉␉␉␉␉␉},␊
␉{FLAGTRUE,␉false,␉"device_type",␉␉␉␉get_nameparent_val,␉␉NULVAL␉␉␉␉␉␉␉},␊
␉{FLAGTRUE,␉false,␉"model",␉␉␉␉␉get_model_val,␉␉␉STRVAL("ATI Radeon")␉␉␉},␊
//␉{FLAGTRUE,␉false,␉"VRAM,totalsize",␉␉␉get_vramtotalsize_val,␉NULVAL␉␉␉␉␉␉␉},␊
␊
␉{FLAGTRUE,␉false,␉NULL,␉␉␉␉␉␉NULL,␉␉␉␉␉NULVAL␉␉␉␉␉␉␉}␊
};␊
␊
static uint32_t accessROM(pci_dt_t *ati_dev, unsigned int mode)␊
bool get_bootdisplay_val(value_t *val)␊
{␊
␉uint32_t␉␉bar[7];␊
␉volatile uint32_t␉*regs;␊
␉static uint32_t v = 0;␊
␊
␉bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );␊
␉regs = (uint32_t *) (bar[2] & ~0x0f);␊
␉if (v)␊
␉␉return false;␊
␊
␉if (mode) {␊
␉␉if (mode != 1) {␊
␉␉␉return 0xe00002c7;␊
␉␉}␊
␉␉REG32W(0x179c, 0x00080000);␊
␉␉REG32W(0x1798, 0x00080721);␊
␉␉REG32W(0x17a0, 0x00080621);␊
␉␉REG32W(0x1600, 0x14030300);␊
␉␉REG32W(0x1798, 0x21);␊
␉␉REG32W(0x17a0, 0x21);␊
␉␉REG32W(0x179c, 0x00);␊
␉␉REG32W(0x17a0, 0x21);␊
␉␉REG32W(0x1798, 0x21);␊
␉␉REG32W(0x1798, 0x21);␊
␉} else {␊
␉␉REG32W(0x1600, 0x14030302);␉␊
␉␉REG32W(0x1798, 0x21);␊
␉␉REG32W(0x17a0, 0x21);␊
␉␉REG32W(0x179c, 0x00080000);␊
␉␉REG32W(0x17a0, 0x00080621);␊
␉␉REG32W(0x1798, 0x00080721);␊
␉␉REG32W(0x1798, 0x21);␊
␉␉REG32W(0x17a0, 0x21);␊
␉␉REG32W(0x179c, 0x00);␊
␉␉REG32W(0x1604, 0x0400e9fc);␊
␉␉REG32W(0x161c, 0x00);␊
␉␉REG32W(0x1620, 0x9f);␊
␉␉REG32W(0x1618, 0x00040004);␊
␉␉REG32W(0x161c, 0x00);␊
␉␉REG32W(0x1604, 0xe9fc);␊
␉␉REG32W(0x179c, 0x00080000);␊
␉␉REG32W(0x1798, 0x00080721);␊
␉␉REG32W(0x17a0, 0x00080621);␊
␉␉REG32W(0x1798, 0x21);␊
␉␉REG32W(0x17a0, 0x21);␊
␉␉REG32W(0x179c, 0x00);␊
␉}␊
␉return 0;␊
␉if (!card->posted)␊
␉␉return false;␊
␊
␉v = 1;␊
␉val->type = kCst;␊
␉val->size = 4;␊
␉val->data = (uint8_t *)&v;␊
␊
␉return true;␊
}␊
␊
static uint8_t *readAtomBIOS(pci_dt_t *ati_dev)␊
bool get_vrammemory_val(value_t *val)␊
{␊
␉uint32_t␉␉bar[7];␊
␉uint32_t␉␉*BIOSBase;␊
␉uint32_t␉␉counter;␊
␉volatile uint32_t␉*regs;␊
␉return false;␊
}␊
␊
␉bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );␊
␉regs = (volatile uint32_t *) (bar[2] & ~0x0f);␊
␉accessROM(ati_dev, 0);␊
␉REG32W(0xa8, 0);␊
␉REG32R(0xac);␊
␉REG32W(0xa8, 0);␊
␉REG32R(0xac);␉␊
bool get_name_val(value_t *val)␊
{␊
␉val->type = aty_name.type;␊
␉val->size = aty_name.size;␊
␉val->data = aty_name.data;␊
␊
␉BIOSBase = malloc(0x10000);␊
␉REG32W(0xa8, 0);␊
␉BIOSBase[0] = REG32R(0xac);␊
␉counter = 4;␊
␉do {␊
␉␉REG32W(0xa8, counter);␊
␉␉BIOSBase[counter/4] = REG32R(0xac);␊
␉␉counter +=4;␊
␉} while (counter != 0x10000);␊
␉accessROM((pci_dt_t *)regs, 1);␊
␉return true;␊
}␊
␊
␉if (*(uint16_t *)BIOSBase != 0xAA55) {␊
␉␉printf("Wrong BIOS signature: %04x\n", *(uint16_t *)BIOSBase);␊
␉␉return 0;␊
␉}␊
␉return (uint8_t *)BIOSBase;␊
bool get_nameparent_val(value_t *val)␊
{␊
␉val->type = aty_nameparent.type;␊
␉val->size = aty_nameparent.size;␊
␉val->data = aty_nameparent.data;␊
␊
␉return true;␊
}␊
␊
#define R5XX_CONFIG_MEMSIZE␉0x00F8␊
#define R6XX_CONFIG_MEMSIZE␉0x5428␊
bool get_model_val(value_t *val)␊
{␊
␉if (!card->info->model_name)␊
␉␉return false;␊
␊
uint32_t getvramsizekb(pci_dt_t *ati_dev)␊
␉val->type = kStr;␊
␉val->size = strlen(card->info->model_name) + 1;␊
␉val->data = (uint8_t *)card->info->model_name;␊
␊
␉return true;␊
}␊
␊
bool get_conntype_val(value_t *val)␊
{␊
␉uint32_t␉␉bar[7];␊
␉uint32_t␉␉size;␊
␉volatile uint32_t␉*regs;␊
/*␊
Connector types:␊
0x4 : DisplayPort␊
0x400: DL DVI-I␊
0x800: HDMI␊
*/␊
␉return false;␊
}␊
␊
␉bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );␊
␉regs = (uint32_t *) (bar[2] & ~0x0f);␊
␉if (ati_dev->device_id < 0x9400) {␊
␉␉size = (REG32R(R5XX_CONFIG_MEMSIZE)) >> 10;␊
␉} else {␊
␉␉size = (REG32R(R6XX_CONFIG_MEMSIZE)) >> 10;␊
␉}␊
␉return size;␊
bool get_vrammemsize_val(value_t *val)␊
{␊
␉static int idx = -1;␊
␉static uint64_t memsize;␊
␊
␉idx++;␊
␉memsize = ((uint64_t)card->vram_size << 32);␊
␉if (idx == 0)␊
␉␉memsize = memsize | (uint64_t)card->vram_size;␊
␊
␉val->type = kCst;␊
␉val->size = 8;␊
␉val->data = (uint8_t *)&memsize;␊
␊
␉return true;␊
}␊
␊
#define AVIVO_D1CRTC_CONTROL␉0x6080␊
#define AVIVO_CRTC_EN␉␉(1<<0)␊
#define AVIVO_D2CRTC_CONTROL␉0x6880␊
bool get_binimage_val(value_t *val)␊
{␊
␉if (!card->rom)␊
␉␉return false;␊
␊
static bool radeon_card_posted(pci_dt_t *ati_dev)␊
␉val->type = kPtr;␊
␉val->size = card->rom_size;␊
␉val->data = card->rom;␊
␊
␉return true;␊
}␊
␊
bool get_deviceid_val(value_t *val)␊
{␊
␉// if devid matches biosimage(from legacy) devid - posted card, fails with X2/crossfire cards.␊
/*␉char *biosimage = 0xC0000;␊
␉␊
␉if ((uint8_t)biosimage[0] == 0x55 && (uint8_t)biosimage[1] == 0xaa)␊
␉{␊
␉␉struct pci_rom_pci_header_t *rom_pci_header; ␊
␉␉rom_pci_header = (struct pci_rom_pci_header_t*)(biosimage + (uint8_t)biosimage[24] + (uint8_t)biosimage[25]*256);␊
␉␊
␉if (rom_pci_header->signature == 0x52494350)␊
␉␉{␊
␉␉if (rom_pci_header->device == ati_dev->device_id)␊
␉val->type = kCst;␊
␉val->size = 2;␊
␉val->data = (uint8_t *)&card->pci_dev->device_id;␊
␊
␉return true;␊
}␊
␊
bool get_mclk_val(value_t *val)␊
{␊
␉return false;␊
}␊
␊
bool get_sclk_val(value_t *val)␊
{␊
␉return false;␊
}␊
␊
bool get_refclk_val(value_t *val)␊
{␊
␉return false;␊
}␊
␊
bool get_platforminfo_val(value_t *val)␊
{␊
␉val->data = malloc(0x80);␊
␉if (!val->data)␊
␉␉return false;␊
␊
␉bzero(val->data, 0x80);␊
␊
␉val->type␉␉= kPtr;␊
␉val->size␉␉= 0x80;␊
␉val->data[0]␉= 1;␊
␊
␉return true;␊
}␊
␊
bool get_vramtotalsize_val(value_t *val)␊
{␊
␉val->type = kCst;␊
␉val->size = 4;␊
␉val->data = (uint8_t *)&card->vram_size;␊
␊
␉return true;␊
}␊
␊
void free_val(value_t *val)␊
{␊
␉if (val->type == kPtr)␊
␉␉free(val->data);␊
␉bzero(val, sizeof(value_t));␊
}␊
␊
void devprop_add_list(dev_prop_t devprop_list[])␊
{␊
␉value_t *val = malloc(sizeof(value_t));␊
␉int i, pnum;␊
␉for (i = 0; devprop_list[i].name != NULL; i++)␊
␉␉if ((devprop_list[i].flags == FLAGTRUE) || (devprop_list[i].flags | card->flags))␊
␉␉␉if (devprop_list[i].get_value && devprop_list[i].get_value(val))␊
␉␉␉{␊
␉␉␉␉return true;␊
␉␉␉␉printf("Card was POSTed\n");␊
␉␉␉␉devprop_add_value(card->device, devprop_list[i].name, val->data, val->size);␊
␉␉␉␉free_val(val);␊
␉␉␉␉if (devprop_list[i].all_ports)␊
␉␉␉␉{␊
␉␉␉␉␉for (pnum = 1; pnum < card->ports; pnum++)␊
␉␉␉␉␉{␊
␉␉␉␉␉␉if (devprop_list[i].get_value(val))␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉devprop_list[i].name[1] = 0x30 + pnum; // convert to ascii␊
␉␉␉␉␉␉␉devprop_add_value(card->device, devprop_list[i].name, val->data, val->size);␊
␉␉␉␉␉␉␉free_val(val);␊
␉␉␉␉␉␉}␊
␉␉␉␉␉}␊
␉␉␉␉␉devprop_list[i].name[1] = 0x30; // write back our "@0," for a next possible card␊
␉␉␉␉}␊
␉␉␉}␊
␉␉}␊
␉}␊
␉return false;␊
␉printf("Card was not POSTed\n");␊
␉*/␊
␉//fails yet␊
␉uint32_t␉␉bar[7];␊
␉uint32_t␉␉val;␊
␉volatile uint32_t␉*regs;␊
␉␉␉else␊
␉␉␉{␊
␉␉␉␉if (devprop_list[i].default_val.type != kNul)␊
␉␉␉␉␉devprop_add_value(card->device, devprop_list[i].name, ␊
␉␉␉␉␉␉devprop_list[i].default_val.type == kCst ? ␊
␉␉␉␉␉␉(uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data, ␊
␉␉␉␉␉␉devprop_list[i].default_val.size);␊
␊
␉bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18);␊
␉regs = (uint32_t *) (bar[2] & ~0x0f);␊
␉␉␉␉if (devprop_list[i].all_ports)␊
␉␉␉␉{␊
␉␉␉␉␉for (pnum = 1; pnum < card->ports; pnum++)␊
␉␉␉␉␉{␊
␉␉␉␉␉␉if (devprop_list[i].default_val.type != kNul)␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉devprop_list[i].name[1] = 0x30 + pnum; // convert to ascii␊
␉␉␉␉␉␉␉devprop_add_value(card->device, devprop_list[i].name, ␊
␉␉␉␉␉␉␉␉devprop_list[i].default_val.type == kCst ? ␊
␉␉␉␉␉␉␉␉(uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data, ␊
␉␉␉␉␉␉␉␉devprop_list[i].default_val.size);␊
␉␉␉␉␉␉}␊
␉␉␉␉␉}␊
␉␉␉␉␉devprop_list[i].name[1] = 0x30; // write back our "@0," for a next possible card␊
␉␉␉␉}␊
␉␉␉}␊
␊
␉val = REG32R(AVIVO_D1CRTC_CONTROL) | REG32R(AVIVO_D2CRTC_CONTROL);␊
␉if (val & AVIVO_CRTC_EN) {␊
␉␉return true;␊
␉} else {␊
␉free(val);␊
}␊
␊
␊
bool validate_rom(option_rom_header_t *rom_header, pci_dt_t *pci_dev)␊
{␊
␉option_rom_pci_header_t *rom_pci_header;␊
␉␊
␉if (rom_header->signature != 0xaa55)␊
␉␉return false;␊
␉}␊
␊
␉rom_pci_header = (option_rom_pci_header_t *)((uint8_t *)rom_header + rom_header->pci_header_offset);␊
␊
␉if (rom_pci_header->signature != 0x52494350)␊
␉␉return false;␊
␊
␉if (rom_pci_header->vendor_id != pci_dev->vendor_id || rom_pci_header->device_id != pci_dev->device_id)␊
␉␉return false;␊
␊
␉return true;␊
}␊
␊
static uint32_t load_ati_bios_file(const char *filename, uint8_t *buf, int bufsize)␊
bool load_vbios_file(const char *key, uint16_t vendor_id, uint16_t device_id, uint32_t subsys_id)␊
{␊
␉int␉fd;␊
␉int␉size;␊
␉char file_name[24];␊
␉bool do_load = false;␊
␊
␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {␊
␉␉return 0;␊
␉getBoolForKey(key, &do_load, &bootInfo->bootConfig);␊
␉if (!do_load)␊
␉␉return false;␊
␊
␉sprintf(file_name, "/Extra/%04x_%04x_%08x.rom", vendor_id, device_id, subsys_id);␊
␉if ((fd = open_bvdev("bt(0,0)", file_name, 0)) < 0)␊
␉␉return false;␊
␊
␉card->rom_size = file_size(fd);␊
␉card->rom = malloc(card->rom_size);␊
␉if (!card->rom)␊
␉␉return false;␊
␊
␉read(fd, (char *)card->rom, card->rom_size);␊
␉␊
␉if (!validate_rom((option_rom_header_t *)card->rom, card->pci_dev))␊
␉{␊
␉␉card->rom_size = 0;␊
␉␉card->rom = 0;␊
␉␉return false;␊
␉}␊
␉size = file_size(fd);␊
␉if (size > bufsize) {␊
␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);␊
␉␉size = bufsize;␊
␉}␊
␉size = read(fd, (char *)buf, size);␊
␊
␉card->rom_size = ((option_rom_header_t *)card->rom)->rom_size * 512;␊
␊
␉close(fd);␊
␉return size > 0 ? size : 0;␊
␊
␉return true;␊
}␊
␊
static char *get_ati_model(uint32_t id)␊
void get_vram_size(void)␊
{␊
␉int␉i;␊
␉chip_family_t chip_family = card->info->chip_family;␊
␊
␉for (i=0; i< (sizeof(ATIKnownChipsets) / sizeof(ATIKnownChipsets[0])); i++) {␊
␉␉if (ATIKnownChipsets[i].device == id) {␊
␉␉␉return ATIKnownChipsets[i].name;␊
␉␉}␊
␉}␊
␉return ATIKnownChipsets[0].name;␊
␉card->vram_size = 0;␊
␊
␉if (chip_family >= CHIP_FAMILY_CEDAR)␊
␉␉/* size in MB on evergreen */␊
␉␉/* XXX watch for overflow!!! */␊
␉␉card->vram_size = RegRead32(R600_CONFIG_MEMSIZE) * 1024 * 1024;␊
␉else␊
␉␉if (chip_family >= CHIP_FAMILY_R600)␊
␉␉␉card->vram_size = RegRead32(R600_CONFIG_MEMSIZE);␊
}␊
␊
static char *get_ati_fb(uint32_t id)␊
bool read_vbios(bool from_pci)␊
{␊
␉int␉i;␊
␉option_rom_header_t *rom_addr;␊
␊
␉for (i=0; i< (sizeof(ATIKnownFramebuffers) / sizeof(ATIKnownFramebuffers[0])); i++) {␊
␉␉if (ATIKnownFramebuffers[i].device == id) {␊
␉␉␉return ATIKnownFramebuffers[i].name;␊
␉␉}␊
␉if (from_pci)␊
␉{␊
␉␉rom_addr = (option_rom_header_t *)(pci_config_read32(card->pci_dev->dev.addr, PCI_ROM_ADDRESS) & ~0x7ff);␊
␉␉verbose(" @0x%x", rom_addr);␊
␉}␊
␉return ATIKnownFramebuffers[0].name;␊
␉else␊
␉␉rom_addr = (option_rom_header_t *)0xc0000;␊
␊
␉if (!validate_rom(rom_addr, card->pci_dev))␊
␉␉return false;␊
␊
␉card->rom_size = rom_addr->rom_size * 512;␊
␉if (!card->rom_size)␊
␉␉return false;␊
␊
␉card->rom = malloc(card->rom_size);␊
␉if (!card->rom)␊
␉␉return false;␊
␊
␉memcpy(card->rom, (void *)rom_addr, card->rom_size);␊
␊
␉return true;␊
}␊
␊
static int devprop_add_iopciconfigspace(struct DevPropDevice *device, pci_dt_t *ati_dev)␊
bool read_disabled_vbios(void)␊
{␊
␉int␉i;␊
␉uint8_t␉*config_space;␊
␉bool ret = false;␊
␉chip_family_t chip_family = card->info->chip_family;␊
␊
␉if (!device || !ati_dev) {␊
␉␉return 0;␊
␉if (chip_family >= CHIP_FAMILY_RV770)␊
␉{␊
␉␉uint32_t viph_control␉␉= RegRead32(RADEON_VIPH_CONTROL);␊
␉␉uint32_t bus_cntl␉␉␉= RegRead32(RADEON_BUS_CNTL);␊
␉␉uint32_t d1vga_control␉␉= RegRead32(AVIVO_D1VGA_CONTROL);␊
␉␉uint32_t d2vga_control␉␉= RegRead32(AVIVO_D2VGA_CONTROL);␊
␉␉uint32_t vga_render_control␉= RegRead32(AVIVO_VGA_RENDER_CONTROL);␊
␉␉uint32_t rom_cntl␉␉␉= RegRead32(R600_ROM_CNTL);␊
␉␉uint32_t cg_spll_func_cntl␉= 0;␊
␉␉uint32_t cg_spll_status;␊
␊
␉␉/* disable VIP */␊
␉␉RegWrite32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));␊
␊
␉␉/* enable the rom */␊
␉␉RegWrite32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));␊
␊
␉␉/* Disable VGA mode */␊
␉␉RegWrite32(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT)));␊
␉␉RegWrite32(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT)));␊
␉␉RegWrite32(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));␊
␊
␉␉if (chip_family == CHIP_FAMILY_RV730)␊
␉␉{␊
␉␉␉cg_spll_func_cntl = RegRead32(R600_CG_SPLL_FUNC_CNTL);␊
␊
␉␉␉/* enable bypass mode */␊
␉␉␉RegWrite32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | R600_SPLL_BYPASS_EN));␊
␊
␉␉␉/* wait for SPLL_CHG_STATUS to change to 1 */␊
␉␉␉cg_spll_status = 0;␊
␉␉␉while (!(cg_spll_status & R600_SPLL_CHG_STATUS))␊
␉␉␉␉cg_spll_status = RegRead32(R600_CG_SPLL_STATUS);␊
␊
␉␉␉RegWrite32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));␊
␉␉}␊
␉␉else␊
␉␉␉RegWrite32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));␊
␊
␉␉ret = read_vbios(true);␊
␊
␉␉/* restore regs */␊
␉␉if (chip_family == CHIP_FAMILY_RV730)␊
␉␉{␊
␉␉␉RegWrite32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);␊
␊
␉␉␉/* wait for SPLL_CHG_STATUS to change to 1 */␊
␉␉␉cg_spll_status = 0;␊
␉␉␉while (!(cg_spll_status & R600_SPLL_CHG_STATUS))␊
␉␉␉cg_spll_status = RegRead32(R600_CG_SPLL_STATUS);␊
␉␉}␊
␉␉RegWrite32(RADEON_VIPH_CONTROL, viph_control);␊
␉␉RegWrite32(RADEON_BUS_CNTL, bus_cntl);␊
␉␉RegWrite32(AVIVO_D1VGA_CONTROL, d1vga_control);␊
␉␉RegWrite32(AVIVO_D2VGA_CONTROL, d2vga_control);␊
␉␉RegWrite32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);␊
␉␉RegWrite32(R600_ROM_CNTL, rom_cntl);␊
␉}␊
␉printf("dumping pci config space, 256 bytes\n");␊
␉config_space = malloc(256);␊
␉for (i=0; i<=255; i++) {␊
␉␉config_space[i] = pci_config_read8( ati_dev->dev.addr, i);␊
␉}␊
␉devprop_add_value(device, "ATY,PCIConfigSpace", config_space, 256);␊
␉free (config_space);␊
␉return 1;␊
}␊
␉else␊
␉␉if (chip_family >= CHIP_FAMILY_R600)␊
␉␉{␊
␉␉␉uint32_t viph_control␉␉␉␉= RegRead32(RADEON_VIPH_CONTROL);␊
␉␉␉uint32_t bus_cntl␉␉␉␉␉= RegRead32(RADEON_BUS_CNTL);␊
␉␉␉uint32_t d1vga_control␉␉␉␉= RegRead32(AVIVO_D1VGA_CONTROL);␊
␉␉␉uint32_t d2vga_control ␉␉␉␉= RegRead32(AVIVO_D2VGA_CONTROL);␊
␉␉␉uint32_t vga_render_control␉␉␉= RegRead32(AVIVO_VGA_RENDER_CONTROL);␊
␉␉␉uint32_t rom_cntl␉␉␉␉␉= RegRead32(R600_ROM_CNTL);␊
␉␉␉uint32_t general_pwrmgt␉␉␉␉= RegRead32(R600_GENERAL_PWRMGT);␊
␉␉␉uint32_t low_vid_lower_gpio_cntl␉= RegRead32(R600_LOW_VID_LOWER_GPIO_CNTL);␊
␉␉␉uint32_t medium_vid_lower_gpio_cntl␉= RegRead32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);␊
␉␉␉uint32_t high_vid_lower_gpio_cntl␉= RegRead32(R600_HIGH_VID_LOWER_GPIO_CNTL);␊
␉␉␉uint32_t ctxsw_vid_lower_gpio_cntl␉= RegRead32(R600_CTXSW_VID_LOWER_GPIO_CNTL);␊
␉␉␉uint32_t lower_gpio_enable␉␉␉= RegRead32(R600_LOWER_GPIO_ENABLE);␊
␊
static int devprop_add_ati_template_4xxx(struct DevPropDevice *device)␊
{␊
␉if(!device)␊
␉␉return 0;␊
␉␊
//␉if(!DP_ADD_TEMP_VAL(device, ati_compatible_0))␊
//␉␉return 0;␊
//␉if(!DP_ADD_TEMP_VAL(device, ati_compatible_1))␊
//␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_device_type_0))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_device_type_1))␊
␉␉return 0;␊
//␉if(!DP_ADD_TEMP_VAL(device, ati_device_type))␊
//␉␉return 0;␊
//␉if(!DP_ADD_TEMP_VAL(device, ati_name_0))␊
//␉␉return 0;␊
//␉if(!DP_ADD_TEMP_VAL(device, ati_name_1))␊
//␉␉return 0;␊
//␉if(!DP_ADD_TEMP_VAL(device, ati_name))␊
//␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_display_type_0))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_display_type_1))␊
␉␉return 0;␊
//␉if(!DP_ADD_TEMP_VAL(device, ati_slot_name))␊
//␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_card_no))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_copyright))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_efi_version))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_mrt))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_romno))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_name_1))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_display_con_fl_type_0))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_disp_conf))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_init_stat))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config))␊
␉␉return 0;␊
␉return 1;␊
␉␉␉/* disable VIP */␊
␉␉␉RegWrite32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));␊
␊
␉␉␉/* enable the rom */␊
␉␉␉RegWrite32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));␊
␊
␉␉␉/* Disable VGA mode */␊
␉␉␉RegWrite32(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT)));␊
␉␉␉RegWrite32(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT)));␊
␉␉␉RegWrite32(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));␊
␉␉␉RegWrite32(R600_ROM_CNTL, ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | R600_SCK_OVERWRITE));␊
␉␉␉RegWrite32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));␊
␉␉␉RegWrite32(R600_LOW_VID_LOWER_GPIO_CNTL, (low_vid_lower_gpio_cntl & ~0x400));␊
␉␉␉RegWrite32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, (medium_vid_lower_gpio_cntl & ~0x400));␊
␉␉␉RegWrite32(R600_HIGH_VID_LOWER_GPIO_CNTL, (high_vid_lower_gpio_cntl & ~0x400));␊
␉␉␉RegWrite32(R600_CTXSW_VID_LOWER_GPIO_CNTL, (ctxsw_vid_lower_gpio_cntl & ~0x400));␊
␉␉␉RegWrite32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));␊
␊
␉␉␉ret = read_vbios(true);␊
␊
␉␉␉/* restore regs */␊
␉␉␉RegWrite32(RADEON_VIPH_CONTROL, viph_control);␊
␉␉␉RegWrite32(RADEON_BUS_CNTL, bus_cntl);␊
␉␉␉RegWrite32(AVIVO_D1VGA_CONTROL, d1vga_control);␊
␉␉␉RegWrite32(AVIVO_D2VGA_CONTROL, d2vga_control);␊
␉␉␉RegWrite32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);␊
␉␉␉RegWrite32(R600_ROM_CNTL, rom_cntl);␊
␉␉␉RegWrite32(R600_GENERAL_PWRMGT, general_pwrmgt);␊
␉␉␉RegWrite32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);␊
␉␉␉RegWrite32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);␊
␉␉␉RegWrite32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);␊
␉␉␉RegWrite32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);␊
␉␉␉RegWrite32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);␊
␊
␉␉}␊
␊
␉return ret;␊
}␊
␊
static int devprop_add_ati_template(struct DevPropDevice *device)␊
bool radeon_card_posted(void)␊
{␊
␉if(!device)␊
␉␉return 0;␊
␉uint32_t reg;␊
␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info))␊
␉␉return 0;␉␊
␉if(!DP_ADD_TEMP_VAL(device, ati_device_type_0))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_device_type_1))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0_n4))␊
␉␉return 0;␊
//␉if(!DP_ADD_TEMP_VAL(device, ati_slot_name_n4))␊
//␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_card_no))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_copyright))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_efi_version))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_mrt))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_romno))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL(device, ati_name_1))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0_n4))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1_n4))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_emc_disp_list_n4))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_fb_offset_n4))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_hwgpio_n4))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_iospace_offset_n4))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk_n4))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk_n4))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_refclk_n4))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_regspace_offset_n4))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_0_n4))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_1_n4))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_swgpio_info_n4))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad_n4))␊
␉␉return 0;␊
␉if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config_n4))␊
␉␉return 0;␊
␉return 1;␊
}␊
␉/* first check CRTCs */␊
␉reg = RegRead32(RADEON_CRTC_GEN_CNTL) | RegRead32(RADEON_CRTC2_GEN_CNTL);␊
␉if (reg & RADEON_CRTC_EN)␊
␉␉return true;␊
␊
␉/* then check MEM_SIZE, in case something turned the crtcs off */␊
␉reg = RegRead32(R600_CONFIG_MEMSIZE);␊
␉if (reg)␊
␉␉return true;␊
␊
bool setup_ati_devprop(pci_dt_t *ati_dev)␊
␉return false;␊
}␊
#if 0␊
bool devprop_add_pci_config_space(void)␊
{␊
␉struct DevPropDevice␉*device;␊
␉char␉␉␉*devicepath;␊
␉char␉␉␉*model;␊
␉char␉␉␉*framebuffer;␊
␉char␉␉␉tmp[64];␊
␉uint8_t␉␉␉*rom = NULL;␊
␉uint32_t␉␉rom_size = 0;␊
␉uint8_t␉␉␉*bios;␊
␉uint32_t␉␉bios_size;␊
␉uint32_t␉␉vram_size;␊
␉uint32_t␉␉boot_display;␊
␉uint8_t␉␉␉cmd;␊
␉bool␉␉␉doit;␊
␉bool␉␉␉toFree;␊
␉int offset;␊
␊
␉devicepath = get_pci_dev_path(ati_dev);␊
␉uint8_t *config_space = malloc(0x100);␊
␉if (!config_space)␊
␉␉return false;␊
␊
␉cmd = pci_config_read8(ati_dev->dev.addr, 4);␊
␉verbose("old pci command - %x\n", cmd);␊
␉if (cmd == 0) {␊
␉␉pci_config_write8(ati_dev->dev.addr, 4, 6);␉␊
␉␉cmd = pci_config_read8(ati_dev->dev.addr, 4);␊
␉␉verbose("new pci command - %x\n", cmd);␊
␉}␊
␉for (offset = 0; offset < 0x100; offset += 4)␊
␉␉config_space[offset / 4] = pci_config_read32(card->pci_dev->dev.addr, offset);␊
␊
␉model = get_ati_model((ati_dev->vendor_id << 16) | ati_dev->device_id);␊
␉framebuffer = get_ati_fb((ati_dev->vendor_id << 16) | ati_dev->device_id);␊
␉if (!string) {␊
␉␉string = devprop_create_string();␊
␉}␊
␉device = devprop_add_device(string, devicepath);␊
␉if (!device) {␊
␉␉printf("Failed initializing dev-prop string dev-entry, press any key...\n");␊
␉␉getc();␊
␉devprop_add_value(card->device, "ATY,PCIConfigSpace", config_space, 0x100);␊
␉free(config_space);␊
␉return true;␊
}␊
#endif␊
␊
static bool init_card(pci_dt_t *pci_dev)␊
{␊
␉const char *fb_name;␊
␉char name[24];␊
␉char name_parent[24];␊
␉int i;␊
␉bool add_vbios = true;␊
␊
␉card = malloc(sizeof(card_t));␊
␉if (!card)␊
␉␉return false;␊
␉}␊
␉bzero(card, sizeof(card_t));␊
␊
␉/* FIXME: for primary graphics card only */␊
␉if (radeon_card_posted(ati_dev)) {␊
␉␉boot_display = 1;␊
␉} else {␊
␉␉boot_display = 0;␊
␉}␊
␉verbose("boot display - %x\n", boot_display);␊
␉devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
␉card->pci_dev = pci_dev;␊
␊
␉if((framebuffer[0] == 'M' && framebuffer[1] == 'o' && framebuffer[2] == 't') || ␊
(framebuffer[0] == 'S' && framebuffer[1] == 'h' && framebuffer[2] == 'r') || ␊
(framebuffer[0] == 'P' && framebuffer[1] == 'e' && framebuffer[2] == 'r')) //faster than strcmp ;)␊
devprop_add_ati_template_4xxx(device);␊
␉else {␊
␉␉devprop_add_ati_template(device);␊
␉␉vram_size = getvramsizekb(ati_dev) * 1024;␊
␉␉if ((vram_size > 0x80000000) || (vram_size == 0)) {␊
␉␉␉vram_size = 0x10000000;␉//vram reported wrong, defaulting to 256 mb␊
␉for (i = 0; radeon_cards[i].device_id ; i++)␊
␉␉if (radeon_cards[i].device_id == pci_dev->device_id)␊
␉␉{␊
␉␉␉card->info = &radeon_cards[i];␊
␉␉␉if ((radeon_cards[i].subsys_id == 0x00000000) || ␊
␉␉␉␉(radeon_cards[i].subsys_id == pci_dev->subsys_id.subsys_id))␊
␉␉␉␉break;␊
␉␉}␊
␉␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&vram_size, 4);␊
␉␉ati_vram_memsize_0.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway␊
␉␉ati_vram_memsize_0.data[7] = (vram_size >> 24) & 0xFF;␉␉␊
␉␉ati_vram_memsize_1.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway␊
␉␉ati_vram_memsize_1.data[7] = (vram_size >> 24) & 0xFF;␊
␉␉DP_ADD_TEMP_VAL_DATA(device, ati_vram_memsize_0);␊
␉␉DP_ADD_TEMP_VAL_DATA(device, ati_vram_memsize_1);␊
␉␉devprop_add_iopciconfigspace(device, ati_dev);␉␉␊
␊
␉if (!card->info->device_id || !card->info->cfg_name)␊
␉{␊
␉␉printf("Unsupported card!\n");␊
␉␉return false;␊
␉}␊
␉devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1));␊
␉devprop_add_value(device, "ATY,DeviceID", (uint8_t*)&ati_dev->device_id, 2);␊
␊
␉//fb setup␊
␉sprintf(tmp, "Slot-%x",devices_number);␊
␉devprop_add_value(device, "AAPL,slot-name", (uint8_t*)tmp, strlen(tmp) + 1);␊
␉devices_number++;␊
␊
␉sprintf(tmp, ati_compatible_0[1], framebuffer);␊
␉devprop_add_value(device, (char *) ati_compatible_0[0], (uint8_t *)tmp, strlen(tmp) + 1);␊
␉card->fb␉␉= (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_0) & ~0x0f);␊
␉card->mmio␉␉= (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_2) & ~0x0f);␊
␉card->io␉␉= (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_4) & ~0x03);␊
␊
␉sprintf(tmp, ati_compatible_1[1], framebuffer);␊
␉devprop_add_value(device, (char *) ati_compatible_1[0], (uint8_t *)tmp, strlen(tmp) + 1);␊
␉card->posted␉= radeon_card_posted();␊
␉verbose("ATI card %s, ", card->posted ? "POSTed" : "non-POSTed");␊
␉␊
␉get_vram_size();␊
␊
␉sprintf(tmp, ati_device_type[1], framebuffer);␊
␉devprop_add_value(device, (char *) ati_device_type[0], (uint8_t *)tmp, strlen(tmp) + 1);␊
␉getBoolForKey(kVBIOS, &add_vbios, &bootInfo->bootConfig);␊
␊
␉sprintf(tmp, ati_name[1], framebuffer);␊
␉devprop_add_value(device, (char *) ati_name[0], (uint8_t *)tmp, strlen(tmp) + 1);␊
␉if (add_vbios)␊
␉␉if (!load_vbios_file(kUseAtiROM, pci_dev->vendor_id, pci_dev->device_id, pci_dev->subsys_id.subsys_id))␊
␉␉{␊
␉␉␉verbose("reading VBIOS from %s", card->posted ? "legacy space" : "PCI ROM");␊
␉␉␉if (card->posted)␊
␉␉␉␉read_vbios(false);␊
␉␉␉else␊
␉␉␉␉read_disabled_vbios();␊
␉␉␉verbose("\n");␊
␉␉}␊
␊
␉sprintf(tmp, ati_name_0[1], framebuffer);␊
␉devprop_add_value(device, (char *) ati_name_0[0], (uint8_t *)tmp, strlen(tmp) + 1);␊
␉card->ports = 2; // default␊
␊
␉sprintf(tmp, ati_name_1[1], framebuffer);␊
␉devprop_add_value(device, (char *) ati_name_1[0], (uint8_t *)tmp, strlen(tmp) + 1);␊
␉if (card->info->chip_family >= CHIP_FAMILY_CEDAR)␊
␉{␊
␉␉card->flags |= EVERGREEN;␊
␉␉card->ports = 3;␊
␉}␊
␊
␉sprintf(tmp, "/Extra/%04x_%04x.rom", (uint16_t)ati_dev->vendor_id, (uint16_t)ati_dev->device_id);␊
␉if (getBoolForKey(kUseAtiROM, &doit, &bootInfo->bootConfig) && doit) {␊
␉␉verbose("looking for ati video bios file %s\n", tmp);␊
␉␉rom = malloc(0x20000);␊
␉␉rom_size = load_ati_bios_file(tmp, rom, 0x20000);␊
␉␉if (rom_size > 0) {␊
␉␉␉verbose("Using ATI Video BIOS File %s (%d Bytes)\n", tmp, rom_size);␊
␉␉␉if (rom_size > 0x10000) {␊
␉␉␉␉rom_size = 0x10000; //we dont need rest anyway;␊
␉␉␉}␊
␉␉} else {␊
␉␉␉printf("ERROR: unable to open ATI Video BIOS File %s\n", tmp);␊
␉␉}␊
␉atN = 0;␊
␊
␉fb_name = getStringForKey(kAtiConfig, &bootInfo->bootConfig);␊
␉if (!fb_name)␊
␉{␊
␉␉fb_name = card_configs[card->info->cfg_name].name;␊
␉␉card->ports = card_configs[card->info->cfg_name].ports;␊
␉}␊
␉if (rom_size == 0) {␊
␉␉if (boot_display) {␉␉// no custom rom␊
␉␉␉bios = NULL;␉// try to dump from legacy space, otherwise can result in 100% fan speed␊
␉␉} else {␊
␉␉␉// readAtomBios result in bug on some cards (100% fan speed and black screen),␊
␉␉␉// not using it for posted card, rading from legacy space instead␊
␉␉␉bios = readAtomBIOS(ati_dev);␊
␉␉}␊
␉} else {␊
␉␉bios = rom;␉//going custom rom way␊
␉␉verbose("Using rom %s\n", tmp);␊
␉else␊
␉{␊
␉␉for (i = 0; i < kCfgEnd; i++)␊
␉␉␉if (strcmp(fb_name, card_configs[card->info->cfg_name].name) == 0)␊
␉␉␉␉card->ports = card_configs[card->info->cfg_name].ports;␊
␉}␊
␉if (bios == NULL) {␊
␉␉bios = (uint8_t *)0x000C0000;␊
␉␉toFree = false;␊
␉␉verbose("Not going to use bios image file\n");␊
␉} else {␊
␉␉toFree = true;␊
␉}␊
␊
␉if (bios[0] == 0x55 && bios[1] == 0xaa) {␊
␉␉printf("Found bios image\n");␊
␉␉bios_size = bios[2] * 512;␊
␉sprintf(name, "ATY,%s", fb_name);␊
␉aty_name.type = kStr;␊
␉aty_name.size = strlen(name) + 1;␊
␉aty_name.data = (uint8_t *)name;␊
␊
␉␉struct pci_rom_pci_header_t *rom_pci_header;␊
␉␉rom_pci_header = (struct pci_rom_pci_header_t*)(bios + bios[24] + bios[25]*256);␊
␉sprintf(name_parent, "ATY,%sParent", fb_name);␊
␉aty_nameparent.type = kStr;␊
␉aty_nameparent.size = strlen(name_parent) + 1;␊
␉aty_nameparent.data = (uint8_t *)name_parent;␊
␊
␉␉if (rom_pci_header->signature == 0x52494350) {␊
␉␉␉if (rom_pci_header->device != ati_dev->device_id) {␊
␉␉␉␉verbose("Bios image (%x) doesnt match card (%x), ignoring\n", rom_pci_header->device, ati_dev->device_id);␊
␉␉␉} else {␊
␉␉␉␉if (toFree) {␊
␉␉␉␉␉verbose("Adding binimage to card %x from mmio space with size %x\n", ati_dev->device_id, bios_size);␊
␉␉␉␉} else {␊
␉␉␉␉␉verbose("Adding binimage to card %x from legacy space with size %x\n", ati_dev->device_id, bios_size);␊
␉␉␉␉}␊
␉␉␉␉devprop_add_value(device, "ATY,bin_image", bios, bios_size);␊
␉␉␉}␊
␉␉} else {␊
␉␉␉verbose("Wrong pci header signature %x\n", rom_pci_header->signature);␊
␉␉}␊
␉} else {␊
␉␉verbose("Bios image not found at %x, content %x %x\n", bios, bios[0], bios[1]);␊
␉}␊
␉if (toFree) {␊
␉␉free(bios);␊
␉}␊
␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
␉return true;␊
}␊
␊
bool setup_ati_devprop(pci_dt_t *ati_dev)␊
{␊
␉char *devicepath;␊
␊
␉if (!init_card(ati_dev))␊
␉␉return false;␊
␊
␉/* ------------------------------------------------- */␊
␉/* Find a better way to do this (in device_inject.c) */␊
␉if (!string)␊
␉␉string = devprop_create_string();␊
␊
␉devicepath = get_pci_dev_path(ati_dev);␊
␉card->device = devprop_add_device(string, devicepath);␊
␉if (!card->device)␊
␉␉return false;␊
␉/* ------------------------------------------------- */␊
␊
#if 0␊
␉uint64_t fb␉␉= (uint32_t)card->fb;␊
␉uint64_t mmio␉= (uint32_t)card->mmio;␊
␉uint64_t io␉␉= (uint32_t)card->io;␊
␉devprop_add_value(card->device, "ATY,FrameBufferOffset", &fb, 8);␊
␉devprop_add_value(card->device, "ATY,RegisterSpaceOffset", &mmio, 8);␊
␉devprop_add_value(card->device, "ATY,IOSpaceOffset", &io, 8);␊
#endif␊
␊
␉devprop_add_list(ati_devprop_list);␊
␊
␉/* ------------------------------------------------- */␊
␉/* Find a better way to do this (in device_inject.c) */␊
␉stringdata = malloc(string->length);␊
␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
␉stringlength = string->length;␊
␉/* ------------------------------------------------- */␊
␊
␉verbose("ATI %s %s %dMB (%s) [%04x:%04x] (subsys [%04x:%04x]):: %s\n", ␊
␉␉␉chip_family_name[card->info->chip_family], card->info->model_name, ␊
␉␉␉(uint32_t)(card->vram_size / (1024 * 1024)), card_configs[card->info->cfg_name].name, ␊
␉␉␉ati_dev->vendor_id, ati_dev->device_id,␊
␉␉␉ati_dev->subsys_id.subsys.vendor_id, ati_dev->subsys_id.subsys.device_id, ␊
␉␉␉devicepath);␊
␊
␉free(card);␊
␊
␉return true;␊
}␊
␊
branches/Kabyl/i386/libsaio/platform.h
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#define SMB_MEM_CHANNEL_TRIPLE␉␉3␊
␊
/* Maximum number of ram slots */␊
#define MAX_RAM_SLOTS␉␉␉12␊
#define MAX_RAM_SLOTS␉␉␉8␊
#define RAM_SLOT_ENUMERATOR␉␉{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}␊
␊
/* Maximum number of SPD bytes */␊
branches/Kabyl/i386/libsaio/pci_setup.c
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#include "boot.h"␊
#include "bootstruct.h"␊
#include "pci.h"␊
#include "nvidia.h"␊
#include "ati.h"␊
␊
extern bool setup_nvidia_devprop(pci_dt_t *nvda_dev);␊
extern bool setup_ati_devprop(pci_dt_t *ati_dev);␊
extern void set_eth_builtin(pci_dt_t *eth_dev);␊
extern void notify_usb_dev(pci_dt_t *pci_dev);␊
extern void force_enable_hpet(pci_dt_t *lpc_dev);␊
␉␉␉␉␉switch (current->vendor_id)␊
␉␉␉␉␉{␊
␉␉␉␉␉␉case PCI_VENDOR_ID_ATI:␊
␉␉␉␉␉␉␉verbose("ATI VGA Controller [%04x:%04x] :: %s \n", ␊
␉␉␉␉␉␉␉current->vendor_id, current->device_id, devicepath);␊
␉␉␉␉␉␉␉setup_ati_devprop(current); ␊
␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␊
branches/Kabyl/i386/libsaio/ati_reg.h
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/*␊
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and␊
* VA Linux Systems Inc., Fremont, California.␊
*␊
* All Rights Reserved.␊
*␊
* Permission is hereby granted, free of charge, to any person obtaining␊
* a copy of this software and associated documentation files (the␊
* "Software"), to deal in the Software without restriction, including␊
* without limitation on the rights to use, copy, modify, merge,␊
* publish, distribute, sublicense, and/or sell copies of the Software,␊
* and to permit persons to whom the Software is furnished to do so,␊
* subject to the following conditions:␊
*␊
* The above copyright notice and this permission notice (including the␊
* next paragraph) shall be included in all copies or substantial␊
* portions of the Software.␊
*␊
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,␊
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF␊
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND␊
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR␊
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,␊
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER␊
* DEALINGS IN THE SOFTWARE.␊
*/␊
␊
/*␊
* Authors:␊
* Kevin E. Martin <martin@xfree86.org>␊
* Rickard E. Faith <faith@valinux.com>␊
* Alan Hourihane <alanh@fairlite.demon.co.uk>␊
*␊
* References:␊
*␊
* !!!! FIXME !!!!␊
* RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical␊
* Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April␊
* 1999.␊
*␊
* !!!! FIXME !!!!␊
* RAGE 128 Software Development Manual (Technical Reference Manual P/N␊
* SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.␊
*␊
*/␊
␊
/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h␊
* AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT␊
* ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */␊
␊
#ifndef _ATI_REG_H_␊
#define _ATI_REG_H_␊
␊
#define ATI_DATATYPE_VQ␉␉␉␉0␊
#define ATI_DATATYPE_CI4␉␉␉1␊
#define ATI_DATATYPE_CI8␉␉␉2␊
#define ATI_DATATYPE_ARGB1555␉␉␉3␊
#define ATI_DATATYPE_RGB565␉␉␉4␊
#define ATI_DATATYPE_RGB888␉␉␉5␊
#define ATI_DATATYPE_ARGB8888␉␉␉6␊
#define ATI_DATATYPE_RGB332␉␉␉7␊
#define ATI_DATATYPE_Y8␉␉␉␉8␊
#define ATI_DATATYPE_RGB8␉␉␉9␊
#define ATI_DATATYPE_CI16␉␉␉10␊
#define ATI_DATATYPE_VYUY_422␉␉␉11␊
#define ATI_DATATYPE_YVYU_422␉␉␉12␊
#define ATI_DATATYPE_AYUV_444␉␉␉14␊
#define ATI_DATATYPE_ARGB4444␉␉␉15␊
␊
␉␉␉␉/* Registers for 2D/Video/Overlay */␊
#define RADEON_ADAPTER_ID 0x0f2c /* PCI */␊
#define RADEON_AGP_BASE 0x0170␊
#define RADEON_AGP_CNTL 0x0174␊
# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)␊
# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)␊
# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)␊
# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)␊
# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)␊
# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)␊
# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)␊
# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)␊
#define RADEON_STATUS_PCI_CONFIG 0x06␊
# define RADEON_CAP_LIST 0x100000␊
#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/␊
# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */␊
# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */␊
# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */␊
# define RADEON_CAP_ID_EXP 0x10 /* PCI Express */␊
#define RADEON_AGP_COMMAND 0x0f60 /* PCI */␊
#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/␊
# define RADEON_AGP_ENABLE (1<<8)␊
#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */␊
#define RADEON_AGP_STATUS 0x0f5c /* PCI */␊
# define RADEON_AGP_1X_MODE 0x01␊
# define RADEON_AGP_2X_MODE 0x02␊
# define RADEON_AGP_4X_MODE 0x04␊
# define RADEON_AGP_FW_MODE 0x10␊
# define RADEON_AGP_MODE_MASK 0x17␊
# define RADEON_AGPv3_MODE 0x08␊
# define RADEON_AGPv3_4X_MODE 0x01␊
# define RADEON_AGPv3_8X_MODE 0x02␊
#define RADEON_ATTRDR 0x03c1 /* VGA */␊
#define RADEON_ATTRDW 0x03c0 /* VGA */␊
#define RADEON_ATTRX 0x03c0 /* VGA */␊
#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8␊
#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc␊
␊
#define RADEON_BASE_CODE 0x0f0b␊
#define RADEON_BIOS_0_SCRATCH 0x0010␊
# define RADEON_FP_PANEL_SCALABLE (1 << 16)␊
# define RADEON_FP_PANEL_SCALE_EN (1 << 17)␊
# define RADEON_FP_CHIP_SCALE_EN (1 << 18)␊
# define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)␊
# define RADEON_DISPLAY_ROT_MASK (3 << 28)␊
# define RADEON_DISPLAY_ROT_00 (0 << 28)␊
# define RADEON_DISPLAY_ROT_90 (1 << 28)␊
# define RADEON_DISPLAY_ROT_180 (2 << 28)␊
# define RADEON_DISPLAY_ROT_270 (3 << 28)␊
#define RADEON_BIOS_1_SCRATCH 0x0014␊
#define RADEON_BIOS_2_SCRATCH 0x0018␊
#define RADEON_BIOS_3_SCRATCH 0x001c␊
#define RADEON_BIOS_4_SCRATCH 0x0020␊
# define RADEON_CRT1_ATTACHED_MASK (3 << 0)␊
# define RADEON_CRT1_ATTACHED_MONO (1 << 0)␊
# define RADEON_CRT1_ATTACHED_COLOR (2 << 0)␊
# define RADEON_LCD1_ATTACHED (1 << 2)␊
# define RADEON_DFP1_ATTACHED (1 << 3)␊
# define RADEON_TV1_ATTACHED_MASK (3 << 4)␊
# define RADEON_TV1_ATTACHED_COMP (1 << 4)␊
# define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)␊
# define RADEON_CRT2_ATTACHED_MASK (3 << 8)␊
# define RADEON_CRT2_ATTACHED_MONO (1 << 8)␊
# define RADEON_CRT2_ATTACHED_COLOR (2 << 8)␊
# define RADEON_DFP2_ATTACHED (1 << 11)␊
#define RADEON_BIOS_5_SCRATCH 0x0024␊
# define RADEON_LCD1_ON (1 << 0)␊
# define RADEON_CRT1_ON (1 << 1)␊
# define RADEON_TV1_ON (1 << 2)␊
# define RADEON_DFP1_ON (1 << 3)␊
# define RADEON_CRT2_ON (1 << 5)␊
# define RADEON_CV1_ON (1 << 6)␊
# define RADEON_DFP2_ON (1 << 7)␊
# define RADEON_LCD1_CRTC_MASK (1 << 8)␊
# define RADEON_LCD1_CRTC_SHIFT 8␊
# define RADEON_CRT1_CRTC_MASK (1 << 9)␊
# define RADEON_CRT1_CRTC_SHIFT 9␊
# define RADEON_TV1_CRTC_MASK (1 << 10)␊
# define RADEON_TV1_CRTC_SHIFT 10␊
# define RADEON_DFP1_CRTC_MASK (1 << 11)␊
# define RADEON_DFP1_CRTC_SHIFT 11␊
# define RADEON_CRT2_CRTC_MASK (1 << 12)␊
# define RADEON_CRT2_CRTC_SHIFT 12␊
# define RADEON_CV1_CRTC_MASK (1 << 13)␊
# define RADEON_CV1_CRTC_SHIFT 13␊
# define RADEON_DFP2_CRTC_MASK (1 << 14)␊
# define RADEON_DFP2_CRTC_SHIFT 14␊
#define RADEON_BIOS_6_SCRATCH 0x0028␊
# define RADEON_ACC_MODE_CHANGE (1 << 2)␊
# define RADEON_EXT_DESKTOP_MODE (1 << 3)␊
# define RADEON_LCD_DPMS_ON (1 << 20)␊
# define RADEON_CRT_DPMS_ON (1 << 21)␊
# define RADEON_TV_DPMS_ON (1 << 22)␊
# define RADEON_DFP_DPMS_ON (1 << 23)␊
# define RADEON_DPMS_MASK (3 << 24)␊
# define RADEON_DPMS_ON (0 << 24)␊
# define RADEON_DPMS_STANDBY (1 << 24)␊
# define RADEON_DPMS_SUSPEND (2 << 24)␊
# define RADEON_DPMS_OFF (3 << 24)␊
# define RADEON_SCREEN_BLANKING (1 << 26)␊
# define RADEON_DRIVER_CRITICAL (1 << 27)␊
# define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)␊
#define RADEON_BIOS_7_SCRATCH 0x002c␊
# define RADEON_SYS_HOTKEY (1 << 10)␊
# define RADEON_DRV_LOADED (1 << 12)␊
#define RADEON_BIOS_ROM 0x0f30 /* PCI */␊
#define RADEON_BIST 0x0f0f /* PCI */␊
#define RADEON_BRUSH_DATA0 0x1480␊
#define RADEON_BRUSH_DATA1 0x1484␊
#define RADEON_BRUSH_DATA10 0x14a8␊
#define RADEON_BRUSH_DATA11 0x14ac␊
#define RADEON_BRUSH_DATA12 0x14b0␊
#define RADEON_BRUSH_DATA13 0x14b4␊
#define RADEON_BRUSH_DATA14 0x14b8␊
#define RADEON_BRUSH_DATA15 0x14bc␊
#define RADEON_BRUSH_DATA16 0x14c0␊
#define RADEON_BRUSH_DATA17 0x14c4␊
#define RADEON_BRUSH_DATA18 0x14c8␊
#define RADEON_BRUSH_DATA19 0x14cc␊
#define RADEON_BRUSH_DATA2 0x1488␊
#define RADEON_BRUSH_DATA20 0x14d0␊
#define RADEON_BRUSH_DATA21 0x14d4␊
#define RADEON_BRUSH_DATA22 0x14d8␊
#define RADEON_BRUSH_DATA23 0x14dc␊
#define RADEON_BRUSH_DATA24 0x14e0␊
#define RADEON_BRUSH_DATA25 0x14e4␊
#define RADEON_BRUSH_DATA26 0x14e8␊
#define RADEON_BRUSH_DATA27 0x14ec␊
#define RADEON_BRUSH_DATA28 0x14f0␊
#define RADEON_BRUSH_DATA29 0x14f4␊
#define RADEON_BRUSH_DATA3 0x148c␊
#define RADEON_BRUSH_DATA30 0x14f8␊
#define RADEON_BRUSH_DATA31 0x14fc␊
#define RADEON_BRUSH_DATA32 0x1500␊
#define RADEON_BRUSH_DATA33 0x1504␊
#define RADEON_BRUSH_DATA34 0x1508␊
#define RADEON_BRUSH_DATA35 0x150c␊
#define RADEON_BRUSH_DATA36 0x1510␊
#define RADEON_BRUSH_DATA37 0x1514␊
#define RADEON_BRUSH_DATA38 0x1518␊
#define RADEON_BRUSH_DATA39 0x151c␊
#define RADEON_BRUSH_DATA4 0x1490␊
#define RADEON_BRUSH_DATA40 0x1520␊
#define RADEON_BRUSH_DATA41 0x1524␊
#define RADEON_BRUSH_DATA42 0x1528␊
#define RADEON_BRUSH_DATA43 0x152c␊
#define RADEON_BRUSH_DATA44 0x1530␊
#define RADEON_BRUSH_DATA45 0x1534␊
#define RADEON_BRUSH_DATA46 0x1538␊
#define RADEON_BRUSH_DATA47 0x153c␊
#define RADEON_BRUSH_DATA48 0x1540␊
#define RADEON_BRUSH_DATA49 0x1544␊
#define RADEON_BRUSH_DATA5 0x1494␊
#define RADEON_BRUSH_DATA50 0x1548␊
#define RADEON_BRUSH_DATA51 0x154c␊
#define RADEON_BRUSH_DATA52 0x1550␊
#define RADEON_BRUSH_DATA53 0x1554␊
#define RADEON_BRUSH_DATA54 0x1558␊
#define RADEON_BRUSH_DATA55 0x155c␊
#define RADEON_BRUSH_DATA56 0x1560␊
#define RADEON_BRUSH_DATA57 0x1564␊
#define RADEON_BRUSH_DATA58 0x1568␊
#define RADEON_BRUSH_DATA59 0x156c␊
#define RADEON_BRUSH_DATA6 0x1498␊
#define RADEON_BRUSH_DATA60 0x1570␊
#define RADEON_BRUSH_DATA61 0x1574␊
#define RADEON_BRUSH_DATA62 0x1578␊
#define RADEON_BRUSH_DATA63 0x157c␊
#define RADEON_BRUSH_DATA7 0x149c␊
#define RADEON_BRUSH_DATA8 0x14a0␊
#define RADEON_BRUSH_DATA9 0x14a4␊
#define RADEON_BRUSH_SCALE 0x1470␊
#define RADEON_BRUSH_Y_X 0x1474␊
#define RADEON_BUS_CNTL 0x0030␊
# define RADEON_BUS_MASTER_DIS (1 << 6)␊
# define RADEON_BUS_BIOS_DIS_ROM (1 << 12)␊
# define RADEON_BUS_RD_DISCARD_EN (1 << 24)␊
# define RADEON_BUS_RD_ABORT_EN (1 << 25)␊
# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)␊
# define RADEON_BUS_WRT_BURST (1 << 29)␊
# define RADEON_BUS_READ_BURST (1 << 30)␊
#define RADEON_BUS_CNTL1 0x0034␊
# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)␊
␊
#define RADEON_PCIE_INDEX 0x0030␊
#define RADEON_PCIE_DATA 0x0034␊
#define R600_PCIE_PORT_INDEX 0x0038␊
#define R600_PCIE_PORT_DATA 0x003c␊
/* PCIE_LC_LINK_WIDTH_CNTL is PCIE on r1xx-r5xx, PCIE_PORT on r6xx-r7xx */␊
#define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */␊
# define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0␊
# define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7␊
# define RADEON_PCIE_LC_LINK_WIDTH_X0 0␊
# define RADEON_PCIE_LC_LINK_WIDTH_X1 1␊
# define RADEON_PCIE_LC_LINK_WIDTH_X2 2␊
# define RADEON_PCIE_LC_LINK_WIDTH_X4 3␊
# define RADEON_PCIE_LC_LINK_WIDTH_X8 4␊
# define RADEON_PCIE_LC_LINK_WIDTH_X12 5␊
# define RADEON_PCIE_LC_LINK_WIDTH_X16 6␊
# define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4␊
# define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70␊
# define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)␊
# define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)␊
# define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)␊
# define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)␊
# define R600_PCIE_LC_RENEGOTIATE_EN (1 << 10)␊
# define R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11)␊
#define R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c␊
#define R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c␊
␊
#define RADEON_CACHE_CNTL 0x1724␊
#define RADEON_CACHE_LINE 0x0f0c /* PCI */␊
#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */␊
#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */␊
#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */␊
# define RADEON_DONT_USE_XTALIN (1 << 4)␊
# define RADEON_SCLK_DYN_START_CNTL (1 << 15)␊
#define RADEON_CLOCK_CNTL_DATA 0x000c␊
#define RADEON_CLOCK_CNTL_INDEX 0x0008␊
# define RADEON_PLL_WR_EN (1 << 7)␊
# define RADEON_PLL_DIV_SEL (3 << 8)␊
# define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8)␊
#define RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */␊
# define RADEON_M_SPLL_REF_DIV_MASK 0xff␊
# define RADEON_M_SPLL_REF_DIV_SHIFT 0␊
# define RADEON_MPLL_FB_DIV_MASK 0xff␊
# define RADEON_MPLL_FB_DIV_SHIFT 8␊
# define RADEON_SPLL_FB_DIV_MASK 0xff␊
# define RADEON_SPLL_FB_DIV_SHIFT 16␊
#define RADEON_SPLL_CNTL 0x000c /* PLL */␊
# define RADEON_SPLL_SLEEP (1 << 0)␊
# define RADEON_SPLL_RESET (1 << 1)␊
# define RADEON_SPLL_PCP_MASK 0x7␊
# define RADEON_SPLL_PCP_SHIFT 8␊
# define RADEON_SPLL_PVG_MASK 0x7␊
# define RADEON_SPLL_PVG_SHIFT 11␊
# define RADEON_SPLL_PDC_MASK 0x3␊
# define RADEON_SPLL_PDC_SHIFT 14␊
#define RADEON_CLK_PWRMGT_CNTL 0x0014 /* PLL */␊
# define RADEON_ENGIN_DYNCLK_MODE (1 << 12)␊
# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13)␊
# define RADEON_ACTIVE_HILO_LAT_SHIFT 13␊
# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)␊
# define RADEON_MC_BUSY (1 << 16)␊
# define RADEON_DLL_READY (1 << 19)␊
# define RADEON_CG_NO1_DEBUG_0 (1 << 24)␊
# define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24)␊
# define RADEON_DYN_STOP_MODE_MASK (7 << 21)␊
# define RADEON_TVPLL_PWRMGT_OFF (1 << 30)␊
# define RADEON_TVCLK_TURNOFF (1 << 31)␊
#define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */␊
# define RADEON_TCL_BYPASS_DISABLE (1 << 20)␊
#define RADEON_CLR_CMP_CLR_3D 0x1a24␊
#define RADEON_CLR_CMP_CLR_DST 0x15c8␊
#define RADEON_CLR_CMP_CLR_SRC 0x15c4␊
#define RADEON_CLR_CMP_CNTL 0x15c0␊
# define RADEON_SRC_CMP_EQ_COLOR (4 << 0)␊
# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0)␊
# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24)␊
#define RADEON_CLR_CMP_MASK 0x15cc␊
# define RADEON_CLR_CMP_MSK 0xffffffff␊
#define RADEON_CLR_CMP_MASK_3D 0x1A28␊
#define RADEON_COMMAND 0x0f04 /* PCI */␊
#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c␊
#define RADEON_CONFIG_APER_0_BASE 0x0100␊
#define RADEON_CONFIG_APER_1_BASE 0x0104␊
#define RADEON_CONFIG_APER_SIZE 0x0108␊
#define RADEON_CONFIG_BONDS 0x00e8␊
#define RADEON_CONFIG_CNTL 0x00e0␊
# define RADEON_CFG_ATI_REV_A11 (0 << 16)␊
# define RADEON_CFG_ATI_REV_A12 (1 << 16)␊
# define RADEON_CFG_ATI_REV_A13 (2 << 16)␊
# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)␊
#define RADEON_CONFIG_MEMSIZE 0x00f8␊
#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114␊
#define RADEON_CONFIG_REG_1_BASE 0x010c␊
#define RADEON_CONFIG_REG_APER_SIZE 0x0110␊
#define RADEON_CONFIG_XSTRAP 0x00e4␊
#define RADEON_CONSTANT_COLOR_C 0x1d34␊
# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff␊
# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff␊
# define RADEON_CONSTANT_COLOR_ZERO 0x00000000␊
#define RADEON_CRC_CMDFIFO_ADDR 0x0740␊
#define RADEON_CRC_CMDFIFO_DOUT 0x0744␊
#define RADEON_GRPH_BUFFER_CNTL 0x02f0␊
# define RADEON_GRPH_START_REQ_MASK (0x7f)␊
# define RADEON_GRPH_START_REQ_SHIFT 0␊
# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)␊
# define RADEON_GRPH_STOP_REQ_SHIFT 8␊
# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)␊
# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16␊
# define RADEON_GRPH_CRITICAL_CNTL (1<<28)␊
# define RADEON_GRPH_BUFFER_SIZE (1<<29)␊
# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)␊
# define RADEON_GRPH_STOP_CNTL (1<<31)␊
#define RADEON_GRPH2_BUFFER_CNTL 0x03f0␊
# define RADEON_GRPH2_START_REQ_MASK (0x7f)␊
# define RADEON_GRPH2_START_REQ_SHIFT 0␊
# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)␊
# define RADEON_GRPH2_STOP_REQ_SHIFT 8␊
# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)␊
# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16␊
# define RADEON_GRPH2_CRITICAL_CNTL (1<<28)␊
# define RADEON_GRPH2_BUFFER_SIZE (1<<29)␊
# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)␊
# define RADEON_GRPH2_STOP_CNTL (1<<31)␊
#define RADEON_CRTC_CRNT_FRAME 0x0214␊
#define RADEON_CRTC_EXT_CNTL 0x0054␊
# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0)␊
# define RADEON_VGA_ATI_LINEAR (1 << 3)␊
# define RADEON_XCRT_CNT_EN (1 << 6)␊
# define RADEON_CRTC_HSYNC_DIS (1 << 8)␊
# define RADEON_CRTC_VSYNC_DIS (1 << 9)␊
# define RADEON_CRTC_DISPLAY_DIS (1 << 10)␊
# define RADEON_CRTC_SYNC_TRISTAT (1 << 11)␊
# define RADEON_CRTC_CRT_ON (1 << 15)␊
#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055␊
# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0)␊
# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1)␊
# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2)␊
#define RADEON_CRTC_GEN_CNTL 0x0050␊
# define RADEON_CRTC_DBL_SCAN_EN (1 << 0)␊
# define RADEON_CRTC_INTERLACE_EN (1 << 1)␊
# define RADEON_CRTC_CSYNC_EN (1 << 4)␊
# define RADEON_CRTC_ICON_EN (1 << 15)␊
# define RADEON_CRTC_CUR_EN (1 << 16)␊
# define RADEON_CRTC_CUR_MODE_MASK (7 << 20)␊
# define RADEON_CRTC_EXT_DISP_EN (1 << 24)␊
# define RADEON_CRTC_EN (1 << 25)␊
# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26)␊
#define RADEON_CRTC2_GEN_CNTL 0x03f8␊
# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0)␊
# define RADEON_CRTC2_INTERLACE_EN (1 << 1)␊
# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4)␊
# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)␊
# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)␊
# define RADEON_CRTC2_CRT2_ON (1 << 7)␊
# define RADEON_CRTC2_PIX_WIDTH_SHIFT 8␊
# define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8)␊
# define RADEON_CRTC2_ICON_EN (1 << 15)␊
# define RADEON_CRTC2_CUR_EN (1 << 16)␊
# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20)␊
# define RADEON_CRTC2_DISP_DIS (1 << 23)␊
# define RADEON_CRTC2_EN (1 << 25)␊
# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26)␊
# define RADEON_CRTC2_CSYNC_EN (1 << 27)␊
# define RADEON_CRTC2_HSYNC_DIS (1 << 28)␊
# define RADEON_CRTC2_VSYNC_DIS (1 << 29)␊
#define RADEON_CRTC_MORE_CNTL 0x27c␊
# define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2)␊
# define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3)␊
# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)␊
# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)␊
#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218␊
# define RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT 0␊
# define RADEON_CRTC_GUI_TRIG_VLINE_INV (1 << 15)␊
# define RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT 16␊
# define RADEON_CRTC_GUI_TRIG_VLINE_STALL (1 << 30)␊
#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204␊
# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)␊
# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)␊
# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3␊
# define RADEON_CRTC_H_SYNC_WID (0x3f << 16)␊
# define RADEON_CRTC_H_SYNC_WID_SHIFT 16␊
# define RADEON_CRTC_H_SYNC_POL (1 << 23)␊
#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304␊
# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)␊
# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)␊
# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3␊
# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16)␊
# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16␊
# define RADEON_CRTC2_H_SYNC_POL (1 << 23)␊
#define RADEON_CRTC_H_TOTAL_DISP 0x0200␊
# define RADEON_CRTC_H_TOTAL (0x03ff << 0)␊
# define RADEON_CRTC_H_TOTAL_SHIFT 0␊
# define RADEON_CRTC_H_DISP (0x01ff << 16)␊
# define RADEON_CRTC_H_DISP_SHIFT 16␊
#define RADEON_CRTC2_H_TOTAL_DISP 0x0300␊
# define RADEON_CRTC2_H_TOTAL (0x03ff << 0)␊
# define RADEON_CRTC2_H_TOTAL_SHIFT 0␊
# define RADEON_CRTC2_H_DISP (0x01ff << 16)␊
# define RADEON_CRTC2_H_DISP_SHIFT 16␊
␊
#define RADEON_CRTC_OFFSET_RIGHT␉ 0x0220␊
#define RADEON_CRTC_OFFSET 0x0224␊
#␉define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)␊
#␉define RADEON_CRTC_OFFSET__OFFSET_LOCK ␉ (1<<31)␊
␊
#define RADEON_CRTC2_OFFSET 0x0324␊
#␉define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)␊
#␉define RADEON_CRTC2_OFFSET__OFFSET_LOCK␉ (1<<31)␊
#define RADEON_CRTC_OFFSET_CNTL 0x0228␊
# define RADEON_CRTC_TILE_LINE_SHIFT 0␊
# define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4␊
#␉define R300_CRTC_X_Y_MODE_EN_RIGHT␉␉(1 << 6)␊
#␉define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7)␊
#␉define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7)␊
#␉define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)␊
#␉define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)␊
#␉define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7)␊
#␉define R300_CRTC_X_Y_MODE_EN␉␉␉(1 << 9)␊
#␉define R300_CRTC_MICRO_TILE_BUFFER_MASK ␉(3 << 10)␊
#␉define R300_CRTC_MICRO_TILE_BUFFER_AUTO ␉(0 << 10)␊
#␉define R300_CRTC_MICRO_TILE_BUFFER_SINGLE ␉(1 << 10)␊
#␉define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE ␉(2 << 10)␊
#␉define R300_CRTC_MICRO_TILE_BUFFER_DIS ␉(3 << 10)␊
#␉define R300_CRTC_MICRO_TILE_EN_RIGHT␉␉(1 << 12)␊
#␉define R300_CRTC_MICRO_TILE_EN␉␉␉(1 << 13)␊
#␉define R300_CRTC_MACRO_TILE_EN_RIGHT␉␉(1 << 14)␊
# define R300_CRTC_MACRO_TILE_EN (1 << 15)␊
# define RADEON_CRTC_TILE_EN_RIGHT (1 << 14)␊
# define RADEON_CRTC_TILE_EN (1 << 15)␊
# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)␊
# define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)␊
␊
#define R300_CRTC_TILE_X0_Y0␉ 0x0350␊
#define R300_CRTC2_TILE_X0_Y0␉ 0x0358␊
␊
#define RADEON_CRTC2_OFFSET_CNTL 0x0328␊
# define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16)␊
# define RADEON_CRTC2_TILE_EN (1 << 15)␊
#define RADEON_CRTC_PITCH 0x022c␊
#␉define RADEON_CRTC_PITCH__SHIFT␉␉ 0␊
#␉define RADEON_CRTC_PITCH__RIGHT_SHIFT␉16␊
␊
#define RADEON_CRTC2_PITCH 0x032c␊
#define RADEON_CRTC_STATUS 0x005c␊
# define RADEON_CRTC_VBLANK_SAVE (1 << 1)␊
# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1)␊
#define RADEON_CRTC2_STATUS 0x03fc␊
# define RADEON_CRTC2_VBLANK_SAVE (1 << 1)␊
# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1)␊
#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c␊
# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0)␊
# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0␊
# define RADEON_CRTC_V_SYNC_WID (0x1f << 16)␊
# define RADEON_CRTC_V_SYNC_WID_SHIFT 16␊
# define RADEON_CRTC_V_SYNC_POL (1 << 23)␊
#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c␊
# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0)␊
# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0␊
# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16)␊
# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16␊
# define RADEON_CRTC2_V_SYNC_POL (1 << 23)␊
#define RADEON_CRTC_V_TOTAL_DISP 0x0208␊
# define RADEON_CRTC_V_TOTAL (0x07ff << 0)␊
# define RADEON_CRTC_V_TOTAL_SHIFT 0␊
# define RADEON_CRTC_V_DISP (0x07ff << 16)␊
# define RADEON_CRTC_V_DISP_SHIFT 16␊
#define RADEON_CRTC2_V_TOTAL_DISP 0x0308␊
# define RADEON_CRTC2_V_TOTAL (0x07ff << 0)␊
# define RADEON_CRTC2_V_TOTAL_SHIFT 0␊
# define RADEON_CRTC2_V_DISP (0x07ff << 16)␊
# define RADEON_CRTC2_V_DISP_SHIFT 16␊
#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210␊
# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16)␊
#define RADEON_CRTC2_CRNT_FRAME 0x0314␊
#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318␊
#define RADEON_CRTC2_STATUS 0x03fc␊
#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310␊
#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */␊
#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */␊
#define RADEON_CUR_CLR0 0x026c␊
#define RADEON_CUR_CLR1 0x0270␊
#define RADEON_CUR_HORZ_VERT_OFF 0x0268␊
#define RADEON_CUR_HORZ_VERT_POSN 0x0264␊
#define RADEON_CUR_OFFSET 0x0260␊
# define RADEON_CUR_LOCK (1 << 31)␊
#define RADEON_CUR2_CLR0 0x036c␊
#define RADEON_CUR2_CLR1 0x0370␊
#define RADEON_CUR2_HORZ_VERT_OFF 0x0368␊
#define RADEON_CUR2_HORZ_VERT_POSN 0x0364␊
#define RADEON_CUR2_OFFSET 0x0360␊
# define RADEON_CUR2_LOCK (1 << 31)␊
␊
#define RADEON_DAC_CNTL 0x0058␊
# define RADEON_DAC_RANGE_CNTL (3 << 0)␊
# define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0)␊
# define RADEON_DAC_RANGE_CNTL_MASK 0x03␊
# define RADEON_DAC_BLANKING (1 << 2)␊
# define RADEON_DAC_CMP_EN (1 << 3)␊
# define RADEON_DAC_CMP_OUTPUT (1 << 7)␊
# define RADEON_DAC_8BIT_EN (1 << 8)␊
# define RADEON_DAC_TVO_EN (1 << 10)␊
# define RADEON_DAC_VGA_ADR_EN (1 << 13)␊
# define RADEON_DAC_PDWN (1 << 15)␊
# define RADEON_DAC_MASK_ALL (0xff << 24)␊
#define RADEON_DAC_CNTL2 0x007c␊
# define RADEON_DAC2_TV_CLK_SEL (0 << 1)␊
# define RADEON_DAC2_DAC_CLK_SEL (1 << 0)␊
# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1)␊
# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)␊
# define RADEON_DAC2_CMP_EN (1 << 7)␊
# define RADEON_DAC2_CMP_OUT_R (1 << 8)␊
# define RADEON_DAC2_CMP_OUT_G (1 << 9)␊
# define RADEON_DAC2_CMP_OUT_B (1 << 10)␊
# define RADEON_DAC2_CMP_OUTPUT (1 << 11)␊
#define RADEON_DAC_EXT_CNTL 0x0280␊
# define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)␊
# define RADEON_DAC2_FORCE_DATA_EN (1 << 1)␊
# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)␊
# define RADEON_DAC_FORCE_DATA_EN (1 << 5)␊
# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)␊
# define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6)␊
# define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6)␊
# define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6)␊
# define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6)␊
# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00␊
# define RADEON_DAC_FORCE_DATA_SHIFT 8␊
#define RADEON_DAC_MACRO_CNTL 0x0d04␊
# define RADEON_DAC_PDWN_R (1 << 16)␊
# define RADEON_DAC_PDWN_G (1 << 17)␊
# define RADEON_DAC_PDWN_B (1 << 18)␊
#define RADEON_TV_DAC_CNTL 0x088c␊
# define RADEON_TV_DAC_NBLANK (1 << 0)␊
# define RADEON_TV_DAC_NHOLD (1 << 1)␊
# define RADEON_TV_DAC_PEDESTAL (1 << 2)␊
# define RADEON_TV_MONITOR_DETECT_EN (1 << 4)␊
# define RADEON_TV_DAC_CMPOUT (1 << 5)␊
# define RADEON_TV_DAC_STD_MASK (3 << 8)␊
# define RADEON_TV_DAC_STD_PAL (0 << 8)␊
# define RADEON_TV_DAC_STD_NTSC (1 << 8)␊
# define RADEON_TV_DAC_STD_PS2 (2 << 8)␊
# define RADEON_TV_DAC_STD_RS343 (3 << 8)␊
# define RADEON_TV_DAC_BGSLEEP (1 << 6)␊
# define RADEON_TV_DAC_BGADJ_MASK (0xf << 16)␊
# define RADEON_TV_DAC_BGADJ_SHIFT 16␊
# define RADEON_TV_DAC_DACADJ_MASK (0xf << 20)␊
# define RADEON_TV_DAC_DACADJ_SHIFT 20␊
# define RADEON_TV_DAC_RDACPD (1 << 24)␊
# define RADEON_TV_DAC_GDACPD (1 << 25)␊
# define RADEON_TV_DAC_BDACPD (1 << 26)␊
# define RADEON_TV_DAC_RDACDET (1 << 29)␊
# define RADEON_TV_DAC_GDACDET (1 << 30)␊
# define RADEON_TV_DAC_BDACDET (1 << 31)␊
# define R420_TV_DAC_DACADJ_MASK (0x1f << 20)␊
# define R420_TV_DAC_RDACPD (1 << 25)␊
# define R420_TV_DAC_GDACPD (1 << 26)␊
# define R420_TV_DAC_BDACPD (1 << 27)␊
# define R420_TV_DAC_TVENABLE (1 << 28)␊
#define RADEON_DISP_HW_DEBUG 0x0d14␊
# define RADEON_CRT2_DISP1_SEL (1 << 5)␊
#define RADEON_DISP_OUTPUT_CNTL 0x0d64␊
# define RADEON_DISP_DAC_SOURCE_MASK 0x03␊
# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c␊
# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01␊
# define RADEON_DISP_DAC_SOURCE_RMX 0x02␊
# define RADEON_DISP_DAC_SOURCE_LTU 0x03␊
# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04␊
# define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2)␊
# define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0␊
# define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2)␊
# define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2)␊
# define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2)␊
# define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4)␊
# define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4)␊
# define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4)␊
# define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4)␊
# define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */␊
# define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */␊
#define RADEON_DISP_TV_OUT_CNTL 0x0d6c␊
# define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16)␊
# define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)␊
#define RADEON_DAC_CRC_SIG 0x02cc␊
#define RADEON_DAC_DATA 0x03c9 /* VGA */␊
#define RADEON_DAC_MASK 0x03c6 /* VGA */␊
#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */␊
#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */␊
#define RADEON_DDA_CONFIG 0x02e0␊
#define RADEON_DDA_ON_OFF 0x02e4␊
#define RADEON_DEFAULT_OFFSET 0x16e0␊
#define RADEON_DEFAULT_PITCH 0x16e4␊
#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8␊
# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)␊
# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)␊
#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820␊
#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824␊
#define RADEON_DEVICE_ID 0x0f02 /* PCI */␊
#define RADEON_DISP_MISC_CNTL 0x0d00␊
# define RADEON_SOFT_RESET_GRPH_PP (1 << 0)␊
#define RADEON_DISP_MERGE_CNTL␉␉ 0x0d60␊
# define RADEON_DISP_ALPHA_MODE_MASK 0x03