Chameleon

Chameleon Commit Details

Date:2010-12-16 10:42:27 (13 years 4 months ago)
Author:Kabyl
Commit:674
Parents: 673
Message:merged changes from trunk
Changes:
M/branches/Kabyl/i386/libsaio/aml_generator.c
M/branches/Kabyl/i386/libsaio/acpi_patcher.c
M/branches/Kabyl/i386/libsaio/console.c
M/branches/Kabyl/doc/BootHelp.txt
M/branches/Kabyl/i386/libsaio/nvidia.c
M/branches/Kabyl/i386/boot2/boot.h
M/branches/Kabyl/CHANGES
M/branches/Kabyl/i386/libsa/zalloc.c

File differences

branches/Kabyl/doc/BootHelp.txt
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␊
GraphicsEnabler=Yes|No Automatic device-properties generation for gfx cards.␊
UseAtiROM=Yes|No Use an alternate Ati ROM image ␊
(path: /Extra/<vendorid>_<devid>.rom)␊
(path: /Extra/<vendorid>_<devid>_<subsysid>.rom)␊
UseNvidiaROM=Yes|No Use an alternate Nvidia ROM image ␊
(path: /Extra/<vendorid>_<devid>.rom)␊
VBIOS=Yes|No Inject VBIOS to device-properties.␊
␊
AtiConfig=<cardcfg> Use a different card config (the list can be found in ati.c).␊
␊
EthernetBuiltIn=Yes|No Automatic "built-in"=yes device-properties generation␊
for ethernet interfaces.␊
␊
␊
DropSSDT=Yes Skip the SSDT tables while relocating the ACPI tables.␊
DSDT=<file> Use an alternate DSDT.aml file ␊
(default path: /DSDT.aml /Extra/DSDT.aml bt(0,0)/Extra/DSDT.aml).␊
(default paths:␊
/DSDT.aml /Extra/DSDT.aml bt(0,0)/Extra/DSDT.aml).␊
␊
GenerateCStates=Yes Enable auto generation of Processor (C-States) and/or␊
GeneratePStates=Yes Performance (P-States) power states.␊
␊
EnableC2State=Yes Enable specific Processor power states, C2,␊
EnableC3State=Yes C3␊
EnableC4State=Yes and C4.␊
␊
SMBIOS=<file> Use an alternate SMBIOS.plist file ␊
(default path: /Extra/SMBIOS.plist bt(0,0)/Extra/SMBIOS.plist).␊
(default paths:␊
/Extra/SMBIOS.plist bt(0,0)/Extra/SMBIOS.plist).␊
␊
SMBIOSdefaults=No Don't use the Default values for SMBIOS overriding␊
if smbios.plist doesn't exist, factory␊
branches/Kabyl/CHANGES
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- Added new ATi/AMD Graphics Card Enabler␊
- Added automatic P-States & C-States generation for native power management.␊
- Added Booter Log Dump Tool␊
- Added Booter message Logging (":/boot-log" ioreg property)␊
- Removed obsolete -f option, use -x instead␊
- Removed -x32 option, use arch=i386 instead␊
- Added automatic SMBusspeed detection for lga1156 core i5/7 cpus␊
- Added new iMac11,1 sbios default model for lga1156 core i5/17 mobos␊
- Optimized cursor spinout in textmode if no verbose mode is set␊
- Added ram table structures definitions␊
- Added getSmbios() a param permitting to select between orig and new smbios entries␊
- Changed "Default Partition" behaviour to accept only native system volumes or foreign partitions.␊
- Changed "Default Partition" behavior to accept only native system volumes or foreign partitions.␊
- Added NVIDIA new NVCAP customization support and support for ION gfx cards from aserebln␊
- Added ATI new framebuffers support and new cards from PCEFI10.6␊
- improved ACPI file search algo by implementing a cache.␊
- Nvidia injection fix␊
- pciroot would not always return correct uuid in autodection mode␊
- pciroot would not always return correct uid in autodection mode␊
- Fixed the hibernation problem in boot2/resume.c␊
- Fixed all new booter versions with SystemType would override the facp value even if correct,␊
now keeps the facp value if correct and no override has been done, implemented a best effort algo.␊
conversions api, to be completed by function that we should reuse.␊
␊
- Fixed SystemType would be always forced to a value, now optionally changed␊
only if ovveriden␊
only if overriden␊
- Kept SystemID as the only option to change manually the system-id ␊
For theses reasons, SystemId from bootConfig and SMUUID from smbiosConfig aer now DEPRECATED.␊
For theses reasons, SystemId from bootConfig and SMUUID from smbiosConfig are now DEPRECATED.␊
␊
- Integrated JrCs fadt patch (kept for RC5 the existing DSDT.aml retry algo that disapeared in his patch, should be more discussed for RC6)␊
- Integrated JrCs fadt patch (kept for RC5 the existing DSDT.aml retry algo that disappeared in his patch, should be more discussed for RC6)␊
- Added JrCs modified convention name change to coding_standards␊
- Now malloc (ex. MALLOC in Asere patch) is renamed malloc(size) and is an alias ␊
to safe_malloc(size, file, line) with _FILE_ and _LINE_ prerocessor definitions␊
to safe_malloc(size, file, line) with _FILE_ and _LINE_ preprocessor definitions␊
- Added a new 'Rename Partition Feature', now permitting to rename partition ␊
like 'System reserved' to a more meaningful name␊
- Added SystemID option permitting to change the System UUID to a fixed value.␊
branches/Kabyl/i386/libsaio/console.c
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bool gErrors;␊
␊
/* Kabyl: BooterLog */␊
#define BOOTER_LOG_SIZE␉(64 * 1024)␊
#define SAFE_LOG_SIZE␉80␊
//Azi: Doubled log available size.␊
// 64kb are not enough to hold the full log while booting with -f argument (ignore caches).␊
// It also seems to fix some reported problems while booting with the mentioned argument.␊
// Note: 96kb are enough to hold full log, booting with -f; even so, this depends on how much␊
// we "play" at the boot prompt, with what patches we're playing and how much they print to the log,␊
// kexts loaded, etc...␊
// Please remove this comment when this gets checked by a "true" dev.␊
#define BOOTER_LOG_SIZE␉(128 * 1024)␊
#define SAFE_LOG_SIZE␉134␊
␊
char *msgbuf = 0;␊
char *cursor = 0;␊
branches/Kabyl/i386/libsaio/acpi_patcher.c
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␉␊
␉if (acpi_cpu_count > 0) ␊
␉{␊
␉␉bool c2_enabled = fadt->C2_Latency < 100;␊
␉␉bool c3_enabled = fadt->C3_Latency < 1000;␊
␉␉bool c2_enabled = false;␊
␉␉bool c3_enabled = false;␊
␉␉bool c4_enabled = false;␊
␉␉␊
␉␉getBoolForKey(kEnableC2States, &c2_enabled, &bootInfo->bootConfig);␊
␉␉getBoolForKey(kEnableC3States, &c3_enabled, &bootInfo->bootConfig);␊
␉␉getBoolForKey(kEnableC4States, &c4_enabled, &bootInfo->bootConfig);␊
␉␉␊
␉␉c2_enabled = c2_enabled | (fadt->C2_Latency < 100);␊
␉␉c3_enabled = c3_enabled | (fadt->C3_Latency < 1000);␊
␊
␉␉unsigned char cstates_count = 1 + (c2_enabled ? 1 : 0) + (c3_enabled ? 1 : 0);␊
␉␉␊
␉␉␉␉␉␉if (maximum.CID < minimum.CID) ␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉DBG("Insane FID values!");␊
␉␉␉␉␉␉␉p_states_count = 1;␊
␉␉␉␉␉␉␉p_states_count = 0;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉else␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉␊
␉␉␉␉␉␉␉p_states_count -= invalid;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉} break;␊
␉␉␉␉␉␉␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉} ␊
␉␉␉␉␉case CPU_MODEL_FIELDS:␊
␉␉␉␉␉case CPU_MODEL_DALES:␊
␉␉␉␉␉case CPU_MODEL_DALES_32NM:␊
␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
␉␉␉␉␉case CPU_MODEL_WESTMERE:␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊
␉␉␉␉␉{␊
␉␉␉␉␉␉maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; // Seems it always contains maximum multiplier value (with turbo, that's we need)...␊
␉␉␉␉␉␉minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff;␊
␉␉␉␉␉␉␊
␉␉␉␉␉␉verbose("P-States: min 0x%x, max 0x%x\n", minimum.Control, maximum.Control);␉␉␉␊
␉␉␉␉␉␉␊
␉␉␉␉␉␉// Sanity check␊
␉␉␉␉␉␉if (maximum.Control < minimum.Control) ␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉DBG("Insane control values!");␊
␉␉␉␉␉␉␉p_states_count = 0;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉else␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉uint8_t i;␊
␉␉␉␉␉␉␉p_states_count = 0;␊
␉␉␉␉␉␉␉␊
␉␉␉␉␉␉␉for (i = maximum.Control; i >= minimum.Control; i--) ␊
␉␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉␉p_states[p_states_count].Control = i;␊
␉␉␉␉␉␉␉␉p_states[p_states_count].CID = p_states[p_states_count].Control << 1;␊
␉␉␉␉␉␉␉␉p_states[p_states_count].Frequency = (Platform.CPU.FSBFrequency / 1000000) * i;␊
␉␉␉␉␉␉␉␉p_states_count++;␊
␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉}␉␊
␉␉␉␉␉default:␊
␉␉␉␉␉␉verbose ("Unsupported CPU: P-States not generated !!!\n");␊
␉␉␉␉␉␉break;␊
branches/Kabyl/i386/libsaio/aml_generator.c
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␉␉␉case AML_CHUNK_DWORD:␊
␉␉␉case AML_CHUNK_QWORD:␊
␉␉␉case AML_CHUNK_ALIAS:␊
␉␉␉␉verbose("aml_add_to_parent: Node isn't supports child nodes!");␊
␉␉␉␉return FALSE;␊
␉␉␉␉verbose("aml_add_to_parent: node doesn't support child nodes!");␊
␉␉␉␉return false;␊
␉␉␉case AML_CHUNK_NAME:␊
␉␉␉␉if (parent->First) ␊
␉␉␉␉{␊
␉␉␉␉␉verbose("aml_add_to_parent: Name node could have only one child node!");␊
␉␉␉␉␉return FALSE;␊
␉␉␉␉␉verbose("aml_add_to_parent: name node supports only one child node!");␊
␉␉␉␉␉return false;␊
␉␉␉␉}␊
␉␉␉␉break;␊
␊
␉␉␊
␉␉parent->Last = node;␊
␉␉␊
␉␉return TRUE;␊
␉␉return true;␊
␉}␊
␉␊
␉return FALSE;␊
␉return false;␊
}␊
␊
struct aml_chunk* aml_create_node(struct aml_chunk* parent)␊
{␊
␉if (strlen(name) < 4) ␊
␉{␊
␉␉verbose("aml_fill_simple_name: simple name %s has incorrect lengh! Must be 4", name);␊
␉␉verbose("aml_fill_simple_name: simple name %s has incorrect lengh! Must be 4.", name);␊
␉␉return 0;␊
␉}␊
␉␊
␉␊
␉if ((len % 4) > 1 || count == 0) ␊
␉{␊
␉␉verbose("aml_fill_name: pathname %s has incorrect length! Must be 4, 8, 12, 16 etc.", name);␊
␉␉verbose("aml_fill_name: pathname %s has incorrect length! Must be 4, 8, 12, 16, etc...", name);␊
␉␉return 0;␊
␉}␊
␉␊
branches/Kabyl/i386/libsaio/nvidia.c
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␉{ 0x10DE065A, "Quadro FX 1700M" },␊
␉{ 0x10DE065B, "GeForce 9400 GT" },␊
␉{ 0x10DE065C, "Quadro FX 770M" },␊
␉{ 0x10DE06C0, "GeForce GTX 480" },␊
␉{ 0x10DE06C4, "GeForce GTX 465" },␊
␉{ 0x10DE06CA, "GeForce GTX 480M" },␊
␉{ 0x10DE06CD, "GeForce GTX 470" },␊
␉{ 0x10DE06E0, "GeForce 9300 GE" },␊
␉{ 0x10DE06E1, "GeForce 9300 GS" },␊
␉{ 0x10DE06E4, "GeForce 8400 GS" },␊
␉{ 0x10DE06F9, "Quadro FX 370 LP" },␊
␉{ 0x10DE06FA, "Quadro NVS 450" },␊
␉{ 0x10DE06FD, "Quadro NVS 295" },␊
␉{ 0x10DE086A, "GeForce 9400" },␊
␉{ 0x10DE0874, "ION 9300M" },␉␊
␉{ 0x10DE086C, "GeForce 9300/nForce 730i" },␊
␉{ 0x10DE087D, "ION 9400M" },␊
␉{ 0x10DE087E, "ION LE" },␊
␉{ 0x10DE0A20, "GeForce GT220" },␊
␉{ 0x10DE0A23, "GeForce 210" },␊
␉{ 0x10DE0A28, "GeForce GT 230M" },␊
␉{ 0x10DE0A29, "GeForce GT 330M" },␊
␉{ 0x10DE0A2A, "GeForce GT 230M" },␊
␉{ 0x10DE0A34, "GeForce GT 240M" },␊
␉{ 0x10DE0A60, "GeForce G210" },␊
␉{ 0x10DE0A65, "GeForce 210" },␊
␉{ 0x10DE0A66, "GeForce 310" },␊
␉{ 0x10DE0A74, "GeForce G210M" },␊
␉{ 0x10DE0A75, "GeForce G310M" },␊
␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊
␉{ 0x10DE0CA3, "GeForce GT 240" },␊
␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊
␉{ 0x10DE0CA9, "GeForce GTS 250M" },␊
␉{ 0x10DE0CB1, "GeForce GTS 360M" },␊
␉{ 0x10DE0CA3, "GeForce GT240" },␊
␉{ 0x10DE0E22, "GeForce GTX 460" },␊
␉{ 0x10DE0E24, "GeForce GTX 460" },␊
␉␊
␉// 06C0 - 06DFF␊
␉{ 0x10DE06C0, "GeForce GTX 480" },␊
␉{ 0x10DE06C3, "GeForce GTX D12U" },␊
␉{ 0x10DE06C4, "GeForce GTX 465" },␊
␉{ 0x10DE06CA, "GeForce GTX 480M" },␊
␉{ 0x10DE06CD, "GeForce GTX 470" },␊
␉{ 0x10DE06D1, "Tesla C2050" },␉// TODO: sub-device id: 0x0771␊
␉{ 0x10DE06D1, "Tesla C2070" },␉// TODO: sub-device id: 0x0772␊
␉{ 0x10DE06D2, "Tesla M2070" },␊
␉{ 0x10DE06D8, "Quadro 6000" },␊
␉{ 0x10DE06D9, "Quadro 5000" },␊
␉{ 0x10DE06DA, "Quadro 5000M" },␊
␉{ 0x10DE06DC, "Quadro 6000" },␊
␉{ 0x10DE06DE, "Tesla M2050" },␉// TODO: sub-device id: 0x0846␊
␉{ 0x10DE06DE, "Tesla M2070" }␉// TODO: sub-device id: ?␊
␉{ 0x10DE06DE, "Tesla M2070" },␉// TODO: sub-device id: ?␊
␉// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070␊
␉{ 0x10DE06DD, "Quadro 4000" },␊
␉␊
␉// 0DC0 - 0DFF␊
␉{ 0x10DE0DC0, "GeForce GT 440" },␊
␉{ 0x10DE0DC1, "D12-P1-35" },␊
␉{ 0x10DE0DC2, "D12-P1-35" },␊
␉{ 0x10DE0DC4, "GeForce GTS 450" },␊
␉{ 0x10DE0DC5, "GeForce GTS 450" },␊
␉{ 0x10DE0DC6, "GeForce GTS 450" },␊
␉{ 0x10DE0DCA, "GF10x" },␊
␉{ 0x10DE0DD1, "GeForce GTX 460M" },␊
␉{ 0x10DE0DD2, "GeForce GT 445M" },␊
␉{ 0x10DE0DD3, "GeForce GT 435M" },␊
␉{ 0x10DE0DD8, "Quadro 2000" },␊
␉{ 0x10DE0DDE, "GF106-ES" },␊
␉{ 0x10DE0DDF, "GF106-INT" },␊
␉{ 0x10DE0DE1, "GeForce GT 430" },␊
␉{ 0x10DE0DE2, "GeForce GT 420" },␊
␉{ 0x10DE0DEB, "GeForce GT 555M" },␊
␉{ 0x10DE0DEE, "GeForce GT 415M" },␊
␉{ 0x10DE0DF0, "GeForce GT 425M" },␊
␉{ 0x10DE0DF1, "GeForce GT 420M" },␊
␉{ 0x10DE0DF2, "GeForce GT 435M" },␊
␉{ 0x10DE0DF3, "GeForce GT 420M" },␊
␉{ 0x10DE0DF8, "Quadro 600" },␊
␉{ 0x10DE0DFE, "GF108 ES" },␊
␉{ 0x10DE0DFF, "GF108 INT" },␊
␉␊
␉// 0E20 - 0E3F␊
␉{ 0x10DE0E21, "D12U-25" },␊
␉{ 0x10DE0E22, "GeForce GTX 460" },␊
␉{ 0x10DE0E23, "GeForce GTX 460 SE" },␊
␉{ 0x10DE0E24, "GeForce GTX 460" },␊
␉{ 0x10DE0E25, "D12U-50" },␊
␉{ 0x10DE0E30, "GeForce GTX 470M" },␊
␉{ 0x10DE0E38, "GF104GL" },␊
␉{ 0x10DE0E3E, "GF104-ES" },␊
␉{ 0x10DE0E3F, "GF104-INT" },␊
␉␊
␉// 0EE0 - 0EFF: none yet␊
␉// 0F00 - 0F3F: none yet␊
␉// 1040 - 107F: none yet␊
␉␊
␉// 1080 - 109F␊
␉{ 0x10DE1080, "GeForce GTX 580" },␊
␉{ 0x10DE1081, "D13U" },␊
␉{ 0x10DE1082, "D13U" },␊
␉{ 0x10DE1083, "D13U" },␊
␉{ 0x10DE1098, "D13U" },␊
␉{ 0x10DE109A, "N12E-Q5" },␊
};␊
␊
static uint16_t swap16(uint16_t x)␊
␉␉␉return PATCH_ROM_FAILED;␊
␉␉}␊
␉} else {␊
␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊
␉␉return PATCH_ROM_FAILED;␊
␉}␊
␉␊
␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊
␉}␊
␉else if (nvCardType >= NV_ARCH_C0) {␊
␉␉vram_size = REG32(NVC0_MEM_CTRLR_COUNT);␊
␉␉vram_size *= REG32(NVC0_MEM_CTRLR_RAM_AMOUNT);␊
␉␉vram_size <<= 20;␊
␉}␊
␉else {␊
␉else if (nvCardType < NV_ARCH_C0) {␊
␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
␉␉vram_size |= (vram_size & 0xff) << 32;␊
␉␉vram_size &= 0xffffffff00ll;␊
␉}␊
␉else { // >= NV_ARCH_C0␊
␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊
␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊
␉}␊
␉␉␊
␉return vram_size;␊
}␊
␉devicepath = get_pci_dev_path(nvda_dev);␊
␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
␉␊
␉delay(50);␊
␉␉␊
␉// get card type␊
␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊
␉␉}␊
␉}␊
␊
/*␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
␉␉return false;␊
␉␉//return false;␊
␉}␊
*/␊
␉rom_pci_header = (option_rom_pci_header_t *)(rom + *(uint16_t *)&rom[24]);␊
␊
␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
␊
␉// check for 'PCIR' sig␊
␉if (rom_pci_header->signature == 0x53454550)//0x52494350)␊
␉␉if (rom_pci_header->device_id != nvda_dev->device_id)␊
␉if (rom_pci_header->signature == 0x50434952) {␊
␉␉if (rom_pci_header->device_id != nvda_dev->device_id) {␊
␉␉␉// Get Model from the OpROM␊
␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊
␉else␊
␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
␉␉} else {␊
␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
␉␉}␊
␉}␊
␊
␉if (!string)␊
␉if (!string) {␊
␉␉string = devprop_create_string();␊
␊
␉}␊
␉device = devprop_add_device(string, devicepath);␊
␊
␉/* FIXME: for primary graphics card only */␊
␉␉}␊
␉}␊
␊
#if DEBUG_NVCAP␊
#if DEBUG_NVCAP␊
printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
␉␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
␉␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
branches/Kabyl/i386/boot2/boot.h
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#define kRestartFix␉␉␉"RestartFix"␉␉/* acpi_patcher.c */␊
#define kGeneratePStates␉"GeneratePStates"␉/* acpi_patcher.c */␊
#define kGenerateCStates␉"GenerateCStates"␉/* acpi_patcher.c */␊
#define kEnableC2States␉␉"EnableC2State"␉␉/* acpi_patcher.c */␊
#define kEnableC3States␉␉"EnableC3State"␉␉/* acpi_patcher.c */␊
#define kEnableC4States␉␉"EnableC4State"␉␉/* acpi_patcher.c */␊
#define kDeviceProperties␉"device-properties"␉/* device_inject.c */␊
#define kHidePartition␉␉"Hide Partition"␉/* disk.c */␊
branches/Kabyl/i386/libsa/zalloc.c
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*/␊
␊
#include "libsa.h"␊
//#include "saio_internal.h" - Azi: needed for ZDEBUG (printf)␊
#include "memory.h"␊
␊
#define ZDEBUG 0␊
#define ZDEBUG 0 //Azi: booter doesn't load with this enabled; instant reboot at "boot1: ..."␊
␊
#if ZDEBUG␊
int zout;␊

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