Chameleon

Chameleon Commit Details

Date:2011-01-10 13:18:32 (13 years 3 months ago)
Author:valv
Commit:701
Parents: 700
Message:Centaur support began, amd code reworked, cpu model 0xC added, boot-log size increased (thanks Azi)
Changes:
M/branches/valv/i386/libsaio/ntfs.c
M/branches/valv/i386/libsaio/bootstruct.h
M/branches/valv/i386/libsaio/aml_generator.c
M/branches/valv/i386/libsaio/acpi_patcher.c
M/branches/valv/i386/boot2/mboot.c
M/branches/valv/i386/libsaio/msdos.c
M/branches/valv/i386/boot2/gui.c
M/branches/valv/i386/libsaio/cpu.c
M/branches/valv/version
M/branches/valv/i386/libsaio/fake_efi.c
M/branches/valv/i386/libsaio/disk.c
M/branches/valv/i386/libsaio/cpu.h
M/branches/valv/i386/libsaio/gma_resolution.h
M/branches/valv/i386/libsaio/nvidia_resolution.c
M/branches/valv/i386/boot2/options.c
M/branches/valv/i386/libsaio/autoresolution.h
M/branches/valv/revision
M/branches/valv/i386/libsaio/smbios_patcher.c
M/branches/valv/i386/libsaio/nvidia_resolution.h
M/branches/valv/i386/libsaio/console.c
M/branches/valv/doc/BootHelp.txt
M/branches/valv/i386/libsaio/edid.c

File differences

branches/valv/doc/BootHelp.txt
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␊
kernel: kernel name (e.g. "mach_kernel" - must be in "/" )␊
␊
flags: -v (verbose) -s (single user mode), ␊
flags: -v (verbose) -s (single user mode),␊
-x (safe mode) -F (ignore boot configuration file)␊
␊
"Graphics Mode"="WIDTHxHEIGHTxDEPTH" (e.g. "1024x768x32")␊
alt+v Verbose␊
alt+x Safe mode␊
alt+l Legacy mode (not sure why you need this)␊
6+4 64-bit␊
3+2 32-bit␊
␊
6 64-bit␊
3 32-bit␊
␊
Special booter commands:␊
------------------------␊
?memory Display information about the computer's memory.␊
branches/valv/version
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5.0.1␊
5.1␊
branches/valv/i386/libsaio/console.c
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bool gErrors;␊
␊
/* Kabyl: BooterLog */␊
#define BOOTER_LOG_SIZE␉(64 * 1024)␊
#define SAFE_LOG_SIZE␉80␊
#define BOOTER_LOG_SIZE␉(128 * 1024)␊
#define SAFE_LOG_SIZE␉134␊
␊
char *msgbuf = 0;␊
char *cursor = 0;␊
}␊
/* Kabyl: !BooterLog */␊
␊
␊
/*␊
* write one character to console␊
*/␊
/** Print a "Press a key to continue..." message and wait for a key press. */␊
void pause() ␊
{␊
printf("Press a key to continue...");␊
printf("Press a key to continue...\n");␊
getc();␊
}␊
branches/valv/i386/libsaio/bootstruct.h
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#define CONFIG_SIZE (40 * 4096)␊
␊
/*␊
* Max size fo config data array, in bytes.␊
* Max size for config data array, in bytes.␊
*/␊
#define IO_CONFIG_DATA_SIZE␉␉163840␊
␊
branches/valv/i386/libsaio/acpi_patcher.c
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␉␉␉int intelCPU = Platform.CPU.Model;␊
␉␉␉switch (intelCPU) ␊
␉␉␉{␊
␉␉␉␉case 0x0C:␊
␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Atom")) goto ncst_atm;␊
␉␉␉␉case 0x0F: // Core (65nm)␊
␉␉␉␉case 0x1A: // Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP - LGA1366 (45nm)␊
␉␉␉␉case 0x1E: // Core i5, i7 - Clarksfield, Lynnfield, Jasper Forest - LGA1156 (45nm)␊
␉␉␉␉␉break;␊
␉␉␉␉case 0x1C: // Atom (45nm)␊
␉␉␉␉case 0x26: // Atom Lincroft␊
␉␉␉␉␉ncst_atm:␊
␉␉␉␉␉cstates_count = 1 + (c2_enabled ? 1 : 0) + (c4_enabled ? 1 : 0) + (c6_enabled ? 1 : 0);␊
␉␉␉␉␉verbose("C-State: Adding %d states: ", cstates_count);␊
␉␉␉␉␉break;␊
␉␉␉{␊
␉␉␉␉switch (Platform.CPU.Model) ␊
␉␉␉␉{␊
␉␉␉␉␉case 0x0C:␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Atom")) goto cst_atm;␊
␉␉␉␉␉case 0x0F: // Core (65nm)␊
␉␉␉␉␉case 0x1A: // Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP - LGA1366 (45nm)␊
␉␉␉␉␉case 0x1E: // Core i5, i7 - Clarksfield, Lynnfield, Jasper Forest - LGA1156 (45nm)␊
␉␉␉␉␉case 0x1C: // Atom (45nm)␊
␉␉␉␉␉//valv: was 0x26 ??? rely on cpu.c & smbios_patcher.c␊
␉␉␉␉␉case 0x27: // Atom Lincroft␊
␊
␉␉␉␉␉␉␉cst_atm:␊
␉␉␉␉␉␉␉// C1␊
␉␉␉␉␉␉␉cstate_resource_template[11] = 0x00; // C1-Atom␊
␉␉␉␉␉␉␉aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template));␊
branches/valv/i386/libsaio/smbios_patcher.c
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␉␉␉{␊
␉␉␉␉switch (Platform.CPU.Model)␊
␉␉␉␉{␊
␉␉␉␉␉case 0x0D:␉// Pentium M model D␊
␉␉␉␉␉case 0x0d:␉// Pentium M, "Dothan", 90nm␊
␉␉␉␉␉case 0x0e:␉// Core Solo/Duo, "Yonah", 65nm␊
␉␉␉␉␉case 0x0f:␉// Pentium 4, Core 2, Xeon, "Merom", "Conroe", 65nm␊
␉␉␉␉␉case 0x17:␉// Core 2 Extreme, Xeon, "Penryn", "Wolfdale", 45nm␊
␉␉␉␉␉case 0x2f:␉// Core i7, "Westmere-Ex", 45nm, Hexa-Core␊
␉␉␉␉␉␉return 0; // TODO: populate bus speed for these processors␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉case 0x0c:␉// Core i7 & Atom␊
␉␉␉␉␉␉if(strstr(Platform.CPU.BrandString, "Atom")) return 0;␊
␉␉␉␉␉case 0x19:␉// Core i5 650␊
␉␉␉␉␉case 0x1a:␉// Core i7 LGA1366, Xeon 550, 45nm␊
␉␉␉␉␉case 0x1e:␉// Core i7, i5 LGA1156, "Lynnfield", "Jasper", 45nm␊
␊
␉␉switch (intelPM)␊
␉␉{␊
␉␉␉case 0xc:␉␉␉␉␉// Core i7 & Atom␊
␉␉␉␉if(strstr(Platform.CPU.BrandString, "Atom")) return sm_get_cores();␊
␉␉␉␉else return 0x0701;␊
␉␉␉␉break;␊
␉␉␉case 0x0d:␉␉␉␉␉// Pentium M model D␊
␉␉␉␉return 0x0101;␊
␉␉␉␉break;␊
branches/valv/i386/libsaio/aml_generator.c
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␉␉␉case AML_CHUNK_NAME:␊
␉␉␉␉if (parent->First) ␊
␉␉␉␉{␊
␉␉␉␉␉verbose("aml_add_to_parent: Name node could only have one child!");␊
␉␉␉␉␉verbose("aml_add_to_parent: Name node could have one child only!");␊
␉␉␉␉␉return FALSE;␊
␉␉␉␉}␊
␉␉␉␉break;␊
␉}␊
␉␊
␉return offset;␊
}
}␊
branches/valv/i386/libsaio/autoresolution.h
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␉struct sModeTable_ *prev;␊
␉struct sModeTable_ *next;␊
} sModeTable;␊
␉␊
␊
␊
typedef struct␊
{␊
␉uint32_t chipsetId;␊
branches/valv/i386/libsaio/ntfs.c
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␉␉␉␉␉␉␉␉␉(unsigned short)boot->bf_volsn & 0xFFFF);␊
␊
␉return 0;␊
} ␊
}␊
␊
bool NTFSProbe(const void * buffer)␊
{␊
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␉int␉␉␉len, myfsb, i;␊
␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency, fsbi;␊
␉uint64_t␉msr, flex_ratio = 0;␊
␉uint32_t␉tms, ida, amo, max_ratio, min_ratio;␊
␉uint32_t␉tms, ida, max_ratio, min_ratio;␊
␉uint8_t␉␉bus_ratio_max, maxdiv, bus_ratio_min, currdiv;␊
␉bool␉␉fix_fsb, did, core_i, turbo;␊
␉bool␉␉fix_fsb, did, core_i, turbo, isatom, fsbad;␊
␊
␉max_ratio = min_ratio = myfsb = bus_ratio_max = maxdiv = bus_ratio_min = currdiv = i = 0;␊
␊
␉did = false;␊
␉core_i = false;␊
␉turbo = false;␊
␉isatom = false;␊
␉fsbad = false;␊
␊
␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f)))␊
␉{␊
␊
␉␉␉␉switch (intelCPU)␊
␉␉␉␉{␊
␉␉␉␉␉case 0xc:␉␉// Core i7 & Atom␊
␉␉␉␉␉␉if (strstr(p->CPU.BrandString, "Atom")) goto teleport;␊
␉␉␉␉␉case 0x1a:␉␉// Core i7 LGA1366, Xeon 5500, "Bloomfield", "Gainstown", 45nm␊
␉␉␉␉␉case 0x1e:␉␉// Core i7, i5 LGA1156, "Clarksfield", "Lynnfield", "Jasper", 45nm␊
␉␉␉␉␉case 0x1f:␉␉// Core i7, i5, Nehalem␊
␉␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
␉␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
␉␉␉␉␉␉␊
␉␉␉␉␉␉fsbi = fsbFrequency;␊
␉␉␉␉␉␉//fsbi = fsbFrequency;␊
␉␉␉␉␉␉if(getIntForKey(kForceFSB, &myfsb, &bootInfo->bootConfig)) goto forcefsb;␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉case 0xd:␉␉// Pentium D; valv: is this the right place ?␊
␉␉␉␉␉case 0xd:␉␉// Pentium M, Dothan, 90nm␊
␉␉␉␉␉case 0xe:␉␉// Core Duo/Solo, Pentium M DC␊
␉␉␉␉␉␉goto teleport;␊
␉␉␉␉␉case 0xf:␉␉// Core Xeon, Core 2 DC, 65nm␊
␉␉␉␉␉␉core_i = false;␊
␉␉␉␉␉␉//valv: todo: msr_therm2_ctl (0x19d) bit 16 (mode of automatic thermal monitor): 0=tm1, 1=tm2␊
␉␉␉␉␉␉//also, if bit 3 of misc_enable is cleared the above would have no effect␊
␉␉␉␉␉␉if(platformCPUFeature(CPU_FEATURE_TM1))␊
␉␉␉␉␉␉if (strstr(p->CPU.BrandString, "Atom"))␊
␉␉␉␉␉␉␉isatom = true;␊
␉␉␉␉␉␉if(!isatom && (platformCPUFeature(CPU_FEATURE_TM1)))␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉msr_t msr32;␊
␉␉␉␉␉␉␉msr32 = rdmsr(MSR_IA32_MISC_ENABLE);␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉msr = rdmsr64(MSR_FSB_FREQ);␊
␉␉␉␉␉␉␉bus = (msr >> 0) & 0x7;␊
␉␉␉␉␉␉␉switch (bus)␊
␉␉␉␉␉␉␉if(p->CPU.Model == 0xd && bus == 0)␊
␉␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉␉case 0:␊
␉␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊
␉␉␉␉␉␉␉␉␉myfsb = 266;␊
␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉case 1:␊
␉␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊
␉␉␉␉␉␉␉␉␉myfsb = 133;␊
␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉case 3:␊
␉␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊
␉␉␉␉␉␉␉␉␉myfsb = 166;␊
␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉case 4:␊
␉␉␉␉␉␉␉␉␉fsbFrequency = 333333333;␊
␉␉␉␉␉␉␉␉␉myfsb = 333;␊
␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉case 5:␊
␉␉␉␉␉␉␉␉␉fsbFrequency = 100000000;␊
␉␉␉␉␉␉␉␉␉myfsb = 100;␊
␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉case 6:␊
␉␉␉␉␉␉␉␉␉fsbFrequency = 400000000;␊
␉␉␉␉␉␉␉␉␉myfsb = 400;␊
␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉case 2:␊
␉␉␉␉␉␉␉␉default:␊
␉␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
␉␉␉␉␉␉␉␉␉myfsb = 200;␊
␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉fsbFrequency = 100000000;␊
␉␉␉␉␉␉␉␉myfsb = 100;␊
␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉␉else if(p->CPU.Model == 0xe && p->CPU.ExtModel == 1) goto ratio;␊
␉␉␉␉␉␉␉else␊
␉␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉␉switch (bus)␊
␉␉␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉␉␉case 0:␊
␉␉␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊
␉␉␉␉␉␉␉␉␉␉myfsb = 266;␊
␉␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉␉case 1:␊
␉␉␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊
␉␉␉␉␉␉␉␉␉␉myfsb = 133;␊
␉␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉␉case 3:␊
␉␉␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊
␉␉␉␉␉␉␉␉␉␉myfsb = 166;␊
␉␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉␉case 4:␊
␉␉␉␉␉␉␉␉␉␉fsbFrequency = 333333333;␊
␉␉␉␉␉␉␉␉␉␉myfsb = 333;␊
␉␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉␉case 5:␊
␉␉␉␉␉␉␉␉␉␉fsbFrequency = 100000000;␊
␉␉␉␉␉␉␉␉␉␉myfsb = 100;␊
␉␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉␉case 6:␊
␉␉␉␉␉␉␉␉␉␉fsbFrequency = 400000000;␊
␉␉␉␉␉␉␉␉␉␉myfsb = 400;␊
␉␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉␉case 2:␊
␉␉␉␉␉␉␉␉␉default:␊
␉␉␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
␉␉␉␉␉␉␉␉␉␉myfsb = 200;␊
␉␉␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉␉uint64_t minfsb = 183000000, maxfsb = 185000000;␊
␉␉␉␉␉␉␉if (((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || (!fsbFrequency)) fsbFrequency = 200000000;␊
␉␉␉␉␉␉␉if (((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || (!fsbFrequency))␊
␉␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
␉␉␉␉␉␉␉␉fsbad = true;␊
␉␉␉␉␉␉␉}␊
␉␉␉␉␉␉␉goto ratio;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉case 0x1d:␉␉// Xeon MP MP 7400␊
␉␉␉␉currdiv = (msr >> 15) & 0x01;␊
␉␉␉␉uint8_t XE = (msr >> 31) & 0x01;␊
␊
␉␉␉␉msr_t msr;␊
␉␉␉␉msr = rdmsr(MSR_IA32_PERF_STATUS);␊
␉␉␉␉bus_ratio_min = (msr.lo >> 24) & 0x1f;␊
␉␉␉␉msr_t msr32;␊
␉␉␉␉msr32 = rdmsr(MSR_IA32_PERF_STATUS);␊
␉␉␉␉bus_ratio_min = (msr32.lo >> 24) & 0x1f;␊
␉␉␉␉min_ratio = bus_ratio_min * 10;␊
␉␉␉␉if(currdiv) min_ratio = min_ratio + 5;␊
␉␉␉␉␊
␉␉␉␉if(XE) bus_ratio_max = (msr.hi >> (40-32)) & 0x1f;␊
␉␉␉␉if(XE || (p->CPU.Family == 0x0f)) bus_ratio_max = (msr32.hi >> (40-32)) & 0x1f;␊
␉␉␉␉else bus_ratio_max = ((rdmsr64(MSR_IA32_PLATFORM_ID) >> 8) & 0x1f);␊
␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
␉␉␉␉if (((p->CPU.Family == 0x06) && (p->CPU.Model < 0x0e)) && (p->CPU.Family != 0x0f)) bus_ratio_max = bus_ratio_min;␊
␉␉␉␉// bad hack! Could force a value relying on kpstates, but I fail to see its benefits.␊
␉␉␉␉if(bus_ratio_min == 0) bus_ratio_min = bus_ratio_max;␊
␉␉␉␉␊
␉␉␉␉if(p->CPU.Family == 0x0f)␊
␉␉␉␉{␊
␉␉␉␉␉getBoolForKey(kFixFSB, &fix_fsb, &bootInfo->bootConfig);␊
␉␉␉␉␉if(fix_fsb)␊
␉␉␉␉␉{␊
␉␉␉␉␉␉msr = rdmsr64(MSR_EBC_FREQUENCY_ID);␊
␉␉␉␉␉␉int bus = (msr >> 16) & 0x7;␊
␉␉␉␉␉␉switch (bus)␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉case 0:␊
␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊
␉␉␉␉␉␉␉␉myfsb = 266;␊
␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉case 1:␊
␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊
␉␉␉␉␉␉␉␉myfsb = 133;␊
␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉case 3:␊
␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊
␉␉␉␉␉␉␉␉myfsb = 166;␊
␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉case 2:␊
␉␉␉␉␉␉␉default:␊
␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
␉␉␉␉␉␉␉␉myfsb = 200;␊
␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉␉uint64_t minfsb = 183000000, maxfsb = 185000000;␊
␉␉␉␉␉␉if (((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || (!fsbFrequency))␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉fsbFrequency = 200000000;␊
␉␉␉␉␉␉␉fsbad = true;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉}␊
␉␉␉␉}␊
␊
␉␉␉␉if(fix_fsb)␊
␉␉␉␉{␊
␉␉␉␉␉␉␉goto ratio_vldt;␊
␉␉␉␉␉␉}␊
␉␉␉␉␉}␊
␉␉␉␉␉else ␊
␉␉␉␉␉else␊
␉␉␉␉␉{␊
␉␉␉␉␉␉ratio_vldt:␊
␉␉␉␉␉␉if (maxdiv)␊
␉␉␉␉}␊
␉␉␉␉else␊
␉␉␉␉{␊
␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
␉␉␉␉␉if (((p->CPU.Family == 0x06) && (p->CPU.Model < 0x0e)) && (p->CPU.Family != 0x0f)) bus_ratio_max = bus_ratio_min;␊
␊
␉␉␉␉␉if (bus_ratio_max)␊
␉␉␉␉␉{␊
␉␉␉␉␉␉if (maxdiv)␊
␉␉}␊
␉}␊
//#if 0␊
␉else if(p->CPU.Vendor == 0x68747541 /* AMD */) // valv: work in progress␊
␉else if(p->CPU.Vendor == 0x68747541 /* AMD */ && p->CPU.Family == 0x0f) // valv: work in progress␊
␉{␊
␉␉verbose("CPU: ");␊
␉␉// valv: very experimental mobility check␊
␉␉if (p->CPU.CPUID[0x80000000][0] >= 0x80000007)␊
␉␉{␊
␉␉␉uint32_t amo, const_tsc;␊
␉␉␉do_cpuid(0x80000007, p->CPU.CPUID[CPUID_MAX]);␊
␉␉␉amo = bitfield(p->CPU.CPUID[CPUID_MAX][0], 6, 6);␊
␉␉␉const_tsc = bitfield(p->CPU.CPUID[CPUID_MAX][3], 8, 8);␊
␉␉␉␊
␉␉␉if (const_tsc != 0) verbose("Constant TSC!\n");␊
␉␉␉if (amo == 1)␊
␉␉␉{␊
␉␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
␉␉␉}␊
␉␉}␊
␉␉verbose("%s\n", p->CPU.BrandString);␊
␉␉int amdCPU = p->CPU.Family;␊
␉␉␊
␉␉switch (amdCPU)␊
␊
␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */)␊
␉␉{␊
␉␉␉case 0x0f:␊
␉␉␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */)␊
␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
␉␉␉bus_ratio_max = (msr & 0x3f) / 2 + 4;␊
␉␉␉currdiv = (msr & 0x01) * 2;␊
␉␉␉if (bus_ratio_max)␊
␉␉␉{␊
␉␉␉␉if (currdiv)␊
␉␉␉␉{␊
␉␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
␉␉␉␉␉bus_ratio_max = (msr & 0x3f) / 2 + 4;␊
␉␉␉␉␉currdiv = (msr & 0x01) * 2;␊
␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / bus_ratio_max); // ?␊
␉␉␉␉␉DBG("%d.%d\n", bus_ratio_max / currdiv, ((bus_ratio_max % currdiv) * 100) / currdiv);␊
␉␉␉␉}␊
␉␉␉␉else if(p->CPU.ExtFamily >= 0x01 /* K10+ */)␊
␉␉␉␉else␊
␉␉␉␉{␊
␉␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
␉␉␉␉␉if(p->CPU.ExtFamily == 0x01 /* K10 */)␊
␉␉␉␉␉␉bus_ratio_max = (msr & 0x3f) + 0x10;␊
␉␉␉␉␉else /* K11+ */␊
␉␉␉␉␉␉bus_ratio_max = (msr & 0x3f) + 0x08;␊
␉␉␉␉␉currdiv = (2 << ((msr >> 6) & 0x07));␊
␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
␉␉␉␉␉DBG("%d\n", bus_ratio_max);␊
␉␉␉␉}␊
␉␉␉␉␊
␉␉␉␉p->CPU.MaxRatio = bus_ratio_max * 10;␊
␉␉␉␉//fsbFrequency = (tscFrequency / bus_ratio_max); // ?␊
␉␉␉␉cpuFrequency = tscFrequency; // ?␊
␉␉␉}␊
␉␉}␊
␉␉else if(p->CPU.ExtFamily >= 0x01 /* K10+ */)␊
␉␉{␊
␉␉␉msr = rdmsr64(AMD_10H_11H_CONFIG);␊
␉␉␉if(p->CPU.ExtFamily == 0x01 /* K10 */)␊
␉␉␉{␊
␉␉␉␉bus_ratio_max = ((msr) & 0x3F);␊
␉␉␉␉currdiv = (((msr) >> 6) & 0x07);␊
␉␉␉␉cpuFrequency = 100 * (bus_ratio_max + 0x08) / (1 << currdiv);␊
␉␉␉}␊
␉␉␉else /* K11+ */␊
␉␉␉{␊
␉␉␉␉bus_ratio_max = ((msr) & 0x3F);␊
␉␉␉␉currdiv = (((msr) >> 6) & 0x07);␊
␉␉␉␉cpuFrequency = 100 * (bus_ratio_max + 0x10) / (1 << currdiv);␊
␉␉␉}␊
␉␉␉fsbFrequency = (cpuFrequency / bus_ratio_max);␊
␉␉}␊
␉␉␊
␉␉p->CPU.MaxRatio = bus_ratio_max * 10;␊
␉␉␊
␉␉// valv: to be moved to acpi_patcher when ready␊
␉␉msr_t amsr = rdmsr(K8_FIDVID_STATUS);␊
␉␉uint8_t max_fid = (amsr.lo & 0x3F) >> 16;␊
␉␉uint8_t min_fid = (amsr.lo & 0x3F) >> 8;␊
␉␉uint8_t max_vid = (amsr.hi & 0x3F) >> 16;␊
␉␉uint8_t min_vid = (amsr.hi & 0x3F) >> 8;␊
␉␉verbose("AMD: max[fid: %d, vid: %d] min[fid: %d, vid: %d]\n", max_fid, max_vid, min_fid, min_vid);␊
␊
␉␉␉␉if (bus_ratio_max)␊
␉␉␉␉{␊
␉␉␉␉␉if (currdiv)␊
␉␉␉␉␉{␊
␉␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / bus_ratio_max); // ?␊
␉␉␉␉␉␉DBG("%d.%d\n", bus_ratio_max / currdiv, ((bus_ratio_max % currdiv) * 100) / currdiv);␊
␉␉␉␉␉}␊
␉␉␉␉␉else␊
␉␉␉␉␉{␊
␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
␉␉␉␉␉␉DBG("%d\n", bus_ratio_max);␊
␉␉␉␉␉}␊
␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max); // ?␊
␉␉␉␉␉cpuFrequency = tscFrequency; // ?␊
␉␉␉␉}␊
␉␉␉␉break;␊
/*␊
␉␉␉case 0x10:␉// phenom␊
␉␉␉␉msr = rdmsr64(AMD_10H_11H_CONFIG);␊
␉␉␉␉bus_ratio_max = ((msr) & 0x3F);␊
␉␉␉␉cpuFrequency = 100 * (bus_ratio_max + 0x10) / (1 << currdiv);␊
␉␉␉␉break;␊
␉␉}␊
*/␊
␉}␊
␉else if(p->CPU.Vendor == 0x746e6543 /* CENTAUR */ && p->CPU.Family == 6) //valv: partial!␊
␉{␊
␉␉msr = rdmsr64(MSR_EBL_CR_POWERON);␊
␉␉int bus = (msr >> 18) & 0x3;␊
␉␉switch (bus)␊
␉␉{␊
␉␉␉case 1:␊
␉␉␉␉fsbFrequency = 133333333;␊
␉␉␉␉break;␊
␉␉␉case 2:␊
␉␉␉␉fsbFrequency = 200000000;␊
␉␉␉␉break;␊
␉␉␉case 3:␊
␉␉␉␉fsbFrequency = 166666667;␊
␉␉␉␉break;␊
␉␉␉case 0:␊
␉␉␉default:␉␉␉␉␊
␉␉␉␉fsbFrequency = 100000000;␊
␉␉␉␉break;␊
␉␉}␊
␉␉msr_t msr;␊
␉␉msr = rdmsr(MSR_IA32_PERF_STATUS);␊
␉␉bus_ratio_min = (msr.lo >> 24) & 0x1f;␊
␉␉min_ratio = bus_ratio_min * 10;␊
␉␉bus_ratio_max = (msr.hi >> (40-32)) & 0x1f;␊
␉␉max_ratio = bus_ratio_max * 10;␊
␉␉cpuFrequency = ((fsbFrequency * max_ratio) / 10);␊
␉}␊
␊
␉if (!fsbFrequency)␊
␉{␊
␉p->CPU.ISerie = false;␊
␉p->CPU.Turbo = false;␊
␊
␉if(fsbi == 0) p->CPU.FSBIFrequency = fsbFrequency;␊
␉if(!fsbad) p->CPU.FSBIFrequency = fsbFrequency;␊
␉else p->CPU.FSBIFrequency = fsbi;␊
␊
␉if (platformCPUFeature(CPU_FEATURE_EST))␊
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kBIOSDevTypeHardDrive, bvrFlags);␊
}␊
␊
␉␉␉␉␉␉// zef - foreign OS support␊
␉␉␉// zef - foreign OS support␊
if ( (efi_guid_compare(&GPT_BASICDATA_GUID, (EFI_GUID const*)gptMap->ent_type) == 0) ||␊
(efi_guid_compare(&GPT_BASICDATA2_GUID, (EFI_GUID const*)gptMap->ent_type) == 0) )␊
{␊
branches/valv/i386/libsaio/cpu.h
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#define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊
#define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊
␊
#define CPU_STRING_UNKNOWN␉␉"Unknown CPU Typ"␊
#define CPU_STRING_UNKNOWN␉␉"Unknown CPU Type"␊
␊
#define MSR_FSB_FREQ 0xCD␊
#define MSR_EBC_FREQUENCY_ID 0x2C␊
#define MSR_TURBO_RATIO_LIMIT 0x1AD␊
#define MSR_IA32_PLATFORM_ID 0x17␊
#define␉MSR_IA32_PERF_STATUS 0x198␊
#define MSR_IA32_CLOCK_MODULATION 0x19A␊
#define MSR_THERMAL_TARGET 0x01A2␊
#define PIC_SENS_CFG 0x1aa␊
#define MSR_EBL_CR_POWERON 0x02a␊
#define K8_FIDVID_STATUS 0xC0010042␊
#define␉AMD_10H_11H_CONFIG 0xc0010064␊
#define K10_COFVID_STATUS 0xC0010071␊
branches/valv/i386/libsaio/nvidia_resolution.c
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␉␉}␊
␉␉i++;␊
␉}␊
␉␊
␉␊
␉␊
␊
␉if (nvModeline_2_Offset == (VBIOS_SIZE-1) || nvModeline_2_Offset == 0)␊
␉{␊
␉␉//If no second vesa table is available, free the corresponding table in chain␊
␉␊
␉saveTables(map->modeTables);␊
␉␊
#if AUTORES_DEBUG␊
␉PRINT("Press Any Key...\n");␊
#ifdef AUTORES_DEBUG␊
␉getc();␊
#endif␊
␉␊
␉␉␉␊
␉␉␉idx++;␊
␉␉}␊
␉␉␊
␉␉␊
␉␉␊
␉}␊
␉return TRUE;␊
}
}␊
branches/valv/i386/libsaio/nvidia_resolution.h
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/*␊
* nviviaresolution.h␊
* nvidia_resolution.h␊
* ␊
*␊
* Created by Le Bidou on 19/03/10.␊
*␊
*/␊
␊
#ifndef _NVDA_RESOLUTION_HEADER_␊
#define _NVDA_RESOLUTION_HEADER_␊
#ifndef _NVIDIA_RESOLUTION_HEADER_␊
#define _NVIDIA_RESOLUTION_HEADER_␊
␊
#include "libsaio.h"␊
#include "autoresolution.h"␊
␊
bool nvidiaSetMode(sModeTable* table, uint8_t idx, uint32_t* x, uint32_t* y);␊
␊
#endif
#endif␊
branches/valv/i386/libsaio/edid.c
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␊
␉␉status = getEDID(edidInfo, blocks_left);␊
␉␉␊
␉␉␉␉//printf("Buffer location: 0x%X\n", SEG(buffer) << 16 | OFF(buffer));␊
␉␉//printf("Buffer location: 0x%X\n", SEG(buffer) << 16 | OFF(buffer));␊
␊
␉␉/*␊
␉␉int j, i;␊
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.␊
*/␊
␊
#define tolower(c) (((c)>='A' && c<='Z')?((c) | 0x20):(c))␊
#include "libsaio.h"␊
#include "sl.h"␊
␊
#include "msdos_private.h"␊
#include "msdos.h"␊
␊
#define tolower(c) (((c)>='A' && c<='Z')?((c) | 0x20):(c))␊
#define LABEL_LENGTH␉␉11␊
#define MSDOS_CACHE_BLOCKSIZE BPS␊
␊
branches/valv/i386/libsaio/fake_efi.c
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␊
/*␊
* Copyright 2007 David F. Elliott.␉ All rights reserved.␊
* Copyright 2007 David F. Elliott. All rights reserved.␊
*/␊
␊
#include "libsaio.h"␊
*/␊
␊
/* Identify ourselves as the EFI firmware vendor */␊
static EFI_CHAR16 const FIRMWARE_VENDOR[] = {'A','n','V','A','L','_','5','.','0', 1};␊
static EFI_CHAR16 const FIRMWARE_VENDOR[] = {'A','n','V','A','L','_','5','.','1', 1};␊
static EFI_UINT32 const FIRMWARE_REVISION = 132; /* FIXME: Find a constant for this. */␊
␊
/* Default platform system_id (fix by IntVar) */␊
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*/␊
␊
#ifndef _GMA_RESOLUTION_H_␊
#define _GMA_RESOLTUION_H_␊
#define _GMA_RESOLUTION_H_␊
␊
#include "libsaio.h"␊
#include "autoresolution.h"␊
bool intelSetMode_2(sModeTable* table, uint8_t idx, uint32_t* x, uint32_t* y);␊
bool intelSetMode_3(sModeTable* table, uint8_t idx, uint32_t* x, uint32_t* y);␊
␊
#endif
#endif␊
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␊
#include "mboot.h"␊
␊
struct multiboot_info *gMI;␊
␊
int multiboot_timeout=0;␊
int multiboot_timeout_set=0;␊
int multiboot_partition=0;␊
int multiboot_partition_set=0;␊
␊
// Global multiboot info, if using multiboot.␊
struct multiboot_info *gMI;␊
␊
extern void continue_at_low_address(void);␊
␊
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␉int compareIndex = (upperLimit - lowerLimit) >> 1; // Midpoint␊
␉int result;␊
␉␊
␉// NOTE: This algorithm assumes that the embeddedImages is sorted.␊
␉// This is currently done using the make file. If the array is every ␊
␉// manualy generated, this *will* fail to work properly.␊
␉// NOTE: This algorithm assumes that the embedded images are sorted.␊
␉// This is currently done using the make file. If the array is ever␊
␉// manually generated, this *will* fail to work properly.␊
␉while((result = strcmp(name, embeddedImages[compareIndex].name)) != 0)␊
␉{␊
␉␉if(result > 0)␉// We need to search a HIGHER index␊
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␉␉␉key = bgetc ();␊
␉␉␉if (key == 0x4200) f8 = true;␊
␉␉␉if (key == 0x2100) altf = true;␊
␉␉␉if (key == 0x2146) shiftf = true;␊
␉␉␉if (key == 0x0046) shiftf = true;␊
␉␉␉if (key == 0x1F00) alts = true;␊
␉␉␉if (key == 0x2F00) altv = true;␊
␉␉␉if (key == 0x2D00) altx = true;␊
␉␉␉if (key == 0x0403) x32 = true;␊
␉␉␉if (key == 0x0705) x64 = true;␊
␉␉␉if (key == 0x0004) x32 = true;␊
␉␉␉if (key == 0x0007) x64 = true;␊
␉␉}␊
␊
␉// If user typed F8, abort quiet mode, and display the menu.␊
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Revision: 701