Chameleon

Chameleon Commit Details

Date:2011-01-10 13:18:32 (9 years 6 months ago)
Author:valv
Commit:701
Parents: 700
Message:Centaur support began, amd code reworked, cpu model 0xC added, boot-log size increased (thanks Azi)
Changes:
M/branches/valv/i386/libsaio/ntfs.c
M/branches/valv/i386/libsaio/bootstruct.h
M/branches/valv/i386/libsaio/aml_generator.c
M/branches/valv/i386/libsaio/acpi_patcher.c
M/branches/valv/i386/boot2/mboot.c
M/branches/valv/i386/libsaio/msdos.c
M/branches/valv/i386/boot2/gui.c
M/branches/valv/i386/libsaio/cpu.c
M/branches/valv/version
M/branches/valv/i386/libsaio/fake_efi.c
M/branches/valv/i386/libsaio/disk.c
M/branches/valv/i386/libsaio/cpu.h
M/branches/valv/i386/libsaio/gma_resolution.h
M/branches/valv/i386/libsaio/nvidia_resolution.c
M/branches/valv/i386/boot2/options.c
M/branches/valv/i386/libsaio/autoresolution.h
M/branches/valv/revision
M/branches/valv/i386/libsaio/smbios_patcher.c
M/branches/valv/i386/libsaio/nvidia_resolution.h
M/branches/valv/i386/libsaio/console.c
M/branches/valv/doc/BootHelp.txt
M/branches/valv/i386/libsaio/edid.c

File differences

branches/valv/doc/BootHelp.txt
1414
1515
1616
17
17
1818
1919
2020
......
4040
4141
4242
43
44
45
43
44
45
4646
4747
4848
kernel: kernel name (e.g. "mach_kernel" - must be in "/" )
flags: -v (verbose) -s (single user mode),
flags: -v (verbose) -s (single user mode),
-x (safe mode) -F (ignore boot configuration file)
"Graphics Mode"="WIDTHxHEIGHTxDEPTH" (e.g. "1024x768x32")
alt+v Verbose
alt+x Safe mode
alt+l Legacy mode (not sure why you need this)
6+4 64-bit
3+2 32-bit
6 64-bit
3 32-bit
Special booter commands:
------------------------
?memory Display information about the computer's memory.
branches/valv/version
1
1
5.0.1
5.1
branches/valv/i386/libsaio/console.c
5353
5454
5555
56
57
56
57
5858
5959
6060
......
112112
113113
114114
115
116115
117116
118117
......
249248
250249
251250
252
251
253252
254253
bool gErrors;
/* Kabyl: BooterLog */
#define BOOTER_LOG_SIZE(64 * 1024)
#define SAFE_LOG_SIZE80
#define BOOTER_LOG_SIZE(128 * 1024)
#define SAFE_LOG_SIZE134
char *msgbuf = 0;
char *cursor = 0;
}
/* Kabyl: !BooterLog */
/*
* write one character to console
*/
/** Print a "Press a key to continue..." message and wait for a key press. */
void pause()
{
printf("Press a key to continue...");
printf("Press a key to continue...\n");
getc();
}
branches/valv/i386/libsaio/bootstruct.h
4646
4747
4848
49
49
5050
5151
5252
#define CONFIG_SIZE (40 * 4096)
/*
* Max size fo config data array, in bytes.
* Max size for config data array, in bytes.
*/
#define IO_CONFIG_DATA_SIZE163840
branches/valv/i386/libsaio/acpi_patcher.c
288288
289289
290290
291
292
291293
292294
293295
......
301303
302304
303305
306
304307
305308
306309
......
338341
339342
340343
344
345
341346
342347
343348
......
385390
386391
387392
388
393
389394
390395
391396
int intelCPU = Platform.CPU.Model;
switch (intelCPU)
{
case 0x0C:
if (strstr(Platform.CPU.BrandString, "Atom")) goto ncst_atm;
case 0x0F: // Core (65nm)
case 0x1A: // Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP - LGA1366 (45nm)
case 0x1E: // Core i5, i7 - Clarksfield, Lynnfield, Jasper Forest - LGA1156 (45nm)
break;
case 0x1C: // Atom (45nm)
case 0x26: // Atom Lincroft
ncst_atm:
cstates_count = 1 + (c2_enabled ? 1 : 0) + (c4_enabled ? 1 : 0) + (c6_enabled ? 1 : 0);
verbose("C-State: Adding %d states: ", cstates_count);
break;
{
switch (Platform.CPU.Model)
{
case 0x0C:
if (strstr(Platform.CPU.BrandString, "Atom")) goto cst_atm;
case 0x0F: // Core (65nm)
case 0x1A: // Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP - LGA1366 (45nm)
case 0x1E: // Core i5, i7 - Clarksfield, Lynnfield, Jasper Forest - LGA1156 (45nm)
case 0x1C: // Atom (45nm)
//valv: was 0x26 ??? rely on cpu.c & smbios_patcher.c
case 0x27: // Atom Lincroft
cst_atm:
// C1
cstate_resource_template[11] = 0x00; // C1-Atom
aml_add_buffer(tmpl, cstate_resource_template, sizeof(cstate_resource_template));
branches/valv/i386/libsaio/smbios_patcher.c
315315
316316
317317
318
318
319319
320320
321321
......
326326
327327
328328
329
330
329331
330332
331333
......
400402
401403
402404
405
406
407
408
403409
404410
405411
{
switch (Platform.CPU.Model)
{
case 0x0D:// Pentium M model D
case 0x0d:// Pentium M, "Dothan", 90nm
case 0x0e:// Core Solo/Duo, "Yonah", 65nm
case 0x0f:// Pentium 4, Core 2, Xeon, "Merom", "Conroe", 65nm
case 0x17:// Core 2 Extreme, Xeon, "Penryn", "Wolfdale", 45nm
case 0x2f:// Core i7, "Westmere-Ex", 45nm, Hexa-Core
return 0; // TODO: populate bus speed for these processors
break;
case 0x0c:// Core i7 & Atom
if(strstr(Platform.CPU.BrandString, "Atom")) return 0;
case 0x19:// Core i5 650
case 0x1a:// Core i7 LGA1366, Xeon 550, 45nm
case 0x1e:// Core i7, i5 LGA1156, "Lynnfield", "Jasper", 45nm
switch (intelPM)
{
case 0xc:// Core i7 & Atom
if(strstr(Platform.CPU.BrandString, "Atom")) return sm_get_cores();
else return 0x0701;
break;
case 0x0d:// Pentium M model D
return 0x0101;
break;
branches/valv/i386/libsaio/aml_generator.c
2626
2727
2828
29
29
3030
3131
3232
......
495495
496496
497497
498
498
case AML_CHUNK_NAME:
if (parent->First)
{
verbose("aml_add_to_parent: Name node could only have one child!");
verbose("aml_add_to_parent: Name node could have one child only!");
return FALSE;
}
break;
}
return offset;
}
}
branches/valv/i386/libsaio/autoresolution.h
9393
9494
9595
96
9796
98
9997
10098
10199
struct sModeTable_ *prev;
struct sModeTable_ *next;
} sModeTable;
typedef struct
{
uint32_t chipsetId;
branches/valv/i386/libsaio/ntfs.c
328328
329329
330330
331
331
332332
333333
334334
(unsigned short)boot->bf_volsn & 0xFFFF);
return 0;
}
}
bool NTFSProbe(const void * buffer)
{
branches/valv/i386/libsaio/cpu.c
100100
101101
102102
103
103
104104
105
105
106106
107107
108108
......
192192
193193
194194
195
196
195197
196198
197199
......
215217
216218
217219
220
221
218222
219223
220224
......
278282
279283
280284
281
285
282286
283287
284
288
285289
286290
287291
......
334338
335339
336340
337
341
342
343
338344
339345
340346
......
393399
394400
395401
396
402
397403
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
404
405
427406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
428443
429
444
445
446
447
448
430449
431450
432451
......
491510
492511
493512
494
495
496
513
514
515
497516
498517
499518
500
519
501520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
502561
503562
504563
......
528587
529588
530589
531
590
532591
533592
534593
......
546605
547606
548607
549
550
551
552608
553609
554610
......
610666
611667
612668
613
669
614670
615671
616672
617673
618674
675
619676
620677
678
679
680
621681
622682
623683
......
633693
634694
635695
636
637
638
696
697
639698
640
641
699
700
701
702
703
704
642705
643
644
645
706
707
646708
647
709
648710
649
650
651
652
653
654
711
712
655713
656
657
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
658745
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
746
675747
676748
677749
......
685757
686758
687759
760
688761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
689790
690791
691792
......
704805
705806
706807
707
808
708809
709810
710811
intlen, myfsb, i;
uint64_ttscFrequency, fsbFrequency, cpuFrequency, fsbi;
uint64_tmsr, flex_ratio = 0;
uint32_ttms, ida, amo, max_ratio, min_ratio;
uint32_ttms, ida, max_ratio, min_ratio;
uint8_tbus_ratio_max, maxdiv, bus_ratio_min, currdiv;
boolfix_fsb, did, core_i, turbo;
boolfix_fsb, did, core_i, turbo, isatom, fsbad;
max_ratio = min_ratio = myfsb = bus_ratio_max = maxdiv = bus_ratio_min = currdiv = i = 0;
did = false;
core_i = false;
turbo = false;
isatom = false;
fsbad = false;
if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f)))
{
switch (intelCPU)
{
case 0xc:// Core i7 & Atom
if (strstr(p->CPU.BrandString, "Atom")) goto teleport;
case 0x1a:// Core i7 LGA1366, Xeon 5500, "Bloomfield", "Gainstown", 45nm
case 0x1e:// Core i7, i5 LGA1156, "Clarksfield", "Lynnfield", "Jasper", 45nm
case 0x1f:// Core i7, i5, Nehalem
p->CPU.MaxRatio = max_ratio;
p->CPU.MinRatio = min_ratio;
fsbi = fsbFrequency;
//fsbi = fsbFrequency;
if(getIntForKey(kForceFSB, &myfsb, &bootInfo->bootConfig)) goto forcefsb;
break;
case 0xd:// Pentium D; valv: is this the right place ?
case 0xd:// Pentium M, Dothan, 90nm
case 0xe:// Core Duo/Solo, Pentium M DC
goto teleport;
case 0xf:// Core Xeon, Core 2 DC, 65nm
core_i = false;
//valv: todo: msr_therm2_ctl (0x19d) bit 16 (mode of automatic thermal monitor): 0=tm1, 1=tm2
//also, if bit 3 of misc_enable is cleared the above would have no effect
if(platformCPUFeature(CPU_FEATURE_TM1))
if (strstr(p->CPU.BrandString, "Atom"))
isatom = true;
if(!isatom && (platformCPUFeature(CPU_FEATURE_TM1)))
{
msr_t msr32;
msr32 = rdmsr(MSR_IA32_MISC_ENABLE);
{
msr = rdmsr64(MSR_FSB_FREQ);
bus = (msr >> 0) & 0x7;
switch (bus)
if(p->CPU.Model == 0xd && bus == 0)
{
case 0:
fsbFrequency = 266666667;
myfsb = 266;
break;
case 1:
fsbFrequency = 133333333;
myfsb = 133;
break;
case 3:
fsbFrequency = 166666667;
myfsb = 166;
break;
case 4:
fsbFrequency = 333333333;
myfsb = 333;
break;
case 5:
fsbFrequency = 100000000;
myfsb = 100;
break;
case 6:
fsbFrequency = 400000000;
myfsb = 400;
break;
case 2:
default:
fsbFrequency = 200000000;
myfsb = 200;
break;
fsbFrequency = 100000000;
myfsb = 100;
}
else if(p->CPU.Model == 0xe && p->CPU.ExtModel == 1) goto ratio;
else
{
switch (bus)
{
case 0:
fsbFrequency = 266666667;
myfsb = 266;
break;
case 1:
fsbFrequency = 133333333;
myfsb = 133;
break;
case 3:
fsbFrequency = 166666667;
myfsb = 166;
break;
case 4:
fsbFrequency = 333333333;
myfsb = 333;
break;
case 5:
fsbFrequency = 100000000;
myfsb = 100;
break;
case 6:
fsbFrequency = 400000000;
myfsb = 400;
break;
case 2:
default:
fsbFrequency = 200000000;
myfsb = 200;
break;
}
}
uint64_t minfsb = 183000000, maxfsb = 185000000;
if (((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || (!fsbFrequency)) fsbFrequency = 200000000;
if (((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || (!fsbFrequency))
{
fsbFrequency = 200000000;
fsbad = true;
}
goto ratio;
}
case 0x1d:// Xeon MP MP 7400
currdiv = (msr >> 15) & 0x01;
uint8_t XE = (msr >> 31) & 0x01;
msr_t msr;
msr = rdmsr(MSR_IA32_PERF_STATUS);
bus_ratio_min = (msr.lo >> 24) & 0x1f;
msr_t msr32;
msr32 = rdmsr(MSR_IA32_PERF_STATUS);
bus_ratio_min = (msr32.lo >> 24) & 0x1f;
min_ratio = bus_ratio_min * 10;
if(currdiv) min_ratio = min_ratio + 5;
if(XE) bus_ratio_max = (msr.hi >> (40-32)) & 0x1f;
if(XE || (p->CPU.Family == 0x0f)) bus_ratio_max = (msr32.hi >> (40-32)) & 0x1f;
else bus_ratio_max = ((rdmsr64(MSR_IA32_PLATFORM_ID) >> 8) & 0x1f);
/* On lower models, currcoef defines TSC freq */
if (((p->CPU.Family == 0x06) && (p->CPU.Model < 0x0e)) && (p->CPU.Family != 0x0f)) bus_ratio_max = bus_ratio_min;
// bad hack! Could force a value relying on kpstates, but I fail to see its benefits.
if(bus_ratio_min == 0) bus_ratio_min = bus_ratio_max;
if(p->CPU.Family == 0x0f)
{
getBoolForKey(kFixFSB, &fix_fsb, &bootInfo->bootConfig);
if(fix_fsb)
{
msr = rdmsr64(MSR_EBC_FREQUENCY_ID);
int bus = (msr >> 16) & 0x7;
switch (bus)
{
case 0:
fsbFrequency = 266666667;
myfsb = 266;
break;
case 1:
fsbFrequency = 133333333;
myfsb = 133;
break;
case 3:
fsbFrequency = 166666667;
myfsb = 166;
break;
case 2:
default:
fsbFrequency = 200000000;
myfsb = 200;
break;
}
uint64_t minfsb = 183000000, maxfsb = 185000000;
if (((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || (!fsbFrequency))
{
fsbFrequency = 200000000;
fsbad = true;
}
}
}
if(fix_fsb)
{
goto ratio_vldt;
}
}
else
else
{
ratio_vldt:
if (maxdiv)
}
else
{
/* On lower models, currcoef defines TSC freq */
if (((p->CPU.Family == 0x06) && (p->CPU.Model < 0x0e)) && (p->CPU.Family != 0x0f)) bus_ratio_max = bus_ratio_min;
if (bus_ratio_max)
{
if (maxdiv)
}
}
//#if 0
else if(p->CPU.Vendor == 0x68747541 /* AMD */) // valv: work in progress
else if(p->CPU.Vendor == 0x68747541 /* AMD */ && p->CPU.Family == 0x0f) // valv: work in progress
{
verbose("CPU: ");
// valv: very experimental mobility check
if (p->CPU.CPUID[0x80000000][0] >= 0x80000007)
{
uint32_t amo, const_tsc;
do_cpuid(0x80000007, p->CPU.CPUID[CPUID_MAX]);
amo = bitfield(p->CPU.CPUID[CPUID_MAX][0], 6, 6);
const_tsc = bitfield(p->CPU.CPUID[CPUID_MAX][3], 8, 8);
if (const_tsc != 0) verbose("Constant TSC!\n");
if (amo == 1)
{
p->CPU.Features |= CPU_FEATURE_MOBILE;
}
}
verbose("%s\n", p->CPU.BrandString);
int amdCPU = p->CPU.Family;
switch (amdCPU)
if(p->CPU.ExtFamily == 0x00 /* K8 */)
{
case 0x0f:
if(p->CPU.ExtFamily == 0x00 /* K8 */)
msr = rdmsr64(K8_FIDVID_STATUS);
bus_ratio_max = (msr & 0x3f) / 2 + 4;
currdiv = (msr & 0x01) * 2;
if (bus_ratio_max)
{
if (currdiv)
{
msr = rdmsr64(K8_FIDVID_STATUS);
bus_ratio_max = (msr & 0x3f) / 2 + 4;
currdiv = (msr & 0x01) * 2;
fsbFrequency = ((tscFrequency * currdiv) / bus_ratio_max); // ?
DBG("%d.%d\n", bus_ratio_max / currdiv, ((bus_ratio_max % currdiv) * 100) / currdiv);
}
else if(p->CPU.ExtFamily >= 0x01 /* K10+ */)
else
{
msr = rdmsr64(K10_COFVID_STATUS);
if(p->CPU.ExtFamily == 0x01 /* K10 */)
bus_ratio_max = (msr & 0x3f) + 0x10;
else /* K11+ */
bus_ratio_max = (msr & 0x3f) + 0x08;
currdiv = (2 << ((msr >> 6) & 0x07));
fsbFrequency = (tscFrequency / bus_ratio_max);
DBG("%d\n", bus_ratio_max);
}
p->CPU.MaxRatio = bus_ratio_max * 10;
//fsbFrequency = (tscFrequency / bus_ratio_max); // ?
cpuFrequency = tscFrequency; // ?
}
}
else if(p->CPU.ExtFamily >= 0x01 /* K10+ */)
{
msr = rdmsr64(AMD_10H_11H_CONFIG);
if(p->CPU.ExtFamily == 0x01 /* K10 */)
{
bus_ratio_max = ((msr) & 0x3F);
currdiv = (((msr) >> 6) & 0x07);
cpuFrequency = 100 * (bus_ratio_max + 0x08) / (1 << currdiv);
}
else /* K11+ */
{
bus_ratio_max = ((msr) & 0x3F);
currdiv = (((msr) >> 6) & 0x07);
cpuFrequency = 100 * (bus_ratio_max + 0x10) / (1 << currdiv);
}
fsbFrequency = (cpuFrequency / bus_ratio_max);
}
p->CPU.MaxRatio = bus_ratio_max * 10;
// valv: to be moved to acpi_patcher when ready
msr_t amsr = rdmsr(K8_FIDVID_STATUS);
uint8_t max_fid = (amsr.lo & 0x3F) >> 16;
uint8_t min_fid = (amsr.lo & 0x3F) >> 8;
uint8_t max_vid = (amsr.hi & 0x3F) >> 16;
uint8_t min_vid = (amsr.hi & 0x3F) >> 8;
verbose("AMD: max[fid: %d, vid: %d] min[fid: %d, vid: %d]\n", max_fid, max_vid, min_fid, min_vid);
if (bus_ratio_max)
{
if (currdiv)
{
fsbFrequency = ((tscFrequency * currdiv) / bus_ratio_max); // ?
DBG("%d.%d\n", bus_ratio_max / currdiv, ((bus_ratio_max % currdiv) * 100) / currdiv);
}
else
{
fsbFrequency = (tscFrequency / bus_ratio_max);
DBG("%d\n", bus_ratio_max);
}
fsbFrequency = (tscFrequency / bus_ratio_max); // ?
cpuFrequency = tscFrequency; // ?
}
break;
/*
case 0x10:// phenom
msr = rdmsr64(AMD_10H_11H_CONFIG);
bus_ratio_max = ((msr) & 0x3F);
cpuFrequency = 100 * (bus_ratio_max + 0x10) / (1 << currdiv);
break;
}
*/
}
else if(p->CPU.Vendor == 0x746e6543 /* CENTAUR */ && p->CPU.Family == 6) //valv: partial!
{
msr = rdmsr64(MSR_EBL_CR_POWERON);
int bus = (msr >> 18) & 0x3;
switch (bus)
{
case 1:
fsbFrequency = 133333333;
break;
case 2:
fsbFrequency = 200000000;
break;
case 3:
fsbFrequency = 166666667;
break;
case 0:
default:
fsbFrequency = 100000000;
break;
}
msr_t msr;
msr = rdmsr(MSR_IA32_PERF_STATUS);
bus_ratio_min = (msr.lo >> 24) & 0x1f;
min_ratio = bus_ratio_min * 10;
bus_ratio_max = (msr.hi >> (40-32)) & 0x1f;
max_ratio = bus_ratio_max * 10;
cpuFrequency = ((fsbFrequency * max_ratio) / 10);
}
if (!fsbFrequency)
{
p->CPU.ISerie = false;
p->CPU.Turbo = false;
if(fsbi == 0) p->CPU.FSBIFrequency = fsbFrequency;
if(!fsbad) p->CPU.FSBIFrequency = fsbFrequency;
else p->CPU.FSBIFrequency = fsbi;
if (platformCPUFeature(CPU_FEATURE_EST))
branches/valv/i386/libsaio/disk.c
13131313
13141314
13151315
1316
1316
13171317
13181318
13191319
kBIOSDevTypeHardDrive, bvrFlags);
}
// zef - foreign OS support
// zef - foreign OS support
if ( (efi_guid_compare(&GPT_BASICDATA_GUID, (EFI_GUID const*)gptMap->ent_type) == 0) ||
(efi_guid_compare(&GPT_BASICDATA2_GUID, (EFI_GUID const*)gptMap->ent_type) == 0) )
{
branches/valv/i386/libsaio/cpu.h
1515
1616
1717
18
18
1919
2020
21
2122
2223
2324
......
3031
3132
3233
34
3335
3436
3537
#define bitmask(h,l)((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
#define bitfield(x,h,l)(((x) & bitmask(h,l)) >> l)
#define CPU_STRING_UNKNOWN"Unknown CPU Typ"
#define CPU_STRING_UNKNOWN"Unknown CPU Type"
#define MSR_FSB_FREQ 0xCD
#define MSR_EBC_FREQUENCY_ID 0x2C
#define MSR_TURBO_RATIO_LIMIT 0x1AD
#define MSR_IA32_PLATFORM_ID 0x17
#defineMSR_IA32_PERF_STATUS 0x198
#define MSR_IA32_CLOCK_MODULATION 0x19A
#define MSR_THERMAL_TARGET 0x01A2
#define PIC_SENS_CFG 0x1aa
#define MSR_EBL_CR_POWERON 0x02a
#define K8_FIDVID_STATUS 0xC0010042
#defineAMD_10H_11H_CONFIG 0xc0010064
#define K10_COFVID_STATUS 0xC0010071
branches/valv/i386/libsaio/nvidia_resolution.c
5656
5757
5858
59
60
61
59
6260
6361
6462
......
122120
123121
124122
125
126
123
127124
128125
129126
......
216213
217214
218215
219
220
221
222216
223217
224
218
}
i++;
}
if (nvModeline_2_Offset == (VBIOS_SIZE-1) || nvModeline_2_Offset == 0)
{
//If no second vesa table is available, free the corresponding table in chain
saveTables(map->modeTables);
#if AUTORES_DEBUG
PRINT("Press Any Key...\n");
#ifdef AUTORES_DEBUG
getc();
#endif
idx++;
}
}
return TRUE;
}
}
branches/valv/i386/libsaio/nvidia_resolution.h
11
2
2
33
44
55
......
77
88
99
10
11
10
11
1212
1313
1414
......
7575
7676
7777
78
78
/*
* nviviaresolution.h
* nvidia_resolution.h
*
*
* Created by Le Bidou on 19/03/10.
*
*/
#ifndef _NVDA_RESOLUTION_HEADER_
#define _NVDA_RESOLUTION_HEADER_
#ifndef _NVIDIA_RESOLUTION_HEADER_
#define _NVIDIA_RESOLUTION_HEADER_
#include "libsaio.h"
#include "autoresolution.h"
bool nvidiaSetMode(sModeTable* table, uint8_t idx, uint32_t* x, uint32_t* y);
#endif
#endif
branches/valv/i386/libsaio/edid.c
7777
7878
7979
80
80
8181
8282
8383
status = getEDID(edidInfo, blocks_left);
//printf("Buffer location: 0x%X\n", SEG(buffer) << 16 | OFF(buffer));
//printf("Buffer location: 0x%X\n", SEG(buffer) << 16 | OFF(buffer));
/*
int j, i;
branches/valv/i386/libsaio/msdos.c
4646
4747
4848
49
5049
5150
5251
5352
5453
5554
55
5656
5757
5858
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#define tolower(c) (((c)>='A' && c<='Z')?((c) | 0x20):(c))
#include "libsaio.h"
#include "sl.h"
#include "msdos_private.h"
#include "msdos.h"
#define tolower(c) (((c)>='A' && c<='Z')?((c) | 0x20):(c))
#define LABEL_LENGTH11
#define MSDOS_CACHE_BLOCKSIZE BPS
branches/valv/i386/libsaio/fake_efi.c
11
22
3
3
44
55
66
......
7676
7777
7878
79
79
8080
8181
8282
/*
* Copyright 2007 David F. Elliott. All rights reserved.
* Copyright 2007 David F. Elliott. All rights reserved.
*/
#include "libsaio.h"
*/
/* Identify ourselves as the EFI firmware vendor */
static EFI_CHAR16 const FIRMWARE_VENDOR[] = {'A','n','V','A','L','_','5','.','0', 1};
static EFI_CHAR16 const FIRMWARE_VENDOR[] = {'A','n','V','A','L','_','5','.','1', 1};
static EFI_UINT32 const FIRMWARE_REVISION = 132; /* FIXME: Find a constant for this. */
/* Default platform system_id (fix by IntVar) */
branches/valv/i386/libsaio/gma_resolution.h
88
99
1010
11
11
1212
1313
1414
......
100100
101101
102102
103
103
*/
#ifndef _GMA_RESOLUTION_H_
#define _GMA_RESOLTUION_H_
#define _GMA_RESOLUTION_H_
#include "libsaio.h"
#include "autoresolution.h"
bool intelSetMode_2(sModeTable* table, uint8_t idx, uint32_t* x, uint32_t* y);
bool intelSetMode_3(sModeTable* table, uint8_t idx, uint32_t* x, uint32_t* y);
#endif
#endif
branches/valv/i386/boot2/mboot.c
88
99
1010
11
12
1311
1412
1513
1614
1715
1816
17
1918
2019
2120
#include "mboot.h"
struct multiboot_info *gMI;
int multiboot_timeout=0;
int multiboot_timeout_set=0;
int multiboot_partition=0;
int multiboot_partition_set=0;
// Global multiboot info, if using multiboot.
struct multiboot_info *gMI;
extern void continue_at_low_address(void);
branches/valv/i386/boot2/gui.c
199199
200200
201201
202
203
204
202
203
204
205205
206206
207207
int compareIndex = (upperLimit - lowerLimit) >> 1; // Midpoint
int result;
// NOTE: This algorithm assumes that the embeddedImages is sorted.
// This is currently done using the make file. If the array is every
// manualy generated, this *will* fail to work properly.
// NOTE: This algorithm assumes that the embedded images are sorted.
// This is currently done using the make file. If the array is ever
// manually generated, this *will* fail to work properly.
while((result = strcmp(name, embeddedImages[compareIndex].name)) != 0)
{
if(result > 0)// We need to search a HIGHER index
branches/valv/i386/boot2/options.c
741741
742742
743743
744
744
745745
746746
747747
748
749
748
749
750750
751751
752752
key = bgetc ();
if (key == 0x4200) f8 = true;
if (key == 0x2100) altf = true;
if (key == 0x2146) shiftf = true;
if (key == 0x0046) shiftf = true;
if (key == 0x1F00) alts = true;
if (key == 0x2F00) altv = true;
if (key == 0x2D00) altx = true;
if (key == 0x0403) x32 = true;
if (key == 0x0705) x64 = true;
if (key == 0x0004) x32 = true;
if (key == 0x0007) x64 = true;
}
// If user typed F8, abort quiet mode, and display the menu.
branches/valv/revision
1
1
665:688
665:698

Archive Download the corresponding diff file

Revision: 701