Chameleon

Chameleon Commit Details

Date:2011-01-16 16:50:15 (9 years 10 months ago)
Author:valv
Commit:705
Parents: 704
Message:kernel_patcher (meklort's r252), sandy-bridge support, phenom/shanghai rework, nvidia's rom size raised
Changes:
M/branches/valv/i386/libsaio/nvidia.c
M/branches/valv/i386/boot2/boot.h
M/branches/valv/i386/boot2/drivers.c
M/branches/valv/i386/MakeInc.dir
M/branches/valv/i386/boot2/prompt.c
M/branches/valv/i386/libsaio/memvendors.h
M/branches/valv/i386/libsaio/spd.c
M/branches/valv/i386/boot2/gui.c
M/branches/valv/i386/libsaio/cpu.c
M/branches/valv/i386/util/Makefile
M/branches/valv/version
M/branches/valv/i386/libsaio/fake_efi.c
M/branches/valv/i386/libsaio/cpu.h
M/branches/valv/i386/boot2/Makefile
M/branches/valv/revision
M/branches/valv/i386/libsaio/smbios_patcher.c
M/branches/valv/i386/boot2/graphics.c
M/branches/valv/i386/boot2/boot.c

File differences

branches/valv/version
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5.1
5.1.3
branches/valv/i386/libsaio/spd.c
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#include "pci.h"
#include "platform.h"
#include "spd.h"
#include "cpu.h"
#include "saio_internal.h"
#include "bootstruct.h"
#include "memvendors.h"
#if DEBUG_SPD
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#define DBG(x...)msglog(x)
#endif
static const char *spd_memory_types[] =
uint8_t code = 0;
int i = 0;
uint8_t * spd = (uint8_t *) slot->spd;
if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { // DDR3
bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1
code = spd[SPD_DDR3_MEMORY_CODE];
slot = &Platform.RAM.DIMM[i];
spd_size = smb_read_byte_intel(base, 0x50 + i, 0);
// Check spd is present
if (spd_size && (spd_size != 0xff) ) {
if (spd_size && (spd_size != 0xff))
{
slot->spd = spdbuf;
slot->InUse = true;
//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);
init_spd(slot->spd, base, i);
switch (slot->spd[SPD_MEMORY_TYPE]) {
case SPD_MEMORY_TYPE_SDRAM_DDR2:
}
slot->Frequency = freq;
}
verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n",
i,
(int)slot->Type,
slot->Vendor,
slot->PartNo,
slot->SerialNo);
if(DEBUG_SPD) {
dumpPhysAddr("spd content: ",slot->spd, spd_size);
#if DEBUG_SPD
dumpPhysAddr("spd content: ", slot->spd, spd_size);
getc();
}
#endif
}
// laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:
Platform.DMI.DIMM[i]=
i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.MaxMemorySlots==2 ?
i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.MaxMemorySlots == 2 ?
mapping[i] : i; // for laptops case, mapping setup would need to be more generic than this
slot->spd = NULL;
branches/valv/i386/libsaio/smbios_patcher.c
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else sm_defaults=sm_imac_core_defaults;
break;
case 0x1a: // Core i7 LGA1366, Xeon 550, 45nm
case 0x2a: // Sandy Bridge, 32nm
case 0x2c: // Core i7 LGA1366, "Westmere", 32nm, Hexa-Core
case 0x2e: // Core i7, Nehalem-Ex, Xeon
case 0x2f: // Core i7, "Westmere-Ex", 45nm, Hexa-Core
case 0x1e:// Core i7, i5 LGA1156, "Lynnfield", "Jasper", 45nm
case 0x1f:// Core i7, i5, Nehalem
case 0x25:// Core i7, i5, i3 LGA1156, "Westmere", 32nm
case 0x2a:// Sandy Bridge, 32nm
case 0x2c:// Core i7 LGA1366, "Westmere", 32nm, Hexa-Core
case 0x2e:// Core i7, Nehalem-Ex, Xeon
{
case 0x2f:// Core i7, "Westmere-Ex", 45nm, Hexa-Core
return 0x0501;
break;
case 0x2a:// Sandy Bridge, 32nm; valv: probably not here
case 0x25:// Nehalem, "Clarkdale", 32nm
if(strstr(Platform.CPU.BrandString, "Core(TM) i3"))
return 0x0901;
branches/valv/i386/libsaio/memvendors.h
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} VenIdName;
VenIdName vendorMap[] = {
{ 0, 0x01, "AMD"},
{ 0, 0x01, "AMD"},
{ 0, 0x02, "AMI"},
{ 0, 0x83, "Fairchild"},
{ 0, 0x04, "Fujitsu"},
branches/valv/i386/libsaio/nvidia.c
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#define DBG(x...)
#endif
#define NVIDIA_ROM_SIZE 0x10000
#define NVIDIA_ROM_SIZE 0x20000
#define PATCH_ROM_SUCCESS 1
#define PATCH_ROM_SUCCESS_HAS_LVDS 2
#define PATCH_ROM_FAILED 0
branches/valv/i386/libsaio/cpu.c
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switch (intelCPU)
{
case 0xc:// Core i7 & Atom
if (strstr(p->CPU.BrandString, "Atom")) goto teleport;
if (strstr(p->CPU.BrandString, "Atom")) goto teleport1;
case 0x1a:// Core i7 LGA1366, Xeon 5500, "Bloomfield", "Gainstown", 45nm
case 0x1e:// Core i7, i5 LGA1156, "Clarksfield", "Lynnfield", "Jasper", 45nm
case 0x1f:// Core i7, i5, Nehalem
case 0x25:// Core i7, i5, i3 LGA1156, "Westmere", "Clarkdale", "Arrandale", 32nm
case 0x2a:// Sandy Bridge, 32nm
case 0x2c:// Core i7 LGA1366, Six-core, "Westmere", "Gulftown", 32nm
case 0x2e:// Core i7, Nehalem-Ex Xeon, "Beckton"
case 0x2f:// Core i7, Nehalem-Ex Xeon, "Eagleton"
break;
case 0xd:// Pentium M, Dothan, 90nm
case 0xe:// Core Duo/Solo, Pentium M DC
goto teleport;
teleport1:
msr = rdmsr64(MSR_IA32_EXT_CONFIG);
if(msr & (1 << 30)) tjmax = 85;
goto teleport2;
case 0xf:// Core Xeon, Core 2 DC, 65nm
switch (Stepp)
{
break;
case 0xd:
default:
teleport:
msr = rdmsr64(MSR_IA32_EXT_CONFIG);
if(msr & (1 << 30)) tjmax = 85;
break;
}
case 0x16:// Celeron, Core 2 SC, 65nm
case 0x27:// Atom Lincroft, 45nm
teleport2:
core_i = false;
//valv: todo: msr_therm2_ctl (0x19d) bit 16 (mode of automatic thermal monitor): 0=tm1, 1=tm2
//also, if bit 3 of misc_enable is cleared the above would have no effect
{
msr_t msr32;
msr32 = rdmsr(MSR_IA32_MISC_ENABLE);
//thermally-initiated on-die modulation of the stop-clock duty cycle
if(!(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 3))) msr32.lo |= (1 << 3);
verbose("CPU: Thermal Monitor: TM, ");
//BIOS must enable this feature if the TM2 feature flag (CPUID.1:ECX[8]) is set
if(platformCPUFeature(CPU_FEATURE_TM2))
{
//thermally-initiated frequency transitions
msr32.lo |= (1 << 13);
verbose("TM2, ");
bool tmfix = false;
getBoolForKey(kFixTM, &tmfix, &bootInfo->bootConfig);
if(tmfix)
{
//thermally-initiated on-die modulation of the stop-clock duty cycle
if(!(rdmsr64(MSR_IA32_MISC_ENABLE) & (1 << 3))) msr32.lo |= (1 << 3);
verbose("CPU: Thermal Monitor: TM, ");
//BIOS must enable this feature if the TM2 feature flag (CPUID.1:ECX[8]) is set
if(platformCPUFeature(CPU_FEATURE_TM2))
{
//thermally-initiated frequency transitions
msr32.lo |= (1 << 13);
verbose("TM2, ");
}
msr32.lo |= (1 << 17);
verbose("PROCHOT, ");
msr32.lo |= (1 << 10);
verbose("FERR\n");
}
msr32.lo |= (1 << 17);
verbose("PROCHOT, ");
msr32.lo |= (1 << 10);
verbose("FERR\n");
bool oem_ssdt, tmpval;
oem_ssdt = false;
if((c4e) && platformCPUFeature(CPU_FEATURE_MOBILE)) msr32.hi |= (1 << (32 - 32));
getBoolForKey(kHardC4EEnable, &hc4e, &bootInfo->bootConfig);
if((hc4e) && platformCPUFeature(CPU_FEATURE_MOBILE)) msr32.hi |= (1 << (33 - 32));
if(c2e || c4e || hc4e) tmfix = true;
}
msr32.hi |= (1 << (36 - 32)); // EMTTM
wrmsr(MSR_IA32_MISC_ENABLE, msr32);
msr32 = rdmsr(PIC_SENS_CFG);
msr32.lo |= (1 << 21);
wrmsr(PIC_SENS_CFG, msr32);
if(tmfix)
{
msr32.hi |= (1 << (36 - 32)); // EMTTM
wrmsr(MSR_IA32_MISC_ENABLE, msr32);
}
if(tmfix)
{
msr32 = rdmsr(PIC_SENS_CFG);
msr32.lo |= (1 << 21);
wrmsr(PIC_SENS_CFG, msr32);
}
}
if (rdmsr64(MSR_IA32_EXT_CONFIG) & (1 << 27))
break;
}
}
uint64_t minfsb = 183000000, maxfsb = 185000000;
if (((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || (!fsbFrequency))
uint64_t minfsb = 182000000, maxfsb = 185000000;
if(((fsbFrequency > minfsb) && (fsbFrequency < maxfsb)) || !fsbFrequency)
{
fsbFrequency = 200000000;
fsbad = true;
}
}
//#if 0
else if(p->CPU.Vendor == 0x68747541 /* AMD */ && p->CPU.Family == 0x0f) // valv: work in progress
// valv: work in progress. Most of this code is going to be moved when ready
else if(p->CPU.Vendor == 0x68747541 /* AMD */ && p->CPU.Family == 0x0f)
{
verbose("CPU: ");
// valv: very experimental mobility check
do_cpuid(0x80000007, p->CPU.CPUID[CPUID_MAX]);
amo = bitfield(p->CPU.CPUID[CPUID_MAX][0], 6, 6);
const_tsc = bitfield(p->CPU.CPUID[CPUID_MAX][3], 8, 8);
// valv: p-state support verification
//uint32_t pstate_support = bitfield(p->CPU.CPUID[CPUID_MAX][3], 2, 1);
//if(pstate_support != 0) verbose("supproted p-state transition\n")
if (const_tsc != 0) verbose("Constant TSC!\n");
if (amo == 1)
if(p->CPU.ExtFamily == 0x00 /* K8 */)
{
// valv: this section needs some work
msr = rdmsr64(K8_FIDVID_STATUS);
bus_ratio_max = (msr & 0x3f) / 2 + 4;
bus_ratio_max = bitfield(msr, 21, 16);
//bus_ratio_max = (msr & 0x3f) / 2 + 4;
bus_ratio_min = bitfield(msr, 13, 8);
currdiv = (msr & 0x01) * 2;
if (bus_ratio_max)
{
cpuFrequency = tscFrequency; // ?
}
}
else if(p->CPU.ExtFamily >= 0x01 /* K10+ */)
{
msr = rdmsr64(K10_COFVID_STATUS);
currdiv = (2 << ((msr >> 6) & 0x07)) / 2;
currdiv = (2 << ((msr >> 6) & 0x07));
msr = rdmsr64(AMD_10H_11H_CONFIG);
if(p->CPU.ExtFamily == 0x01 /* K10 */)
bus_ratio_max = ((msr) & 0x3F);
//verbose("max_multi: %d\n", bus_ratio_max);
/*msr_t divmsr;
divmsr = rdmsr(AMD_10H_11H_CONFIG);
maxdiv = (divmsr.hi >> 0x08) & 0x01;
verbose("maxdiv: %d, currdiv: %d\n", maxdiv, currdiv);*/
if(p->CPU.ExtFamily == 0x01)
cpuFrequency = 100 * (bus_ratio_max + 0x10);
else
cpuFrequency = 100 * (bus_ratio_max + 0x08);
uint32_t minFreq = cpuFrequency / (1 << currdiv);
uint8_t maxrtio = (cpuFrequency / 20);
p->CPU.MaxRatio = maxrtio;
fsbFrequency = ((tscFrequency / 100000) / maxrtio);
verbose("fsb: %d\n", fsbFrequency);
if(maxrtio == ((bus_ratio_max * 10) - 5))
{
bus_ratio_max = ((msr) & 0x3F);
//currdiv = (((msr) >> 6) & 0x07);
//cpuFrequency = 100 * (bus_ratio_max + 0x08) / (1 << currdiv);
verbose("multi: max:%d.5, ", (bus_ratio_max - 1));
maxdiv = 1;
}
else /* K11+ */
else if(maxrtio == ((bus_ratio_max - 1) * 10))
{
bus_ratio_max = ((msr) & 0x3F);
//currdiv = (((msr) >> 6) & 0x07);
//cpuFrequency = 100 * (bus_ratio_max + 0x10) / (1 << currdiv);
verbose("multi: max:%d, min:", (bus_ratio_max - 1));
maxdiv = 0;
}
fsbFrequency = (tscFrequency / bus_ratio_max);
cpuFrequency = tscFrequency;
}
p->CPU.MaxRatio = bus_ratio_max * 10;
// valv: to be moved to acpi_patcher when ready
/*msr_t amsr = rdmsr(K8_FIDVID_STATUS);
uint8_t max_fid = (amsr.lo & 0x3F) >> 16;
uint8_t min_fid = (amsr.lo & 0x3F) >> 8;
uint8_t max_vid = (amsr.hi & 0x3F) >> 16;
uint8_t min_vid = (amsr.hi & 0x3F) >> 8;
verbose("AMD: max[fid: %d, vid: %d] min[fid: %d, vid: %d]\n", max_fid, max_vid, min_fid, min_vid);
bus_ratio_min = (minFreq / fsbFrequency);
verbose("%d", bus_ratio_min);
while(minFreq < 800)
{
bus_ratio_min = bus_ratio_min + 1; // bus_ratio_min++; ???
verbose(" >> %d", bus_ratio_min);
}
verbose("\n");
case 0x10:// phenom
msr = rdmsr64(AMD_10H_11H_CONFIG);
bus_ratio_max = ((msr) & 0x3F);
currdiv = (((msr) >> 6) & 0x07);
cpuFrequency = 100 * (bus_ratio_max + 0x08) / (1 << currdiv);
break;
case 0x11:// shangai
msr = rdmsr64(AMD_10H_11H_CONFIG);
bus_ratio_max = ((msr) & 0x3F);
currdiv = (((msr) >> 6) & 0x07);
cpuFrequency = 100 * (bus_ratio_max + 0x10) / (1 << currdiv);
break;
struct hwpstate
{
uint32_tfreq;/* CPU clock in Mhz. */
uint32_tvolts;/* Voltage in mV. */
uint32_tpower;/* Power consumed in mW. */
uint8_tlat;/* Transition latency in us. */
uint8_tpstate_id;/* P-State id */
};
struct hwpstate state[32];
int max_state, i,/* did,*/ vid;
uint8_t fid;
msr = rdmsr64(MSR_AMD_10H_11H_LIMIT);
max_state = 1 + (((msr) >> 4) & 0x7);
for(i=0; i<max_state; i++)
{
msr = rdmsr64(AMD_10H_11H_CONFIG + i);
//msr_t didmsr;
//didmsr = rdmsr(AMD_10H_11H_CONFIG + i);
if ((msr & ((uint64_t)1 << 63)) != ((uint64_t)1 << 63)) verbose("Invalid MSR!\n");
else
{
//did = (didmsr.hi >> 0x08) & 0x01;
if(i == 0)
{
//maxdiv = did;
fid = p->CPU.MaxRatio;
state[i].freq = ((fid * fsbFrequency) / 10);
fid = (fid / 10);
}
else
{
fid = bitfield(msr, 5, 0);
state[i].freq = (fid * fsbFrequency);
}
if(i == (max_state -1))
{
fid = bus_ratio_min;
state[i].freq = (fid * fsbFrequency);
}
vid = bitfield(msr, 15, 9);
if(i == 0) verbose("P-State %d: Frequency: %d, Multiplier: %d%s, vid: %d\n", i, state[i].freq, fid, maxdiv ? ".5" : "", vid);
else if((state[i].freq > state[i+1].freq) || (state[i].freq < 800)) verbose("P-State %d: Removed!", i);
else verbose("P-State %d: Frequency: %d, Multiplier: %d, vid: %d\n", i, state[i].freq, fid, vid);
state[i].pstate_id = i;
// valv: zeroed for now
state[i].volts = 0;
state[i].power = 0;
state[i].lat = 0;
}
}
fsbFrequency = (fsbFrequency * 1000000);
cpuFrequency = (state[0].freq * 1000000);
}
*/
p->CPU.MinRatio = bus_ratio_min * 10;
}
else if(p->CPU.Vendor == 0x746e6543 /* CENTAUR */ && p->CPU.Family == 6) //valv: partial!
{
branches/valv/i386/libsaio/cpu.h
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#define PIC_SENS_CFG 0x1aa
#define MSR_EBL_CR_POWERON 0x02a
#define K8_FIDVID_STATUS 0xC0010042
#defineMSR_AMD_10H_11H_LIMIT 0xc0010061
#defineAMD_10H_11H_CONFIG 0xc0010064
#define K10_COFVID_STATUS 0xC0010071
branches/valv/i386/libsaio/fake_efi.c
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*/
/* Identify ourselves as the EFI firmware vendor */
static EFI_CHAR16 const FIRMWARE_VENDOR[] = {'A','n','V','A','L','_','5','.','1', 1};
static EFI_CHAR16 const FIRMWARE_VENDOR[] = {'A','n','V','A','L','_','5','.','1', 0};
static EFI_UINT32 const FIRMWARE_REVISION = 132; /* FIXME: Find a constant for this. */
/* Default platform system_id (fix by IntVar) */
branches/valv/i386/MakeInc.dir
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installhdrs::
.SUFFIXES: .s .i .c .o
.SUFFIXES: .s .i .c .o .o32 .o64
.c.o32:
$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) -arch i386 $< -o $(OBJROOT)/$*.o32 \
-MD -dependency-file $(OBJROOT)/$*.d
md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
.c.o64:
$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) -arch x86_64 $< -o $(OBJROOT)/$*.o64 \
-MD -dependency-file $(OBJROOT)/$*.d
md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
.c.o .m.o:
$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) $< -o $(OBJROOT)/$*.o \
-MD -dependency-file $(OBJROOT)/$*.d
-MD -dependency-file $(OBJROOT)/$*.d
md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
$(OBJROOT)/%.o32: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) -arch i386 $< -o $(OBJROOT)/$*.o32 \
-MD -dependency-file $(OBJROOT)/$*.d
md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
$(OBJROOT)/%.o64: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) -arch x86_64 $< -o $(OBJROOT)/$*.o64 \
-MD -dependency-file $(OBJROOT)/$*.d
md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
$(OBJROOT)/%.o: %.m
$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) $< -o $(OBJROOT)/$*.o \
-MD -dependency-file $(OBJROOT)/$*.d
branches/valv/i386/boot2/graphics.c
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params[1] = 25;
}
setVESATextMode( params[0], params[1], 4 );
setVESATextMode( params[0], params[1], 4 );
bootArgs->Video.v_display = VGA_TEXT_MODE;
}
branches/valv/i386/boot2/boot.c
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if (getValueForKey(k64BitModeFlag, &val, &len, &bootInfo->bootConfig)) {
archCpuType = CPU_TYPE_X86_64;
}
if (!getBoolForKey (kWake, &tryresume, &bootInfo->bootConfig)) {
tryresume = true;
tryresumedefault = true;
branches/valv/i386/boot2/boot.h
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#define kC2EEnable"C2E"/* cpu.c */
#define kC4EEnable"C4E"/* cpu.c */
#define kHardC4EEnable"HC4E"/* cpu.c */
#define kFixTM"FixTM"/* cpu.c */
#define kdcfg0"display_0"/* nvidia.c */
#define kdcfg1"display_1"/* nvidia.c */
#define kpstates"PStates"/* acpi_patcher.c */
branches/valv/i386/boot2/drivers.c
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#include "bootstruct.h"
#include "xml.h"
#include "ramdisk.h"
#include "kernel_patcher.h"
extern char gMacOSVersion;
ret = ThinFatFile(&binary, &len);
}
patch_kernel(binary);
ret = DecodeMachO(binary, rentry, raddr, rsize);
if (ret<0 && archCpuType==CPU_TYPE_X86_64)
branches/valv/i386/boot2/prompt.c
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#include "vers.h"
char bootBanner[] = "\nDarwin/x86 boot v" I386BOOT_VERSION " - Chameleon v" I386BOOT_CHAMELEONVERSION " r" I386BOOT_CHAMELEONREVISION "\n"
char bootBanner[] = "\nDarwin/x86 boot v" I386BOOT_VERSION " - AnVAL v" I386BOOT_CHAMELEONVERSION " r" I386BOOT_CHAMELEONREVISION "\n"
"Build date: " I386BOOT_BUILDDATE "\n"
"%dMB memory\n";
branches/valv/i386/boot2/gui.c
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gui.screen.height = screen_params[1];
PRINT("Found mode %dx%d in VESA Table\n", gui.screen.width, gui.screen.height);
// load graphics otherwise fail and return
if (loadGraphics() == 0) {
loadThemeValues(&bootInfo->themeConfig);
branches/valv/i386/boot2/Makefile
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# The ordering is important;
# boot2.o must be first.
OBJS = boot2.o boot.o graphics.o drivers.o prompt.o options.o lzss.o mboot.o \
ramdisk.o picopng.o resume.o bmdecompress.o graphic_utils.o gui.o
ramdisk.o kernel_patcher.o picopng.o resume.o bmdecompress.o graphic_utils.o gui.o
# button.o browser.o scrollbar.o == NOTYET
UTILDIR = ../util
branches/valv/i386/util/Makefile
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all embedtheme autores_dbg debug: $(DIRS_NEEDED) $(PROGRAMS)
debug: CFLAGS += -DDEBUG
machOconv: machOconv.o
$(CC) $(CFLAGS) $(LDFLAGS) $(DEFINES) -o $(SYMROOT)/$(@F) machOconv.o
machOconv: machOconv.o32 machOconv.o64
$(CC) $(CFLAGS) $(LDFLAGS) $(DEFINES) -arch i386 -o $(SYMROOT)/$(@F)_32 $(OBJROOT)/$(@F).o32
$(CC) $(CFLAGS) $(LDFLAGS) $(DEFINES) -arch x86_64 -o $(SYMROOT)/$(@F)_64 $(OBJROOT)/$(@F).o64
lipo -create -arch i386 $(SYMROOT)/$(@F)_32 -arch x86_64 $(SYMROOT)/$(@F)_64 -output $(SYMROOT)/$(@F)
$(RM) $(SYMROOT)/$(@F)_32 $(SYMROOT)/$(@F)_64
bdmesg: bdmesg.o
$(CC) $(CFLAGS) $(LDFLAGS) -framework IOKit -framework CoreFoundation -mmacosx-version-min=10.5 -o $(SYMROOT)/$(@F) bdmesg.o
bdmesg: bdmesg.o32 bdmesg.o64
$(CC) $(CFLAGS) $(LDFLAGS) -framework IOKit -framework CoreFoundation -mmacosx-version-min=10.5 \
-arch i386 -o $(SYMROOT)/$(@F)_32 $(OBJROOT)/$(@F).o32
$(CC) $(CFLAGS) $(LDFLAGS) -framework IOKit -framework CoreFoundation -mmacosx-version-min=10.5 \
-arch x86_64 -o $(SYMROOT)/$(@F)_64 $(OBJROOT)/$(@F).o64
lipo -create -arch i386 $(SYMROOT)/$(@F)_32 -arch x86_64 $(SYMROOT)/$(@F)_64 -output $(SYMROOT)/$(@F)
$(RM) $(SYMROOT)/$(@F)_32 $(SYMROOT)/$(@F)_64
include ../MakeInc.dir
branches/valv/revision
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Revision: 705