Chameleon

Chameleon Commit Details

Date:2011-01-18 15:51:31 (3 years 9 months ago)
Author:Sergey Slice
Commit:708
Parents: 707
Message:CPUID, some mistakes, NVRAM beta2
Changes:
M/branches/slice/ChamMek/ChamMek.xcodeproj/slice.pbxuser
M/branches/slice/revision
M/branches/slice/i386/modules/ATI5000Enabler/ati5.c
M/branches/slice/i386/libsaio/platform.c
M/branches/slice/ChamMek/ChamMek.xcodeproj/slice.mode1v3
M/branches/slice/i386/boot2/boot.c
M/branches/slice/i386/libsaio/cpu.c
M/branches/slice/i386/modules/ATI5000Enabler/ati5.h
M/branches/slice/i386/libsaio/fake_efi.c
M/branches/slice/i386/boot2/boot.h
M/branches/slice/i386/boot2/modules.c
M/branches/slice/i386/libsaio/cpu.h
M/branches/slice/i386/modules/NVRAM/NVRAM.c
M/branches/slice/i386/libsaio/sys.c

File differences

branches/slice/i386/libsaio/sys.c
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#define MAX_HDD_COUNT 32
int bvCount;
int hd = 0;
// Testing up to MAX_HDD_COUNT hard drives.
while(!testBiosread(0x80 + hd, 0) && hd < MAX_HDD_COUNT)
while(!testBiosread(0x80 + hd, 0) && hd < MAX_HDD_COUNT)
{
bvCount = 0;
scanBootVolumes(0x80 + hd, &bvCount);
verbose("scanVolume %d\n", hd);
hd++;
}
// Also scanning CD/DVD drive.
if (biosDevIsCDROM(gBIOSDev))
// if (biosDevIsCDROM(gBIOSDev))
if (biosDevIsCDROM(gBIOSDev)) // 0 = CDROM
{
bvCount = 0;
//scanBootVolumes(gBIOSDev, &bvCount);
scanBootVolumes(gBIOSDev, &bvCount);
msglog("biosDevIsCDROM and bvCount=%d\n", bvCount);
}
branches/slice/i386/libsaio/platform.c
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#include "platform.h"
#include "cpu.h"
#include "modules.h"
#include "efi.h"
#ifndef DEBUG_PLATFORM
#define DEBUG_PLATFORM 0
#define DBG(x...)
#endif
//static
PlatformInfo_t* Platform;
BLESS_EFI_LOAD_OPTION* BootOrder;
/** Return if a CPU feature specified by feature is activated (true) or not (false) */
inline bool platformCPUFeature(uint32_t feature)
{
Platform = malloc(sizeof(PlatformInfo_t));
memset(Platform, 0, sizeof(PlatformInfo_t));
gPlatform = (void*)Platform;
BootOrder = malloc(sizeof(BLESS_EFI_LOAD_OPTION));
memset(BootOrder, 0, sizeof(BLESS_EFI_LOAD_OPTION));
gBootOrder = (void*)BootOrder;
build_pci_dt();
scan_cpu(); //Platform);
//scan_mem(); Rek: called after pci devs init in fake_efi now ...
branches/slice/i386/libsaio/cpu.c
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#endif
#if DEBUG_CPU
#define DBG(x...)verbose(x)
#define DBG(x...)printf(x)
#else
#define DBG(x...)msglog(x)
#endif
{
PlatformInfo_t *p = Platform;
int i = 0;
uint8_t turbo;
uint64_ttscFrequency, fsbFrequency, cpuFrequency;
uint64_tmsr; //, flex_ratio;
uint8_tmaxcoef, maxdiv, currcoef, currdiv, mindiv;
maxcoef = maxdiv = currcoef = currdiv = mindiv = 0;
#if DEBUG_CPU
printf("Enter cpuid_info\n");
pause();
#endif
cpuid_update_generic_info();
#if DEBUG_CPU
printf("...OK\n");
pause();
#endif
#if OLDMETHOD
/* get cpuid values */
for( ; i <= 3; i++)
{
if (p->CPU.NoThreads > p->CPU.NoCores) {
p->CPU.Features |= CPU_FEATURE_HTT;
}
#else //Slice
p->CPU.Vendor= *(UInt32*)&cpuid_info()->cpuid_vendor;
p->CPU.Signature= cpuid_info()->cpuid_signature;
p->CPU.Stepping= cpuid_info()->cpuid_stepping;
p->CPU.Model= cpuid_info()->cpuid_model;
p->CPU.Family= cpuid_info()->cpuid_family;
p->CPU.ExtModel= cpuid_info()->cpuid_extmodel;
p->CPU.ExtFamily= cpuid_info()->cpuid_extfamily;
//DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel);
//DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily);
strlcpy(p->CPU.BrandString, cpuid_info()->cpuid_brand_string, sizeof(p->CPU.BrandString));
DBG("CPU: BrandString %s\n", p->CPU.BrandString);
p->CPU.Features = cpuid_info()->cpuid_features;
p->CPU.NoCores = cpuid_info()->core_count;
p->CPU.NoThreads = cpuid_info()->thread_count;
//DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);
//DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv?2:1, p->CPU.CurrDiv?2:1);
//DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);
//DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);
//DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);
//DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);
//DBG("CPU: Features: 0x%08x\n", p->CPU.Features);
#if DEBUG_CPU
pause();
#endif
#endif
tscFrequency = measure_tsc_frequency();
DBG("measure_tsc_frequency = %dMHz\n", tscFrequency / MEGA);
(msr >> 32) & 0xffffffff, msr & 0xffffffff);
mindiv = (msr >> 40) & 0xff;
maxcoef = (msr >> 8) & 0xff;
msr = rdmsr64(MSR_TURBO_RATIO);
turbo = msr & 0x7f;
//Slice - doesn't work
/*
msr = rdmsr64(MSR_FLEX_RATIO);
fsbFrequency = 0;
break;
}
DBG("msr(0x%04x): MSR_FSB_FREQ %dMHz\n", MSR_FSB_FREQ, fsbFrequency/MEGA);
DBG("msr(0x%04x): MSR_FSB_FREQ %d.%dMHz\n", MSR_FSB_FREQ,
fsbFrequency/MEGA, (fsbFrequency%MEGA)/1000);
}
msr = rdmsr64(MSR_PLATFORM_INFO);
msr = rdmsr64(MSR_PLATFORM_INFO); //info only?
uint32_t m2 = msr >> 32;
DBG("msr(0x%04x): platform_info %08x-%08x\n", MSR_PLATFORM_INFO,
m2 & 0xffffffff, msr & 0xffffffff);
turbo = (m2 >> 8) & 0x1f;
msr = rdmsr64(MSR_IA32_PERF_STATUS);
m2 = msr >> 32;
*/
p->CPU.MaxCoef = maxcoef;
p->CPU.MaxCoef = turbo;
p->CPU.MaxDiv = maxdiv;
p->CPU.MinCoef = mindiv;
p->CPU.CurrCoef = currcoef;
DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel);
DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily);
DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);
DBG("CPU: MaxCoef/CurrCoef/Turbo: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef, turbo);
DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv?2:1, p->CPU.CurrDiv?2:1);
DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);
DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);
branches/slice/i386/libsaio/cpu.h
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extern void scan_cpu(); //PlatformInfo_t *);
#define min(a,b) ((a) < (b) ? (a) : (b))
#define quad(hi,lo) (((uint64_t)(hi)) << 32 | (lo))
#define bit(n)(1UL << (n))
#define bitmask(h,l)((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
#define bitfield(x,h,l)(((x) & bitmask(h,l)) >> l)
#define CPU_STRING_UNKNOWN"Unknown CPU Typ"
#defineCPUID_VID_INTEL"GenuineIntel"
#defineCPUID_VID_AMD"AuthenticAMD"
#define CPUID_STRING_UNKNOWN "Unknown CPU Typ"
#define _Bit(n)(1ULL << n)
#define _HBit(n)(1ULL << ((n)+32))
/*
* The CPUID_FEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 1:
*/
#defineCPUID_FEATURE_FPU _Bit(0)/* Floating point unit on-chip */
#defineCPUID_FEATURE_VME _Bit(1)/* Virtual Mode Extension */
#defineCPUID_FEATURE_DE _Bit(2)/* Debugging Extension */
#defineCPUID_FEATURE_PSE _Bit(3)/* Page Size Extension */
#defineCPUID_FEATURE_TSC _Bit(4)/* Time Stamp Counter */
#defineCPUID_FEATURE_MSR _Bit(5)/* Model Specific Registers */
#define CPUID_FEATURE_PAE _Bit(6)/* Physical Address Extension */
#defineCPUID_FEATURE_MCE _Bit(7)/* Machine Check Exception */
#defineCPUID_FEATURE_CX8 _Bit(8)/* CMPXCHG8B */
#defineCPUID_FEATURE_APIC _Bit(9)/* On-chip APIC */
#define CPUID_FEATURE_SEP _Bit(11)/* Fast System Call */
#defineCPUID_FEATURE_MTRR _Bit(12)/* Memory Type Range Register */
#defineCPUID_FEATURE_PGE _Bit(13)/* Page Global Enable */
#defineCPUID_FEATURE_MCA _Bit(14)/* Machine Check Architecture */
#defineCPUID_FEATURE_CMOV _Bit(15)/* Conditional Move Instruction */
#define CPUID_FEATURE_PAT _Bit(16)/* Page Attribute Table */
#define CPUID_FEATURE_PSE36 _Bit(17)/* 36-bit Page Size Extension */
#define CPUID_FEATURE_PSN _Bit(18)/* Processor Serial Number */
#define CPUID_FEATURE_CLFSH _Bit(19)/* CLFLUSH Instruction supported */
#define CPUID_FEATURE_DS _Bit(21)/* Debug Store */
#define CPUID_FEATURE_ACPI _Bit(22)/* Thermal monitor and Clock Ctrl */
#define CPUID_FEATURE_MMX _Bit(23)/* MMX supported */
#define CPUID_FEATURE_FXSR _Bit(24)/* Fast floating pt save/restore */
#define CPUID_FEATURE_SSE _Bit(25)/* Streaming SIMD extensions */
#define CPUID_FEATURE_SSE2 _Bit(26)/* Streaming SIMD extensions 2 */
#define CPUID_FEATURE_SS _Bit(27)/* Self-Snoop */
#define CPUID_FEATURE_HTT _Bit(28)/* Hyper-Threading Technology */
#define CPUID_FEATURE_TM _Bit(29)/* Thermal Monitor (TM1) */
#define CPUID_FEATURE_PBE _Bit(31)/* Pend Break Enable */
#define CPUID_FEATURE_SSE3 _HBit(0)/* Streaming SIMD extensions 3 */
#define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ Instruction */
#define CPUID_FEATURE_MONITOR _HBit(3)/* Monitor/mwait */
#define CPUID_FEATURE_DSCPL _HBit(4)/* Debug Store CPL */
#define CPUID_FEATURE_VMX _HBit(5)/* VMX */
#define CPUID_FEATURE_SMX _HBit(6)/* SMX */
#define CPUID_FEATURE_EST _HBit(7)/* Enhanced SpeedsTep (GV3) */
#define CPUID_FEATURE_TM2 _HBit(8)/* Thermal Monitor 2 */
#define CPUID_FEATURE_SSSE3 _HBit(9)/* Supplemental SSE3 instructions */
#define CPUID_FEATURE_CID _HBit(10)/* L1 Context ID */
#define CPUID_FEATURE_CX16 _HBit(13)/* CmpXchg16b instruction */
#define CPUID_FEATURE_xTPR _HBit(14)/* Send Task PRiority msgs */
#define CPUID_FEATURE_PDCM _HBit(15)/* Perf/Debug Capability MSR */
#define CPUID_FEATURE_DCA _HBit(18)/* Direct Cache Access */
#define CPUID_FEATURE_SSE4_1 _HBit(19)/* Streaming SIMD extensions 4.1 */
#define CPUID_FEATURE_SSE4_2 _HBit(20)/* Streaming SIMD extensions 4.2 */
#define CPUID_FEATURE_xAPIC _HBit(21)/* Extended APIC Mode */
#define CPUID_FEATURE_POPCNT _HBit(23)/* POPCNT instruction */
#define CPUID_FEATURE_AES _HBit(25)/* AES instructions */
#define CPUID_FEATURE_VMM _HBit(31)/* VMM (Hypervisor) present */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
*/
#define CPUID_EXTFEATURE_SYSCALL _Bit(11)/* SYSCALL/sysret */
#define CPUID_EXTFEATURE_XD _Bit(20)/* eXecute Disable */
#define CPUID_EXTFEATURE_1GBPAGE _Bit(26) /* 1G-Byte Page support */
#define CPUID_EXTFEATURE_RDTSCP _Bit(27)/* RDTSCP */
#define CPUID_EXTFEATURE_EM64T _Bit(29)/* Extended Mem 64 Technology */
//#define CPUID_EXTFEATURE_LAHF _HBit(20)/* LAFH/SAHF instructions */
// New definition with Snow kernel
#define CPUID_EXTFEATURE_LAHF _HBit(0)/* LAHF/SAHF instructions */
/*
* The CPUID_EXTFEATURE_XXX values define 64-bit values
* returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
*/
#define CPUID_EXTFEATURE_TSCI _Bit(8)/* TSC Invariant */
#defineCPUID_CACHE_SIZE16/* Number of descriptor values */
#define CPUID_MWAIT_EXTENSION_Bit(0)/* enumeration of WMAIT extensions */
#define CPUID_MWAIT_BREAK_Bit(1)/* interrupts are break events */
#define MSR_IA32_PLATFORM_ID0x0017
#define MSR_P4_EBC_FREQUENCY_ID0x002C
#define MSR_CORE_THREAD_COUNT0x0035
#defineMSR_IA32_PERF_STATUS0x0198
#define MSR_IA32_PERF_CONTROL0x0199
#define MSR_IA32_EXT_CONFIG0x00EE
#define CALIBRATE_TIME_MSEC30/* 30 msecs */
#define CALIBRATE_LATCH((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)
typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
/*
* Cache ID descriptor structure, used to parse CPUID leaf 2.
* Note: not used in kernel.
*/
typedef enum { Lnone, L1I, L1D, L2U, L3U, LCACHE_MAX } cache_type_t ;
typedef struct {
unsigned charvalue; /* Descriptor value */
cache_type_t type; /* Cache type */
unsigned int size; /* Cache size */
unsigned int linesize; /* Cache line size */
const char*description; /* Cache description */
} cpuid_cache_desc_t;
#define CACHE_DESC(value,type,size,linesize,text) \
{ value, type, size, linesize, text }
/* Physical CPU info - this is exported out of the kernel (kexts), so be wary of changes */
typedef struct {
charcpuid_vendor[16];
charcpuid_brand_string[48];
const char*cpuid_model_string;
cpu_type_tcpuid_type;/* this is *not* a cpu_type_t in our <mach/machine.h> */
uint8_tcpuid_family;
uint8_tcpuid_model;
uint8_tcpuid_extmodel;
uint8_tcpuid_extfamily;
uint8_tcpuid_stepping;
uint64_tcpuid_features;
uint64_tcpuid_extfeatures;
uint32_tcpuid_signature;
uint8_t cpuid_brand;
uint32_tcache_size[LCACHE_MAX];
uint32_tcache_linesize;
uint8_tcache_info[64]; /* list of cache descriptors */
uint32_tcpuid_cores_per_package;
uint32_tcpuid_logical_per_package;
uint32_tcache_sharing[LCACHE_MAX];
uint32_tcache_partitions[LCACHE_MAX];
cpu_type_tcpuid_cpu_type;/* <mach/machine.h> */
cpu_subtype_tcpuid_cpu_subtype;/* <mach/machine.h> */
/* Monitor/mwait Leaf: */
uint32_tcpuid_mwait_linesize_min;
uint32_tcpuid_mwait_linesize_max;
uint32_tcpuid_mwait_extensions;
uint32_tcpuid_mwait_sub_Cstates;
/* Thermal and Power Management Leaf: */
boolean_tcpuid_thermal_sensor;
boolean_tcpuid_thermal_dynamic_acceleration;
uint32_tcpuid_thermal_thresholds;
boolean_tcpuid_thermal_ACNT_MCNT;
/* Architectural Performance Monitoring Leaf: */
uint8_tcpuid_arch_perf_version;
uint8_tcpuid_arch_perf_number;
uint8_tcpuid_arch_perf_width;
uint8_tcpuid_arch_perf_events_number;
uint32_tcpuid_arch_perf_events;
uint8_tcpuid_arch_perf_fixed_number;
uint8_tcpuid_arch_perf_fixed_width;
/* Cache details: */
uint32_tcpuid_cache_linesize;
uint32_tcpuid_cache_L2_associativity;
uint32_tcpuid_cache_size;
/* Virtual and physical address aize: */
uint32_tcpuid_address_bits_physical;
uint32_tcpuid_address_bits_virtual;
uint32_tcpuid_microcode_version;
/* Numbers of tlbs per processor [i|d, small|large, level0|level1] */
uint32_tcpuid_tlb[2][2][2];
#defineTLB_INST0
#defineTLB_DATA1
#defineTLB_SMALL0
#defineTLB_LARGE1
uint32_tcpuid_stlb;
uint32_tcore_count;
uint32_tthread_count;
/* Max leaf ids available from CPUID */
uint32_tcpuid_max_basic;
uint32_tcpuid_max_ext;
} i386_cpu_info_t;
static i386_cpu_info_t cpuid_cpu_info;
static i386_cpu_info_t*cpuid_info(void)
{
return &cpuid_cpu_info;
}
static inline uint64_t rdtsc64(void)
{
uint64_t ret;
return count;
}
static void cpuid_update_generic_info()
{
uint32_t cpuid_reg[4];
uint32_t max_extid;
char str[128];
char* p;
i386_cpu_info_t* info_p = cpuid_info();
/* Get vendor */
do_cpuid(0, cpuid_reg);
bcopy((char *)&cpuid_reg[ebx], &info_p->cpuid_vendor[0], 4); /* ug */
bcopy((char *)&cpuid_reg[ecx], &info_p->cpuid_vendor[8], 4);
bcopy((char *)&cpuid_reg[edx], &info_p->cpuid_vendor[4], 4);
info_p->cpuid_vendor[12] = 0;
/* Get extended CPUID results */
do_cpuid(0x80000000, cpuid_reg);
max_extid = cpuid_reg[eax];
/* Check to see if we can get the brand string */
if (max_extid >= 0x80000004) {
/*
* The brand string is up to 48 bytes and is guaranteed to be
* NUL terminated.
*/
do_cpuid(0x80000002, cpuid_reg);
bcopy((char *)cpuid_reg, &str[0], 16);
do_cpuid(0x80000003, cpuid_reg);
bcopy((char *)cpuid_reg, &str[16], 16);
do_cpuid(0x80000004, cpuid_reg);
bcopy((char *)cpuid_reg, &str[32], 16);
for (p = str; *p != '\0'; p++) {
if (*p != ' ') break;
}
strncpy(info_p->cpuid_brand_string, p,
sizeof(info_p->cpuid_brand_string));
if (!strncmp(info_p->cpuid_brand_string, CPUID_STRING_UNKNOWN,
min(sizeof(info_p->cpuid_brand_string),
strlen(CPUID_STRING_UNKNOWN) + 1))) {
/*
* This string means we have a firmware-programmable brand string,
* and the firmware couldn't figure out what sort of CPU we have.
*/
info_p->cpuid_brand_string[0] = '\0';
}
}
/* Get cache and addressing info */
if (max_extid >= 0x80000006) {
do_cpuid(0x80000006, cpuid_reg);
info_p->cpuid_cache_linesize = bitfield(cpuid_reg[ecx], 7, 0);
info_p->cpuid_cache_L2_associativity = bitfield(cpuid_reg[ecx], 15, 12);
info_p->cpuid_cache_size = bitfield(cpuid_reg[ecx], 31, 16);
do_cpuid(0x80000008, cpuid_reg);
info_p->cpuid_address_bits_physical = bitfield(cpuid_reg[eax], 7, 0);
info_p->cpuid_address_bits_virtual = bitfield(cpuid_reg[eax], 15, 8);
}
/* Get processor signature and decode */
do_cpuid(1, cpuid_reg);
info_p->cpuid_signature = cpuid_reg[eax];
info_p->cpuid_stepping = bitfield(cpuid_reg[eax], 3, 0);
info_p->cpuid_model = bitfield(cpuid_reg[eax], 7, 4);
info_p->cpuid_family = bitfield(cpuid_reg[eax], 11, 8);
info_p->cpuid_type = bitfield(cpuid_reg[eax], 13, 12);
info_p->cpuid_extmodel = bitfield(cpuid_reg[eax], 19, 16);
info_p->cpuid_extfamily = bitfield(cpuid_reg[eax], 27, 20);
info_p->cpuid_brand = bitfield(cpuid_reg[ebx], 7, 0);
info_p->cpuid_features = quad(cpuid_reg[ecx], cpuid_reg[edx]);
/* Fold extensions into family/model */
if (info_p->cpuid_family == 0x0f) {
info_p->cpuid_family += info_p->cpuid_extfamily;
}
if (info_p->cpuid_family == 0x0f || info_p->cpuid_family== 0x06) {
info_p->cpuid_model += (info_p->cpuid_extmodel << 4);
}
if (info_p->cpuid_features & CPUID_FEATURE_HTT) {
info_p->cpuid_logical_per_package = bitfield(cpuid_reg[ebx], 23, 16);
} else {
info_p->cpuid_logical_per_package = 1;
}
if (max_extid >= 0x80000001) {
do_cpuid(0x80000001, cpuid_reg);
info_p->cpuid_extfeatures = quad(cpuid_reg[ecx], cpuid_reg[edx]);
}
if (info_p->cpuid_extfeatures & CPUID_FEATURE_MONITOR) {
do_cpuid(5, cpuid_reg);
info_p->cpuid_mwait_linesize_min = cpuid_reg[eax];
info_p->cpuid_mwait_linesize_max = cpuid_reg[ebx];
info_p->cpuid_mwait_extensions = cpuid_reg[ecx];
info_p->cpuid_mwait_sub_Cstates = cpuid_reg[edx];
do_cpuid(6, cpuid_reg);
info_p->cpuid_thermal_sensor = bitfield(cpuid_reg[eax], 0, 0);
info_p->cpuid_thermal_dynamic_acceleration =
bitfield(cpuid_reg[eax], 1, 1);
info_p->cpuid_thermal_thresholds = bitfield(cpuid_reg[ebx], 3, 0);
info_p->cpuid_thermal_ACNT_MCNT = bitfield(cpuid_reg[ecx], 0, 0);
do_cpuid(0xa, cpuid_reg);
info_p->cpuid_arch_perf_version = bitfield(cpuid_reg[eax], 7, 0);
info_p->cpuid_arch_perf_number = bitfield(cpuid_reg[eax],15, 8);
info_p->cpuid_arch_perf_width = bitfield(cpuid_reg[eax],23,16);
info_p->cpuid_arch_perf_events_number = bitfield(cpuid_reg[eax],31,24);
info_p->cpuid_arch_perf_events = cpuid_reg[ebx];
info_p->cpuid_arch_perf_fixed_number = bitfield(cpuid_reg[edx], 4, 0);
info_p->cpuid_arch_perf_fixed_width = bitfield(cpuid_reg[edx],12, 5);
}
do_cpuid(4, cpuid_reg);
info_p->cpuid_cores_per_package = bitfield(cpuid_reg[eax], 31, 26) + 1;
if (info_p->cpuid_cores_per_package == 0) {
info_p->cpuid_cores_per_package = 1;
}
switch (info_p->cpuid_model)
{
case 0x1C:
{
//uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT);
info_p->core_count = 1; //bitfield((uint32_t)msr, 19, 16);
info_p->thread_count = 2; //bitfield((uint32_t)msr, 15, 0);
}
break;
case 0x19: // some i5 ???
case 0x1A: // Intel Core i7 LGA1366 (45nm)
case 0x1E: // Intel Core i5, i7 LGA1156 (45nm)
case 0x25: // Intel Core i3, i5, i7 LGA1156 (32nm)
{
uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT);
info_p->core_count = bitfield((uint32_t)msr, 31, 16);
info_p->thread_count = bitfield((uint32_t)msr, 15, 0);
} break;
case 0x2C: // Intel Core i7 LGA1366 (32nm) 6 Core
case 0x1F:
case 0x2F:
{
uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT);
info_p->core_count = bitfield((uint32_t)msr, 19, 16);
info_p->thread_count = bitfield((uint32_t)msr, 15, 0);
break;
}
default:
{
do_cpuid(1, cpuid_reg);
info_p->core_count = bitfield(cpuid_reg[1], 23, 16);
} break;
}
if (info_p->core_count == 0) {
info_p->core_count = info_p->cpuid_cores_per_package;
info_p->thread_count = info_p->cpuid_logical_per_package;
}
}
#endif /* !__LIBSAIO_CPU_H */
branches/slice/i386/libsaio/fake_efi.c
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#undef static
#endif
//BLESS_EFI_LOAD_OPTION* BootOrder;
extern struct SMBEntryPoint * getSmbios(int which); // now cached
//extern void setup_pci_devs(pci_dt_t *pci_dt);
//Slice - remember globals
Platform = (PlatformInfo_t *)gPlatform;
root_pci_dev = (pci_dt_t*)gRootPCIDev;
//gBootOrder = (void*)BootOrder;
//verbose("setupFakeEfi: root_pci_dev_Vendor=%04x\n", (root_pci_dev->children)->vendor_id);
setup_pci_devs((pci_dt_t*)gRootPCIDev);
continue;
}
//TODO validate
msglog("Patched platform CPU Info:\n FSB=%d\n MaxSpeed=%d\n CurrentSpeed=%d\n", Platform->CPU.FSBFrequency/MEGA, Platform->CPU.TSCFrequency/MEGA, Platform->CPU.CPUFrequency/MEGA);
//msglog("Patched platform CPU Info:\n FSB=%d\n MaxSpeed=%d\n CurrentSpeed=%d\n",
// Platform->CPU.FSBFrequency/MEGA, Platform->CPU.TSCFrequency/MEGA, Platform->CPU.CPUFrequency/MEGA);
msglog("Patched SMBIOS CPU Info:\n FSB=%d\n MaxSpeed=%d\n CurrentSpeed=%d\n", cpuInfo->externalClock, cpuInfo->maximumClock, cpuInfo->currentClock);
msglog(" Family=%x\n Socket=%x\n Cores=%d Enabled=%d Threads=%d\n", cpuInfo->processorFamily, cpuInfo->processorUpgrade, cpuInfo->coreCount, cpuInfo->coreEnabled, cpuInfo->Threads);
msglog(" Family=%x Socket=%x\n Cores=%d Enabled=%d Threads=%d\n", cpuInfo->processorFamily, cpuInfo->processorUpgrade, cpuInfo->coreCount, cpuInfo->coreEnabled, cpuInfo->Threads);
}
#endif
}
branches/slice/i386/boot2/boot.c
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char gMacOSVersion[8];
void *gRootPCIDev;
void *gPlatform;
void *gBootOrder;
void *gSMBIOS;
int gDualLink;
#ifndef OPTION_ROM
#endif
#if DEBUG
printf(" Default: %x, ->biosdev: %x, ->part_no: %d ->flags: %x\n", gBootVolume, gBootVolume->biosdev, gBootVolume->part_no, gBootVolume->flags);
printf(" bt(0,0): %x, ->biosdev: %x, ->part_no: %d ->flags: %x\n", gBIOSBootVolume, gBIOSBootVolume->biosdev, gBIOSBootVolume->part_no, gBIOSBootVolume->flags);
getc();
printf(" Default: %x, ->gBootVolume: %x, ->part_no: %d ->flags: %x\n", gBootVolume, gBootVolume->biosdev, gBootVolume->part_no, gBootVolume->flags);
printf(" bt(0,0): %x, ->gBIOSBootVolume: %x, ->part_no: %d ->flags: %x\n", gBIOSBootVolume, gBIOSBootVolume->biosdev, gBIOSBootVolume->part_no, gBIOSBootVolume->flags);
pause();
/* Results
Rescan found 1 HDD and bvCount=4
bvr: 836bc10, dev: 80, part: 4, flags: 4a, vis: 1
branches/slice/i386/boot2/modules.c
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if(strcmp(&name[strlen(name) - sizeof("dylib")], ".dylib") == 0)
{
char* tmp = malloc(strlen(name) + 1);
if (name[0] == '.') {
continue;
}
strcpy(tmp, name);
DBG("Attempting to load %s\n", tmp);
if(fh < 0)
{
DBG("Unable to locate module %s\n", modString);
getc();
//getc();
return 0;
}
branches/slice/i386/boot2/boot.h
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extern int bvCount;
extern void *gRootPCIDev;
extern void* gPlatform;
extern void* gBootOrder;
/*
/* AsereBLN: added the other keys */
#define kUseAtiROM"UseAtiROM"/* ati.c */
#define kAtiConfig"AtiConfig"/* ati.c */
#define kATYbinimage"ATYbinimage"/* ati.c */
#define kWake"Wake"/* boot.c */
#define kForceWake"ForceWake"/* boot.c */
#define kWakeImage"WakeImage"/* boot.c */
branches/slice/i386/modules/NVRAM/NVRAM.c
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#include "pci.h"
#include "efi.h"
#include "smbios_patcher.h"
#include "xml.h"
#ifndef DEBUG_NVRAM
#define DEBUG_NVRAM 0
#define DEBUG_NVRAM 1
#endif
#if DEBUG_NVRAM
#define DBG(x...) verbose(x)
#define DBG(x...) printf(x)
#else
#define DBG(x...) msglog(x)
#endif
char*bnName;
EFI_GUID*ret = 0;
uint16_tbootOptionNumber = 0;
//msglog("NVRAM is not implemented yet\n");
int i, j;
//return;
BLESS_EFI_LOAD_OPTION* NextBoot =(BLESS_EFI_LOAD_OPTION*)gBootOrder;
DBG("NVRAM started with ModulesLoaded\n");
//bool UseNVRAM = FALSE;
bool ClearNVRAM = FALSE;
const char* buff;
TagPtrdictionary;
int cnt;
var = malloc(sizeof(variables)+1);
ClearNVRAM = getValueForKey(kClearNVRAM, &buff, &cnt, &bootInfo->bootConfig);
if (!ClearNVRAM) {
readNVRAM(var);
}
Node* optionsNode = DT__FindNode("/options", true);
for (i=0; i<32; i++) {
if (var[i].Name[0] == 0) {
break;
}
if (strcmp(var[i].Name, "efi-boot-device")==0) {
//XMLParseFile(var[i].Value, &dictionary);
//buff = XMLGetProperty(dictionary, "BLLastBSDName")->string;
verbose("Required boot device is %s\n", var[i].Value);
//NextBoot->FilePathListLength = 1;
//strcpy(NextBoot->Description, buff);
break;
}
}
Node* optionsNode = DT__FindNode("/fakenvram", true);
ffName = malloc(sizeof(PLATFORM_UUID)+1);
strcpy(ffName, PLATFORM_UUID);
ret = getSystemID();
*/
//
int i,j;
for (i=0; i<32; i++) {
DBG("NVRAM get a name %s\n", var[i].Name);
if (var[i].Name[0]) {
DBG("NVRAM add name=%s value=%s length=%d\n", var[i].Name, var[i].Value, j);
#endif
} else {
return;
break;
}
}
//Serialization?
bnName[0] = bnName[1] = 0;
DT__AddProperty(optionsNode, bnName, sizeof(uint32_t), (EFI_UINT32*)&STATIC_ZERO);
}
const char NVRAM_INF[] = "nvram.inf";
return -1;
}
close (fd);
if ((var = malloc(fsize)) == NULL) {
/*if ((var = malloc(fsize)) == NULL) {
DBG("[ERROR] alloc VAR memory failed\n");
return -1;
}
}*/
int i = 0;
char * onvr = nvr;
bool skipGUID;
while (*nvr) {
int j = 0;
skipGUID = false;
DBG("Name[%d]:", i);
while (*nvr != 9) {
//DBG("%c", *nvr);
if (*nvr == 4) {
skipGUID = true; //TODO this is GUID
}
var[i].Name[j++] = *nvr++;
nvr++;
} else
var[i].Name[j++] = *nvr++;
}
DBG("\n");
nvr++; //skip \09
var[i].Name[j] = 0; //end of c-string
if (skipGUID) {
//TODO this is GUID
DBG("skip GUID\n");
while (*nvr++ != 0x0A) {}
i--;
} else {
j = 0;
char c;
unsigned char c;
while (*nvr != 0x0A) {
c = *nvr++;
if (c == 0x25) { //TODO this is hex
k2 = k2 - 0x60 + 10;
}
c = (k1 << 4) + k2;
break;
//break;
}
var[i].Value[j++] = c;
}
nvr++;
DBG("Value[%d]:", i);
int m;
for (m=0; m<j; m++) {
//DBG("%02x ", var[i].Value[m]);
}
//DBG("Value[%d]:%s\n", i, var[i].Value);
DBG("\n");
}
i++;
if (i > fsize) {
if ((int)(nvr - onvr) > fsize) {
DBG("end of buffer\n");
break;
}
}
var[i].Name[0]=0;
var[i].Name[1]=0;
return 0;
}
branches/slice/i386/modules/ATI5000Enabler/ati5.c
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#include "ati_reg.h"
#include "ati5.h"
#defineOFFSET_TO_GET_ATOMBIOS_STRINGS_START0x6e
#define Reg32(reg)(*(volatile uint32_t *)(card->mmio + reg))
#define RegRead32(reg)(Reg32(reg))
#define RegWrite32(reg, value)(Reg32(reg) = value)
{"Langur",3},
{"Megalodon",3},
{"Motmot",2},
{"Nomascus",5},
{"Orangutan",2},
{"Peregrine",2},
{"Quail",3},
{"Raven",3},
kLangur,
kMegalodon,
kMotmot,
kNomascus,
kOrangutan,
kPeregrine,
kQuail,
kRaven,
/* Evergreen */
{ 0x6898,0x032E1043,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kUakari},
{ 0x6898,0xE140174B,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kUakari},
{ 0x6898,0x29611682,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kUakari},
{ 0x6898,0x0B001002,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kZonalis},
{ 0x6898,0x00D0106B,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kLangur},
{ 0x6899,0x21E41458,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5850",kUakari},
{ 0x6899,0x200A1787,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5850",kUakari},
{ 0x68B8,0x29911682,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x200B1787,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x22881787,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x00CF106B,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kHoolock},
{ 0x68D8,0x301117AF,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5690",kNull},
{ 0x68D8,0x301017AF,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5730",kNull},
bool get_conntype_val(value_t *val);
bool get_vrammemsize_val(value_t *val);
bool get_binimage_val(value_t *val);
bool get_romrevision_val(value_t *val);
bool get_deviceid_val(value_t *val);
bool get_mclk_val(value_t *val);
bool get_sclk_val(value_t *val);
//{FLAGTRUE,false,"AAPL,backlight-control",NULL,DWRVAL((uint32_t)0)},
{FLAGTRUE,false,"ATY,bin_image",get_binimage_val,NULVAL},
{FLAGTRUE,false,"ATY,Copyright",NULL,STRVAL("Copyright AMD Inc. All Rights Reserved. 2005-2010")},
{FLAGTRUE,false,"ATY,Card#",get_romrevision_val,NULVAL},
{FLAGTRUE,false,"ATY,VendorID",NULL,WRDVAL((uint16_t)0x1002)},
{FLAGTRUE,false,"ATY,DeviceID",get_deviceid_val,NULVAL},
return true;
}
bool get_romrevision_val(value_t *val)
{
uint8_t *rev;
if (!card->rom)
return false;
rev = card->rom + *(uint8_t *)(card->rom + OFFSET_TO_GET_ATOMBIOS_STRINGS_START);
val->type = kPtr;
val->size = strlen((char *)rev);
val->data = malloc(val->size);
if (!val->data)
return false;
memcpy(val->data, rev, val->size);
return true;
}
bool get_deviceid_val(value_t *val)
{
val->type = kCst;
get_vram_size();
getBoolForKey(kVBIOS, &add_vbios, &bootInfo->bootConfig);
getBoolForKey(kATYbinimage, &add_vbios, &bootInfo->bootConfig);
if (add_vbios)
if (!load_vbios_file(kUseAtiROM, pci_dev->vendor_id, pci_dev->device_id, pci_dev->subsys_id.subsys_id))
branches/slice/i386/modules/ATI5000Enabler/ati5.h
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/*
* ATI injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas
* Copyright (C) 2010 Kabyl
*
* ATI injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
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