Chameleon

Chameleon Commit Details

Date:2011-05-18 05:13:43 (12 years 11 months ago)
Author:mozo
Commit:829
Parents: 828
Message:Sandy Bridge Xeon, mem.c & mem.h removed, cores/treads count resolving from Chimera branch
Changes:
D/trunk/i386/libsaio/mem.h
D/trunk/i386/libsaio/mem.c
M/trunk/i386/libsaio/acpi_patcher.c
M/trunk/Chameleon.xcodeproj/project.pbxproj
M/trunk/i386/libsaio/cpu.c
M/trunk/i386/libsaio/platform.h
M/trunk/i386/libsaio/smbios_getters.c
M/trunk/i386/libsaio/cpu.h
M/trunk/i386/libsaio/smbios.c

File differences

trunk/Chameleon.xcodeproj/project.pbxproj
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␉␉B0056D4A11F3868000754B65 /* load.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = load.c; sourceTree = "<group>"; };␊
␉␉B0056D4B11F3868000754B65 /* Makefile */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.make; path = Makefile; sourceTree = "<group>"; };␊
␉␉B0056D4C11F3868000754B65 /* md5c.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = md5c.c; sourceTree = "<group>"; };␊
␉␉B0056D4D11F3868000754B65 /* mem.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = mem.c; sourceTree = "<group>"; };␊
␉␉B0056D4E11F3868000754B65 /* mem.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = mem.h; sourceTree = "<group>"; };␊
␉␉B0056D4F11F3868000754B65 /* memvendors.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = memvendors.h; sourceTree = "<group>"; };␊
␉␉B0056D5011F3868000754B65 /* misc.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = misc.c; sourceTree = "<group>"; };␊
␉␉B0056D5111F3868000754B65 /* msdos.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; path = msdos.c; sourceTree = "<group>"; };␊
␉␉␉␉B0056D4A11F3868000754B65 /* load.c */,␊
␉␉␉␉B0056D4B11F3868000754B65 /* Makefile */,␊
␉␉␉␉B0056D4C11F3868000754B65 /* md5c.c */,␊
␉␉␉␉B0056D4D11F3868000754B65 /* mem.c */,␊
␉␉␉␉B0056D4E11F3868000754B65 /* mem.h */,␊
␉␉␉␉B0056D4F11F3868000754B65 /* memvendors.h */,␊
␉␉␉␉B0056D5011F3868000754B65 /* misc.c */,␊
␉␉␉␉B0056D5111F3868000754B65 /* msdos.c */,␊
trunk/i386/libsaio/mem.c
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/*␊
* Copyright 2010 AsereBLN. All rights reserved. <aserebln@googlemail.com>␊
*␊
* mem.c - obtain system memory information␊
*/␊
␊
#include "libsaio.h"␊
#include "pci.h"␊
#include "platform.h"␊
#include "cpu.h"␊
#include "mem.h"␊
#include "smbios_patcher.h"␊
␊
#ifndef DEBUG_MEM␊
#define DEBUG_MEM 0␊
#endif␊
␊
#if DEBUG_MEM␊
#define DBG(x...)␉␉printf(x)␊
#else␊
#define DBG(x...)␊
#endif␊
␊
#define DC(c) (c >= 0x20 && c < 0x7f ? (char) c : '.')␊
#define STEP 16␊
␊
void dumpPhysAddr(const char * title, void * a, int len)␊
{␊
int i,j;␊
u_int8_t* ad = (u_int8_t*) a;␊
char buffer[80];␊
char str[16];␊
␊
if(ad==NULL) return;␊
␊
printf("%s addr=0x%08x len=%04d\n",title ? title : "Dump of ", a, len);␊
printf("Ofs-00-01-02-03-04-05-06-07-08-09-0A-0B-0C-0D-0E-0F ASCII\n");␊
i = (len/STEP)*STEP;␊
for (j=0; j < i; j+=STEP)␊
{␊
printf("%02x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c\n",␊
j, ␊
ad[j], ad[j+1], ad[j+2], ad[j+3] , ad[j+4], ad[j+5], ad[j+6], ad[j+7],␊
ad[j+8], ad[j+9], ad[j+10], ad[j+11] , ad[j+12], ad[j+13], ad[j+14], ad[j+15],␊
DC(ad[j]), DC(ad[j+1]), DC(ad[j+2]), DC(ad[j+3]) , DC(ad[j+4]), DC(ad[j+5]), DC(ad[j+6]), DC(ad[j+7]),␊
DC(ad[j+8]), DC(ad[j+9]), DC(ad[j+10]), DC(ad[j+11]) , DC(ad[j+12]), DC(ad[j+13]), DC(ad[j+14]), DC(ad[j+15])␊
); ␊
}␊
␊
if (len%STEP==0) return;␊
sprintf(buffer,"%02x:", i);␊
for (j=0; j < STEP; j++) {␊
if (j<(len%STEP))␊
sprintf(str, " %02x", ad[i+j]);␊
else␊
strcpy(str, " " ); ␊
strncat(buffer, str, sizeof(buffer));␊
}␊
strncat(buffer," ", sizeof(buffer));␊
for (j=0; j < (len%STEP); j++) {␊
sprintf(str, "%c", DC(ad[i+j])); ␊
strncat(buffer, str, sizeof(buffer));␊
}␊
printf("%s\n",buffer);␊
}␊
␊
void dumpAllTablesOfType(int i)␊
{␊
char title[32];␊
struct DMIHeader * dmihdr;␊
for(dmihdr = FindFirstDmiTableOfType(i, 4);␊
dmihdr;␊
dmihdr = FindNextDmiTableOfType(i, 4)) {␊
sprintf(title,"Table (type %d) :" , i); ␊
dumpPhysAddr(title, dmihdr, dmihdr->length+32);␊
}␊
}␊
␊
const char * getDMIString(struct DMIHeader * dmihdr, uint8_t strNum)␊
{␊
const char * ret =NULL;␊
const char * startAddr = (const char *) dmihdr;␊
const char * limit = NULL;␊
␊
if (!dmihdr || dmihdr->length<4 || strNum==0) return NULL;␊
startAddr += dmihdr->length;␊
limit = startAddr + 256;␊
for(; strNum; strNum--) {␊
if ((*startAddr)==0 && *(startAddr+1)==0) break;␊
if (*startAddr && strNum<=1) {␊
ret = startAddr; // current str␊
break;␊
}␊
while(*startAddr && startAddr<limit) startAddr++;␊
if (startAddr==limit) break; // no terminator found␊
else if((*startAddr==0) && *(startAddr+1)==0) break;␊
else startAddr++;␊
}␊
␊
return ret;␊
}␊
␊
void scan_memory(PlatformInfo_t *p)␊
{␊
int i=0;␊
struct DMIHeader * dmihdr = NULL;␊
␊
struct DMIMemoryModuleInfo* memInfo[MAX_RAM_SLOTS]; // 6␊
struct DMIPhysicalMemoryArray* physMemArray; // 16␊
struct DMIMemoryDevice* memDev[MAX_RAM_SLOTS]; //17␊
␊
/* We mainly don't use obsolete tables 5,6 because most of computers don't handle it anymore */␊
Platform.DMI.MemoryModules = 0;␊
/* Now lets peek info rom table 16,17 as for some bios, table 5 & 6 are not used */␊
physMemArray = (struct DMIPhysicalMemoryArray*) FindFirstDmiTableOfType(16, 4);␊
Platform.DMI.MaxMemorySlots = physMemArray ? physMemArray->numberOfMemoryDevices : 0;␊
␊
i = 0;␊
for(dmihdr = FindFirstDmiTableOfType(17, 4);␊
dmihdr;␊
dmihdr = FindNextDmiTableOfType(17, 4) ) {␊
memDev[i] = (struct DMIMemoryDevice*) dmihdr;␊
if (memDev[i]->size !=0 ) Platform.DMI.MemoryModules++;␊
if (memDev[i]->speed>0) Platform.RAM.DIMM[i].Frequency = memDev[i]->speed; // take it here for now but we'll check spd and dmi table 6 as well␊
i++;␊
}␊
// for table 6, we only have a look at the current speed␊
i = 0;␊
for(dmihdr = FindFirstDmiTableOfType(6, 4);␊
dmihdr;␊
dmihdr = FindNextDmiTableOfType(6, 4) ) {␊
memInfo[i] = (struct DMIMemoryModuleInfo*) dmihdr;␊
if (memInfo[i]->currentSpeed > Platform.RAM.DIMM[i].Frequency) ␊
Platform.RAM.DIMM[i].Frequency = memInfo[i]->currentSpeed; // favor real overclocked speed if any␊
i++;␊
}␊
#if 0␊
dumpAllTablesOfType(17);␊
getc();␊
#endif␊
}␊
trunk/i386/libsaio/mem.h
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/*␊
* Copyright 2010 AsereBLN. All rights reserved. <aserebln@googlemail.com>␊
*␊
* mem.h␊
*/␊
␊
#ifndef __LIBSAIO_MEM_H␊
#define __LIBSAIO_MEM_H␊
␊
#include "platform.h"␊
␊
extern void scan_memory(PlatformInfo_t *);␊
␊
␊
#endif␉/* __LIBSAIO_MEM_H */␊
trunk/i386/libsaio/acpi_patcher.c
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␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
␉␉␉␉␉case CPU_MODEL_WESTMERE:␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊
␉␉␉␉␉case CPU_MODEL_SANDY:␊
case CPU_MODEL_SANDY:␊
case CPU_MODEL_SANDY_XEON: ␊
␉␉␉␉␉{␊
␉␉␉␉␉␉maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; // Seems it always contains maximum multiplier value (with turbo, that's we need)...␊
␉␉␉␉␉␉minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff;␊
trunk/i386/libsaio/cpu.c
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␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
␊
␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
␉␊
p->CPU.Model += (p->CPU.ExtModel << 4);␊
␊
if (p->CPU.Vendor == 0x756E6547 /* Intel */ && p->CPU.Family == 0x06 && p->CPU.Model >= 0x1a){␊
msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉␉␉␉␉// Using undocumented MSR to get actual values␊
p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉␉␉␉␉// Using undocumented MSR to get actual values␊
␉} else {␊
p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␉␉// Use previous method for Cores and Threads␊
p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
␉}␊
␉␊
␉/* get brand string (if supported) */␊
␉/* Copyright: from Apple's XNU cpuid.c */␊
␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
␉␉int intelCPU = p->CPU.Model;␊
␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊
␉␉␉/* Nehalem CPU model */␊
␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == 0x1a || p->CPU.Model == 0x1e␊
␉␉␉ || p->CPU.Model == 0x1f || p->CPU.Model == 0x25 || p->CPU.Model == 0x2c || p->CPU.Model == CPU_MODEL_SANDY)) {␊
␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM || ␊
p->CPU.Model == CPU_MODEL_FIELDS || ␊
p->CPU.Model == CPU_MODEL_DALES || ␊
p->CPU.Model == CPU_MODEL_DALES_32NM || ␊
p->CPU.Model == CPU_MODEL_WESTMERE ||␊
p->CPU.Model == CPU_MODEL_NEHALEM_EX ||␊
p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊
p->CPU.Model == CPU_MODEL_SANDY ||␊
p->CPU.Model == CPU_MODEL_SANDY_XEON)) {␊
␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, msr & 0xffffffff);␊
␉␉␉␉bus_ratio_max = (msr >> 8) & 0xff;␊
trunk/i386/libsaio/platform.h
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#define CPU_MODEL_DALES_32NM␉0x25␉/* Clarkdale, Arrandale */␊
#define CPU_MODEL_SANDY␉␉␉0x2a␉/* Sandy bridge */␊
#define CPU_MODEL_WESTMERE␉␉0x2C␉/* Gulftown, Westmere-EP, Westmere-WS */␊
#define CPU_MODEL_SANDY_XEON␉0x2D␊
#define CPU_MODEL_NEHALEM_EX␉0x2E␊
#define CPU_MODEL_WESTMERE_EX␉0x2F␊
␊
trunk/i386/libsaio/cpu.h
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#define MSR_IA32_PERF_CONTROL␉0x199␊
#define MSR_IA32_EXT_CONFIG␉␉0x00EE␊
#define MSR_FLEX_RATIO␉␉␉0x194␊
#define MSR_TURBO_RATIO_LIMIT␉␉0x1AD␊
#define MSR_TURBO_RATIO_LIMIT␉0x1AD␊
#define␉MSR_PLATFORM_INFO␉␉0xCE␊
#define MSR_CORE_THREAD_COUNT␉0x35␉␉␉// Undocumented␊
␊
#define K8_FIDVID_STATUS␉␉0xC0010042␊
#define K10_COFVID_STATUS␉␉0xC0010071␊
␊
trunk/i386/libsaio/smbios.c
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␉␉␉␉␉␉␉␉break;␊
␊
␉␉␉␉␉␉␉case CPU_MODEL_SANDY:␊
case CPU_MODEL_SANDY_XEON:␊
␉␉␉␉␉␉␉␉defaultBIOSInfo.version␉␉␉= kDefaultiMacSandyBIOSVersion;␊
␉␉␉␉␉␉␉␉defaultSystemInfo.productName␉= kDefaultiMacSandy;␊
␉␉␉␉␉␉␉␉defaultSystemInfo.family␉␉= kDefaultiMacFamily;␊
trunk/i386/libsaio/smbios_getters.c
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␊
␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
␉␉␉␉␉case CPU_MODEL_SANDY:␉␉// Intel Core i5, i7 LGA1155 sandy bridge␊
case CPU_MODEL_SANDY_XEON: ␊
␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊
␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊
␉␉␉␉␉case CPU_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_SANDY:␉␉␉␉// Intel Core i3, i5, i7 LGA1155 sandy bridge␊
case CPU_MODEL_SANDY_XEON:␊
␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊

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