Chameleon Commit Details - 842 - Chameleon open source boot loader project.

Date:

2011-05-20 08:36:19 (12 years 11 months ago)

Author:

Azimutz

Commit:

842

Parents:

841

Message:

Merge trunk (r827/828/829). Update xcodeproj.

Changes:

D	/branches/azimutz/Chazi/i386/modules/Memory/mem.h
D	/branches/azimutz/Chazi/i386/modules/Memory/mem.c
M	/branches/azimutz/Chazi/i386/libsaio/smbios_getters.h
M	/branches/azimutz/Chazi/i386/libsaio/acpi_patcher.c
M	/branches/azimutz/Chazi
M	/branches/azimutz/Chazi/Chameleon.xcodeproj/project.pbxproj
M	/branches/azimutz/Chazi/i386/modules/Memory/spd.c
M	/branches/azimutz/Chazi/i386/libsaio/cpu.c
M	/branches/azimutz/Chazi/i386/libsaio/fake_efi.c
M	/branches/azimutz/Chazi/i386/libsaio/platform.h
M	/branches/azimutz/Chazi/i386/libsaio/smbios_getters.c
M	/branches/azimutz/Chazi/i386/boot2/boot.h
M	/branches/azimutz/Chazi/i386/libsaio/cpu.h
M	/branches/azimutz/Chazi/i386/libsaio/smbios.c

File differences

-10
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+#define SMBIOS_RANGE_START      0x000F0000␊
#define SMBIOS_RANGE_END        0x000FFFFF␊
␊
#define NOT_AVAILABLE␉␉␉"N/A"␊
␊
typedef enum {␊
␉kSMBString,␊
␉kSMBByte,␊
 #define SMBIOS_RANGE_START      0x000F0000␊
 #define SMBIOS_RANGE_END        0x000FFFFF␊
 ␊
+#define NOT_AVAILABLE␉␉␉"N/A"␊
+␊
 typedef enum {␊
 ␉kSMBString,␊
 ␉kSMBByte,␊

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+␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
␉␉␉␉␉case CPU_MODEL_WESTMERE:␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊
␉␉␉␉␉case CPU_MODEL_SANDY:␊
␉␉␉␉␉case CPU_MODEL_SANDY_XEON:␊
␉␉␉␉␉{␊
␉␉␉␉␉␉// Seems it always contains maximum multiplier value (with turbo, that's what we need)...␊
␉␉␉␉␉␉maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff;␊
␉␉␉␉␉␉␊
␉␉␉␉␉␉minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff;␊
␊
␉␉␉␉␉␉verbose("P-States: min 0x%x, max 0x%x\n", minimum.Control, maximum.Control);␊
 ␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
 ␉␉␉␉␉case CPU_MODEL_WESTMERE:␊
 ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊
+␉␉␉␉␉case CPU_MODEL_SANDY:␊
+␉␉␉␉␉case CPU_MODEL_SANDY_XEON:␊
 ␉␉␉␉␉{␊
-␉␉␉␉␉␉// Seems it always contains maximum multiplier value (with turbo, that's what we need)...␊
 ␉␉␉␉␉␉maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff;␊
-␉␉␉␉␉␉␊
 ␉␉␉␉␉␉minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff;␊
 ␊
 ␉␉␉␉␉␉verbose("P-States: min 0x%x, max 0x%x\n", minimum.Control, maximum.Control);␊

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+#define CPU_MODEL_FIELDS␉␉0x1E␉␉␉␉␉// Lynnfield, Clarksfield, Jasper␊
#define CPU_MODEL_DALES␉␉␉0x1F␉␉␉␉␉// Havendale, Auburndale␊
#define CPU_MODEL_DALES_32NM␉0x25␉␉␉␉␉// Clarkdale, Arrandale␊
#define CPU_MODEL_SANDY␉␉␉0x2a␉␉␉␉␉// Sandy bridge␊
#define CPU_MODEL_WESTMERE␉␉0x2C␉␉␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊
#define CPU_MODEL_SANDY_XEON␉0x2D␊
#define CPU_MODEL_NEHALEM_EX␉0x2E␊
#define CPU_MODEL_WESTMERE_EX␉0x2F␊
␊

␉␉uint64_t␉␉␉␉TSCFrequency;␉␉␉// TSC Frequency Hz␊
␉␉uint64_t␉␉␉␉FSBFrequency;␉␉␉// FSB Frequency Hz␊
␉␉uint64_t␉␉␉␉CPUFrequency;␉␉␉// CPU Frequency Hz␊
␉␉uint32_t␉␉␉␉MaxRatio;␉␉␉␉// Max Bus Ratio␊
␉␉uint32_t␉␉␉␉MinRatio;␉␉␉␉// Min Bus Ratio␊
␉␉char␉␉␉␉␉BrandString[48];␉␉// 48 Byte Branding String␊
␉␉uint32_t␉␉␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊
␉} CPU;␊
 ...
 #define CPU_MODEL_FIELDS␉␉0x1E␉␉␉␉␉// Lynnfield, Clarksfield, Jasper␊
 #define CPU_MODEL_DALES␉␉␉0x1F␉␉␉␉␉// Havendale, Auburndale␊
 #define CPU_MODEL_DALES_32NM␉0x25␉␉␉␉␉// Clarkdale, Arrandale␊
+#define CPU_MODEL_SANDY␉␉␉0x2a␉␉␉␉␉// Sandy bridge␊
 #define CPU_MODEL_WESTMERE␉␉0x2C␉␉␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊
+#define CPU_MODEL_SANDY_XEON␉0x2D␊
 #define CPU_MODEL_NEHALEM_EX␉0x2E␊
 #define CPU_MODEL_WESTMERE_EX␉0x2F␊
 ␊
 ␉␉uint64_t␉␉␉␉TSCFrequency;␉␉␉// TSC Frequency Hz␊
 ␉␉uint64_t␉␉␉␉FSBFrequency;␉␉␉// FSB Frequency Hz␊
 ␉␉uint64_t␉␉␉␉CPUFrequency;␉␉␉// CPU Frequency Hz␊
+␉␉uint32_t␉␉␉␉MaxRatio;␉␉␉␉// Max Bus Ratio␊
+␉␉uint32_t␉␉␉␉MinRatio;␉␉␉␉// Min Bus Ratio␊
 ␉␉char␉␉␉␉␉BrandString[48];␉␉// 48 Byte Branding String␊
 ␉␉uint32_t␉␉␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊
 ␉} CPU;␊

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+#define kDefaultiMacNehalem␉␉␉␉␉␉␉"iMac11,1"␊
#define kDefaultiMacNehalemBIOSVersion␉␉␉␉"    IM111.88Z.0034.B00.0802091538"␊
#define kDefaultiMacNehalemBoardProduct␉␉␉␉"Mac-F2268DAE"␊
// defaults for an iMac12,1␊
#define kDefaultiMacSandy␉␉␉␉␉␉␉"iMac12,1"␊
#define kDefaultiMacSandyBIOSVersion␉␉␉␉"    IM121.88Z.0047.B00.1102091756"␊
#define kDefaultiMacSandyBoardProduct␉␉␉␉"Mac-F2268DAE" // find value ??␊
␊
// defaults for a Mac Pro␊
#define kDefaultMacProFamily␉␉␉␉␉␉"MacPro"␊

␉␉␉␉␉␉␉␉defaultBaseBoard.product␉␉= kDefaultiMacNehalemBoardProduct;␊
␉␉␉␉␉␉␉␉break;␊
␊
␉␉␉␉␉␉␉case CPU_MODEL_SANDY:␊
␉␉␉␉␉␉␉case CPU_MODEL_SANDY_XEON:␊
␉␉␉␉␉␉␉␉defaultBIOSInfo.version␉␉␉= kDefaultiMacSandyBIOSVersion;␊
␉␉␉␉␉␉␉␉defaultSystemInfo.productName␉= kDefaultiMacSandy;␊
␉␉␉␉␉␉␉␉defaultSystemInfo.family␉␉= kDefaultiMacFamily;␊
␉␉␉␉␉␉␉␉defaultBaseBoard.product␉␉= kDefaultiMacSandyBoardProduct; // ??␊
␉␉␉␉␉␉␉␉break;␊
␉␉␉␉␉␉␉case CPU_MODEL_NEHALEM: ␊
␉␉␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
␉␉␉␉␉␉␉␉defaultBIOSInfo.version␉␉␉= kDefaultMacProNehalemBIOSVersion;␊

␉}␊
}␊
␊
/* Used for SM*_N smbios.plist keys */␊
/* Used for SM*n smbios.plist keys */␊
bool getSMBValueForKey(SMBStructHeader *structHeader, const char *keyString, const char **string, returnType *value)␊
{␊
␉static int idx = -1;␊
 ...
 ...
 #define kDefaultiMacNehalem␉␉␉␉␉␉␉"iMac11,1"␊
 #define kDefaultiMacNehalemBIOSVersion␉␉␉␉"    IM111.88Z.0034.B00.0802091538"␊
 #define kDefaultiMacNehalemBoardProduct␉␉␉␉"Mac-F2268DAE"␊
+// defaults for an iMac12,1␊
+#define kDefaultiMacSandy␉␉␉␉␉␉␉"iMac12,1"␊
+#define kDefaultiMacSandyBIOSVersion␉␉␉␉"    IM121.88Z.0047.B00.1102091756"␊
+#define kDefaultiMacSandyBoardProduct␉␉␉␉"Mac-F2268DAE" // find value ??␊
 ␊
 // defaults for a Mac Pro␊
 #define kDefaultMacProFamily␉␉␉␉␉␉"MacPro"␊
 ␉␉␉␉␉␉␉␉defaultBaseBoard.product␉␉= kDefaultiMacNehalemBoardProduct;␊
 ␉␉␉␉␉␉␉␉break;␊
 ␊
+␉␉␉␉␉␉␉case CPU_MODEL_SANDY:␊
+␉␉␉␉␉␉␉case CPU_MODEL_SANDY_XEON:␊
+␉␉␉␉␉␉␉␉defaultBIOSInfo.version␉␉␉= kDefaultiMacSandyBIOSVersion;␊
+␉␉␉␉␉␉␉␉defaultSystemInfo.productName␉= kDefaultiMacSandy;␊
+␉␉␉␉␉␉␉␉defaultSystemInfo.family␉␉= kDefaultiMacFamily;␊
+␉␉␉␉␉␉␉␉defaultBaseBoard.product␉␉= kDefaultiMacSandyBoardProduct; // ??␊
+␉␉␉␉␉␉␉␉break;␊
 ␉␉␉␉␉␉␉case CPU_MODEL_NEHALEM: ␊
 ␉␉␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
 ␉␉␉␉␉␉␉␉defaultBIOSInfo.version␉␉␉= kDefaultMacProNehalemBIOSVersion;␊
 ␉}␊
 }␊
 ␊
-/* Used for SM*_N smbios.plist keys */␊
+/* Used for SM*n smbios.plist keys */␊
 bool getSMBValueForKey(SMBStructHeader *structHeader, const char *keyString, const char **string, returnType *value)␊
 {␊
 ␉static int idx = -1;␊

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+#define MSR_IA32_PERF_CONTROL␉0x199␊
#define MSR_IA32_EXT_CONFIG␉␉0x00EE␊
#define MSR_FLEX_RATIO␉␉␉0x194␊
#define MSR_TURBO_RATIO_LIMIT␉0x1AD␊
#define␉MSR_PLATFORM_INFO␉␉0xCE␊
#define K8_FIDVID_STATUS␉␉0xC0010042␊
#define K10_COFVID_STATUS␉␉0xC0010071␊
#define MSR_CORE_THREAD_COUNT␉0x35␉␉// Undocumented␊
␊
//#define DEFAULT_FSB␉␉100000          // for now, hardcoding 100MHz for old CPUs - disabled␊
␊
 #define MSR_IA32_PERF_CONTROL␉0x199␊
 #define MSR_IA32_EXT_CONFIG␉␉0x00EE␊
 #define MSR_FLEX_RATIO␉␉␉0x194␊
+#define MSR_TURBO_RATIO_LIMIT␉0x1AD␊
 #define␉MSR_PLATFORM_INFO␉␉0xCE␊
 #define K8_FIDVID_STATUS␉␉0xC0010042␊
 #define K10_COFVID_STATUS␉␉0xC0010071␊
+#define MSR_CORE_THREAD_COUNT␉0x35␉␉// Undocumented␊
 ␊
 //#define DEFAULT_FSB␉␉100000          // for now, hardcoding 100MHz for old CPUs - disabled␊
 ␊

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+␉}␊
}␊
␊
/**␊
␉what for ??␊
**/␊
void saveOriginalSMBIOS(void)␊
{␊
␉Node *node;␊
␉SMBEntryPoint *origeps;␊
␉void *tableAddress;␊
␊
␉node = DT__FindNode("/efi/platform", false);␊
␉if (!node)␊
␉{␊
␉␉verbose("/efi/platform node not found\n");␊
␉␉return;␊
␉}␊
␊
␉origeps = getSmbios(SMBIOS_ORIGINAL);␊
␉if (!origeps)␊
␉{␊
␉␉return;␊
␉}␊
␊
␉tableAddress = (void *)AllocateKernelMemory(origeps->dmi.tableLength);␊
␉if (!tableAddress)␊
␉{␊
␉␉return;␊
␉}␊
␊
␉memcpy(tableAddress, (void *)origeps->dmi.tableAddress, origeps->dmi.tableLength);␊
␉DT__AddProperty(node, "SMBIOS", origeps->dmi.tableLength, tableAddress);␊
}␊
␊
/*␊
 * Entrypoint from boot.c␊
 */␊

␉setup_pci_devs(root_pci_dev);␊
␉␊
␉readSMBIOSInfo(getSmbios(SMBIOS_ORIGINAL));␊
␊
␉␊
␉// load smbios.plist file if any␊
//␉setupSmbiosConfigFile("SMBIOS.plist");␊
␉scan_mem();␊

␉// Initialize the device tree␊
␉setupEfiDeviceTree();␊
␉␊
␉saveOriginalSMBIOS();␊
␉␊
␉// Add configuration table entries to both the services table and the device tree␊
␉setupEfiConfigurationTable();␊
}␊
 ...
 ...
 ␉}␊
 }␊
 ␊
+/**␊
+␉what for ??␊
+**/␊
+void saveOriginalSMBIOS(void)␊
+{␊
+␉Node *node;␊
+␉SMBEntryPoint *origeps;␊
+␉void *tableAddress;␊
+␊
+␉node = DT__FindNode("/efi/platform", false);␊
+␉if (!node)␊
+␉{␊
+␉␉verbose("/efi/platform node not found\n");␊
+␉␉return;␊
+␉}␊
+␊
+␉origeps = getSmbios(SMBIOS_ORIGINAL);␊
+␉if (!origeps)␊
+␉{␊
+␉␉return;␊
+␉}␊
+␊
+␉tableAddress = (void *)AllocateKernelMemory(origeps->dmi.tableLength);␊
+␉if (!tableAddress)␊
+␉{␊
+␉␉return;␊
+␉}␊
+␊
+␉memcpy(tableAddress, (void *)origeps->dmi.tableAddress, origeps->dmi.tableLength);␊
+␉DT__AddProperty(node, "SMBIOS", origeps->dmi.tableLength, tableAddress);␊
+}␊
+␊
 /*␊
  * Entrypoint from boot.c␊
  */␊
 ␉setup_pci_devs(root_pci_dev);␊
 ␉␊
 ␉readSMBIOSInfo(getSmbios(SMBIOS_ORIGINAL));␊
-␊
+␉␊
 ␉// load smbios.plist file if any␊
 //␉setupSmbiosConfigFile("SMBIOS.plist");␊
 ␉scan_mem();␊
 ␉// Initialize the device tree␊
 ␉setupEfiDeviceTree();␊
 ␉␊
+␉saveOriginalSMBIOS();␊
+␉␊
 ␉// Add configuration table entries to both the services table and the device tree␊
 ␉setupEfiConfigurationTable();␊
 }␊

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+␉␉␉␉␉␉return false;␊
␊
␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
␉␉␉␉␉case CPU_MODEL_SANDY:␉␉// Intel Core i5, i7 LGA1155 sandy bridge␊
␉␉␉␉␉case CPU_MODEL_SANDY_XEON:␊
␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊
␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊
␉␉␉␉␉case CPU_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊

␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_SANDY:␉␉␉␉// Intel Core i3, i5, i7 LGA1155 sandy bridge␊
␉␉␉␉␉case CPU_MODEL_SANDY_XEON:␊
␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊

␉␉}␊
␉}␊
␊
␉return false;␊
//␉value->string = "N/A";␊
//␉return true;␊
//␉return false;␊
␉value->string = NOT_AVAILABLE;␊
␉return true;␊
}␊
␉␊
bool getSMBMemoryDeviceSerialNumber(returnType *value)␊

␉␉map = Platform.DMI.DIMM[idx];␊
␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
␉␉{␊
␉␉␉DBG("name = %s, map=%d,  RAM Detected SerialNo[%d]='%s'\n", name ? name : "", ␊
␉␉␉␉map, idx, Platform.RAM.DIMM[map].SerialNo);␊
␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
␉␉␉return true;␊
␉␉}␊
␉}␊
␊
␉return false;␊
//␉value->string = "N/A";␊
//␉return true;␊
//␉return false;␊
␉value->string = NOT_AVAILABLE;␊
␉return true;␊
}␊
␊
bool getSMBMemoryDevicePartNumber(returnType *value)␊

␉␉map = Platform.DMI.DIMM[idx];␊
␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
␉␉{␊
␉␉␉DBG("Ram Detected PartNo[%d]='%s'\n", idx, Platform.RAM.DIMM[map].PartNo);␊
␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
␉␉␉return true;␊
␉␉}␊
␉}␊
␊
␉return false;␊
//␉value->string = "N/A";␊
//␉return true;␊
//␉return false;␊
␉value->string = NOT_AVAILABLE;␊
␉return true;␊
}␊
␊
␊
 ...
 ...
 ...
 ...
 ␉␉␉␉␉␉return false;␊
 ␊
 ␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
+␉␉␉␉␉case CPU_MODEL_SANDY:␉␉// Intel Core i5, i7 LGA1155 sandy bridge␊
+␉␉␉␉␉case CPU_MODEL_SANDY_XEON:␊
 ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊
 ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊
 ␉␉␉␉␉case CPU_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊
 ␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
 ␉␉␉␉␉␉return true;␊
 ␊
+␉␉␉␉␉case CPU_MODEL_SANDY:␉␉␉␉// Intel Core i3, i5, i7 LGA1155 sandy bridge␊
+␉␉␉␉␉case CPU_MODEL_SANDY_XEON:␊
 ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)␊
 ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
 ␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
 ␉␉}␊
 ␉}␊
 ␊
-␉return false;␊
-//␉value->string = "N/A";␊
-//␉return true;␊
+//␉return false;␊
+␉value->string = NOT_AVAILABLE;␊
+␉return true;␊
 }␊
 ␉␊
 bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
 ␉␉map = Platform.DMI.DIMM[idx];␊
 ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
 ␉␉{␊
-␉␉␉DBG("name = %s, map=%d,  RAM Detected SerialNo[%d]='%s'\n", name ? name : "", ␊
-␉␉␉␉map, idx, Platform.RAM.DIMM[map].SerialNo);␊
+␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
 ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
 ␉␉␉return true;␊
 ␉␉}␊
 ␉}␊
 ␊
-␉return false;␊
-//␉value->string = "N/A";␊
-//␉return true;␊
+//␉return false;␊
+␉value->string = NOT_AVAILABLE;␊
+␉return true;␊
 }␊
 ␊
 bool getSMBMemoryDevicePartNumber(returnType *value)␊
 ␉␉map = Platform.DMI.DIMM[idx];␊
 ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
 ␉␉{␊
-␉␉␉DBG("Ram Detected PartNo[%d]='%s'\n", idx, Platform.RAM.DIMM[map].PartNo);␊
+␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
 ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
 ␉␉␉return true;␊
 ␉␉}␊
 ␉}␊
 ␊
-␉return false;␊
-//␉value->string = "N/A";␊
-//␉return true;␊
+//␉return false;␊
+␉value->string = NOT_AVAILABLE;␊
+␉return true;␊
 }␊
 ␊
 ␊

-144
145 145
146 146
147
147 148
148 149
149 150
+#define kEHCIhardKey␉␉ "EHCIhard"␉␉␉ // usb.c␉␉␉␉getBoolFK␉␉␉␉- ??␊
#define kUHCIresetKey␉␉ "UHCIreset"␉␉ // usb.c␉␉␉␉getBoolFK␊
#define kLegacyOffKey␉␉ "USBLegacyOff"␉␉ // usb.c␉␉␉␉getBoolFK␊
#define kBusRatioKey␉␉ "busratio"␉␉␉ // cpu.c␉␉␉␉getValFK␊
␊
/*␊
 * Flags to the booter and/or kernel - these end with "Flag".␊
 #define kEHCIhardKey␉␉ "EHCIhard"␉␉␉ // usb.c␉␉␉␉getBoolFK␉␉␉␉- ??␊
 #define kUHCIresetKey␉␉ "UHCIreset"␉␉ // usb.c␉␉␉␉getBoolFK␊
 #define kLegacyOffKey␉␉ "USBLegacyOff"␉␉ // usb.c␉␉␉␉getBoolFK␊
+#define kBusRatioKey␉␉ "busratio"␉␉␉ // cpu.c␉␉␉␉getValFK␊
 ␊
 /*␊
  * Flags to the booter and/or kernel - these end with "Flag".␊

-
2 
3 
4 
5 
6 
7 
8 
9 
10 
11 
12 
13 
14 
15
+/*␊
 * Copyright 2010 AsereBLN. All rights reserved. <aserebln@googlemail.com>␊
 *␊
 * mem.h␊
 */␊
␊
#ifndef __LIBSAIO_MEM_H␊
#define __LIBSAIO_MEM_H␊
␊
#include "platform.h"␊
␊
extern void scan_memory(PlatformInfo_t *);␊
␊
␊
#endif␉/* __LIBSAIO_MEM_H */␊
-/*␊
- * Copyright 2010 AsereBLN. All rights reserved. <aserebln@googlemail.com>␊
- *␊
- * mem.h␊
- */␊
-␊
-#ifndef __LIBSAIO_MEM_H␊
-#define __LIBSAIO_MEM_H␊
-␊
-#include "platform.h"␊
-␊
-extern void scan_memory(PlatformInfo_t *);␊
-␊
-␊
-#endif␉/* __LIBSAIO_MEM_H */␊

-237
238 238
239 239
240 
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242 241
243 242
+␉}␊
␉␊
␉return strdup(asciiPartNo);␊
    return NULL;␊
}␊
␊
int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊␊
 ␉}␊
 ␉␊
 ␉return strdup(asciiPartNo);␊
-    return NULL;␊
 }␊
 ␊
 int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊␊

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