Chameleon

Chameleon Commit Details

Date:2011-05-20 17:14:17 (8 years 3 months ago)
Author:MacMan
Commit:849
Parents: 848
Message:Reverting to trunk r833
Changes:
D/branches/Chimera/i386/libsaio/mem.c
D/branches/Chimera/i386/libsaio/mem.h
D/branches/Chimera/i386/libsaio/smbios_patcher.c
D/branches/Chimera/i386/libsaio/smbios_patcher.h
M/branches/Chimera/i386/libsaio/bootstruct.c
M/branches/Chimera/TODO
M/branches/Chimera/i386/Makefile
M/branches/Chimera/i386/libsaio/nvidia.c
M/branches/Chimera/i386/boot2/boot.h
M/branches/Chimera/i386/libsaio/pci.c
M/branches/Chimera/i386/libsaio/bootstruct.h
M/branches/Chimera/i386/libsaio/load.c
M/branches/Chimera/i386/libsaio/pci.h
M/branches/Chimera/i386/libsaio/acpi_patcher.c
M/branches/Chimera/i386/libsaio/platform.c
M/branches/Chimera/i386/libsaio/table.c
M/branches/Chimera/i386/util/Makefile
M/branches/Chimera/i386/libsaio/platform.h
M/branches/Chimera/i386/libsaio/Makefile
M/branches/Chimera/i386/boot1/Makefile
M/branches/Chimera/i386/doc/README
M/branches/Chimera/i386/libsaio/xml.c
M/branches/Chimera/i386/libsaio/SMBIOS.h
M/branches/Chimera/CREDITS
M/branches/Chimera/doc/BootHelp.txt
M/branches/Chimera/i386/libsa/Makefile
M/branches/Chimera/i386/libsaio/fdisk.h
M/branches/Chimera/i386/libsaio/xml.h
M/branches/Chimera/CHANGES
M/branches/Chimera/i386/libsaio/ati.c
M/branches/Chimera/i386/boot2/drivers.c
M/branches/Chimera/Makefile
M/branches/Chimera/i386/MakeInc.dir
M/branches/Chimera/i386/boot2/mboot.c
M/branches/Chimera/i386/cdboot/Makefile
M/branches/Chimera/i386/boot2/prompt.c
M/branches/Chimera/i386/libsaio/memvendors.h
M/branches/Chimera/i386/libsaio/saio_types.h
M/branches/Chimera/i386/libsa/memory.h
M/branches/Chimera/i386/libsaio/spd.c
M/branches/Chimera/i386/libsaio/cpu.c
M/branches/Chimera/i386/libsaio/md5c.c
M/branches/Chimera/i386/libsaio/fake_efi.c
M/branches/Chimera/version
M/branches/Chimera/i386/libsaio/pci_setup.c
M/branches/Chimera/i386/libsaio/cpu.h
M/branches/Chimera/i386/boot0/Makefile
M/branches/Chimera/i386/boot2/Makefile
M/branches/Chimera/revision
M/branches/Chimera/i386/boot2/boot.c

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branches/Chimera/version
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branches/Chimera/i386/libsaio/smbios_patcher.c
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/*
* Copyright 2008 mackerintel
*/
#include "libsaio.h"
#include "boot.h"
#include "bootstruct.h"
#include "acpi.h"
#include "efi_tables.h"
#include "fake_efi.h"
#include "platform.h"
#include "smbios_patcher.h"
#include "pci.h"
#ifndef DEBUG_SMBIOS
#define DEBUG_SMBIOS 0
#endif
#if DEBUG_SMBIOS
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
typedef struct {
const char* key;
const char* value;
} SMStrEntryPair;
// defaults for a MacBook
static const SMStrEntryPair const sm_macbook_defaults[]={
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","MB41.88Z.00C1.B00.0802091535"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","MacBook4,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","MacBook"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F22788A9"},
{ "",""}
};
// defaults for a MacBook Pro
static const SMStrEntryPair const sm_macbookpro_defaults[]={
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","MBP41.88Z.00C1.B03.0802271651"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","MacBookPro4,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","MacBookPro"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F42C89C8"},
{ "",""}
};
// defaults for a Mac mini
static const SMStrEntryPair const sm_macmini_defaults[]={
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","MM21.88Z.009A.B00.0706281359"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","Macmini2,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","Napa Mac"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F4208EAA"},
{ "",""}
};
// defaults for an iMac
static const SMStrEntryPair const sm_imac_defaults[]={
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","IM81.88Z.00C1.B00.0802091538"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","iMac8,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","Mac"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F227BEC8"},
{ "",""}
};
// defaults for an iMac11,1 core i3/i5/i7
static const SMStrEntryPair const sm_imac_core_defaults[]={
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","IM111.88Z.0034.B00.0802091538"},
{"SMbiosdate","06/01/2009"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","iMac11,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","iMac"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F2268DAE"},
{ "",""}
};
// defaults for a Mac Pro 3,1 Xenon
static const SMStrEntryPair const sm_macpro_defaults[]={
{"SMbiosvendor","Apple Computer, Inc."},
{"SMbiosversion","MP31.88Z.006C.B05.0802291410"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","MacPro3,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","MacPro"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F42C88C8"},
{ "",""}
};
// defaults for a Mac Pro 4,1 Core i7/Xeon
static const SMStrEntryPair const sm_macpro_core_defaults[]={
{"SMbiosvendor","Apple Computer, Inc."},
{"SMbiosversion","MP41.88Z.0081.B07.0903051113"},
{"SMbiosdate","11/06/2009"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","MacPro4,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","MacPro"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F221BEC8"},
{ "",""}
};
static const char* sm_get_defstr(const char * key, int table_num)
{
inti;
const SMStrEntryPair*sm_defaults;
if (platformCPUFeature(CPU_FEATURE_MOBILE)) {
if (Platform.CPU.NoCores > 1) {
sm_defaults=sm_macbookpro_defaults;
} else {
sm_defaults=sm_macbook_defaults;
}
} else {
switch (Platform.CPU.NoCores)
{
case 1:
sm_defaults=sm_macmini_defaults;
break;
case 2:
sm_defaults=sm_imac_defaults;
break;
default:
{
switch (Platform.CPU.Family)
{
case 0x06:
{
switch (Platform.CPU.Model)
{
case CPU_MODEL_FIELDS:// Intel Core i5, i7 LGA1156 (45nm)
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)
case CPU_MODEL_SANDY_BRIDGE:// Intel Core i3, i5, i7 LGA1155 (32nm)
sm_defaults=sm_imac_core_defaults;
break;
case CPU_MODEL_NEHALEM:// Intel Core i7 LGA1366 (45nm)
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X7500
case CPU_MODEL_WESTMERE:// Intel Core i7 LGA13766 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
sm_defaults=sm_macpro_core_defaults;
break;
default:
sm_defaults=sm_macpro_defaults;
break;
}
break;
}
default:
sm_defaults=sm_macpro_defaults;
break;
}
break;
}
}
}
for (i=0; sm_defaults[i].key[0]; i++) {
if (!strcmp (sm_defaults[i].key, key)) {
return sm_defaults[i].value;
}
}
// Shouldn't happen
printf ("Error: no default for '%s' known\n", key);
sleep (2);
return "";
}
static int sm_get_fsb(const char *name, int table_num)
{
return Platform.CPU.FSBFrequency/1000000;
}
static int sm_get_cpu (const char *name, int table_num)
{
return Platform.CPU.CPUFrequency/1000000;
}
static int sm_get_bus_speed (const char *name, int table_num)
{
if (Platform.CPU.Vendor == 0x756E6547) // Intel
{
switch (Platform.CPU.Family)
{
case 0x06:
{
switch (Platform.CPU.Model)
{
case CPU_MODEL_YONAH:// Intel Mobile Core Solo, Duo
case CPU_MODEL_MEROM:// Intel Mobile Core 2 Solo, Duo
case CPU_MODEL_PENRYN:// Intel Core 2 Solo, Duo, Quad, Extreme
case CPU_MODEL_ATOM:// Intel Atom (45nm)
return 0;// TODO: populate bus speed for these processors
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
return 0;// Unknown
case CPU_MODEL_SANDY_BRIDGE:// Intel Core i3, i5, i7 LGA1155 (32nm)
return 4800;
case CPU_MODEL_NEHALEM:// Intel Core i7 LGA1366 (45nm)
case CPU_MODEL_FIELDS:// Intel Core i5, i7 LGA1156 (45nm)
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
case CPU_MODEL_WESTMERE:// Intel Core i7 LGA1366 (32nm) 6 Core
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X7500
{ // thanks to dgobe for i3/i5/i7 bus speed detection
int nhm_bus = 0x3F;
static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};
unsigned long did, vid;
int i;
// Nehalem supports Scrubbing
// First, locate the PCI bus where the MCH is located
for(i = 0; i < sizeof(possible_nhm_bus); i++)
{
vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);
did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);
vid &= 0xFFFF;
did &= 0xFF00;
if(vid == 0x8086 && did >= 0x2C00)
nhm_bus = possible_nhm_bus[i];
}
unsigned long qpimult, qpibusspeed;
qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);
DBG("FSBFrequency %d\n", Platform.CPU.FSBFrequency);
qpimult &= 0x7F;
DBG("qpimult %x\n", qpimult);
qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));
// Rek: rounding decimals to match original mac profile info
if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;
DBG("qpibusspeed %d\n", qpibusspeed);
return qpibusspeed;
}
}
}
}
}
return 0;
}
static int sm_get_simplecputype()
{
if (Platform.CPU.NoCores >= 4)
{
return 0x0501;// Quad-Core Intel Xeon
}
else if (Platform.CPU.NoCores == 1)
{
return 0x0201;// Core Solo
};
return 0x0301;// Core 2 Duo
}
static int sm_get_cputype (const char *name, int table_num)
{
static bool done = false;
if (Platform.CPU.Vendor == 0x756E6547) // Intel
{
if (!done) {
verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);
done = true;
}
switch (Platform.CPU.Family)
{
case 0x06:
{
switch (Platform.CPU.Model)
{
case CPU_MODEL_YONAH:// Intel Mobile Core Solo, Duo
case CPU_MODEL_MEROM:// Intel Mobile Core 2 Solo, Duo
case CPU_MODEL_PENRYN:// Intel Core 2 Solo, Duo, Quad, Extreme
case CPU_MODEL_ATOM:// Intel Atom (45nm)
return sm_get_simplecputype();
case CPU_MODEL_NEHALEM:// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
if (strstr(Platform.CPU.BrandString, "Xeon"))
return 0x501;// Quad-Core Intel Xeon
return 0x0701;// Core i7
case CPU_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
if (strstr(Platform.CPU.BrandString, "Xeon"))
return 0x501;// Quad-Core Intel Xeon
if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))
return 0x601;// Core i5
return 0x701;// Core i7
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))
return 0x901;// Core i3
if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))
return 0x601;// Core i5
return 0x0701;// Core i7
case CPU_MODEL_SANDY_BRIDGE: // Intel Core i3, i5, i7 LGA1155 (32nm)
if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))
return 0x901;// Core i3
if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))
return 0x601;// Core i5
return 0x0701;// Core i7
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx
case CPU_MODEL_WESTMERE:// Intel Core i7 LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7
if (strstr(Platform.CPU.BrandString, "Xeon"))
return 0x501;// Quad-Core Intel Xeon
return 0x0701;// Core i7
}
}
}
}
return sm_get_simplecputype();
}
static int sm_get_memtype (const char *name, int table_num)
{
intmap;
if (table_num < MAX_RAM_SLOTS) {
map = Platform.DMI.DIMM[table_num];
if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0) {
DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);
return Platform.RAM.DIMM[map].Type;
}
}
return SMB_MEM_TYPE_DDR2;
}
static int sm_get_memspeed (const char *name, int table_num)
{
intmap;
if (table_num < MAX_RAM_SLOTS) {
map = Platform.DMI.DIMM[table_num];
if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0) {
DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);
return Platform.RAM.DIMM[map].Frequency;
}
}
return 800;
}
static const char *sm_get_memvendor (const char *name, int table_num)
{
intmap;
if (table_num < MAX_RAM_SLOTS) {
map = Platform.DMI.DIMM[table_num];
if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0) {
DBG("RAM Detected Vendor[%d]='%s'\n", table_num, Platform.RAM.DIMM[map].Vendor);
return Platform.RAM.DIMM[map].Vendor;
}
}
return "N/A";
}
static const char *sm_get_memserial (const char *name, int table_num)
{
intmap;
if (table_num < MAX_RAM_SLOTS) {
map = Platform.DMI.DIMM[table_num];
if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0) {
DBG("name = %s, map=%d, RAM Detected SerialNo[%d]='%s'\n", name ? name : "",
map, table_num, Platform.RAM.DIMM[map].SerialNo);
return Platform.RAM.DIMM[map].SerialNo;
}
}
return "N/A";
}
static const char *sm_get_mempartno (const char *name, int table_num)
{
intmap;
if (table_num < MAX_RAM_SLOTS) {
map = Platform.DMI.DIMM[table_num];
if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0) {
DBG("Ram Detected PartNo[%d]='%s'\n", table_num, Platform.RAM.DIMM[map].PartNo);
return Platform.RAM.DIMM[map].PartNo;
}
}
return "N/A";
}
static int sm_one (int tablen)
{
return 1;
}
struct smbios_property smbios_properties[]=
{
{.name="SMbiosvendor",.table_type= 0,.value_type=SMSTRING,.offset=0x04,.auto_str=sm_get_defstr},
{.name="SMbiosversion",.table_type= 0,.value_type=SMSTRING,.offset=0x05,.auto_str=sm_get_defstr},
{.name="SMbiosdate",.table_type= 0,.value_type=SMSTRING,.offset=0x08,.auto_str=sm_get_defstr},
{.name="SMmanufacter",.table_type= 1,.value_type=SMSTRING,.offset=0x04,.auto_str=sm_get_defstr},
{.name="SMproductname",.table_type= 1,.value_type=SMSTRING,.offset=0x05,.auto_str=sm_get_defstr},
{.name="SMsystemversion",.table_type= 1,.value_type=SMSTRING,.offset=0x06,.auto_str=sm_get_defstr},
{.name="SMserial",.table_type= 1,.value_type=SMSTRING,.offset=0x07,.auto_str=sm_get_defstr},
{.name="SMUUID",.table_type= 1, .value_type=SMOWORD,.offset=0x08,.auto_oword=0},
{.name="SMfamily",.table_type= 1,.value_type=SMSTRING,.offset=0x1a,.auto_str=sm_get_defstr},
{.name="SMboardmanufacter",.table_type= 2, .value_type=SMSTRING,.offset=0x04,.auto_str=sm_get_defstr},
{.name="SMboardproduct",.table_type= 2, .value_type=SMSTRING,.offset=0x05,.auto_str=sm_get_defstr},
{.name="SMexternalclock",.table_type= 4,.value_type=SMWORD,.offset=0x12,.auto_int=sm_get_fsb},
{.name="SMmaximalclock",.table_type= 4,.value_type=SMWORD,.offset=0x14,.auto_int=sm_get_cpu},
{.name="SMmemdevloc",.table_type=17,.value_type=SMSTRING,.offset=0x10,.auto_str=0},
{.name="SMmembankloc",.table_type=17,.value_type=SMSTRING,.offset=0x11,.auto_str=0},
{.name="SMmemtype",.table_type=17,.value_type=SMBYTE,.offset=0x12,.auto_int=sm_get_memtype},
{.name="SMmemspeed",.table_type=17,.value_type=SMWORD,.offset=0x15,.auto_int=sm_get_memspeed},
{.name="SMmemmanufacter",.table_type=17,.value_type=SMSTRING,.offset=0x17,.auto_str=sm_get_memvendor},
{.name="SMmemserial",.table_type=17,.value_type=SMSTRING,.offset=0x18,.auto_str=sm_get_memserial},
{.name="SMmempart",.table_type=17,.value_type=SMSTRING,.offset=0x1A,.auto_str=sm_get_mempartno},
{.name="SMcputype",.table_type=131,.value_type=SMWORD,.offset=0x04,.auto_int=sm_get_cputype},
{.name="SMbusspeed",.table_type=132,.value_type=SMWORD,.offset=0x04,.auto_int=sm_get_bus_speed}
};
struct smbios_table_description smbios_table_descriptions[]=
{
{.type=0,.len=0x18,.numfunc=sm_one},
{.type=1,.len=0x1b,.numfunc=sm_one},
{.type=2,.len=0x0f,.numfunc=sm_one},
{.type=4,.len=0x2a,.numfunc=sm_one},
{.type=17,.len=0x1c,.numfunc=0},
{.type=131,.len=0x06,.numfunc=sm_one},
{.type=132,.len=0x06,.numfunc=sm_one}
};
// getting smbios addr with fast compare ops, late checksum testing ...
#define COMPARE_DWORD(a,b) ( *((u_int32_t *) a) == *((u_int32_t *) b) )
static const char * const SMTAG = "_SM_";
static const char* const DMITAG= "_DMI_";
static struct SMBEntryPoint *getAddressOfSmbiosTable(void)
{
struct SMBEntryPoint*smbios;
/*
* The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking
* for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").
*/
smbios = (struct SMBEntryPoint*) SMBIOS_RANGE_START;
while (smbios <= (struct SMBEntryPoint *)SMBIOS_RANGE_END) {
if (COMPARE_DWORD(smbios->anchor, SMTAG) &&
COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&
smbios->dmi.anchor[4]==DMITAG[4] &&
checksum8(smbios, sizeof(struct SMBEntryPoint)) == 0)
{
return smbios;
}
smbios = (struct SMBEntryPoint*) ( ((char*) smbios) + 16 );
}
printf("ERROR: Unable to find SMBIOS!\n");
pause();
return NULL;
}
/** Compute necessary space requirements for new smbios */
static struct SMBEntryPoint *smbios_dry_run(struct SMBEntryPoint *origsmbios)
{
struct SMBEntryPoint*ret;
char *smbiostables;
char *tablesptr;
int origsmbiosnum;
int i, j;
int tablespresent[256];
bool do_auto=true;
bzero(tablespresent, sizeof(tablespresent));
getBoolForKey(kSMBIOSdefaults, &do_auto, &bootInfo->bootConfig);
ret = (struct SMBEntryPoint *)AllocateKernelMemory(sizeof(struct SMBEntryPoint));
if (origsmbios) {
smbiostables = (char *)origsmbios->dmi.tableAddress;
origsmbiosnum = origsmbios->dmi.structureCount;
} else {
smbiostables = NULL;
origsmbiosnum = 0;
}
// _SM_
ret->anchor[0] = 0x5f;
ret->anchor[1] = 0x53;
ret->anchor[2] = 0x4d;
ret->anchor[3] = 0x5f;
ret->entryPointLength = sizeof(*ret);
ret->majorVersion = 2;
ret->minorVersion = 1;
ret->maxStructureSize = 0; // will be calculated later in this function
ret->entryPointRevision = 0;
for (i=0;i<5;i++) {
ret->formattedArea[i] = 0;
}
//_DMI_
ret->dmi.anchor[0] = 0x5f;
ret->dmi.anchor[1] = 0x44;
ret->dmi.anchor[2] = 0x4d;
ret->dmi.anchor[3] = 0x49;
ret->dmi.anchor[4] = 0x5f;
ret->dmi.tableLength = 0; // will be calculated later in this function
ret->dmi.tableAddress = 0; // will be initialized in smbios_real_run()
ret->dmi.structureCount = 0; // will be calculated later in this function
ret->dmi.bcdRevision = 0x21;
tablesptr = smbiostables;
// add stringlen of overrides to original stringlen, update maxStructure size adequately,
// update structure count and tablepresent[type] with count of type.
if (smbiostables) {
for (i=0; i<origsmbiosnum; i++) {
struct smbios_table_header*cur = (struct smbios_table_header *)tablesptr;
char*stringsptr;
intstringlen;
tablesptr += cur->length;
stringsptr = tablesptr;
for (; tablesptr[0]!=0 || tablesptr[1]!=0; tablesptr++);
tablesptr += 2;
stringlen = tablesptr - stringsptr - 1;
if (stringlen == 1) {
stringlen = 0;
}
for (j=0; j<sizeof(smbios_properties)/sizeof(smbios_properties[0]); j++) {
const char*str;
intsize;
charaltname[40];
sprintf(altname, "%s_%d",smbios_properties[j].name, tablespresent[cur->type] + 1);
if (smbios_properties[j].table_type == cur->type &&
smbios_properties[j].value_type == SMSTRING &&
(getValueForKey(smbios_properties[j].name, &str, &size, &bootInfo->smbiosConfig) ||
getValueForKey(altname,&str, &size, &bootInfo->smbiosConfig)))
{
stringlen += size + 1;
} else if (smbios_properties[j].table_type == cur->type &&
smbios_properties[j].value_type == SMSTRING &&
do_auto && smbios_properties[j].auto_str)
{
stringlen += strlen(smbios_properties[j].auto_str(smbios_properties[j].name, tablespresent[cur->type])) + 1;
}
}
if (stringlen == 0) {
stringlen = 1;
}
stringlen++;
if (ret->maxStructureSize < cur->length+stringlen) {
ret->maxStructureSize=cur->length+stringlen;
}
ret->dmi.tableLength += cur->length+stringlen;
ret->dmi.structureCount++;
tablespresent[cur->type]++;
}
}
// Add eventually table types whose detected count would be < required count, and update ret header with:
// new stringlen addons, structure count, and tablepresent[type] count adequately
for (i=0; i<sizeof(smbios_table_descriptions)/sizeof(smbios_table_descriptions[0]); i++) {
intnumnec=-1;
charbuffer[40];
sprintf(buffer, "SMtable%d", i);
if (!getIntForKey(buffer, &numnec, &bootInfo->smbiosConfig)) {
numnec = -1;
}
if (numnec==-1 && do_auto && smbios_table_descriptions[i].numfunc) {
numnec = smbios_table_descriptions[i].numfunc(smbios_table_descriptions[i].type);
}
while (tablespresent[smbios_table_descriptions[i].type] < numnec) {
intstringlen = 0;
for (j=0; j<sizeof(smbios_properties)/sizeof(smbios_properties[0]); j++) {
const char*str;
intsize;
charaltname[40];
sprintf(altname, "%s_%d",smbios_properties[j].name, tablespresent[smbios_table_descriptions[i].type] + 1);
if (smbios_properties[j].table_type == smbios_table_descriptions[i].type &&
smbios_properties[j].value_type == SMSTRING &&
(getValueForKey(altname, &str, &size, &bootInfo->smbiosConfig) ||
getValueForKey(smbios_properties[j].name, &str, &size, &bootInfo->smbiosConfig)))
{
stringlen += size + 1;
} else if (smbios_properties[j].table_type == smbios_table_descriptions[i].type &&
smbios_properties[j].value_type==SMSTRING &&
do_auto && smbios_properties[j].auto_str)
{
stringlen += strlen(smbios_properties[j].auto_str(smbios_properties[j].name, tablespresent[smbios_table_descriptions[i].type])) + 1;
}
}
if (stringlen == 0) {
stringlen = 1;
}
stringlen++;
if (ret->maxStructureSize < smbios_table_descriptions[i].len+stringlen) {
ret->maxStructureSize = smbios_table_descriptions[i].len + stringlen;
}
ret->dmi.tableLength += smbios_table_descriptions[i].len + stringlen;
ret->dmi.structureCount++;
tablespresent[smbios_table_descriptions[i].type]++;
}
}
return ret;
}
/** From the origsmbios detected by getAddressOfSmbiosTable() to newsmbios whose entrypoint
* struct has been created by smbios_dry_run, update each table struct content of new smbios
* int the new allocated table address of size newsmbios->tablelength.
*/
static void smbios_real_run(struct SMBEntryPoint * origsmbios, struct SMBEntryPoint * newsmbios)
{
char *smbiostables;
char *tablesptr, *newtablesptr;
int origsmbiosnum;
// bitmask of used handles
uint8_t handles[8192];
uint16_t nexthandle=0;
int i, j;
int tablespresent[256];
bool do_auto=true;
static bool done = false; // IMPROVEME: called twice via getSmbios(), but only the second call can get all necessary info !
extern void dumpPhysAddr(const char * title, void * a, int len);
bzero(tablespresent, sizeof(tablespresent));
bzero(handles, sizeof(handles));
getBoolForKey(kSMBIOSdefaults, &do_auto, &bootInfo->bootConfig);
newsmbios->dmi.tableAddress = (uint32_t)AllocateKernelMemory(newsmbios->dmi.tableLength);
if (origsmbios) {
smbiostables = (char *)origsmbios->dmi.tableAddress;
origsmbiosnum = origsmbios->dmi.structureCount;
} else {
smbiostables = NULL;
origsmbiosnum = 0;
}
tablesptr = smbiostables;
newtablesptr = (char *)newsmbios->dmi.tableAddress;
// if old smbios exists then update new smbios with old smbios original content first
if (smbiostables) {
for (i=0; i<origsmbiosnum; i++) {
struct smbios_table_header*oldcur = (struct smbios_table_header *) tablesptr;
struct smbios_table_header*newcur = (struct smbios_table_header *) newtablesptr;
char*stringsptr;
intnstrings = 0;
handles[(oldcur->handle) / 8] |= 1 << ((oldcur->handle) % 8);
// copy table length from old table to new table but not the old strings
memcpy(newcur,oldcur, oldcur->length);
tablesptr += oldcur->length;
stringsptr = tablesptr;
newtablesptr += oldcur->length;
// calculate the number of strings in the old content
for (;tablesptr[0]!=0 || tablesptr[1]!=0; tablesptr++) {
if (tablesptr[0] == 0) {
nstrings++;
}
}
if (tablesptr != stringsptr) {
nstrings++;
}
tablesptr += 2;
// copy the old strings to new table
memcpy(newtablesptr, stringsptr, tablesptr-stringsptr);
// point to next possible space for a string (deducting the second 0 char at the end)
newtablesptr += tablesptr - stringsptr - 1;
if (nstrings == 0) { // if no string was found rewind to the first 0 char of the 0,0 terminator
newtablesptr--;
}
// now for each property in the table update the overrides if any (auto or user)
for (j=0; j<sizeof(smbios_properties)/sizeof(smbios_properties[0]); j++) {
const char*str;
intsize;
intnum;
charaltname[40];
sprintf(altname, "%s_%d", smbios_properties[j].name, tablespresent[newcur->type] + 1);
if (smbios_properties[j].table_type == newcur->type) {
switch (smbios_properties[j].value_type) {
case SMSTRING:
if (getValueForKey(altname, &str, &size, &bootInfo->smbiosConfig) ||
getValueForKey(smbios_properties[j].name, &str, &size, &bootInfo->smbiosConfig))
{
memcpy(newtablesptr, str, size);
newtablesptr[size] = 0;
newtablesptr += size + 1;
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset)) = ++nstrings;
} else if (do_auto && smbios_properties[j].auto_str) {
str = smbios_properties[j].auto_str(smbios_properties[j].name, tablespresent[newcur->type]);
size = strlen(str);
memcpy(newtablesptr, str, size);
newtablesptr[size] = 0;
newtablesptr += size + 1;
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset)) = ++nstrings;
}
break;
case SMOWORD:
if (getValueForKey(altname, &str, &size, &bootInfo->smbiosConfig) ||
getValueForKey(smbios_properties[j].name, &str, &size, &bootInfo->smbiosConfig))
{
intk=0, t=0, kk=0;
const char*ptr = str;
memset(((char*)newcur) + smbios_properties[j].offset, 0, 16);
while (ptr-str<size && *ptr && (*ptr==' ' || *ptr=='\t' || *ptr=='\n')) {
ptr++;
}
if (size-(ptr-str)>=2 && ptr[0]=='0' && (ptr[1]=='x' || ptr[1]=='X')) {
ptr += 2;
}
for (;ptr-str<size && *ptr && k<16;ptr++) {
if (*ptr>='0' && *ptr<='9') {
(t=(t<<4)|(*ptr-'0')),kk++;
}
if (*ptr>='a' && *ptr<='f') {
(t=(t<<4)|(*ptr-'a'+10)),kk++;
}
if (*ptr>='A' && *ptr<='F') {
(t=(t<<4)|(*ptr-'A'+10)),kk++;
}
if (kk == 2) {
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset + k)) = t;
k++;
kk = 0;
t = 0;
}
}
}
break;
case SMBYTE:
if (getIntForKey(altname, &num, &bootInfo->smbiosConfig) ||
getIntForKey(smbios_properties[j].name, &num, &bootInfo->smbiosConfig))
{
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset)) = num;
} else if (do_auto && smbios_properties[j].auto_int) {
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset)) = smbios_properties[j].auto_int(smbios_properties[j].name, tablespresent[newcur->type]);
}
break;
case SMWORD:
if (getIntForKey(altname, &num, &bootInfo->smbiosConfig) ||
getIntForKey(smbios_properties[j].name, &num, &bootInfo->smbiosConfig))
{
*((uint16_t*)(((char*)newcur) + smbios_properties[j].offset)) = num;
} else if (do_auto && smbios_properties[j].auto_int) {
*((uint16_t*)(((char*)newcur) + smbios_properties[j].offset)) = smbios_properties[j].auto_int(smbios_properties[j].name, tablespresent[newcur->type]);
}
break;
}
}
}
if (nstrings == 0) {
newtablesptr[0] = 0;
newtablesptr++;
}
newtablesptr[0] = 0;
newtablesptr++;
tablespresent[newcur->type]++;
}
}
// for each eventual complementary table not present in the original smbios, do the overrides
for (i=0; i<sizeof(smbios_table_descriptions)/sizeof(smbios_table_descriptions[0]); i++) {
intnumnec = -1;
charbuffer[40];
sprintf(buffer, "SMtable%d", i);
if (!getIntForKey(buffer, &numnec, &bootInfo->smbiosConfig)) {
numnec = -1;
}
if (numnec == -1 && do_auto && smbios_table_descriptions[i].numfunc) {
numnec = smbios_table_descriptions[i].numfunc(smbios_table_descriptions[i].type);
}
while (tablespresent[smbios_table_descriptions[i].type] < numnec) {
struct smbios_table_header*newcur = (struct smbios_table_header *) newtablesptr;
intnstrings = 0;
memset(newcur,0, smbios_table_descriptions[i].len);
while (handles[(nexthandle)/8] & (1 << ((nexthandle) % 8))) {
nexthandle++;
}
newcur->handle = nexthandle;
handles[nexthandle / 8] |= 1 << (nexthandle % 8);
newcur->type = smbios_table_descriptions[i].type;
newcur->length = smbios_table_descriptions[i].len;
newtablesptr += smbios_table_descriptions[i].len;
for (j=0; j<sizeof(smbios_properties)/sizeof(smbios_properties[0]); j++) {
const char*str;
intsize;
intnum;
charaltname[40];
sprintf(altname, "%s_%d", smbios_properties[j].name, tablespresent[newcur->type] + 1);
if (smbios_properties[j].table_type == newcur->type) {
switch (smbios_properties[j].value_type) {
case SMSTRING:
if (getValueForKey(altname, &str, &size, &bootInfo->smbiosConfig) ||
getValueForKey(smbios_properties[j].name, &str, &size, &bootInfo->smbiosConfig))
{
memcpy(newtablesptr, str, size);
newtablesptr[size] = 0;
newtablesptr += size + 1;
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset)) = ++nstrings;
} else if (do_auto && smbios_properties[j].auto_str) {
str = smbios_properties[j].auto_str(smbios_properties[j].name, tablespresent[newcur->type]);
size = strlen(str);
memcpy(newtablesptr, str, size);
newtablesptr[size] = 0;
newtablesptr += size + 1;
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset)) = ++nstrings;
}
break;
case SMOWORD:
if (getValueForKey(altname, &str, &size, &bootInfo->smbiosConfig) ||
getValueForKey(smbios_properties[j].name, &str, &size, &bootInfo->smbiosConfig))
{
intk=0, t=0, kk=0;
const char*ptr = str;
memset(((char*)newcur) + smbios_properties[j].offset, 0, 16);
while (ptr-str<size && *ptr && (*ptr==' ' || *ptr=='\t' || *ptr=='\n')) {
ptr++;
}
if (size-(ptr-str)>=2 && ptr[0]=='0' && (ptr[1]=='x' || ptr[1]=='X')) {
ptr += 2;
}
for (;ptr-str<size && *ptr && k<16;ptr++) {
if (*ptr>='0' && *ptr<='9') {
(t=(t<<4)|(*ptr-'0')),kk++;
}
if (*ptr>='a' && *ptr<='f') {
(t=(t<<4)|(*ptr-'a'+10)),kk++;
}
if (*ptr>='A' && *ptr<='F') {
(t=(t<<4)|(*ptr-'A'+10)),kk++;
}
if (kk == 2) {
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset + k)) = t;
k++;
kk = 0;
t = 0;
}
}
}
break;
case SMBYTE:
if (getIntForKey(altname, &num, &bootInfo->smbiosConfig) ||
getIntForKey(smbios_properties[j].name, &num, &bootInfo->smbiosConfig))
{
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset)) = num;
} else if (do_auto && smbios_properties[j].auto_int) {
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset)) = smbios_properties[j].auto_int(smbios_properties[j].name, tablespresent[newcur->type]);
}
break;
case SMWORD:
if (getIntForKey(altname, &num, &bootInfo->smbiosConfig) ||
getIntForKey(smbios_properties[j].name, &num, &bootInfo->smbiosConfig))
{
*((uint16_t*)(((char*)newcur) + smbios_properties[j].offset)) = num;
} else if (do_auto && smbios_properties[j].auto_int) {
*((uint16_t*)(((char*)newcur)+smbios_properties[j].offset)) = smbios_properties[j].auto_int(smbios_properties[j].name, tablespresent[newcur->type]);
}
break;
}
}
}
if (nstrings == 0) {
newtablesptr[0] = 0;
newtablesptr++;
}
newtablesptr[0] = 0;
newtablesptr++;
tablespresent[smbios_table_descriptions[i].type]++;
}
}
// calculate new checksums
newsmbios->dmi.checksum = 0;
newsmbios->dmi.checksum = 256 - checksum8(&newsmbios->dmi, sizeof(newsmbios->dmi));
newsmbios->checksum = 0;
newsmbios->checksum = 256 - checksum8(newsmbios, sizeof(*newsmbios));
if (!done) {
verbose("Patched DMI Table\n");
done=true;
}
}
#define MAX_DMI_TABLES 128 //Thanks Andy
typedef struct DmiNumAssocTag {
struct DMIHeader * dmi;
uint8_t type;
} DmiNumAssoc;
static DmiNumAssoc DmiTablePair[MAX_DMI_TABLES];
static int DmiTablePairCount = 0;
static int current_pos=0;
static bool ftTablePairInit = true;
/**
* Get a table structure entry from a type specification and a smbios address
* return NULL if table is not found
*/
static void getSmbiosTableStructure(struct SMBEntryPoint *smbios)
{
struct DMIHeader * dmihdr=NULL;
SMBByte* p;
int i;
if (ftTablePairInit && smbios!=NULL) {
ftTablePairInit = false;
#if DEBUG_SMBIOS
printf(">>> SMBIOSAddr=0x%08x\n", smbios);
printf(">>> DMI: addr=0x%08x, len=%d, count=%d\n", smbios->dmi.tableAddress,
smbios->dmi.tableLength, smbios->dmi.structureCount);
#endif
p = (SMBByte *) smbios->dmi.tableAddress;
for (i=0;
i < smbios->dmi.structureCount &&
p + 4 <= (SMBByte *)smbios->dmi.tableAddress + smbios->dmi.tableLength;
i++) {
dmihdr = (struct DMIHeader *) p;
#if DEBUG_SMBIOS
printf(">>>>>> DMI(%d): type=0x%02x, len=0x%d\n",i,dmihdr->type,dmihdr->length);
#endif
if (dmihdr->length < 4 || dmihdr->type == 127 /* EOT */) break;
if (DmiTablePairCount < MAX_DMI_TABLES) {
DmiTablePair[DmiTablePairCount].dmi = dmihdr;
DmiTablePair[DmiTablePairCount].type = dmihdr->type;
DmiTablePairCount++;
}
else {
printf("DMI table entries list is full! Next entries won't be stored.\n");
}
#if DEBUG_SMBIOS
printf("DMI header found for table type %d, length = %d\n", dmihdr->type, dmihdr->length);
#endif
p = p + dmihdr->length;
while ((p - (SMBByte *)smbios->dmi.tableAddress + 1 < smbios->dmi.tableLength) && (p[0] != 0x00 || p[1] != 0x00)) {
p++;
}
p += 2;
}
}
}
/** Get original or new smbios entry point, if sucessful, the adresses are cached for next time */
struct SMBEntryPoint *getSmbios(int which)
{
static struct SMBEntryPoint *orig = NULL; // cached
static struct SMBEntryPoint *patched = NULL; // cached
// whatever we are called with orig or new flag, initialize asap both structures
switch (which) {
case SMBIOS_ORIGINAL:
if (orig==NULL) {
orig = getAddressOfSmbiosTable();
getSmbiosTableStructure(orig); // generate tables entry list for fast table finding
}
return orig;
case SMBIOS_PATCHED:
if (orig==NULL && (orig = getAddressOfSmbiosTable())==NULL ) {
printf("Could not find original SMBIOS !!\n");
pause();
} else {
patched = smbios_dry_run(orig);
if(patched==NULL) {
printf("Could not create new SMBIOS !!\n");
pause();
}
else {
smbios_real_run(orig, patched);
}
}
return patched;
default:
printf("ERROR: invalid option for getSmbios() !!\n");
break;
}
return NULL;
}
/** Find first original dmi Table with a particular type */
struct DMIHeader* FindFirstDmiTableOfType(int type, int minlength)
{
current_pos = 0;
return FindNextDmiTableOfType(type, minlength);
};
/** Find next original dmi Table with a particular type */
struct DMIHeader* FindNextDmiTableOfType(int type, int minlength)
{
int i;
if (ftTablePairInit) getSmbios(SMBIOS_ORIGINAL);
for (i=current_pos; i < DmiTablePairCount; i++) {
if (type == DmiTablePair[i].type &&
DmiTablePair[i].dmi &&
DmiTablePair[i].dmi->length >= minlength ) {
current_pos = i+1;
return DmiTablePair[i].dmi;
}
}
return NULL; // not found
};
branches/Chimera/i386/libsaio/smbios_patcher.h
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/*
* Copyright 2008 mackerintel
*/
/*
* AsereBLN: cleanup
*/
#ifndef __LIBSAIO_SMBIOS_PATCHER_H
#define __LIBSAIO_SMBIOS_PATCHER_H
#include "libsaio.h"
#include "SMBIOS.h"
/* From Foundation/Efi/Guid/Smbios/SmBios.h */
/* Modified to wrap Data4 array init with {} */
#define EFI_SMBIOS_TABLE_GUID {0xeb9d2d31, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}}
#define SMBIOS_RANGE_START 0x000F0000
#define SMBIOS_RANGE_END 0x000FFFFF
#define SMBIOS_ORIGINAL0
#define SMBIOS_PATCHED1
struct smbios_table_header
{
uint8_ttype;
uint8_tlength;
uint16_thandle;
} __attribute__ ((packed));
struct smbios_property
{
const char*name;
uint8_ttable_type;
enum {SMSTRING, SMWORD, SMBYTE, SMOWORD} value_type;
intoffset;
int(*auto_int) (const char *name, int table_num);
const char*(*auto_str) (const char *name, int table_num);
const char*(*auto_oword) (const char *name, int table_num);
};
struct smbios_table_description
{
uint8_ttype;
intlen;
int(*numfunc)(int tablen);
};
/** call with flag SMBIOS_ORIGINAL to get orig. entrypoint
or call with flag SMBIOS_PATCHED to get patched smbios entrypoint
*/
extern struct SMBEntryPoint*getSmbios(int);
extern struct DMIHeader* FindNextDmiTableOfType(int type, int minlen);
extern struct DMIHeader* FindFirstDmiTableOfType(int type, int minlen);
#endif /* !__LIBSAIO_SMBIOS_PATCHER_H */
branches/Chimera/i386/libsaio/mem.c
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/*
* Copyright 2010 AsereBLN. All rights reserved. <aserebln@googlemail.com>
*
* mem.c - obtain system memory information
*/
#include "libsaio.h"
#include "pci.h"
#include "platform.h"
#include "cpu.h"
#include "mem.h"
#include "smbios_patcher.h"
#ifndef DEBUG_MEM
#define DEBUG_MEM 0
#endif
#if DEBUG_MEM
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
#define DC(c) (c >= 0x20 && c < 0x7f ? (char) c : '.')
#define STEP 16
void dumpPhysAddr(const char * title, void * a, int len)
{
int i,j;
u_int8_t* ad = (u_int8_t*) a;
char buffer[80];
char str[16];
if(ad==NULL) return;
printf("%s addr=0x%08x len=%04d\n",title ? title : "Dump of ", a, len);
printf("Ofs-00-01-02-03-04-05-06-07-08-09-0A-0B-0C-0D-0E-0F ASCII\n");
i = (len/STEP)*STEP;
for (j=0; j < i; j+=STEP)
{
printf("%02x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c\n",
j,
ad[j], ad[j+1], ad[j+2], ad[j+3] , ad[j+4], ad[j+5], ad[j+6], ad[j+7],
ad[j+8], ad[j+9], ad[j+10], ad[j+11] , ad[j+12], ad[j+13], ad[j+14], ad[j+15],
DC(ad[j]), DC(ad[j+1]), DC(ad[j+2]), DC(ad[j+3]) , DC(ad[j+4]), DC(ad[j+5]), DC(ad[j+6]), DC(ad[j+7]),
DC(ad[j+8]), DC(ad[j+9]), DC(ad[j+10]), DC(ad[j+11]) , DC(ad[j+12]), DC(ad[j+13]), DC(ad[j+14]), DC(ad[j+15])
);
}
if (len%STEP==0) return;
sprintf(buffer,"%02x:", i);
for (j=0; j < STEP; j++) {
if (j<(len%STEP))
sprintf(str, " %02x", ad[i+j]);
else
strcpy(str, " " );
strncat(buffer, str, sizeof(buffer));
}
strncat(buffer," ", sizeof(buffer));
for (j=0; j < (len%STEP); j++) {
sprintf(str, "%c", DC(ad[i+j]));
strncat(buffer, str, sizeof(buffer));
}
printf("%s\n",buffer);
}
void dumpAllTablesOfType(int i)
{
char title[32];
struct DMIHeader * dmihdr;
for(dmihdr = FindFirstDmiTableOfType(i, 4);
dmihdr;
dmihdr = FindNextDmiTableOfType(i, 4)) {
sprintf(title,"Table (type %d) :" , i);
dumpPhysAddr(title, dmihdr, dmihdr->length+32);
}
}
const char * getDMIString(struct DMIHeader * dmihdr, uint8_t strNum)
{
const char * ret =NULL;
const char * startAddr = (const char *) dmihdr;
const char * limit = NULL;
if (!dmihdr || dmihdr->length<4 || strNum==0) return NULL;
startAddr += dmihdr->length;
limit = startAddr + 256;
for(; strNum; strNum--) {
if ((*startAddr)==0 && *(startAddr+1)==0) break;
if (*startAddr && strNum<=1) {
ret = startAddr; // current str
break;
}
while(*startAddr && startAddr<limit) startAddr++;
if (startAddr==limit) break; // no terminator found
else if((*startAddr==0) && *(startAddr+1)==0) break;
else startAddr++;
}
return ret;
}
void scan_memory(PlatformInfo_t *p)
{
int i=0;
struct DMIHeader * dmihdr = NULL;
struct DMIMemoryModuleInfo* memInfo[MAX_RAM_SLOTS]; // 6
struct DMIPhysicalMemoryArray* physMemArray; // 16
struct DMIMemoryDevice* memDev[MAX_RAM_SLOTS]; //17
/* We mainly don't use obsolete tables 5,6 because most of computers don't handle it anymore */
Platform.DMI.MemoryModules = 0;
/* Now lets peek info rom table 16,17 as for some bios, table 5 & 6 are not used */
physMemArray = (struct DMIPhysicalMemoryArray*) FindFirstDmiTableOfType(16, 4);
Platform.DMI.MaxMemorySlots = physMemArray ? physMemArray->numberOfMemoryDevices : 0;
i = 0;
for(dmihdr = FindFirstDmiTableOfType(17, 4);
dmihdr;
dmihdr = FindNextDmiTableOfType(17, 4) ) {
memDev[i] = (struct DMIMemoryDevice*) dmihdr;
if (memDev[i]->size !=0 ) Platform.DMI.MemoryModules++;
if (memDev[i]->speed>0) Platform.RAM.DIMM[i].Frequency = memDev[i]->speed; // take it here for now but we'll check spd and dmi table 6 as well
i++;
}
// for table 6, we only have a look at the current speed
i = 0;
for(dmihdr = FindFirstDmiTableOfType(6, 4);
dmihdr;
dmihdr = FindNextDmiTableOfType(6, 4) ) {
memInfo[i] = (struct DMIMemoryModuleInfo*) dmihdr;
if (memInfo[i]->currentSpeed > Platform.RAM.DIMM[i].Frequency)
Platform.RAM.DIMM[i].Frequency = memInfo[i]->currentSpeed; // favor real overclocked speed if any
i++;
}
#if 0
dumpAllTablesOfType(17);
getc();
#endif
}
branches/Chimera/i386/libsaio/mem.h
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/*
* Copyright 2010 AsereBLN. All rights reserved. <aserebln@googlemail.com>
*
* mem.h
*/
#ifndef __LIBSAIO_MEM_H
#define __LIBSAIO_MEM_H
#include "platform.h"
extern void scan_memory(PlatformInfo_t *);
#endif/* __LIBSAIO_MEM_H */
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#include "sl.h"
#include "xml.h"
string_ref *ref_strings = NULL;
/// TODO: remove below
static char* buffer_start = NULL;
// TODO: redo the next two functions
void SaveRefString(char* string, int id)
{
//printf("Adding Ref String %d (%s)\n", id, string);
string_ref* tmp = ref_strings;
while(tmp)
{
if(tmp->id == id)
{
tmp->string = malloc(strlen(string)+1);
sprintf(tmp->string, "%s", string);
return;
}
tmp = tmp->next;
}
string_ref* new_ref = malloc(sizeof(string_ref));
new_ref->string = malloc(strlen(string)+1);
sprintf(new_ref->string, "%s", string);
new_ref->id = id;
new_ref->next = ref_strings;
ref_strings = new_ref;
}
char* GetRefString(int id)
{
string_ref* tmp = ref_strings;
while(tmp)
{
if(tmp->id == id) return tmp->string;
tmp = tmp->next;
}
//verbose("Unable to locate Ref String %d\n", id);
return "";
}
struct Module {
struct Module *nextModule;
long willLoad;
unsigned long signature1;
unsigned long signature2;
unsigned long length;
unsigned long alder32;
unsigned long adler32;
unsigned long version;
unsigned long numDrivers;
unsigned long reserved1;
return 0;
}
// XMLGetTag(int index)
// XMLTagCount( TagPtr dict )
int XMLTagCount( TagPtr dict )
{
int count = 0;
TagPtr tagList, tag;
if (dict->type != kTagTypeDict && dict->type != kTagTypeArray) return 0;
tag = 0;
tagList = dict->tag;
while (tagList)
{
tag = tagList;
tagList = tag->tagNext;
if (((tag->type != kTagTypeKey) && ((tag->string == 0) || (tag->string[0] == 0)))
&& (dict->type != kTagTypeArray)// If we are an array, any element is valid
) continue;
if(tag->type == kTagTypeKey) printf("Located key %s\n", tag->string);
count++;
}
return count;
}
TagPtr XMLGetElement( TagPtr dict, int id )
{
if(dict->type != kTagTypeArray) return 0;
int element = 0;
TagPtr tmp = dict->tag;
while(element < id)
{
element++;
tmp = tmp->tagNext;
}
return tmp;
}
/* Function for basic XML character entities parsing */
char*
return out;
}
#if UNUSED
//#if UNUSED
//==========================================================================
// XMLParseFile
// Expects to see one dictionary in the XML file.
// Expects to see one dictionary in the XML file, the final pos will be returned
// If the pos is not equal to the strlen, then there are multiple dicts
// Puts the first dictionary it finds in the
// tag pointer and returns 0, or returns -1 if not found.
// tag pointer and returns the end of the dic, or returns -1 if not found.
//
long
XMLParseFile( char * buffer, TagPtr * dict )
long length, pos;
TagPtr tag;
pos = 0;
char *configBuffer;
configBuffer = malloc(strlen(buffer)+1);
strcpy(configBuffer, buffer);
buffer_start = configBuffer;
while (1)
{
length = XMLParseNextTag(buffer + pos, &tag);
length = XMLParseNextTag(configBuffer + pos, &tag);
if (length == -1) break;
pos += length;
XMLFreeTag(tag);
}
if (length < 0) {
free(configBuffer);
if (length < 0) {
return -1;
}
*dict = tag;
return 0;
return pos;
}
#endif /* UNUSED */
//#endif /* UNUSED */
//==========================================================================
// ParseNextTag
// TODO: cleanup
long
XMLParseNextTag( char * buffer, TagPtr * tag )
{
length = GetNextTag(buffer, &tagName, 0);
if (length == -1) return -1;
pos = length;
if (!strncmp(tagName, kXMLTagPList, 6))
{
length = 0;
}
/***** dict ****/
else if (!strcmp(tagName, kXMLTagDict))
{
length = ParseTagList(buffer + pos, tag, kTagTypeDict, 0);
}
else if (!strcmp(tagName, kXMLTagDict "/"))
else if (!strncmp(tagName, kXMLTagDict, strlen(kXMLTagDict)) && tagName[strlen(tagName)-1] == '/')
{
length = ParseTagList(buffer + pos, tag, kTagTypeDict, 1);
}
else if (!strncmp(tagName, kXMLTagDict " ", strlen(kXMLTagDict " ")))
{
length = ParseTagList(buffer + pos, tag, kTagTypeDict, 0);
}
/***** key ****/
else if (!strcmp(tagName, kXMLTagKey))
{
length = ParseTagKey(buffer + pos, tag);
}
/***** string ****/
else if (!strcmp(tagName, kXMLTagString))
{
length = ParseTagString(buffer + pos, tag);
}
else if (!strncmp(tagName, kXMLTagString " ", strlen(kXMLTagString " ")))
{
// TODO: save tag if if found
if(!strncmp(tagName + strlen(kXMLTagString " "), kXMLStringID, strlen(kXMLStringID)))
{
// ID=
int id = 0;
int cnt = strlen(kXMLTagString " " kXMLStringID "\"") + 1;
while ((tagName[cnt] != '\0') && (tagName[cnt] != '"')) cnt++;
tagName[cnt] = 0;
char* val = tagName + strlen(kXMLTagString " " kXMLStringID "\"");
while(*val)
{
if ((*val >= '0' && *val <= '9'))// 0 - 9
{
id = (id * 10) + (*val++ - '0');
}
else
{
printf("ParseStringID error (0x%x)\n", *val);
getc();
return -1;
}
}
length = ParseTagString(buffer + pos, tag);
SaveRefString(buffer + pos, id);
}
else if(!strncmp(tagName + strlen(kXMLTagString " "), kXMLStringIDRef, strlen(kXMLStringIDRef)))
{
// IDREF=
int id = 0;
int cnt = strlen(kXMLTagString " " kXMLStringIDRef "\"") + 1;
while ((tagName[cnt] != '\0') && (tagName[cnt] != '"')) cnt++;
tagName[cnt] = 0;
char* val = tagName + strlen(kXMLTagString " " kXMLStringIDRef "\"");
while(*val)
{
if ((*val >= '0' && *val <= '9'))// 0 - 9
{
id = (id * 10) + (*val++ - '0');
}
else
{
printf("ParseStringIDREF error (0x%x)\n", *val);
getc();
return -1;
}
}
char* str = GetRefString(id);
TagPtr tmpTag = NewTag();
tmpTag->type = kTagTypeString;
tmpTag->string = str;
tmpTag->tag = 0;
tmpTag->tagNext = 0;
tmpTag->offset = buffer_start ? buffer - buffer_start + pos : 0;
*tag = tmpTag;
length = 0;
//printf("Located IDREF, id = %d, string = %s\n", id, str);
}
}
/***** integer ****/
else if (!strcmp(tagName, kXMLTagInteger))
{
length = ParseTagInteger(buffer + pos, tag);
}
else if (!strncmp(tagName, kXMLTagInteger " ", strlen(kXMLTagInteger " ")))
{
if(!strncmp(tagName + strlen(kXMLTagInteger " "), kXMLStringID, strlen(kXMLStringID)))
{
// ID=
int id = 0;
int cnt = strlen(kXMLTagInteger " " kXMLStringID "\"") + 1;
while ((tagName[cnt] != '\0') && (tagName[cnt] != '"')) cnt++;
tagName[cnt] = 0;
char* val = tagName + strlen(kXMLTagInteger " " kXMLStringID "\"");
while(*val)
{
if ((*val >= '0' && *val <= '9'))// 0 - 9
{
id = (id * 10) + (*val++ - '0');
}
else
{
printf("ParseIntegerID error (0x%x)\n", *val);
getc();
return -1;
}
}
length = ParseTagInteger(buffer + pos, tag);
SaveRefString((*tag)->string, id);
}
else if(!strncmp(tagName + strlen(kXMLTagInteger " "), kXMLStringIDRef, strlen(kXMLStringIDRef)))
{
// IDREF=
int id = 0;
int cnt = strlen(kXMLTagInteger " " kXMLStringIDRef "\"") + 1;
while ((tagName[cnt] != '\0') && (tagName[cnt] != '"')) cnt++;
tagName[cnt] = 0;
char* val = tagName + strlen(kXMLTagInteger " " kXMLStringIDRef "\"");
while(*val)
{
if ((*val >= '0' && *val <= '9'))// 0 - 9
{
id = (id * 10) + (*val++ - '0');
}
else
{
printf("ParseStringIDREF error (0x%x)\n", *val);
getc();
return -1;
}
}
int integer = (int)GetRefString(id);
TagPtr tmpTag = NewTag();
tmpTag->type = kTagTypeInteger;
tmpTag->string = (char*) integer;
tmpTag->tag = 0;
tmpTag->tagNext = 0;
tmpTag->offset = buffer_start ? buffer - buffer_start + pos : 0;
*tag = tmpTag;
length = 0;
//printf("Located IDREF, id = %d, string = %s\n", id, str);
}
else
{
length = ParseTagInteger(buffer + pos, tag);
}
}
/***** data ****/
else if (!strcmp(tagName, kXMLTagData))
{
length = ParseTagData(buffer + pos, tag);
}
else if (!strncmp(tagName, kXMLTagData " ", strlen(kXMLTagData " ")))
{
length = ParseTagData(buffer + pos, tag);
}
else if (!strcmp(tagName, kXMLTagDate))
{
length = ParseTagDate(buffer + pos, tag);
}
/***** date ****/
else if (!strncmp(tagName, kXMLTagDate " ", strlen(kXMLTagDate " ")))
{
length = ParseTagDate(buffer + pos, tag);
}
/***** false ****/
else if (!strcmp(tagName, kXMLTagFalse))
{
length = ParseTagBoolean(buffer + pos, tag, kTagTypeFalse);
}
/***** true ****/
else if (!strcmp(tagName, kXMLTagTrue))
{
length = ParseTagBoolean(buffer + pos, tag, kTagTypeTrue);
}
/***** array ****/
else if (!strcmp(tagName, kXMLTagArray))
{
length = ParseTagList(buffer + pos, tag, kTagTypeArray, 0);
}
else if (!strncmp(tagName, kXMLTagArray " ", strlen(kXMLTagArray " ")))
{
length = ParseTagList(buffer + pos, tag, kTagTypeArray, 0);
}
else if (!strcmp(tagName, kXMLTagArray "/"))
{
length = ParseTagList(buffer + pos, tag, kTagTypeArray, 1);
}
/***** unknown ****/
else
{
*tag = 0;
length = 0;
}
if (length == -1) return -1;
return pos + length;
tmpTag->type = type;
tmpTag->string = 0;
tmpTag->offset = buffer_start ? buffer - buffer_start : 0;
tmpTag->tag = tagList;
tmpTag->tagNext = 0;
tmpTag->type = kTagTypeKey;
tmpTag->string = string;
tmpTag->tag = subTag;
tmpTag->offset = buffer_start ? buffer - buffer_start: 0;
tmpTag->tagNext = 0;
*tag = tmpTag;
{
long length;
char * string;
TagPtr tmpTag;
length = FixDataMatchingTag(buffer, kXMLTagString);
if (length == -1) return -1;
tmpTag = NewTag();
TagPtr tmpTag = NewTag();
if (tmpTag == 0) return -1;
string = NewSymbol(buffer);
tmpTag->type = kTagTypeString;
tmpTag->string = string;
tmpTag->tag = 0;
tmpTag->offset = buffer_start ? buffer - buffer_start: 0;
tmpTag->tagNext = 0;
*tag = tmpTag;
ParseTagInteger( char * buffer, TagPtr * tag )
{
long length, integer;
bool negative = false;
TagPtr tmpTag;
length = FixDataMatchingTag(buffer, kXMLTagInteger);
char* val = buffer;
int size;
if(buffer[0] == '<')
{
printf("Warning integer is non existant\n");
getc();
tmpTag = NewTag();
tmpTag->type = kTagTypeInteger;
tmpTag->string = 0;
tmpTag->tag = 0;
tmpTag->offset = 0;
tmpTag->tagNext = 0;
*tag = tmpTag;
return 0;
}
size = length = FixDataMatchingTag(buffer, kXMLTagInteger);
if (length == -1) return -1;
tmpTag = NewTag();
if (tmpTag == 0) return -1;
integer = 0;
if(size > 1 && (val[1] == 'x' || val[1] == 'X'))// Hex value
{
val += 2;
while(*val)
{
if ((*val >= '0' && *val <= '9'))// 0 - 9
{
integer = (integer * 16) + (*val++ - '0');
}
else if ((*val >= 'a' && *val <= 'f'))// a - f
{
integer = (integer * 16) + (*val++ - 'a' + 10);
}
else if ((*val >= 'A' && *val <= 'F'))// A - F
{
integer = (integer * 16) + (*val++ - 'a' + 10);
}
else
{
printf("ParseTagInteger hex error (0x%x) in buffer %s\n", *val, buffer);
getc();
return -1;
}
}
}
else if ( size )// Decimal value
{
if (*val == '-')
{
negative = true;
val++;
size--;
}
for (integer = 0; size > 0; size--)
{
if(*val) // UGLY HACK, fix me.
{
if (*val < '0' || *val > '9')
{
printf("ParseTagInteger decimal error (0x%x) in buffer %s\n", *val, buffer);
getc();
return -1;
}
integer = (integer * 10) + (*val++ - '0');
}
}
if (negative)
integer = -integer;
}
tmpTag->type = kTagTypeInteger;
tmpTag->string = (char *)integer;
tmpTag->tag = 0;
tmpTag->string = (char *)integer;
tmpTag->tag = 0;
tmpTag->offset = buffer_start ? buffer - buffer_start: 0;
tmpTag->tagNext = 0;
*tag = tmpTag;
return length;
}
{
long length;
TagPtr tmpTag;
length = FixDataMatchingTag(buffer, kXMLTagData);
if (length == -1) return -1;
tmpTag = NewTag();
if (tmpTag == 0) return -1;
//printf("ParseTagData unimplimented\n");
//printf("Data: %s\n", buffer);
//getc();
// TODO: base64 decode
char* string = NewSymbol(buffer);
tmpTag->type = kTagTypeData;
tmpTag->string = 0;
tmpTag->string = string;
tmpTag->tag = 0;
tmpTag->offset = buffer_start ? buffer - buffer_start: 0;
tmpTag->tagNext = 0;
*tag = tmpTag;
tmpTag = NewTag();
if (tmpTag == 0) return -1;
printf("ParseTagDate unimplimented\n");
getc();
tmpTag->type = kTagTypeDate;
tmpTag->string = 0;
tmpTag->tag = 0;
tmpTag->offset = buffer_start ? buffer - buffer_start: 0;
tmpTag->tagNext = 0;
*tag = tmpTag;
tmpTag->type = type;
tmpTag->string = 0;
tmpTag->tag = 0;
tmpTag->offset = buffer_start ? buffer - buffer_start: 0;
tmpTag->tagNext = 0;
*tag = tmpTag;
tag->type = kTagTypeNone;
tag->string = 0;
tag->tag = 0;
tag->offset = 0;
tag->tagNext = gTagsFree;
gTagsFree = tag;
#else
return symbol;
}
bool XMLIsType(TagPtr dict, enum xmltype type)
{
if(!dict) return (type == kTagTypeNone);
return (dict->type == type);
}
/*** Cast functions ***/
TagPtr XMLCastArray(TagPtr dict)
{
if(!dict) return NULL;
if(dict->type == kTagTypeArray) return dict;
else return NULL;
}
TagPtr XMLCastDict(TagPtr dict)
{
if(!dict) return NULL;
if(dict->type == kTagTypeDict) return dict;
else return NULL;
}
char* XMLCastString(TagPtr dict)
{
if(!dict) return NULL;
if((dict->type == kTagTypeString) ||
(dict->type == kTagTypeKey)) return dict->string;
return NULL;
}
long XMLCastStringOffset(TagPtr dict)
{
if(dict &&
((dict->type == kTagTypeString) ||
(dict->type == kTagTypeKey)))
{
return dict->offset;
}
else
{
return -1;
}
}
bool XMLCastBoolean(TagPtr dict)
{
if(!dict) return false;
if(dict->type == kTagTypeTrue) return true;
return false;
}
int XMLCastInteger(TagPtr dict)
{
if(!dict)
{
printf("XMLCastInteger: null dict\n");
return 0;
}
if(dict->type == kTagTypeInteger) return (int)(dict->string);
return 0;
}
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#ifndef __LIBSAIO_XML_H
#define __LIBSAIO_XML_H
enum {
enum xmltype {
kTagTypeNone = 0,
kTagTypeDict,
kTagTypeKey,
kTagTypeArray
};
struct string_ref
{
char* string;
int id;
struct string_ref* next;
};
typedef struct string_ref string_ref;
extern string_ref* ref_strings;
#define kXMLTagPList "plist "
#define kXMLTagDict "dict"
#define kXMLTagKey "key"
#define kXMLTagTrue "true/"
#define kXMLTagArray "array"
#define kXMLStringID"ID="
#define kXMLStringIDRef "IDREF="
#define kPropCFBundleIdentifier ("CFBundleIdentifier")
#define kPropCFBundleExecutable ("CFBundleExecutable")
#define kPropOSBundleRequired ("OSBundleRequired")
extern long gImageLastKernelAddr;
TagPtr XMLGetProperty( TagPtr dict, const char * key );
TagPtr XMLGetElement( TagPtr dict, int id );
int XMLTagCount( TagPtr dict );
bool XMLIsType(TagPtr dict, enum xmltype type);
bool XMLCastBoolean( TagPtr dict );
char* XMLCastString( TagPtr dict );
long XMLCastStringOffset(TagPtr dict);
int XMLCastInteger ( TagPtr dict );
TagPtr XMLCastDict ( TagPtr dict );
TagPtr XMLCastArray( TagPtr dict );
long XMLParseNextTag(char *buffer, TagPtr *tag);
void XMLFreeTag(TagPtr tag);
char* XMLDecode(const char *in);
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bootArgsPreLion->Version = kBootArgsPreLionVersion;
bootArgsPreLion->Revision = kBootArgsPreLionRevision;
init_done = 1;
}
bootArgsPreLion = (boot_args_pre_lion *)AllocateKernelMemory(sizeof(boot_args_pre_lion));
bcopy(oldAddr, bootArgsPreLion, sizeof(boot_args_pre_lion));
}
}
void
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char * configEnd; // pointer to end of config files
char config[CONFIG_SIZE];
config_file_t bootConfig; // boot.plist
config_file_t bootConfig; // boot.plist
config_file_t overrideConfig; // additional boot.plist which can override bootConfig keys
config_file_t themeConfig; // theme.plist
config_file_t smbiosConfig; // smbios.plist
config_file_t themeConfig; // theme.plist
config_file_t smbiosConfig; // smbios.plist
config_file_t helperConfig; // boot helper partition's boot.plist
config_file_t ramdiskConfig; // RAMDisk.plist
} PrivateBootInfo_t;
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{
switch (Platform.CPU.Model)
{
case CPU_MODEL_YONAH:// Intel Mobile Core Solo, Duo
case CPU_MODEL_MEROM:// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx
case CPU_MODEL_PENRYN:// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx
case CPU_MODEL_ATOM:// Intel Atom (45nm)
case 0x0D: // ?
case CPU_MODEL_YONAH: // Yonah
case CPU_MODEL_MEROM: // Merom
case CPU_MODEL_PENRYN: // Penryn
case CPU_MODEL_ATOM: // Intel Atom (45nm)
{
bool cpu_dynamic_fsb = false;
break;
}
case CPU_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
case CPU_MODEL_FIELDS:
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
case CPU_MODEL_NEHALEM:// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx
case CPU_MODEL_SANDY_BRIDGE:// Intel Core i3, i5, i7, Xeon E3 LGA1155 (32nm)
case CPU_MODEL_WESTMERE:// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
case CPU_MODEL_DALES_32NM:
case CPU_MODEL_NEHALEM:
case CPU_MODEL_NEHALEM_EX:
case CPU_MODEL_WESTMERE:
case CPU_MODEL_WESTMERE_EX:
case CPU_MODEL_SANDY:
case CPU_MODEL_SANDY_XEON:
{
maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; // Seems it always contains maximum multiplier value (with turbo, that's we need)...
minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff;
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#include "pci.h"
#include "platform.h"
#include "spd.h"
#include "cpu.h"
#include "saio_internal.h"
#include "bootstruct.h"
#include "memvendors.h"
#if DEBUG_SPD
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#define DBG(x...)msglog(x)
#endif
static const char *spd_memory_types[] =
{
"RAM",/* 00h Undefined */
"FPM",/* 01h FPM */
"EDO",/* 02h EDO */
"",/* 03h PIPELINE NIBBLE */
"SDRAM",/* 04h SDRAM */
"",/* 05h MULTIPLEXED ROM */
"DDR SGRAM",/* 06h SGRAM DDR */
"DDR SDRAM",/* 07h SDRAM DDR */
"DDR2 SDRAM",/* 08h SDRAM DDR 2 */
"",/* 09h Undefined */
"",/* 0Ah Undefined */
"DDR3 SDRAM"/* 0Bh SDRAM DDR 3 */
"RAM", /* 00h Undefined */
"FPM", /* 01h FPM */
"EDO", /* 02h EDO */
"",/* 03h PIPELINE NIBBLE */
"SDRAM", /* 04h SDRAM */
"",/* 05h MULTIPLEXED ROM */
"DDR SGRAM",/* 06h SGRAM DDR */
"DDR SDRAM",/* 07h SDRAM DDR */
"DDR2 SDRAM", /* 08h SDRAM DDR 2 */
"",/* 09h Undefined */
"",/* 0Ah Undefined */
"DDR3 SDRAM" /* 0Bh SDRAM DDR 3 */
};
#define UNKNOWN_MEM_TYPE 2
static uint8_t spd_mem_to_smbios[] =
{
UNKNOWN_MEM_TYPE,/* 00h Undefined */
UNKNOWN_MEM_TYPE,/* 01h FPM */
UNKNOWN_MEM_TYPE,/* 02h EDO */
UNKNOWN_MEM_TYPE,/* 03h PIPELINE NIBBLE */
SMB_MEM_TYPE_SDRAM,/* 04h SDRAM */
SMB_MEM_TYPE_ROM,/* 05h MULTIPLEXED ROM */
SMB_MEM_TYPE_SGRAM,/* 06h SGRAM DDR */
SMB_MEM_TYPE_DDR,/* 07h SDRAM DDR */
SMB_MEM_TYPE_DDR2,/* 08h SDRAM DDR 2 */
UNKNOWN_MEM_TYPE,/* 09h Undefined */
UNKNOWN_MEM_TYPE,/* 0Ah Undefined */
SMB_MEM_TYPE_DDR3/* 0Bh SDRAM DDR 3 */
UNKNOWN_MEM_TYPE, /* 00h Undefined */
UNKNOWN_MEM_TYPE, /* 01h FPM */
UNKNOWN_MEM_TYPE, /* 02h EDO */
UNKNOWN_MEM_TYPE, /* 03h PIPELINE NIBBLE */
SMB_MEM_TYPE_SDRAM, /* 04h SDRAM */
SMB_MEM_TYPE_ROM, /* 05h MULTIPLEXED ROM */
SMB_MEM_TYPE_SGRAM, /* 06h SGRAM DDR */
SMB_MEM_TYPE_DDR, /* 07h SDRAM DDR */
SMB_MEM_TYPE_DDR2, /* 08h SDRAM DDR 2 */
UNKNOWN_MEM_TYPE, /* 09h Undefined */
UNKNOWN_MEM_TYPE, /* 0Ah Undefined */
SMB_MEM_TYPE_DDR3 /* 0Bh SDRAM DDR 3 */
};
#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))
outb(base + SMBHSTSTS, 0x1f);// reset SMBus Controller
outb(base + SMBHSTDAT, 0xff);
while( inb(base + SMBHSTSTS) & 0x01);// wait until ready
rdtsc(l1, h1);
while ( inb(base + SMBHSTSTS) & 0x01) // wait until read
{
rdtsc(l2, h2);
t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);
if (t > 5)
return 0xFF; // break
}
outb(base + SMBHSTCMD, cmd);
outb(base + SMBHSTADD, (adr << 1) | 0x01 );
}
return strdup(asciiPartNo);
return NULL;
}
int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};
{
int i, speed;
uint8_t spd_size, spd_type;
uint32_t base;
uint32_t base, mmio, hostc;
bool dump = false;
RamSlotInfo_t* slot;
uint16_t cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);
DBG("SMBus CmdReg: 0x%x\n", cmd);
pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);
mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;
base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;
DBG("Scanning smbus_dev <%04x, %04x> ...\n",smbus_dev->vendor_id, smbus_dev->device_id);
hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);
verbose("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n",
smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);
getBoolForKey("DumpSPD", &dump, &bootInfo->bootConfig);
bool fullBanks = // needed at least for laptops
Platform.DMI.MemoryModules == Platform.DMI.MaxMemorySlots;
// Search MAX_RAM_SLOTS slots
char spdbuf[256];
// needed at least for laptops
bool fullBanks = Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots;
char spdbuf[MAX_SPD_SIZE];
// Search MAX_RAM_SLOTS slots
for (i = 0; i < MAX_RAM_SLOTS; i++){
slot = &Platform.RAM.DIMM[i];
spd_size = smb_read_byte_intel(base, 0x50 + i, 0);
DBG("SPD[0] (size): %d @0x%x\n", spd_size, 0x50 + i);
// Check spd is present
if (spd_size && (spd_size != 0xff) ) {
if (spd_size && (spd_size != 0xff))
{
slot->spd = spdbuf;
slot->InUse = true;
//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);
init_spd(slot->spd, base, i);
switch (slot->spd[SPD_MEMORY_TYPE]) {
case SPD_MEMORY_TYPE_SDRAM_DDR2:
}
slot->Frequency = freq;
}
verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n",
i,
(int)slot->Type,
slot->Vendor,
slot->PartNo,
slot->SerialNo);
if(DEBUG_SPD) {
dumpPhysAddr("spd content: ",slot->spd, spd_size);
#if DEBUG_SPD
dumpPhysAddr("spd content: ", slot->spd, spd_size);
getc();
}
#endif
}
// laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:
Platform.DMI.DIMM[i]=
i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.MaxMemorySlots==2 ?
i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.CntMemorySlots == 2 ?
mapping[i] : i; // for laptops case, mapping setup would need to be more generic than this
slot->spd = NULL;
static struct smbus_controllers_t smbus_controllers[] = {
{0x8086, 0x269B, "ESB2", read_smb_intel },
{0x8086, 0x25A4, "6300ESB", read_smb_intel },
{0x8086, 0x24C3, "ICH4", read_smb_intel },
{0x8086, 0x24D3, "ICH5", read_smb_intel },
{0x8086, 0x266A, "ICH6", read_smb_intel },
{0x8086, 0x27DA, "ICH7", read_smb_intel },
{0x8086, 0x283E, "ICH8", read_smb_intel },
{0x8086, 0x2930, "ICH9", read_smb_intel },
{0x8086, 0x3A30, "ICH10R", read_smb_intel },
{0x8086, 0x3A60, "ICH10B", read_smb_intel },
{0x8086, 0x3B30, "5 Series", read_smb_intel },
{0x8086, 0x1C22, "6 Series", read_smb_intel },
{0x8086, 0x5032, "EP80579", read_smb_intel }
{0x8086, 0x269B, "ESB2", read_smb_intel },
{0x8086, 0x25A4, "6300ESB", read_smb_intel },
{0x8086, 0x24C3, "ICH4", read_smb_intel },
{0x8086, 0x24D3, "ICH5", read_smb_intel },
{0x8086, 0x266A, "ICH6", read_smb_intel },
{0x8086, 0x27DA, "ICH7", read_smb_intel },
{0x8086, 0x283E, "ICH8", read_smb_intel },
{0x8086, 0x2930, "ICH9", read_smb_intel },
{0x8086, 0x3A30, "ICH10R", read_smb_intel },
{0x8086, 0x3A60, "ICH10B", read_smb_intel },
{0x8086, 0x3B30, "P55", read_smb_intel },
{0x8086, 0x5032, "EP80579", read_smb_intel }
};
{
find_and_read_smbus_controller(root_pci_dev);
}
branches/Chimera/i386/libsaio/Makefile
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vbe.o nbp.o hfs.o hfs_compare.o \
xml.o ntfs.o msdos.o md5c.o device_tree.o \
cpu.o platform.o acpi_patcher.o \
smbios_patcher.o fake_efi.o ext2fs.o \
smbios.o smbios_getters.o smbios_decode.o \
fake_efi.o ext2fs.o \
hpet.o dram_controllers.o spd.o usb.o pci_setup.o \
device_inject.o nvidia.o ati.o pci_root.o \
convert.o mem.o aml_generator.o
convert.o aml_generator.o
SAIO_EXTERN_OBJS = console.o
#ranlib $(SYMROOT)/$@
libsaio.a: $(SAIO_EXTERN_OBJS) $(SAIO_OBJS)
rm -f $(SYMROOT)/$(@F)
ar q $(SYMROOT)/$(@F) $^
ranlib $(SYMROOT)/$(@F)
@echo "\t[RM] $(SYMROOT)/$(@F)"
@rm -f $(SYMROOT)/$(@F)
@echo "\t[AR] $@"
@ar q $(SYMROOT)/$(@F) $^ &> /dev/null
@echo "\t[RANLIB] $@"
@ranlib $(SYMROOT)/$(@F)
#saio_internal.h: saio_external.h
#saio_table.c: saio_external.h
#saio_defs.h: saio_external.h
branches/Chimera/i386/libsaio/SMBIOS.h
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/*
* Copyright (c) 1998-2006 Apple Computer, Inc. All rights reserved.
* Copyright (c) 1998-2009 Apple Computer, Inc. All rights reserved.
*
* @APPLE_LICENSE_HEADER_START@
*
* @APPLE_LICENSE_HEADER_END@
*/
/* This file is a stripped-down version of the one found in the AppleSMBIOS project.
* Changes:
* - Don't use pragma pack but instead use GCC's packed attribute
*/
#ifndef __LIBSAIO_SMBIOS_H
#define __LIBSAIO_SMBIOS_H
#ifndef _LIBSAIO_SMBIOS_H
#define _LIBSAIO_SMBIOS_H
//
// Based on System Management BIOS Reference Specification v2.5
//
/*
* Based on System Management BIOS Reference Specification v2.5
*/
typedef uint8_t SMBString;
typedef uint8_t SMBByte;
typedef uint16_t SMBWord;
typedef uint32_t SMBDWord;
typedef uint64_t SMBQWord;
typedef uint8_tSMBString;
typedef uint8_tSMBByte;
typedef uint16_tSMBWord;
typedef uint32_tSMBDWord;
typedef uint64_tSMBQWord;
struct DMIHeader {
SMBBytetype;
SMBBytelength;
SMBWordhandle;
} __attribute__((packed));
typedef struct DMIEntryPoint {
SMBByte anchor[5];
SMBByte checksum;
SMBWord tableLength;
SMBDWord tableAddress;
SMBWord structureCount;
SMBByte bcdRevision;
} __attribute__((packed)) DMIEntryPoint;
struct DMIEntryPoint {
SMBByteanchor[5];
SMBBytechecksum;
SMBWordtableLength;
SMBDWordtableAddress;
SMBWordstructureCount;
SMBBytebcdRevision;
} __attribute__((packed));
typedef struct SMBEntryPoint {
SMBByte anchor[4];
SMBByte checksum;
SMBByte entryPointLength;
SMBByte majorVersion;
SMBByte minorVersion;
SMBWord maxStructureSize;
SMBByte entryPointRevision;
SMBByte formattedArea[5];
DMIEntryPoint dmi;
} __attribute__((packed)) SMBEntryPoint;
struct SMBEntryPoint {
SMBByteanchor[4];
SMBBytechecksum;
SMBByteentryPointLength;
SMBBytemajorVersion;
SMBByteminorVersion;
SMBWordmaxStructureSize;
SMBByteentryPointRevision;
SMBByteformattedArea[5];
struct DMIEntryPointdmi;
} __attribute__((packed));
//
// Header common to all SMBIOS structures
//
struct DMIMemoryControllerInfo {/* 3.3.6 Memory Controller Information (Type 5) */
struct DMIHeaderdmiHeader;
SMBByteerrorDetectingMethod;
SMBByteerrorCorrectingCapability;
SMBBytesupportedInterleave;
SMBBytecurrentInterleave;
SMBBytemaxMemoryModuleSize;
SMBWordsupportedSpeeds;
SMBWordsupportedMemoryTypes;
SMBBytememoryModuleVoltage;
SMBBytenumberOfMemorySlots;
} __attribute__((packed));
typedef struct SMBStructHeader {
SMBByte type;
SMBByte length;
SMBWord handle;
} __attribute__((packed)) SMBStructHeader;
struct DMIMemoryModuleInfo {/* 3.3.7 Memory Module Information (Type 6) */
struct DMIHeaderdmiHeader;
SMBBytesocketDesignation;
SMBBytebankConnections;
SMBBytecurrentSpeed;
SMBWordcurrentMemoryType;
SMBByteinstalledSize;
SMBByteenabledSize;
SMBByteerrorStatus;
} __attribute__((packed));
#define SMB_STRUCT_HEADER SMBStructHeader header;
struct DMIPhysicalMemoryArray {/* 3.3.17 Physical Memory Array (Type 16) */
struct DMIHeaderdmiHeader;
SMBBytelocation;
SMBByteuse;
SMBBytememoryCorrectionError;
SMBDWordmaximumCapacity;
SMBWordmemoryErrorInformationHandle;
SMBWordnumberOfMemoryDevices;
} __attribute__((packed));
typedef struct SMBAnchor
{
const SMBStructHeader *header;
const uint8_t *next;
const uint8_t *end;
} SMBAnchor;
struct DMIMemoryDevice {/* 3.3.18 Memory Device (Type 17) */
struct DMIHeaderdmiHeader;
SMBWordphysicalMemoryArrayHandle;
SMBWordmemoryErrorInformationHandle;
SMBWordtotalWidth;
SMBWorddataWidth;
SMBWordsize;
SMBByteformFactor;
SMBBytedeviceSet;
SMBBytedeviceLocator;
SMBBytebankLocator;
SMBBytememoryType;
SMBWordtypeDetail;
SMBWord speed;
} __attribute__((packed));
#define SMB_ANCHOR_IS_VALID(x)\
((x) && ((x)->header) && ((x)->next) && ((x)->end))
#endif /* !_LIBSAIO_SMBIOS_H */
#define SMB_ANCHOR_RESET(x)\
bzero(x, sizeof(typedef struct SMBAnchor));
//
// SMBIOS structure types.
//
enum {
kSMBTypeBIOSInformation = 0,
kSMBTypeSystemInformation = 1,
kSMBTypeBaseBoard= 2,
kSMBTypeSystemEnclosure = 3,
kSMBTypeProcessorInformation = 4,
kSMBTypeMemoryModule = 6,
kSMBTypeCacheInformation = 7,
kSMBTypeSystemSlot = 9,
kSMBTypePhysicalMemoryArray = 16,
kSMBTypeMemoryDevice = 17,
kSMBType32BitMemoryErrorInfo = 18,
kSMBType64BitMemoryErrorInfo = 33,
kSMBTypeEndOfTable = 127,
/* Apple Specific Structures */
kSMBTypeFirmwareVolume = 128,
kSMBTypeMemorySPD = 130,
kSMBTypeOemProcessorType = 131,
kSMBTypeOemProcessorBusSpeed = 132
};
//
// BIOS Information (Type 0)
//
typedef struct SMBBIOSInformation {
SMB_STRUCT_HEADER // Type 0
SMBString vendor; // BIOS vendor name
SMBString version; // BIOS version
SMBWord startSegment; // BIOS segment start
SMBString releaseDate; // BIOS release date
SMBByte romSize; // (n); 64K * (n+1) bytes
SMBQWord characteristics; // supported BIOS functions
} __attribute__((packed)) SMBBIOSInformation;
//
// System Information (Type 1)
//
typedef struct SMBSystemInformation {
// 2.0+ spec (8 bytes)
SMB_STRUCT_HEADER // Type 1
SMBString manufacturer;
SMBString productName;
SMBString version;
SMBString serialNumber;
// 2.1+ spec (25 bytes)
SMBByte uuid[16]; // can be all 0 or all 1's
SMBByte wakeupReason; // reason for system wakeup
// 2.4+ spec (27 bytes)
SMBString skuNumber;
SMBString family;
} __attribute__((packed)) SMBSystemInformation;
//
// Base Board (Type 2)
//
typedef struct SMBBaseBoard {
SMB_STRUCT_HEADER // Type 2
SMBStringmanufacturer;
SMBStringproduct;
SMBStringversion;
SMBStringserialNumber;
SMBStringassetTagNumber;
SMBBytefeatureFlags;
SMBStringlocationInChassis;
SMBWordchassisHandle;
SMBByteboardType;
SMBBytenumberOfContainedHandles;
// 0 - 255 contained handles go here but we do not include
// them in our structure. Be careful to use numberOfContainedHandles
// times sizeof(SMBWord) when computing the actual record size,
// if you need it.
} __attribute__((packed)) SMBBaseBoard;
// Values for boardType in Type 2 records
enum {
kSMBBaseBoardUnknown= 0x01,
kSMBBaseBoardOther= 0x02,
kSMBBaseBoardServerBlade= 0x03,
kSMBBaseBoardConnectivitySwitch= 0x04,
kSMBBaseBoardSystemMgmtModule= 0x05,
kSMBBaseBoardProcessorModule= 0x06,
kSMBBaseBoardIOModule= 0x07,
kSMBBaseBoardMemoryModule= 0x08,
kSMBBaseBoardDaughter= 0x09,
kSMBBaseBoardMotherboard= 0x0A,
kSMBBaseBoardProcessorMemoryModule= 0x0B,
kSMBBaseBoardProcessorIOModule= 0x0C,
kSMBBaseBoardInterconnect= 0x0D,
};
//
// System Enclosure (Type 3)
//
typedef struct SMBSystemEnclosure {
SMB_STRUCT_HEADER // Type 3
SMBString manufacturer;
SMBByte type;
SMBString version;
SMBString serialNumber;
SMBString assetTagNumber;
SMBByte bootupState;
SMBByte powerSupplyState;
SMBByte thermalState;
SMBByte securityStatus;
SMBDWord oemDefined;
} __attribute__((packed)) SMBSystemEnclosure;
//
// Processor Information (Type 4)
//
typedef struct SMBProcessorInformation {
// 2.0+ spec (26 bytes)
SMB_STRUCT_HEADER // Type 4
SMBString socketDesignation;
SMBByte processorType; // CPU = 3
SMBByte processorFamily; // processor family enum
SMBString manufacturer;
SMBQWord processorID; // based on CPUID
SMBString processorVersion;
SMBByte voltage; // bit7 cleared indicate legacy mode
SMBWord externalClock; // external clock in MHz
SMBWord maximumClock; // max internal clock in MHz
SMBWord currentClock; // current internal clock in MHz
SMBByte status;
SMBByte processorUpgrade; // processor upgrade enum
// 2.1+ spec (32 bytes)
SMBWord L1CacheHandle;
SMBWord L2CacheHandle;
SMBWord L3CacheHandle;
// 2.3+ spec (35 bytes)
SMBString serialNumber;
SMBString assetTag;
SMBString partNumber;
} __attribute__((packed)) SMBProcessorInformation;
#define kSMBProcessorInformationMinSize 26
//
// Memory Module Information (Type 6)
// Obsoleted since SMBIOS version 2.1
//
typedef struct SMBMemoryModule {
SMB_STRUCT_HEADER // Type 6
SMBString socketDesignation;
SMBByte bankConnections;
SMBByte currentSpeed;
SMBWord currentMemoryType;
SMBByte installedSize;
SMBByte enabledSize;
SMBByte errorStatus;
} __attribute__((packed)) SMBMemoryModule;
#define kSMBMemoryModuleSizeNotDeterminable 0x7D
#define kSMBMemoryModuleSizeNotEnabled 0x7E
#define kSMBMemoryModuleSizeNotInstalled 0x7F
//
// Cache Information (Type 7)
//
typedef struct SMBCacheInformation {
SMB_STRUCT_HEADER // Type 7
SMBString socketDesignation;
SMBWord cacheConfiguration;
SMBWord maximumCacheSize;
SMBWord installedSize;
SMBWord supportedSRAMType;
SMBWord currentSRAMType;
SMBByte cacheSpeed;
SMBByte errorCorrectionType;
SMBByte systemCacheType;
SMBByte associativity;
} __attribute__((packed)) SMBCacheInformation;
typedef struct SMBSystemSlot {
// 2.0+ spec (12 bytes)
SMB_STRUCT_HEADER // Type 9
SMBString slotDesignation;
SMBByte slotType;
SMBByte slotDataBusWidth;
SMBByte currentUsage;
SMBByte slotLength;
SMBWord slotID;
SMBByte slotCharacteristics1;
// 2.1+ spec (13 bytes)
SMBByte slotCharacteristics2;
} __attribute__((packed)) SMBSystemSlot;
//
// Physical Memory Array (Type 16)
//
typedef struct SMBPhysicalMemoryArray {
// 2.1+ spec (15 bytes)
SMB_STRUCT_HEADER // Type 16
SMBByte physicalLocation; // physical location
SMBByte arrayUse; // the use for the memory array
SMBByte errorCorrection; // error correction/detection method
SMBDWord maximumCapacity; // maximum memory capacity in kilobytes
SMBWord errorHandle; // handle of a previously detected error
SMBWord numMemoryDevices; // number of memory slots or sockets
} __attribute__((packed)) SMBPhysicalMemoryArray;
// Memory Array - Use
enum {
kSMBMemoryArrayUseOther = 0x01,
kSMBMemoryArrayUseUnknown = 0x02,
kSMBMemoryArrayUseSystemMemory = 0x03,
kSMBMemoryArrayUseVideoMemory = 0x04,
kSMBMemoryArrayUseFlashMemory = 0x05,
kSMBMemoryArrayUseNonVolatileMemory = 0x06,
kSMBMemoryArrayUseCacheMemory = 0x07
};
// Memory Array - Error Correction Types
enum {
kSMBMemoryArrayErrorCorrectionTypeOther = 0x01,
kSMBMemoryArrayErrorCorrectionTypeUnknown = 0x02,
kSMBMemoryArrayErrorCorrectionTypeNone = 0x03,
kSMBMemoryArrayErrorCorrectionTypeParity = 0x04,
kSMBMemoryArrayErrorCorrectionTypeSingleBitECC = 0x05,
kSMBMemoryArrayErrorCorrectionTypeMultiBitECC = 0x06,
kSMBMemoryArrayErrorCorrectionTypeCRC = 0x07
};
//
// Memory Device (Type 17)
//
typedef struct SMBMemoryDevice {
// 2.1+ spec (21 bytes)
SMB_STRUCT_HEADER // Type 17
SMBWord arrayHandle; // handle of the parent memory array
SMBWord errorHandle; // handle of a previously detected error
SMBWord totalWidth; // total width in bits; including ECC bits
SMBWord dataWidth; // data width in bits
SMBWord memorySize; // bit15 is scale, 0 = MB, 1 = KB
SMBByte formFactor; // memory device form factor
SMBByte deviceSet; // parent set of identical memory devices
SMBString deviceLocator; // labeled socket; e.g. "SIMM 3"
SMBString bankLocator; // labeled bank; e.g. "Bank 0" or "A"
SMBByte memoryType; // type of memory
SMBWord memoryTypeDetail; // additional detail on memory type
// 2.3+ spec (27 bytes)
SMBWord memorySpeed; // speed of device in MHz (0 for unknown)
SMBString manufacturer;
SMBString serialNumber;
SMBString assetTag;
SMBString partNumber;
} __attribute__((packed)) SMBMemoryDevice;
//
// Firmware Volume Description (Apple Specific - Type 128)
//
enum {
FW_REGION_RESERVED = 0,
FW_REGION_RECOVERY = 1,
FW_REGION_MAIN = 2,
FW_REGION_NVRAM = 3,
FW_REGION_CONFIG = 4,
FW_REGION_DIAGVAULT = 5,
NUM_FLASHMAP_ENTRIES = 8
};
typedef struct FW_REGION_INFO
{
SMBDWord StartAddress;
SMBDWord EndAddress;
} __attribute__((packed)) FW_REGION_INFO;
typedef struct SMBFirmwareVolume {
SMB_STRUCT_HEADER // Type 128
SMBByte RegionCount;
SMBByte Reserved[3];
SMBDWord FirmwareFeatures;
SMBDWord FirmwareFeaturesMask;
SMBByte RegionType[ NUM_FLASHMAP_ENTRIES ];
FW_REGION_INFO FlashMap[ NUM_FLASHMAP_ENTRIES ];
} __attribute__((packed)) SMBFirmwareVolume;
//
// Memory SPD Data (Apple Specific - Type 130)
//
typedef struct SMBMemorySPD {
SMB_STRUCT_HEADER // Type 130
SMBWord Type17Handle;
SMBWord Offset;
SMBWord Size;
SMBWord Data[];
} __attribute__((packed)) SMBMemorySPD;
static const char *
SMBMemoryDeviceTypes[] =
{
"RAM", /* 00h Undefined */
"RAM", /* 01h Other */
"RAM", /* 02h Unknown */
"DRAM", /* 03h DRAM */
"EDRAM", /* 04h EDRAM */
"VRAM", /* 05h VRAM */
"SRAM", /* 06h SRAM */
"RAM", /* 07h RAM */
"ROM", /* 08h ROM */
"FLASH", /* 09h FLASH */
"EEPROM", /* 0Ah EEPROM */
"FEPROM", /* 0Bh FEPROM */
"EPROM", /* 0Ch EPROM */
"CDRAM", /* 0Dh CDRAM */
"3DRAM", /* 0Eh 3DRAM */
"SDRAM", /* 0Fh SDRAM */
"SGRAM", /* 10h SGRAM */
"RDRAM", /* 11h RDRAM */
"DDR SDRAM", /* 12h DDR */
"DDR2 SDRAM", /* 13h DDR2 */
"DDR2 FB-DIMM", /* 14h DDR2 FB-DIMM */
"RAM",/* 15h unused */
"RAM",/* 16h unused */
"RAM",/* 17h unused */
"DDR3",/* 18h DDR3, chosen in [5776134] */
};
static const int
kSMBMemoryDeviceTypeCount = sizeof(SMBMemoryDeviceTypes) /
sizeof(SMBMemoryDeviceTypes[0]);
//
// OEM Processor Type (Apple Specific - Type 131)
//
typedef struct SMBOemProcessorType {
SMB_STRUCT_HEADER
SMBWord ProcessorType;
} __attribute__((packed)) SMBOemProcessorType;
//
// OEM Processor Bus Speed (Apple Specific - Type 132)
//
typedef struct SMBOemProcessorBusSpeed {
SMB_STRUCT_HEADER
SMBWord ProcessorBusSpeed; // MT/s unit
} __attribute__((packed)) SMBOemProcessorBusSpeed;
//----------------------------------------------------------------------------------------------------------
/* From Foundation/Efi/Guid/Smbios/SmBios.h */
/* Modified to wrap Data4 array init with {} */
#define EFI_SMBIOS_TABLE_GUID {0xeb9d2d31, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}}
#define SMBIOS_ORIGINAL0
#define SMBIOS_PATCHED1
extern void *getSmbios(int which);
extern void readSMBIOSInfo(SMBEntryPoint *eps);
extern void setupSMBIOSTable(void);
extern void decodeSMBIOSTable(SMBEntryPoint *eps);
#endif /* !__LIBSAIO_SMBIOS_H */
branches/Chimera/i386/libsaio/memvendors.h
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} VenIdName;
VenIdName vendorMap[] = {
{ 0, 0x01, "AMD"},
{ 0, 0x01, "AMD"},
{ 0, 0x02, "AMI"},
{ 0, 0x83, "Fairchild"},
{ 0, 0x04, "Fujitsu"},
branches/Chimera/i386/libsaio/table.c
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/* 0x8 : boot protected mode 32-bit code segment
byte granularity, 1MB limit, MEMBASE offset */
{0xFFFF, MEMBASE, 0x00, 0x9E, 0x4F, 0x00},
//{0xFFFF, MEMBASE, 0x00, 0x9E, 0x4F, 0x00},
{0xFFFF, 0x0000, 0x00, 0x9E, 0xCF, 0x00},
/* 0x10 : boot protected mode data segment
page granularity, 4GB limit, MEMBASE offset */
branches/Chimera/i386/libsaio/fdisk.h
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#ifndef __LIBSAIO_FDISK_H
#define __LIBSAIO_FDISK_H
#define DISK_BLK00/* blkno of boot block */
#define DISK_BLK0SZ512/* size of boot block */
#define DISK_BOOTSZ446/* size of boot code in boot block */
#define DISK_SIGNATURE0xAA55/* signature of the boot record */
#define FDISK_NPART4/* number of entries in fdisk table */
#define FDISK_ACTIVE0x80/* indicator of active partition */
#define FDISK_NEXTNAME0xA7/* indicator of NeXT partition */
#define FDISK_DOS120x01/* 12-bit fat < 10MB dos partition */
#define FDISK_DOS16S0x04/* 16-bit fat < 32MB dos partition */
#define FDISK_DOSEXT0x05/* extended dos partition */
#define FDISK_DOS16B0x06/* 16-bit fat >= 32MB dos partition */
#define FDISK_NTFS0x07/* NTFS partition */
#define FDISK_SMALLFAT320x0b/* FAT32 partition */
#define FDISK_FAT320x0c/* FAT32 partition */
#define FDISK_DOS16SLBA0x0e
#define FDISK_LINUX0x83
#define FDISK_UFS0xa8/* Apple UFS partition */
#define FDISK_HFS0xaf/* Apple HFS partition */
#define FDISK_BOOTER0xab/* Apple booter partition */
#define DISK_BLK0 0 /* blkno of boot block */
#define DISK_BLK0SZ 512 /* size of boot block */
#define DISK_BOOTSZ 446 /* size of boot code in boot block */
#define DISK_SIGNATURE 0xAA55 /* signature of the boot record */
#define FDISK_NPART 4 /* number of entries in fdisk table */
#define FDISK_ACTIVE 0x80 /* indicator of active partition */
#define FDISK_NEXTNAME 0xA7 /* indicator of NeXT partition */
#define FDISK_DOS12 0x01 /* 12-bit fat < 10MB dos partition */
#define FDISK_DOS16S 0x04 /* 16-bit fat < 32MB dos partition */
#define FDISK_DOSEXT 0x05 /* extended dos partition */
#define FDISK_DOS16B 0x06 /* 16-bit fat >= 32MB dos partition */
#define FDISK_NTFS 0x07 /* NTFS partition */
#define FDISK_SMALLFAT32 0x0b /* FAT32 partition */
#define FDISK_FAT32 0x0c /* FAT32 partition */
#define FDISK_DOS16SLBA 0x0e
#define FDISK_LINUX0x83
#define FDISK_UFS 0xa8 /* Apple UFS partition */
#define FDISK_HFS 0xaf /* Apple HFS partition */
#define FDISK_BOOTER 0xab /* Apple booter partition */
/*
* Format of fdisk partion entry (if present).
*/
struct fdisk_part {
unsigned char bootid;/* bootable or not */
unsigned char beghead;/* begining head, sector, cylinder */
unsigned char begsect;/* begcyl is a 10-bit number */
unsigned char begcyl;/* High 2 bits are in begsect */
unsigned char systid;/* OS type */
unsigned char endhead;/* ending head, sector, cylinder */
unsigned char endsect;/* endcyl is a 10-bit number */
unsigned char endcyl;/* High 2 bits are in endsect */
unsigned long relsect;/* partion physical offset on disk */
unsigned long numsect;/* number of sectors in partition */
unsigned char bootid; /* bootable or not */
unsigned char beghead; /* begining head, sector, cylinder */
unsigned char begsect; /* begcyl is a 10-bit number */
unsigned char begcyl; /* High 2 bits are in begsect */
unsigned char systid; /* OS type */
unsigned char endhead; /* ending head, sector, cylinder */
unsigned char endsect; /* endcyl is a 10-bit number */
unsigned char endcyl; /* High 2 bits are in endsect */
unsigned long relsect; /* partion physical offset on disk */
unsigned long numsect; /* number of sectors in partition */
} __attribute__((packed));
/*
branches/Chimera/i386/libsaio/nvidia.c
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#define DBG(x...)
#endif
#define NVIDIA_ROM_SIZE 0x20000
#define NVIDIA_ROM_SIZE 0x10000
#define PATCH_ROM_SUCCESS 1
#define PATCH_ROM_SUCCESS_HAS_LVDS 2
#define PATCH_ROM_FAILED 0
const char *nvidia_device_type_0[]={ "@0,device_type","display" };
const char *nvidia_device_type_1[]={ "@1,device_type","display" };
const char *nvidia_device_type[]={ "device_type","NVDA,Parent" };
const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
const char *nvidia_slot_name[]={ "AAPL,slot-name","Slot-1" };
static uint8_t default_dcfg_0[]={0xff, 0xff, 0xff, 0xff};
static uint8_t default_dcfg_1[]={0xff, 0xff, 0xff, 0xff};
static uint8_t default_NVCAP[]= {
0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
0x00, 0x00, 0x00, 0x00
};
static uint8_t default_NVPM[]= {
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
};
#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )
#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )
#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )
static struct nv_chipsets_t NVKnownChipsets[] = {
{ 0x00000000, "Unknown" },
// 0040 - 004F
{ 0x10DE0040, "GeForce 6800 Ultra" },
{ 0x10DE0041, "GeForce 6800" },
{ 0x10DE0042, "GeForce 6800 LE" },
{ 0x10DE0046, "GeForce 6800 GT" },
{ 0x10DE0047, "GeForce 6800 GS" },
{ 0x10DE0048, "GeForce 6800 XT" },
{ 0x10DE004D, "Quadro FX 3400" },
{ 0x10DE004E, "Quadro FX 4000" },
// 0050 - 005F
// 0060 - 006F
// 0070 - 007F
// 0080 - 008F
// 0090 - 009F
{ 0x10DE0090, "GeForce 7800 GTX" },
{ 0x10DE0091, "GeForce 7800 GTX" },
{ 0x10DE0092, "GeForce 7800 GT" },
{ 0x10DE0098, "GeForce Go 7800" },
{ 0x10DE0099, "GeForce Go 7800 GTX" },
{ 0x10DE009D, "Quadro FX 4500" },
// 00A0 - 00AF
// 00B0 - 00BF
// 00C0 - 00CF
{ 0x10DE00C0, "GeForce 6800 GS" },
{ 0x10DE00C1, "GeForce 6800" },
{ 0x10DE00C2, "GeForce 6800 LE" },
{ 0x10DE00CC, "Quadro FX Go1400" },
{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },
{ 0x10DE00CE, "Quadro FX 1400" },
// 00D0 - 00DF
// 00E0 - 00EF
// 00F0 - 00FF
{ 0x10DE00F1, "GeForce 6600 GT" },
{ 0x10DE00F2, "GeForce 6600" },
{ 0x10DE00F3, "GeForce 6200" },
{ 0x10DE00F4, "GeForce 6600 LE" },
{ 0x10DE00F5, "GeForce 7800 GS" },
{ 0x10DE00F6, "GeForce 6800 GS/XT" },
{ 0x10DE00F8, "Quadro FX 3400/4400" },
{ 0x10DE00F9, "GeForce 6800 Series GPU" },
// 0100 - 010F
// 0110 - 011F
// 0120 - 012F
// 0130 - 013F
// 0140 - 014F
{ 0x10DE0140, "GeForce 6600 GT" },
{ 0x10DE0141, "GeForce 6600" },
{ 0x10DE0142, "GeForce 6600 LE" },
{ 0x10DE0147, "GeForce 6700 XL" },
{ 0x10DE0148, "GeForce Go 6600" },
{ 0x10DE0149, "GeForce Go 6600 GT" },
{ 0x10DE014A, "Quadro NVS 440" },
{ 0x10DE014C, "Quadro FX 550" },
{ 0x10DE014D, "Quadro FX 550" },
{ 0x10DE014E, "Quadro FX 540" },
{ 0x10DE014F, "GeForce 6200" },
// 0150 - 015F
// 0160 - 016F
{ 0x10DE0160, "GeForce 6500" },
{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },
{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },
{ 0x10DE0168, "GeForce Go 6400" },
{ 0x10DE0169, "GeForce 6250" },
{ 0x10DE016A, "GeForce 7100 GS" },
// 0170 - 017F
// 0180 - 018F
// 0190 - 019F
{ 0x10DE0191, "GeForce 8800 GTX" },
{ 0x10DE0193, "GeForce 8800 GTS" },
{ 0x10DE0194, "GeForce 8800 Ultra" },
{ 0x10DE0197, "Tesla C870" },
{ 0x10DE019D, "Quadro FX 5600" },
{ 0x10DE019E, "Quadro FX 4600" },
// 01A0 - 01AF
// 01B0 - 01BF
// 01C0 - 01CF
// 01D0 - 01DF
{ 0x10DE01D0, "GeForce 7350 LE" },
{ 0x10DE01D1, "GeForce 7300 LE" },
{ 0x10DE01D2, "GeForce 7550 LE" },
{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },
{ 0x10DE01D3, "GeForce 7300 SE" },
{ 0x10DE01D6, "GeForce Go 7200" },
{ 0x10DE01D7, "GeForce Go 7300" },
{ 0x10DE01D8, "GeForce Go 7400" },
{ 0x10DE01DD, "GeForce 7500 LE" },
{ 0x10DE01DE, "Quadro FX 350" },
{ 0x10DE01DF, "GeForce 7300 GS" },
// 01E0 - 01EF
// 01F0 - 01FF
// 0200 - 020F
// 0210 - 021F
{ 0x10DE0211, "GeForce 6800" },
{ 0x10DE0212, "GeForce 6800 LE" },
{ 0x10DE0215, "GeForce 6800 GT" },
{ 0x10DE0218, "GeForce 6800 XT" },
// 0220 - 022F
{ 0x10DE0221, "GeForce 6200" },
{ 0x10DE0222, "GeForce 6200 A-LE" },
// 0230 - 023F
// 0240 - 024F
{ 0x10DE0240, "GeForce 6150" },
{ 0x10DE0241, "GeForce 6150 LE" },
{ 0x10DE0242, "GeForce 6100" },
{ 0x10DE0244, "GeForce Go 6150" },
{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },
{ 0x10DE0247, "GeForce Go 6100" },
// 0250 - 025F
// 0260 - 026F
// 0270 - 027F
// 0280 - 028F
// 0290 - 029F
{ 0x10DE0290, "GeForce 7900 GTX" },
{ 0x10DE0291, "GeForce 7900 GT/GTO" },
{ 0x10DE0291, "GeForce 7900 GT" },
{ 0x10DE0292, "GeForce 7900 GS" },
{ 0x10DE0293, "GeForce 7950 GX2" },
{ 0x10DE0294, "GeForce 7950 GX2" },
{ 0x10DE0295, "GeForce 7950 GT" },
{ 0x10DE0298, "GeForce Go 7900 GS" },
{ 0x10DE0299, "GeForce Go 7900 GTX" },
{ 0x10DE029A, "Quadro FX 2500M" },
{ 0x10DE029D, "Quadro FX 3500" },
{ 0x10DE029E, "Quadro FX 1500" },
{ 0x10DE029F, "Quadro FX 4500 X2" },
// 02A0 - 02AF
// 02B0 - 02BF
// 02C0 - 02CF
// 02D0 - 02DF
// 02E0 - 02EF
{ 0x10DE02E0, "GeForce 7600 GT" },
{ 0x10DE02E1, "GeForce 7600 GS" },
{ 0x10DE02E2, "GeForce 7300 GT" },
{ 0x10DE02E3, "GeForce 7900 GS" },
{ 0x10DE02E4, "GeForce 7950 GT" },
// 02F0 - 02FF
// 0300 - 030F
{ 0x10DE0301, "GeForce FX 5800 Ultra" },
{ 0x10DE0302, "GeForce FX 5800" },
{ 0x10DE0308, "Quadro FX 2000" },
{ 0x10DE0309, "Quadro FX 1000" },
// 0310 - 031F
{ 0x10DE0311, "GeForce FX 5600 Ultra" },
{ 0x10DE0312, "GeForce FX 5600" },
{ 0x10DE0314, "GeForce FX 5600XT" },
{ 0x10DE031A, "GeForce FX Go5600" },
{ 0x10DE031B, "GeForce FX Go5650" },
{ 0x10DE031C, "Quadro FX Go700" },
// 0320 - 032F
{ 0x10DE0324, "GeForce FX Go5200" },
{ 0x10DE0325, "GeForce FX Go5250" },
{ 0x10DE0326, "GeForce FX 5500" },
{ 0x10DE032B, "Quadro FX 500/600 PCI" },
{ 0x10DE032C, "GeForce FX Go53xx Series" },
{ 0x10DE032D, "GeForce FX Go5100" },
// 0330 - 033F
{ 0x10DE0330, "GeForce FX 5900 Ultra" },
{ 0x10DE0331, "GeForce FX 5900" },
{ 0x10DE0332, "GeForce FX 5900XT" },
{ 0x10DE0334, "GeForce FX 5900ZT" },
{ 0x10DE0338, "Quadro FX 3000" },
{ 0x10DE033F, "Quadro FX 700" },
// 0340 - 034F
{ 0x10DE0341, "GeForce FX 5700 Ultra" },
{ 0x10DE0342, "GeForce FX 5700" },
{ 0x10DE0343, "GeForce FX 5700LE" },
{ 0x10DE0348, "GeForce FX Go5700" },
{ 0x10DE034C, "Quadro FX Go1000" },
{ 0x10DE034E, "Quadro FX 1100" },
// 0350 - 035F
// 0360 - 036F
// 0370 - 037F
// 0380 - 038F
{ 0x10DE038B, "GeForce 7650 GS" },
// 0390 - 039F
{ 0x10DE0390, "GeForce 7650 GS" },
{ 0x10DE0391, "GeForce 7600 GT" },
{ 0x10DE0392, "GeForce 7600 GS" },
{ 0x10DE0393, "GeForce 7300 GT" },
{ 0x10DE039B, "GeForce Go 7900 SE" },
{ 0x10DE039C, "Quadro FX 550M" },
{ 0x10DE039E, "Quadro FX 560" },
// 03A0 - 03AF
// 03B0 - 03BF
// 03C0 - 03CF
// 03D0 - 03DF
{ 0x10DE03D0, "GeForce 6150SE nForce 430" },
{ 0x10DE03D1, "GeForce 6100 nForce 405" },
{ 0x10DE03D2, "GeForce 6100 nForce 400" },
{ 0x10DE03D5, "GeForce 6100 nForce 420" },
{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },
// 03E0 - 03EF
// 03F0 - 03FF
// 0400 - 040F
{ 0x10DE0400, "GeForce 8600 GTS" },
{ 0x10DE0401, "GeForce 8600 GT" },
{ 0x10DE0402, "GeForce 8600 GT" },
{ 0x10DE0403, "GeForce 8600 GS" },
{ 0x10DE0404, "GeForce 8400 GS" },
{ 0x10DE0405, "GeForce 9500M GS" },
{ 0x10DE0406, "GeForce 8300 GS" },
{ 0x10DE0407, "GeForce 8600M GT" },
{ 0x10DE0408, "GeForce 9650M GS" },
{ 0x10DE0409, "GeForce 8700M GT" },
{ 0x10DE040D, "Quadro FX 1600M" },
{ 0x10DE040E, "Quadro FX 570" },
{ 0x10DE040F, "Quadro FX 1700" },
// 0410 - 041F
{ 0x10DE0410, "GeForce GT 330" },
// 0420 - 042F
{ 0x10DE0420, "GeForce 8400 SE" },
{ 0x10DE0421, "GeForce 8500 GT" },
{ 0x10DE0422, "GeForce 8400 GS" },
{ 0x10DE042D, "Quadro FX 360M" },
{ 0x10DE042E, "GeForce 9300M G" },
{ 0x10DE042F, "Quadro NVS 290" },
// 0430 - 043F
// 0440 - 044F
// 0450 - 045F
// 0460 - 046F
// 0470 - 047F
// 0480 - 048F
// 0490 - 049F
// 04A0 - 04AF
// 04B0 - 04BF
// 04C0 - 04CF
// 04D0 - 04DF
// 04E0 - 04EF
// 04F0 - 04FF
// 0500 - 050F
// 0510 - 051F
// 0520 - 052F
// 0530 - 053F
{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },
{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },
{ 0x10DE053E, "GeForce 7025 / nForce 630a" },
// 0540 - 054F
// 0550 - 055F
// 0560 - 056F
// 0570 - 057F
// 0580 - 058F
// 0590 - 059F
// 05A0 - 05AF
// 05B0 - 05BF
// 05C0 - 05CF
// 05D0 - 05DF
// 05E0 - 05EF
{ 0x10DE05E0, "GeForce GTX 295" },
{ 0x10DE05E1, "GeForce GTX 280" },
{ 0x10DE05E2, "GeForce GTX 260" },
{ 0x10DE05E6, "GeForce GTX 275" },
{ 0x10DE05EA, "GeForce GTX 260" },
{ 0x10DE05EB, "GeForce GTX 295" },
{ 0x10DE05ED, "Quadroplex 2200 D2" },
// 05F0 - 05FF
{ 0x10DE05F8, "Quadroplex 2200 S4" },
{ 0x10DE05F9, "Quadro CX" },
{ 0x10DE05FD, "Quadro FX 5800" },
{ 0x10DE05FE, "Quadro FX 4800" },
{ 0x10DE05FF, "Quadro FX 3800" },
// 0600 - 060F
{ 0x10DE0600, "GeForce 8800 GTS 512" },
{ 0x10DE0601, "GeForce 9800 GT" },
{ 0x10DE0602, "GeForce 8800 GT" },
{ 0x10DE0603, "GeForce GT 230" },
{ 0x10DE0604, "GeForce 9800 GX2" },
{ 0x10DE0605, "GeForce 9800 GT" },
{ 0x10DE0606, "GeForce 8800 GS" },
{ 0x10DE060B, "GeForce 9800M GT" },
{ 0x10DE060C, "GeForce 8800M GTX" },
{ 0x10DE060D, "GeForce 8800 GS" },
{ 0x10DE060F, "GeForce GTX 285M" },
// 0610 - 061F
{ 0x10DE0610, "GeForce 9600 GSO" },
{ 0x10DE0611, "GeForce 8800 GT" },
{ 0x10DE0612, "GeForce 9800 GTX" },
{ 0x10DE0614, "GeForce 9800 GT" },
{ 0x10DE0615, "GeForce GTS 250" },
{ 0x10DE0617, "GeForce 9800M GTX" },
{ 0x10DE0618, "GeForce GTX 260M" },
{ 0x10DE0619, "Quadro FX 4700 X2" },
{ 0x10DE0618, "GeForce GTX 260M" },
{ 0x10DE061A, "Quadro FX 3700" },
{ 0x10DE061B, "Quadro VX 200" },
{ 0x10DE061C, "Quadro FX 3600M" },
{ 0x10DE061D, "Quadro FX 2800M" },
{ 0x10DE061F, "Quadro FX 3800M" },
// 0620 - 062F
{ 0x10DE0622, "GeForce 9600 GT" },
{ 0x10DE0623, "GeForce 9600 GS" },
{ 0x10DE0625, "GeForce 9600 GSO 512"},
{ 0x10DE0628, "GeForce 9800M GTS" },
{ 0x10DE062A, "GeForce 9700M GTS" },
{ 0x10DE062C, "GeForce 9800M GTS" },
{ 0x10DE062D, "GeForce 9600 GT" },
{ 0x10DE062E, "GeForce 9600 GT" },
// 0630 - 063F
{ 0x10DE0631, "GeForce GTS 160M" },
{ 0x10DE0632, "GeForce GTS 150M" },
{ 0x10DE0635, "GeForce 9600 GSO" },
{ 0x10DE0637, "GeForce 9600 GT" },
{ 0x10DE0638, "Quadro FX 1800" },
{ 0x10DE063A, "Quadro FX 2700M" },
// 0640 - 064F
{ 0x10DE0640, "GeForce 9500 GT" },
{ 0x10DE0641, "GeForce 9400 GT" },
{ 0x10DE0642, "GeForce 8400 GS" },
{ 0x10DE064A, "GeForce 9700M GT" },
{ 0x10DE064B, "GeForce 9500M G" },
{ 0x10DE064C, "GeForce 9650M GT" },
// 0650 - 065F
{ 0x10DE0651, "GeForce G 110M" },
{ 0x10DE0652, "GeForce GT 130M" },
{ 0x10DE0653, "GeForce GT 120M" },
{ 0x10DE0654, "GeForce GT 220M" },
{ 0x10DE0656, "GeForce 9650 S" },
{ 0x10DE0658, "Quadro FX 380" },
{ 0x10DE0659, "Quadro FX 580" },
{ 0x10DE065A, "Quadro FX 1700M" },
{ 0x10DE065B, "GeForce 9400 GT" },
{ 0x10DE065C, "Quadro FX 770M" },
{ 0x10DE065F, "GeForce G210" },
// 0660 - 066F
// 0670 - 067F
// 0680 - 068F
// 0690 - 069F
// 06A0 - 06AF
// 06B0 - 06BF
// 06C0 - 06CF
{ 0x10DE06C0, "GeForce GTX 480" },
{ 0x10DE06C3, "GeForce GTX D12U" },
{ 0x10DE06C4, "GeForce GTX 465" },
{ 0x10DE06CA, "GeForce GTX 480M" },
{ 0x10DE06CD, "GeForce GTX 470" },
// 06D0 - 06DF
{ 0x10DE06D1, "Tesla C2050" },// TODO: sub-device id: 0x0771
{ 0x10DE06D1, "Tesla C2070" },// TODO: sub-device id: 0x0772
{ 0x10DE06D2, "Tesla M2070" },
{ 0x10DE06D8, "Quadro 6000" },
{ 0x10DE06D9, "Quadro 5000" },
{ 0x10DE06DA, "Quadro 5000M" },
{ 0x10DE06DC, "Quadro 6000" },
{ 0x10DE06DE, "Tesla M2050" },// TODO: sub-device id: 0x0846
{ 0x10DE06DE, "Tesla M2070" },// TODO: sub-device id: ?
// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070
{ 0x10DE06DD, "Quadro 4000" },
{ 0x10DE06DE, "Tesla M2050" },// TODO: sub-device id: 0x0846
{ 0x10DE06DE, "Tesla M2070" },// TODO: sub-device id: ?
// 06E0 - 06EF
{ 0x10DE06E0, "GeForce 9300 GE" },
{ 0x10DE06E1, "GeForce 9300 GS" },
{ 0x10DE06E2, "GeForce 8400" },
{ 0x10DE06E3, "GeForce 8400 SE" },
{ 0x10DE06E4, "GeForce 8400 GS" },
{ 0x10DE06E5, "GeForce 9300M GS" },
{ 0x10DE06E6, "GeForce G100" },
{ 0x10DE06E7, "GeForce 9300 SE" },
{ 0x10DE06E8, "GeForce 9200M GS" },
{ 0x10DE06E9, "GeForce 9300M GS" },
{ 0x10DE06EA, "Quadro NVS 150M" },
{ 0x10DE06EB, "Quadro NVS 160M" },
{ 0x10DE06EC, "GeForce G 105M" },
{ 0x10DE06EF, "GeForce G 103M" },
// 06F0 - 06FF
{ 0x10DE06F8, "Quadro NVS 420" },
{ 0x10DE06F9, "Quadro FX 370 LP" },
{ 0x10DE06FA, "Quadro NVS 450" },
{ 0x10DE06FB, "Quadro FX 370M" },
{ 0x10DE06FD, "Quadro NVS 295" },
// 0700 - 070F
// 0710 - 071F
// 0720 - 072F
// 0730 - 073F
// 0740 - 074F
// 0750 - 075F
// 0760 - 076F
// 0770 - 077F
// 0780 - 078F
// 0790 - 079F
// 07A0 - 07AF
// 07B0 - 07BF
// 07C0 - 07CF
// 07D0 - 07DF
// 07E0 - 07EF
{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },
{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },
{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },
{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },
{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },
// 07F0 - 07FF
// 0800 - 080F
// 0810 - 081F
// 0820 - 082F
// 0830 - 083F
// 0840 - 084F
{ 0x10DE0844, "GeForce 9100M G" },
{ 0x10DE0845, "GeForce 8200M G" },
{ 0x10DE0846, "GeForce 9200" },
{ 0x10DE0847, "GeForce 9100" },
{ 0x10DE0848, "GeForce 8300" },
{ 0x10DE0849, "GeForce 8200" },
{ 0x10DE084A, "nForce 730a" },
{ 0x10DE084B, "GeForce 9200" },
{ 0x10DE084C, "nForce 980a/780a SLI" },
{ 0x10DE084D, "nForce 750a SLI" },
{ 0x10DE084F, "GeForce 8100 / nForce 720a" },
// 0850 - 085F
// 0860 - 086F
{ 0x10DE0860, "GeForce 9400" },
{ 0x10DE0861, "GeForce 9400" },
{ 0x10DE0862, "GeForce 9400M G" },
{ 0x10DE0863, "GeForce 9400M" },
{ 0x10DE0864, "GeForce 9300" },
{ 0x10DE0865, "ION" },
{ 0x10DE0866, "GeForce 9400M G" },
{ 0x10DE0867, "GeForce 9400" },
{ 0x10DE0868, "nForce 760i SLI" },
{ 0x10DE086A, "GeForce 9400" },
{ 0x10DE086C, "GeForce 9300 / nForce 730i" },
{ 0x10DE086D, "GeForce 9200" },
{ 0x10DE086E, "GeForce 9100M G" },
{ 0x10DE086F, "GeForce 8200M G" },
// 0870 - 087F
{ 0x10DE0870, "GeForce 9400M" },
{ 0x10DE0871, "GeForce 9200" },
{ 0x10DE0872, "GeForce G102M" },
{ 0x10DE0873, "GeForce G102M" },
{ 0x10DE0874, "ION 9300M" },
{ 0x10DE0876, "ION" },
{ 0x10DE087A, "GeForce 9400" },
{ 0x10DE086C, "GeForce 9300/nForce 730i" },
{ 0x10DE087D, "ION 9400M" },
{ 0x10DE087E, "ION LE" },
{ 0x10DE087F, "ION LE" },
// 0880 - 088F
// 0890 - 089F
// 08A0 - 08AF
// 08B0 - 08BF
// 08C0 - 08CF
// 08D0 - 08DF
// 08E0 - 08EF
// 08F0 - 08FF
// 0900 - 090F
// 0910 - 091F
// 0920 - 092F
// 0930 - 093F
// 0940 - 094F
// 0950 - 095F
// 0960 - 096F
// 0970 - 097F
// 0980 - 098F
// 0990 - 099F
// 09A0 - 09AF
// 09B0 - 09BF
// 09C0 - 09CF
// 09D0 - 09DF
// 09E0 - 09EF
// 09F0 - 09FF
// 0A00 - 0A0F
// 0A10 - 0A1F
// 0A20 - 0A2F
{ 0x10DE0A20, "GeForce GT220" },
{ 0x10DE0A22, "GeForce 315" },
{ 0x10DE0A23, "GeForce 210" },
{ 0x10DE0A28, "GeForce GT 230M" },
{ 0x10DE0A29, "GeForce GT 330M" },
{ 0x10DE0A2A, "GeForce GT 230M" },
{ 0x10DE0A2B, "GeForce GT 330M" },
{ 0x10DE0A2C, "NVS 5100M" },
{ 0x10DE0A2D, "GeForce GT 320M" },
// 0A30 - 0A3F
{ 0x10DE0A34, "GeForce GT 240M" },
{ 0x10DE0A35, "GeForce GT 325M" },
{ 0x10DE0A3C, "Quadro FX 880M" },
// 0A40 - 0A4F
// 0A50 - 0A5F
// 0A60 - 0A6F
{ 0x10DE0A60, "GeForce G210" },
{ 0x10DE0A62, "GeForce 205" },
{ 0x10DE0A63, "GeForce 310" },
{ 0x10DE0A64, "ION" },
{ 0x10DE0A65, "GeForce 210" },
{ 0x10DE0A66, "GeForce 310" },
{ 0x10DE0A67, "GeForce 315" },
{ 0x10DE0A68, "GeForce G105M" },
{ 0x10DE0A69, "GeForce G105M" },
{ 0x10DE0A6A, "NVS 2100M" },
{ 0x10DE0A6C, "NVS 3100M" },
{ 0x10DE0A6E, "GeForce 305M" },
{ 0x10DE0A6F, "ION" },
// 0A70 - 0A7F
{ 0x10DE0A70, "GeForce 310M" },
{ 0x10DE0A71, "GeForce 305M" },
{ 0x10DE0A72, "GeForce 310M" },
{ 0x10DE0A73, "GeForce 305M" },
{ 0x10DE0A74, "GeForce G210M" },
{ 0x10DE0A75, "GeForce G310M" },
{ 0x10DE0A78, "Quadro FX 380 LP" },
{ 0x10DE0A7C, "Quadro FX 380M" },
// 0A80 - 0A8F
// 0A90 - 0A9F
// 0AA0 - 0AAF
// 0AB0 - 0ABF
// 0AC0 - 0ACF
// 0AD0 - 0ADF
// 0AE0 - 0AEF
// 0AF0 - 0AFF
// 0B00 - 0B0F
// 0B10 - 0B1F
// 0B20 - 0B2F
// 0B30 - 0B3F
// 0B40 - 0B4F
// 0B50 - 0B5F
// 0B60 - 0B6F
// 0B70 - 0B7F
// 0B80 - 0B8F
// 0B90 - 0B9F
// 0BA0 - 0BAF
// 0BB0 - 0BBF
// 0BC0 - 0BCF
// 0BD0 - 0BDF
// 0BE0 - 0BEF
// 0BF0 - 0BFF
// 0C00 - 0C0F
// 0C10 - 0C1F
// 0C20 - 0C2F
// 0C30 - 0C3F
// 0C40 - 0C4F
// 0C50 - 0C5F
// 0C60 - 0C6F
// 0C70 - 0C7F
// 0C80 - 0C8F
// 0C90 - 0C9F
// 0CA0 - 0CAF
{ 0x10DE0CA0, "GeForce GT 330 " },
{ 0x10DE0CA2, "GeForce GT 320" },
{ 0x10DE0CA3, "GeForce GT 240" },
{ 0x10DE0CA4, "GeForce GT 340" },
{ 0x10DE0CA7, "GeForce GT 330" },
{ 0x10DE0CA8, "GeForce GTS 260M" },
{ 0x10DE0CA9, "GeForce GTS 250M" },
{ 0x10DE0CAC, "GeForce 315" },
{ 0x10DE0CAF, "GeForce GT 335M" },
// 0CB0 - 0CBF
{ 0x10DE0CB0, "GeForce GTS 350M" },
{ 0x10DE0CB1, "GeForce GTS 360M" },
{ 0x10DE0CBC, "Quadro FX 1800M" },
// 0CC0 - 0CCF
// 0CD0 - 0CDF
// 0CE0 - 0CEF
// 0CF0 - 0CFF
// 0D00 - 0D0F
// 0D10 - 0D1F
// 0D20 - 0D2F
// 0D30 - 0D3F
// 0D40 - 0D4F
// 0D50 - 0D5F
// 0D60 - 0D6F
// 0D70 - 0D7F
// 0D80 - 0D8F
// 0D90 - 0D9F
// 0DA0 - 0DAF
// 0DB0 - 0DBF
// 0DC0 - 0DCF
{ 0x10DE0CA3, "GeForce GT240" },
// 06C0 - 06DFF
{ 0x10DE06C0, "GeForce GTX 480" },
{ 0x10DE06C3, "GeForce GTX D12U" },
{ 0x10DE06C4, "GeForce GTX 465" },
{ 0x10DE06CA, "GeForce GTX 480M" },
{ 0x10DE06CD, "GeForce GTX 470" },
{ 0x10DE06D1, "Tesla C2050" },// TODO: sub-device id: 0x0771
{ 0x10DE06D1, "Tesla C2070" },// TODO: sub-device id: 0x0772
{ 0x10DE06D2, "Tesla M2070" },
{ 0x10DE06D8, "Quadro 6000" },
{ 0x10DE06D9, "Quadro 5000" },
{ 0x10DE06DA, "Quadro 5000M" },
{ 0x10DE06DC, "Quadro 6000" },
{ 0x10DE06DE, "Tesla M2050" },// TODO: sub-device id: 0x0846
{ 0x10DE06DE, "Tesla M2070" },// TODO: sub-device id: ?
// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070
{ 0x10DE06DD, "Quadro 4000" },
// 0DC0 - 0DFF
{ 0x10DE0DC0, "GeForce GT 440" },
{ 0x10DE0DC1, "D12-P1-35" },
{ 0x10DE0DC2, "D12-P1-35" },
{ 0x10DE0DC5, "GeForce GTS 450" },
{ 0x10DE0DC6, "GeForce GTS 450" },
{ 0x10DE0DCA, "GF10x" },
// 0DD0 - 0DDF
{ 0x10DE0DD1, "GeForce GTX 460M" },
{ 0x10DE0DD2, "GeForce GT 445M" },
{ 0x10DE0DD3, "GeForce GT 435M" },
{ 0x10DE0DD8, "Quadro 2000" },
{ 0x10DE0DDE, "GF106-ES" },
{ 0x10DE0DDF, "GF106-INT" },
// 0DE0 - 0DEF
{ 0x10DE0DE1, "GeForce GT 430" },
{ 0x10DE0DE2, "GeForce GT 420" },
{ 0x10DE0DEB, "GeForce GT 555M" },
{ 0x10DE0DEE, "GeForce GT 415M" },
// 0DF0 - 0DFF
{ 0x10DE0DF0, "GeForce GT 425M" },
{ 0x10DE0DF1, "GeForce GT 420M" },
{ 0x10DE0DF2, "GeForce GT 435M" },
{ 0x10DE0DF8, "Quadro 600" },
{ 0x10DE0DFE, "GF108 ES" },
{ 0x10DE0DFF, "GF108 INT" },
// 0E00 - 0E0F
// 0E10 - 0E1F
// 0E20 - 0E2F
// 0E20 - 0E3F
{ 0x10DE0E21, "D12U-25" },
{ 0x10DE0E22, "GeForce GTX 460" },
{ 0x10DE0E23, "GeForce GTX 460 SE" },
{ 0x10DE0E24, "GeForce GTX 460" },
{ 0x10DE0E25, "D12U-50" },
// 0E30 - 0E3F
{ 0x10DE0E30, "GeForce GTX 470M" },
{ 0x10DE0E38, "GF104GL" },
{ 0x10DE0E3E, "GF104-ES" },
{ 0x10DE0E3F, "GF104-INT" },
// 0E40 - 0E4F
// 0E50 - 0E5F
// 0E60 - 0E6F
// 0E70 - 0E7F
// 0E80 - 0E8F
// 0E90 - 0E9F
// 0EA0 - 0EAF
// 0EB0 - 0EBF
// 0EC0 - 0ECF
// 0ED0 - 0EDF
// 0EE0 - 0EEF
// 0EF0 - 0EFF
// 0F00 - 0F0F
// 0F10 - 0F1F
// 0F20 - 0F2F
// 0F30 - 0F3F
// 0F40 - 0F4F
// 0F50 - 0F5F
// 0F60 - 0F6F
// 0F70 - 0F7F
// 0F80 - 0F8F
// 0F90 - 0F9F
// 0FA0 - 0FAF
// 0FB0 - 0FBF
// 0FC0 - 0FCF
// 0FD0 - 0FDF
// 0FE0 - 0FEF
// 0FF0 - 0FFF
// 1000 - 100F
// 1010 - 101F
// 1020 - 102F
// 1030 - 103F
// 1040 - 104F
// 1050 - 105F
// 1060 - 106F
// 1070 - 107F
// 1080 - 108F
// 0EE0 - 0EFF: none yet
// 0F00 - 0F3F: none yet
// 1040 - 107F: none yet
// 1080 - 109F
{ 0x10DE1080, "GeForce GTX 580" },
{ 0x10DE1081, "GeForce GTX 570" },
{ 0x10DE1081, "D13U" },
{ 0x10DE1082, "D13U" },
{ 0x10DE1083, "D13U" },
{ 0x10DE1088, "GeForce GTX 590" },
// 1090 - 109F
{ 0x10DE1098, "D13U" },
{ 0x10DE109A, "N12E-Q5" },
// 10A0 - 10AF
// 10B0 - 10BF
// 10C0 - 10CF
{ 0x10DE10C3, "GeForce 8400 GS" },
// 1200 -
{ 0x10DE1200, "GeForce GTX 560 Ti" }
};
static uint16_t swap16(uint16_t x)
unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)
{
unsigned long long vram_size = 0;
if (nvCardType < NV_ARCH_50) {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
}
else if (nvCardType >= NV_ARCH_C0) {
vram_size = REG32(NVC0_MEM_CTRLR_COUNT) << 20;
vram_size *= REG32(NVC0_MEM_CTRLR_RAM_AMOUNT);
}
else {
else if (nvCardType < NV_ARCH_C0) {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size |= (vram_size & 0xff) << 32;
vram_size &= 0xffffffff00ll;
}
// workaround code for gt 430 & 9600M GT
switch (nvda_dev->device_id)
{
case 0x0DE1: vram_size = 1024*1024*1024; break; // gt 430
case 0x0649: vram_size = 512*1024*1024; break; // 9600M GT
default: break;
else { // >= NV_ARCH_C0
vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;
vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);
}
return vram_size;
}
{
struct DevPropDevice*device;
char*devicepath;
struct pci_rom_pci_header_t*rom_pci_header;
option_rom_pci_header_t*rom_pci_header;
volatile uint8_t*regs;
uint8_t*rom;
uint8_t*nvRom;
if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {
printf("ERROR: nVidia ROM Patching Failed!\n");
return false;
//return false;
}
rom_pci_header = (struct pci_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);
rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);
// check for 'PCIR' sig
if (rom_pci_header->signature == 0x50434952) {
default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);
#endif
if (getValueForKey(kdcfg0, &value, &len, &bootInfo->bootConfig) && len == DCFG0_LEN * 2)
{
uint8_tnew_dcfg0[DCFG0_LEN];
if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)
{
verbose("Using user supplied @0,display-cfg\n");
memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);
}
}
#if DEBUG_dcfg0
printf("@0,display-cfg: %02x%02x%02x%02x\n",
default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3], default_dcfg_0[4]);
#endif
if (getValueForKey(kdcfg1, &value, &len, &bootInfo->bootConfig) && len == DCFG1_LEN * 2)
{
uint8_tnew_dcfg1[DCFG1_LEN];
if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)
{
verbose("Using user supplied @1,display-cfg\n");
memcpy(default_dcfg_1, new_d