Chameleon

Chameleon Commit Details

Date:2011-05-20 17:14:17 (12 years 10 months ago)
Author:MacMan
Commit:849
Parents: 848
Message:Reverting to trunk r833
Changes:
D/branches/Chimera/i386/libsaio/mem.c
D/branches/Chimera/i386/libsaio/mem.h
D/branches/Chimera/i386/libsaio/smbios_patcher.c
D/branches/Chimera/i386/libsaio/smbios_patcher.h
M/branches/Chimera/i386/libsaio/bootstruct.c
M/branches/Chimera/TODO
M/branches/Chimera/i386/Makefile
M/branches/Chimera/i386/libsaio/nvidia.c
M/branches/Chimera/i386/boot2/boot.h
M/branches/Chimera/i386/libsaio/pci.c
M/branches/Chimera/i386/libsaio/bootstruct.h
M/branches/Chimera/i386/libsaio/load.c
M/branches/Chimera/i386/libsaio/pci.h
M/branches/Chimera/i386/libsaio/acpi_patcher.c
M/branches/Chimera/i386/libsaio/platform.c
M/branches/Chimera/i386/libsaio/table.c
M/branches/Chimera/i386/util/Makefile
M/branches/Chimera/i386/libsaio/platform.h
M/branches/Chimera/i386/libsaio/Makefile
M/branches/Chimera/i386/boot1/Makefile
M/branches/Chimera/i386/doc/README
M/branches/Chimera/i386/libsaio/xml.c
M/branches/Chimera/i386/libsaio/SMBIOS.h
M/branches/Chimera/CREDITS
M/branches/Chimera/doc/BootHelp.txt
M/branches/Chimera/i386/libsa/Makefile
M/branches/Chimera/i386/libsaio/fdisk.h
M/branches/Chimera/i386/libsaio/xml.h
M/branches/Chimera/CHANGES
M/branches/Chimera/i386/libsaio/ati.c
M/branches/Chimera/i386/boot2/drivers.c
M/branches/Chimera/Makefile
M/branches/Chimera/i386/MakeInc.dir
M/branches/Chimera/i386/boot2/mboot.c
M/branches/Chimera/i386/cdboot/Makefile
M/branches/Chimera/i386/boot2/prompt.c
M/branches/Chimera/i386/libsaio/memvendors.h
M/branches/Chimera/i386/libsaio/saio_types.h
M/branches/Chimera/i386/libsa/memory.h
M/branches/Chimera/i386/libsaio/spd.c
M/branches/Chimera/i386/libsaio/cpu.c
M/branches/Chimera/i386/libsaio/md5c.c
M/branches/Chimera/i386/libsaio/fake_efi.c
M/branches/Chimera/version
M/branches/Chimera/i386/libsaio/pci_setup.c
M/branches/Chimera/i386/libsaio/cpu.h
M/branches/Chimera/i386/boot0/Makefile
M/branches/Chimera/i386/boot2/Makefile
M/branches/Chimera/revision
M/branches/Chimera/i386/boot2/boot.c

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branches/Chimera/i386/libsaio/smbios_patcher.c
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/*
* Copyright 2008 mackerintel
*/
#include "libsaio.h"
#include "boot.h"
#include "bootstruct.h"
#include "acpi.h"
#include "efi_tables.h"
#include "fake_efi.h"
#include "platform.h"
#include "smbios_patcher.h"
#include "pci.h"
#ifndef DEBUG_SMBIOS
#define DEBUG_SMBIOS 0
#endif
#if DEBUG_SMBIOS
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
typedef struct {
const char* key;
const char* value;
} SMStrEntryPair;
// defaults for a MacBook
static const SMStrEntryPair const sm_macbook_defaults[]={
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","MB41.88Z.00C1.B00.0802091535"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","MacBook4,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","MacBook"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F22788A9"},
{ "",""}
};
// defaults for a MacBook Pro
static const SMStrEntryPair const sm_macbookpro_defaults[]={
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","MBP41.88Z.00C1.B03.0802271651"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","MacBookPro4,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","MacBookPro"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F42C89C8"},
{ "",""}
};
// defaults for a Mac mini
static const SMStrEntryPair const sm_macmini_defaults[]={
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","MM21.88Z.009A.B00.0706281359"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","Macmini2,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","Napa Mac"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F4208EAA"},
{ "",""}
};
// defaults for an iMac
static const SMStrEntryPair const sm_imac_defaults[]={
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","IM81.88Z.00C1.B00.0802091538"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","iMac8,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","Mac"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F227BEC8"},
{ "",""}
};
// defaults for an iMac11,1 core i3/i5/i7
static const SMStrEntryPair const sm_imac_core_defaults[]={
{"SMbiosvendor","Apple Inc."},
{"SMbiosversion","IM111.88Z.0034.B00.0802091538"},
{"SMbiosdate","06/01/2009"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","iMac11,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","iMac"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F2268DAE"},
{ "",""}
};
// defaults for a Mac Pro 3,1 Xenon
static const SMStrEntryPair const sm_macpro_defaults[]={
{"SMbiosvendor","Apple Computer, Inc."},
{"SMbiosversion","MP31.88Z.006C.B05.0802291410"},
{"SMbiosdate","04/01/2008"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","MacPro3,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","MacPro"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F42C88C8"},
{ "",""}
};
// defaults for a Mac Pro 4,1 Core i7/Xeon
static const SMStrEntryPair const sm_macpro_core_defaults[]={
{"SMbiosvendor","Apple Computer, Inc."},
{"SMbiosversion","MP41.88Z.0081.B07.0903051113"},
{"SMbiosdate","11/06/2009"},
{"SMmanufacter","Apple Inc."},
{"SMproductname","MacPro4,1"},
{"SMsystemversion","1.0"},
{"SMserial","SOMESRLNMBR"},
{"SMfamily","MacPro"},
{"SMboardmanufacter","Apple Inc."},
{"SMboardproduct","Mac-F221BEC8"},
{ "",""}
};
static const char* sm_get_defstr(const char * key, int table_num)
{
inti;
const SMStrEntryPair*sm_defaults;
if (platformCPUFeature(CPU_FEATURE_MOBILE)) {
if (Platform.CPU.NoCores > 1) {
sm_defaults=sm_macbookpro_defaults;
} else {
sm_defaults=sm_macbook_defaults;
}
} else {
switch (Platform.CPU.NoCores)
{
case 1:
sm_defaults=sm_macmini_defaults;
break;
case 2:
sm_defaults=sm_imac_defaults;
break;
default:
{
switch (Platform.CPU.Family)
{
case 0x06:
{
switch (Platform.CPU.Model)
{
case CPU_MODEL_FIELDS:// Intel Core i5, i7 LGA1156 (45nm)
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)
case CPU_MODEL_SANDY_BRIDGE:// Intel Core i3, i5, i7 LGA1155 (32nm)
sm_defaults=sm_imac_core_defaults;
break;
case CPU_MODEL_NEHALEM:// Intel Core i7 LGA1366 (45nm)
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X7500
case CPU_MODEL_WESTMERE:// Intel Core i7 LGA13766 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
sm_defaults=sm_macpro_core_defaults;
break;
default:
sm_defaults=sm_macpro_defaults;
break;
}
break;
}
default:
sm_defaults=sm_macpro_defaults;
break;
}
break;
}
}
}
for (i=0; sm_defaults[i].key[0]; i++) {
if (!strcmp (sm_defaults[i].key, key)) {
return sm_defaults[i].value;
}
}
// Shouldn't happen
printf ("Error: no default for '%s' known\n", key);
sleep (2);
return "";
}
static int sm_get_fsb(const char *name, int table_num)
{
return Platform.CPU.FSBFrequency/1000000;
}
static int sm_get_cpu (const char *name, int table_num)
{
return Platform.CPU.CPUFrequency/1000000;
}
static int sm_get_bus_speed (const char *name, int table_num)
{
if (Platform.CPU.Vendor == 0x756E6547) // Intel
{
switch (Platform.CPU.Family)
{
case 0x06:
{
switch (Platform.CPU.Model)
{
case CPU_MODEL_YONAH:// Intel Mobile Core Solo, Duo
case CPU_MODEL_MEROM:// Intel Mobile Core 2 Solo, Duo
case CPU_MODEL_PENRYN:// Intel Core 2 Solo, Duo, Quad, Extreme
case CPU_MODEL_ATOM:// Intel Atom (45nm)
return 0;// TODO: populate bus speed for these processors
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
return 0;// Unknown
case CPU_MODEL_SANDY_BRIDGE:// Intel Core i3, i5, i7 LGA1155 (32nm)
return 4800;
case CPU_MODEL_NEHALEM:// Intel Core i7 LGA1366 (45nm)
case CPU_MODEL_FIELDS:// Intel Core i5, i7 LGA1156 (45nm)
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
case CPU_MODEL_WESTMERE:// Intel Core i7 LGA1366 (32nm) 6 Core
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X7500
{ // thanks to dgobe for i3/i5/i7 bus speed detection
int nhm_bus = 0x3F;
static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};
unsigned long did, vid;
int i;
// Nehalem supports Scrubbing
// First, locate the PCI bus where the MCH is located
for(i = 0; i < sizeof(possible_nhm_bus); i++)
{
vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);
did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);
vid &= 0xFFFF;
did &= 0xFF00;
if(vid == 0x8086 && did >= 0x2C00)
nhm_bus = possible_nhm_bus[i];
}
unsigned long qpimult, qpibusspeed;
qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);
DBG("FSBFrequency %d\n", Platform.CPU.FSBFrequency);
qpimult &= 0x7F;
DBG("qpimult %x\n", qpimult);
qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));
// Rek: rounding decimals to match original mac profile info
if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;
DBG("qpibusspeed %d\n", qpibusspeed);
return qpibusspeed;
}
}
}
}
}
return 0;
}
static int sm_get_simplecputype()
{
if (Platform.CPU.NoCores >= 4)
{
return 0x0501;// Quad-Core Intel Xeon
}
else if (Platform.CPU.NoCores == 1)
{
return 0x0201;// Core Solo
};
return 0x0301;// Core 2 Duo
}
static int sm_get_cputype (const char *name, int table_num)
{
static bool done = false;
if (Platform.CPU.Vendor == 0x756E6547) // Intel
{
if (!done) {
verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);
done = true;
}
switch (Platform.CPU.Family)
{
case 0x06:
{
switch (Platform.CPU.Model)
{
case CPU_MODEL_YONAH:// Intel Mobile Core Solo, Duo
case CPU_MODEL_MEROM:// Intel Mobile Core 2 Solo, Duo
case CPU_MODEL_PENRYN:// Intel Core 2 Solo, Duo, Quad, Extreme
case CPU_MODEL_ATOM:// Intel Atom (45nm)
return sm_get_simplecputype();
case CPU_MODEL_NEHALEM:// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
if (strstr(Platform.CPU.BrandString, "Xeon"))
return 0x501;// Quad-Core Intel Xeon
return 0x0701;// Core i7
case CPU_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
if (strstr(Platform.CPU.BrandString, "Xeon"))
return 0x501;// Quad-Core Intel Xeon
if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))
return 0x601;// Core i5
return 0x701;// Core i7
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))
return 0x901;// Core i3
if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))
return 0x601;// Core i5
return 0x0701;// Core i7
case CPU_MODEL_SANDY_BRIDGE: // Intel Core i3, i5, i7 LGA1155 (32nm)
if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))
return 0x901;// Core i3
if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))
return 0x601;// Core i5
return 0x0701;// Core i7
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx
case CPU_MODEL_WESTMERE:// Intel Core i7 LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7
if (strstr(Platform.CPU.BrandString, "Xeon"))
return 0x501;// Quad-Core Intel Xeon
return 0x0701;// Core i7
}
}
}
}
return sm_get_simplecputype();
}
static int sm_get_memtype (const char *name, int table_num)
{
intmap;
if (table_num < MAX_RAM_SLOTS) {
map = Platform.DMI.DIMM[table_num];
if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0) {
DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);
return Platform.RAM.DIMM[map].Type;
}
}
return SMB_MEM_TYPE_DDR2;
}
static int sm_get_memspeed (const char *name, int table_num)
{
intmap;
if (table_num < MAX_RAM_SLOTS) {
map = Platform.DMI.DIMM[table_num];
if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0) {
DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);
return Platform.RAM.DIMM[map].Frequency;
}
}
return 800;
}
static const char *sm_get_memvendor (const char *name, int table_num)
{
intmap;
if (table_num < MAX_RAM_SLOTS) {
map = Platform.DMI.DIMM[table_num];
if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0) {
DBG("RAM Detected Vendor[%d]='%s'\n", table_num, Platform.RAM.DIMM[map].Vendor);
return Platform.RAM.DIMM[map].Vendor;
}
}
return "N/A";
}
static const char *sm_get_memserial (const char *name, int table_num)
{
intmap;
if (table_num < MAX_RAM_SLOTS) {
map = Platform.DMI.DIMM[table_num];
if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0) {
DBG("name = %s, map=%d, RAM Detected SerialNo[%d]='%s'\n", name ? name : "",
map, table_num, Platform.RAM.DIMM[map].SerialNo);
return Platform.RAM.DIMM[map].SerialNo;
}
}
return "N/A";
}
static const char *sm_get_mempartno (const char *name, int table_num)
{
intmap;
if (table_num < MAX_RAM_SLOTS) {
map = Platform.DMI.DIMM[table_num];
if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0) {
DBG("Ram Detected PartNo[%d]='%s'\n", table_num, Platform.RAM.DIMM[map].PartNo);
return Platform.RAM.DIMM[map].PartNo;
}
}
return "N/A";
}
static int sm_one (int tablen)
{
return 1;
}
struct smbios_property smbios_properties[]=
{
{.name="SMbiosvendor",.table_type= 0,.value_type=SMSTRING,.offset=0x04,.auto_str=sm_get_defstr},
{.name="SMbiosversion",.table_type= 0,.value_type=SMSTRING,.offset=0x05,.auto_str=sm_get_defstr},
{.name="SMbiosdate",.table_type= 0,.value_type=SMSTRING,.offset=0x08,.auto_str=sm_get_defstr},
{.name="SMmanufacter",.table_type= 1,.value_type=SMSTRING,.offset=0x04,.auto_str=sm_get_defstr},
{.name="SMproductname",.table_type= 1,.value_type=SMSTRING,.offset=0x05,.auto_str=sm_get_defstr},
{.name="SMsystemversion",.table_type= 1,.value_type=SMSTRING,.offset=0x06,.auto_str=sm_get_defstr},
{.name="SMserial",.table_type= 1,.value_type=SMSTRING,.offset=0x07,.auto_str=sm_get_defstr},
{.name="SMUUID",.table_type= 1, .value_type=SMOWORD,.offset=0x08,.auto_oword=0},
{.name="SMfamily",.table_type= 1,.value_type=SMSTRING,.offset=0x1a,.auto_str=sm_get_defstr},
{.name="SMboardmanufacter",.table_type= 2, .value_type=SMSTRING,.offset=0x04,.auto_str=sm_get_defstr},
{.name="SMboardproduct",.table_type= 2, .value_type=SMSTRING,.offset=0x05,.auto_str=sm_get_defstr},
{.name="SMexternalclock",.table_type= 4,.value_type=SMWORD,.offset=0x12,.auto_int=sm_get_fsb},
{.name="SMmaximalclock",.table_type= 4,.value_type=SMWORD,.offset=0x14,.auto_int=sm_get_cpu},
{.name="SMmemdevloc",.table_type=17,.value_type=SMSTRING,.offset=0x10,.auto_str=0},
{.name="SMmembankloc",.table_type=17,.value_type=SMSTRING,.offset=0x11,.auto_str=0},
{.name="SMmemtype",.table_type=17,.value_type=SMBYTE,.offset=0x12,.auto_int=sm_get_memtype},
{.name="SMmemspeed",.table_type=17,.value_type=SMWORD,.offset=0x15,.auto_int=sm_get_memspeed},
{.name="SMmemmanufacter",.table_type=17,.value_type=SMSTRING,.offset=0x17,.auto_str=sm_get_memvendor},
{.name="SMmemserial",.table_type=17,.value_type=SMSTRING,.offset=0x18,.auto_str=sm_get_memserial},
{.name="SMmempart",.table_type=17,.value_type=SMSTRING,.offset=0x1A,.auto_str=sm_get_mempartno},
{.name="SMcputype",.table_type=131,.value_type=SMWORD,.offset=0x04,.auto_int=sm_get_cputype},
{.name="SMbusspeed",.table_type=132,.value_type=SMWORD,.offset=0x04,.auto_int=sm_get_bus_speed}
};
struct smbios_table_description smbios_table_descriptions[]=
{
{.type=0,.len=0x18,.numfunc=sm_one},
{.type=1,.len=0x1b,.numfunc=sm_one},
{.type=2,.len=0x0f,.numfunc=sm_one},
{.type=4,.len=0x2a,.numfunc=sm_one},
{.type=17,.len=0x1c,.numfunc=0},
{.type=131,.len=0x06,.numfunc=sm_one},
{.type=132,.len=0x06,.numfunc=sm_one}
};
// getting smbios addr with fast compare ops, late checksum testing ...
#define COMPARE_DWORD(a,b) ( *((u_int32_t *) a) == *((u_int32_t *) b) )
static const char * const SMTAG = "_SM_";
static const char* const DMITAG= "_DMI_";
static struct SMBEntryPoint *getAddressOfSmbiosTable(void)
{
struct SMBEntryPoint*smbios;
/*
* The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking
* for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").
*/
smbios = (struct SMBEntryPoint*) SMBIOS_RANGE_START;
while (smbios <= (struct SMBEntryPoint *)SMBIOS_RANGE_END) {
if (COMPARE_DWORD(smbios->anchor, SMTAG) &&
COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&
smbios->dmi.anchor[4]==DMITAG[4] &&
checksum8(smbios, sizeof(struct SMBEntryPoint)) == 0)
{
return smbios;
}
smbios = (struct SMBEntryPoint*) ( ((char*) smbios) + 16 );
}
printf("ERROR: Unable to find SMBIOS!\n");
pause();
return NULL;
}
/** Compute necessary space requirements for new smbios */
static struct SMBEntryPoint *smbios_dry_run(struct SMBEntryPoint *origsmbios)
{
struct SMBEntryPoint*ret;
char *smbiostables;
char *tablesptr;
int origsmbiosnum;
int i, j;
int tablespresent[256];
bool do_auto=true;
bzero(tablespresent, sizeof(tablespresent));
getBoolForKey(kSMBIOSdefaults, &do_auto, &bootInfo->bootConfig);
ret = (struct SMBEntryPoint *)AllocateKernelMemory(sizeof(struct SMBEntryPoint));
if (origsmbios) {
smbiostables = (char *)origsmbios->dmi.tableAddress;
origsmbiosnum = origsmbios->dmi.structureCount;
} else {
smbiostables = NULL;
origsmbiosnum = 0;
}
// _SM_
ret->anchor[0] = 0x5f;
ret->anchor[1] = 0x53;
ret->anchor[2] = 0x4d;
ret->anchor[3] = 0x5f;
ret->entryPointLength = sizeof(*ret);
ret->majorVersion = 2;
ret->minorVersion = 1;
ret->maxStructureSize = 0; // will be calculated later in this function
ret->entryPointRevision = 0;
for (i=0;i<5;i++) {
ret->formattedArea[i] = 0;
}
//_DMI_
ret->dmi.anchor[0] = 0x5f;
ret->dmi.anchor[1] = 0x44;
ret->dmi.anchor[2] = 0x4d;
ret->dmi.anchor[3] = 0x49;
ret->dmi.anchor[4] = 0x5f;
ret->dmi.tableLength = 0; // will be calculated later in this function
ret->dmi.tableAddress = 0; // will be initialized in smbios_real_run()
ret->dmi.structureCount = 0; // will be calculated later in this function
ret->dmi.bcdRevision = 0x21;
tablesptr = smbiostables;
// add stringlen of overrides to original stringlen, update maxStructure size adequately,
// update structure count and tablepresent[type] with count of type.
if (smbiostables) {
for (i=0; i<origsmbiosnum; i++) {
struct smbios_table_header*cur = (struct smbios_table_header *)tablesptr;
char*stringsptr;
intstringlen;
tablesptr += cur->length;
stringsptr = tablesptr;
for (; tablesptr[0]!=0 || tablesptr[1]!=0; tablesptr++);
tablesptr += 2;
stringlen = tablesptr - stringsptr - 1;
if (stringlen == 1) {
stringlen = 0;
}
for (j=0; j<sizeof(smbios_properties)/sizeof(smbios_properties[0]); j++) {
const char*str;
intsize;
charaltname[40];
sprintf(altname, "%s_%d",smbios_properties[j].name, tablespresent[cur->type] + 1);
if (smbios_properties[j].table_type == cur->type &&
smbios_properties[j].value_type == SMSTRING &&
(getValueForKey(smbios_properties[j].name, &str, &size, &bootInfo->smbiosConfig) ||
getValueForKey(altname,&str, &size, &bootInfo->smbiosConfig)))
{
stringlen += size + 1;
} else if (smbios_properties[j].table_type == cur->type &&
smbios_properties[j].value_type == SMSTRING &&
do_auto && smbios_properties[j].auto_str)
{
stringlen += strlen(smbios_properties[j].auto_str(smbios_properties[j].name, tablespresent[cur->type])) + 1;
}
}
if (stringlen == 0) {
stringlen = 1;
}
stringlen++;
if (ret->maxStructureSize < cur->length+stringlen) {
ret->maxStructureSize=cur->length+stringlen;
}
ret->dmi.tableLength += cur->length+stringlen;
ret->dmi.structureCount++;
tablespresent[cur->type]++;
}
}
// Add eventually table types whose detected count would be < required count, and update ret header with:
// new stringlen addons, structure count, and tablepresent[type] count adequately
for (i=0; i<sizeof(smbios_table_descriptions)/sizeof(smbios_table_descriptions[0]); i++) {
intnumnec=-1;
charbuffer[40];
sprintf(buffer, "SMtable%d", i);
if (!getIntForKey(buffer, &numnec, &bootInfo->smbiosConfig)) {
numnec = -1;
}
if (numnec==-1 && do_auto && smbios_table_descriptions[i].numfunc) {
numnec = smbios_table_descriptions[i].numfunc(smbios_table_descriptions[i].type);
}
while (tablespresent[smbios_table_descriptions[i].type] < numnec) {
intstringlen = 0;
for (j=0; j<sizeof(smbios_properties)/sizeof(smbios_properties[0]); j++) {
const char*str;
intsize;
charaltname[40];
sprintf(altname, "%s_%d",smbios_properties[j].name, tablespresent[smbios_table_descriptions[i].type] + 1);
if (smbios_properties[j].table_type == smbios_table_descriptions[i].type &&
smbios_properties[j].value_type == SMSTRING &&
(getValueForKey(altname, &str, &size, &bootInfo->smbiosConfig) ||
getValueForKey(smbios_properties[j].name, &str, &size, &bootInfo->smbiosConfig)))
{
stringlen += size + 1;
} else if (smbios_properties[j].table_type == smbios_table_descriptions[i].type &&
smbios_properties[j].value_type==SMSTRING &&
do_auto && smbios_properties[j].auto_str)
{
stringlen += strlen(smbios_properties[j].auto_str(smbios_properties[j].name, tablespresent[smbios_table_descriptions[i].type])) + 1;
}
}
if (stringlen == 0) {
stringlen = 1;
}
stringlen++;
if (ret->maxStructureSize < smbios_table_descriptions[i].len+stringlen) {
ret->maxStructureSize = smbios_table_descriptions[i].len + stringlen;
}
ret->dmi.tableLength += smbios_table_descriptions[i].len + stringlen;
ret->dmi.structureCount++;
tablespresent[smbios_table_descriptions[i].type]++;
}
}
return ret;
}
/** From the origsmbios detected by getAddressOfSmbiosTable() to newsmbios whose entrypoint
* struct has been created by smbios_dry_run, update each table struct content of new smbios
* int the new allocated table address of size newsmbios->tablelength.
*/
static void smbios_real_run(struct SMBEntryPoint * origsmbios, struct SMBEntryPoint * newsmbios)
{
char *smbiostables;
char *tablesptr, *newtablesptr;
int origsmbiosnum;
// bitmask of used handles
uint8_t handles[8192];
uint16_t nexthandle=0;
int i, j;
int tablespresent[256];
bool do_auto=true;
static bool done = false; // IMPROVEME: called twice via getSmbios(), but only the second call can get all necessary info !
extern void dumpPhysAddr(const char * title, void * a, int len);
bzero(tablespresent, sizeof(tablespresent));
bzero(handles, sizeof(handles));
getBoolForKey(kSMBIOSdefaults, &do_auto, &bootInfo->bootConfig);
newsmbios->dmi.tableAddress = (uint32_t)AllocateKernelMemory(newsmbios->dmi.tableLength);
if (origsmbios) {
smbiostables = (char *)origsmbios->dmi.tableAddress;
origsmbiosnum = origsmbios->dmi.structureCount;
} else {
smbiostables = NULL;
origsmbiosnum = 0;
}
tablesptr = smbiostables;
newtablesptr = (char *)newsmbios->dmi.tableAddress;
// if old smbios exists then update new smbios with old smbios original content first
if (smbiostables) {
for (i=0; i<origsmbiosnum; i++) {
struct smbios_table_header*oldcur = (struct smbios_table_header *) tablesptr;
struct smbios_table_header*newcur = (struct smbios_table_header *) newtablesptr;
char*stringsptr;
intnstrings = 0;
handles[(oldcur->handle) / 8] |= 1 << ((oldcur->handle) % 8);
// copy table length from old table to new table but not the old strings
memcpy(newcur,oldcur, oldcur->length);
tablesptr += oldcur->length;
stringsptr = tablesptr;
newtablesptr += oldcur->length;
// calculate the number of strings in the old content
for (;tablesptr[0]!=0 || tablesptr[1]!=0; tablesptr++) {
if (tablesptr[0] == 0) {
nstrings++;
}
}
if (tablesptr != stringsptr) {
nstrings++;
}
tablesptr += 2;
// copy the old strings to new table
memcpy(newtablesptr, stringsptr, tablesptr-stringsptr);
// point to next possible space for a string (deducting the second 0 char at the end)
newtablesptr += tablesptr - stringsptr - 1;
if (nstrings == 0) { // if no string was found rewind to the first 0 char of the 0,0 terminator
newtablesptr--;
}
// now for each property in the table update the overrides if any (auto or user)
for (j=0; j<sizeof(smbios_properties)/sizeof(smbios_properties[0]); j++) {
const char*str;
intsize;
intnum;
charaltname[40];
sprintf(altname, "%s_%d", smbios_properties[j].name, tablespresent[newcur->type] + 1);
if (smbios_properties[j].table_type == newcur->type) {
switch (smbios_properties[j].value_type) {
case SMSTRING:
if (getValueForKey(altname, &str, &size, &bootInfo->smbiosConfig) ||
getValueForKey(smbios_properties[j].name, &str, &size, &bootInfo->smbiosConfig))
{
memcpy(newtablesptr, str, size);
newtablesptr[size] = 0;
newtablesptr += size + 1;
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset)) = ++nstrings;
} else if (do_auto && smbios_properties[j].auto_str) {
str = smbios_properties[j].auto_str(smbios_properties[j].name, tablespresent[newcur->type]);
size = strlen(str);
memcpy(newtablesptr, str, size);
newtablesptr[size] = 0;
newtablesptr += size + 1;
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset)) = ++nstrings;
}
break;
case SMOWORD:
if (getValueForKey(altname, &str, &size, &bootInfo->smbiosConfig) ||
getValueForKey(smbios_properties[j].name, &str, &size, &bootInfo->smbiosConfig))
{
intk=0, t=0, kk=0;
const char*ptr = str;
memset(((char*)newcur) + smbios_properties[j].offset, 0, 16);
while (ptr-str<size && *ptr && (*ptr==' ' || *ptr=='\t' || *ptr=='\n')) {
ptr++;
}
if (size-(ptr-str)>=2 && ptr[0]=='0' && (ptr[1]=='x' || ptr[1]=='X')) {
ptr += 2;
}
for (;ptr-str<size && *ptr && k<16;ptr++) {
if (*ptr>='0' && *ptr<='9') {
(t=(t<<4)|(*ptr-'0')),kk++;
}
if (*ptr>='a' && *ptr<='f') {
(t=(t<<4)|(*ptr-'a'+10)),kk++;
}
if (*ptr>='A' && *ptr<='F') {
(t=(t<<4)|(*ptr-'A'+10)),kk++;
}
if (kk == 2) {
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset + k)) = t;
k++;
kk = 0;
t = 0;
}
}
}
break;
case SMBYTE:
if (getIntForKey(altname, &num, &bootInfo->smbiosConfig) ||
getIntForKey(smbios_properties[j].name, &num, &bootInfo->smbiosConfig))
{
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset)) = num;
} else if (do_auto && smbios_properties[j].auto_int) {
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset)) = smbios_properties[j].auto_int(smbios_properties[j].name, tablespresent[newcur->type]);
}
break;
case SMWORD:
if (getIntForKey(altname, &num, &bootInfo->smbiosConfig) ||
getIntForKey(smbios_properties[j].name, &num, &bootInfo->smbiosConfig))
{
*((uint16_t*)(((char*)newcur) + smbios_properties[j].offset)) = num;
} else if (do_auto && smbios_properties[j].auto_int) {
*((uint16_t*)(((char*)newcur) + smbios_properties[j].offset)) = smbios_properties[j].auto_int(smbios_properties[j].name, tablespresent[newcur->type]);
}
break;
}
}
}
if (nstrings == 0) {
newtablesptr[0] = 0;
newtablesptr++;
}
newtablesptr[0] = 0;
newtablesptr++;
tablespresent[newcur->type]++;
}
}
// for each eventual complementary table not present in the original smbios, do the overrides
for (i=0; i<sizeof(smbios_table_descriptions)/sizeof(smbios_table_descriptions[0]); i++) {
intnumnec = -1;
charbuffer[40];
sprintf(buffer, "SMtable%d", i);
if (!getIntForKey(buffer, &numnec, &bootInfo->smbiosConfig)) {
numnec = -1;
}
if (numnec == -1 && do_auto && smbios_table_descriptions[i].numfunc) {
numnec = smbios_table_descriptions[i].numfunc(smbios_table_descriptions[i].type);
}
while (tablespresent[smbios_table_descriptions[i].type] < numnec) {
struct smbios_table_header*newcur = (struct smbios_table_header *) newtablesptr;
intnstrings = 0;
memset(newcur,0, smbios_table_descriptions[i].len);
while (handles[(nexthandle)/8] & (1 << ((nexthandle) % 8))) {
nexthandle++;
}
newcur->handle = nexthandle;
handles[nexthandle / 8] |= 1 << (nexthandle % 8);
newcur->type = smbios_table_descriptions[i].type;
newcur->length = smbios_table_descriptions[i].len;
newtablesptr += smbios_table_descriptions[i].len;
for (j=0; j<sizeof(smbios_properties)/sizeof(smbios_properties[0]); j++) {
const char*str;
intsize;
intnum;
charaltname[40];
sprintf(altname, "%s_%d", smbios_properties[j].name, tablespresent[newcur->type] + 1);
if (smbios_properties[j].table_type == newcur->type) {
switch (smbios_properties[j].value_type) {
case SMSTRING:
if (getValueForKey(altname, &str, &size, &bootInfo->smbiosConfig) ||
getValueForKey(smbios_properties[j].name, &str, &size, &bootInfo->smbiosConfig))
{
memcpy(newtablesptr, str, size);
newtablesptr[size] = 0;
newtablesptr += size + 1;
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset)) = ++nstrings;
} else if (do_auto && smbios_properties[j].auto_str) {
str = smbios_properties[j].auto_str(smbios_properties[j].name, tablespresent[newcur->type]);
size = strlen(str);
memcpy(newtablesptr, str, size);
newtablesptr[size] = 0;
newtablesptr += size + 1;
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset)) = ++nstrings;
}
break;
case SMOWORD:
if (getValueForKey(altname, &str, &size, &bootInfo->smbiosConfig) ||
getValueForKey(smbios_properties[j].name, &str, &size, &bootInfo->smbiosConfig))
{
intk=0, t=0, kk=0;
const char*ptr = str;
memset(((char*)newcur) + smbios_properties[j].offset, 0, 16);
while (ptr-str<size && *ptr && (*ptr==' ' || *ptr=='\t' || *ptr=='\n')) {
ptr++;
}
if (size-(ptr-str)>=2 && ptr[0]=='0' && (ptr[1]=='x' || ptr[1]=='X')) {
ptr += 2;
}
for (;ptr-str<size && *ptr && k<16;ptr++) {
if (*ptr>='0' && *ptr<='9') {
(t=(t<<4)|(*ptr-'0')),kk++;
}
if (*ptr>='a' && *ptr<='f') {
(t=(t<<4)|(*ptr-'a'+10)),kk++;
}
if (*ptr>='A' && *ptr<='F') {
(t=(t<<4)|(*ptr-'A'+10)),kk++;
}
if (kk == 2) {
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset + k)) = t;
k++;
kk = 0;
t = 0;
}
}
}
break;
case SMBYTE:
if (getIntForKey(altname, &num, &bootInfo->smbiosConfig) ||
getIntForKey(smbios_properties[j].name, &num, &bootInfo->smbiosConfig))
{
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset)) = num;
} else if (do_auto && smbios_properties[j].auto_int) {
*((uint8_t*)(((char*)newcur) + smbios_properties[j].offset)) = smbios_properties[j].auto_int(smbios_properties[j].name, tablespresent[newcur->type]);
}
break;
case SMWORD:
if (getIntForKey(altname, &num, &bootInfo->smbiosConfig) ||
getIntForKey(smbios_properties[j].name, &num, &bootInfo->smbiosConfig))
{
*((uint16_t*)(((char*)newcur) + smbios_properties[j].offset)) = num;
} else if (do_auto && smbios_properties[j].auto_int) {
*((uint16_t*)(((char*)newcur)+smbios_properties[j].offset)) = smbios_properties[j].auto_int(smbios_properties[j].name, tablespresent[newcur->type]);
}
break;
}
}
}
if (nstrings == 0) {
newtablesptr[0] = 0;
newtablesptr++;
}
newtablesptr[0] = 0;
newtablesptr++;
tablespresent[smbios_table_descriptions[i].type]++;
}
}
// calculate new checksums
newsmbios->dmi.checksum = 0;
newsmbios->dmi.checksum = 256 - checksum8(&newsmbios->dmi, sizeof(newsmbios->dmi));
newsmbios->checksum = 0;
newsmbios->checksum = 256 - checksum8(newsmbios, sizeof(*newsmbios));
if (!done) {
verbose("Patched DMI Table\n");
done=true;
}
}
#define MAX_DMI_TABLES 128 //Thanks Andy
typedef struct DmiNumAssocTag {
struct DMIHeader * dmi;
uint8_t type;
} DmiNumAssoc;
static DmiNumAssoc DmiTablePair[MAX_DMI_TABLES];
static int DmiTablePairCount = 0;
static int current_pos=0;
static bool ftTablePairInit = true;
/**
* Get a table structure entry from a type specification and a smbios address
* return NULL if table is not found
*/
static void getSmbiosTableStructure(struct SMBEntryPoint *smbios)
{
struct DMIHeader * dmihdr=NULL;
SMBByte* p;
int i;
if (ftTablePairInit && smbios!=NULL) {
ftTablePairInit = false;
#if DEBUG_SMBIOS
printf(">>> SMBIOSAddr=0x%08x\n", smbios);
printf(">>> DMI: addr=0x%08x, len=%d, count=%d\n", smbios->dmi.tableAddress,
smbios->dmi.tableLength, smbios->dmi.structureCount);
#endif
p = (SMBByte *) smbios->dmi.tableAddress;
for (i=0;
i < smbios->dmi.structureCount &&
p + 4 <= (SMBByte *)smbios->dmi.tableAddress + smbios->dmi.tableLength;
i++) {
dmihdr = (struct DMIHeader *) p;
#if DEBUG_SMBIOS
printf(">>>>>> DMI(%d): type=0x%02x, len=0x%d\n",i,dmihdr->type,dmihdr->length);
#endif
if (dmihdr->length < 4 || dmihdr->type == 127 /* EOT */) break;
if (DmiTablePairCount < MAX_DMI_TABLES) {
DmiTablePair[DmiTablePairCount].dmi = dmihdr;
DmiTablePair[DmiTablePairCount].type = dmihdr->type;
DmiTablePairCount++;
}
else {
printf("DMI table entries list is full! Next entries won't be stored.\n");
}
#if DEBUG_SMBIOS
printf("DMI header found for table type %d, length = %d\n", dmihdr->type, dmihdr->length);
#endif
p = p + dmihdr->length;
while ((p - (SMBByte *)smbios->dmi.tableAddress + 1 < smbios->dmi.tableLength) && (p[0] != 0x00 || p[1] != 0x00)) {
p++;
}
p += 2;
}
}
}
/** Get original or new smbios entry point, if sucessful, the adresses are cached for next time */
struct SMBEntryPoint *getSmbios(int which)
{
static struct SMBEntryPoint *orig = NULL; // cached
static struct SMBEntryPoint *patched = NULL; // cached
// whatever we are called with orig or new flag, initialize asap both structures
switch (which) {
case SMBIOS_ORIGINAL:
if (orig==NULL) {
orig = getAddressOfSmbiosTable();
getSmbiosTableStructure(orig); // generate tables entry list for fast table finding
}
return orig;
case SMBIOS_PATCHED:
if (orig==NULL && (orig = getAddressOfSmbiosTable())==NULL ) {
printf("Could not find original SMBIOS !!\n");
pause();
} else {
patched = smbios_dry_run(orig);
if(patched==NULL) {
printf("Could not create new SMBIOS !!\n");
pause();
}
else {
smbios_real_run(orig, patched);
}
}
return patched;
default:
printf("ERROR: invalid option for getSmbios() !!\n");
break;
}
return NULL;
}
/** Find first original dmi Table with a particular type */
struct DMIHeader* FindFirstDmiTableOfType(int type, int minlength)
{
current_pos = 0;
return FindNextDmiTableOfType(type, minlength);
};
/** Find next original dmi Table with a particular type */
struct DMIHeader* FindNextDmiTableOfType(int type, int minlength)
{
int i;
if (ftTablePairInit) getSmbios(SMBIOS_ORIGINAL);
for (i=current_pos; i < DmiTablePairCount; i++) {
if (type == DmiTablePair[i].type &&
DmiTablePair[i].dmi &&
DmiTablePair[i].dmi->length >= minlength ) {
current_pos = i+1;
return DmiTablePair[i].dmi;
}
}
return NULL; // not found
};
branches/Chimera/i386/libsaio/smbios_patcher.h
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/*
* Copyright 2008 mackerintel
*/
/*
* AsereBLN: cleanup
*/
#ifndef __LIBSAIO_SMBIOS_PATCHER_H
#define __LIBSAIO_SMBIOS_PATCHER_H
#include "libsaio.h"
#include "SMBIOS.h"
/* From Foundation/Efi/Guid/Smbios/SmBios.h */
/* Modified to wrap Data4 array init with {} */
#define EFI_SMBIOS_TABLE_GUID {0xeb9d2d31, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}}
#define SMBIOS_RANGE_START 0x000F0000
#define SMBIOS_RANGE_END 0x000FFFFF
#define SMBIOS_ORIGINAL0
#define SMBIOS_PATCHED1
struct smbios_table_header
{
uint8_ttype;
uint8_tlength;
uint16_thandle;
} __attribute__ ((packed));
struct smbios_property
{
const char*name;
uint8_ttable_type;
enum {SMSTRING, SMWORD, SMBYTE, SMOWORD} value_type;
intoffset;
int(*auto_int) (const char *name, int table_num);
const char*(*auto_str) (const char *name, int table_num);
const char*(*auto_oword) (const char *name, int table_num);
};
struct smbios_table_description
{
uint8_ttype;
intlen;
int(*numfunc)(int tablen);
};
/** call with flag SMBIOS_ORIGINAL to get orig. entrypoint
or call with flag SMBIOS_PATCHED to get patched smbios entrypoint
*/
extern struct SMBEntryPoint*getSmbios(int);
extern struct DMIHeader* FindNextDmiTableOfType(int type, int minlen);
extern struct DMIHeader* FindFirstDmiTableOfType(int type, int minlen);
#endif /* !__LIBSAIO_SMBIOS_PATCHER_H */
branches/Chimera/i386/libsaio/mem.c
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/*
* Copyright 2010 AsereBLN. All rights reserved. <aserebln@googlemail.com>
*
* mem.c - obtain system memory information
*/
#include "libsaio.h"
#include "pci.h"
#include "platform.h"
#include "cpu.h"
#include "mem.h"
#include "smbios_patcher.h"
#ifndef DEBUG_MEM
#define DEBUG_MEM 0
#endif
#if DEBUG_MEM
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
#define DC(c) (c >= 0x20 && c < 0x7f ? (char) c : '.')
#define STEP 16
void dumpPhysAddr(const char * title, void * a, int len)
{
int i,j;
u_int8_t* ad = (u_int8_t*) a;
char buffer[80];
char str[16];
if(ad==NULL) return;
printf("%s addr=0x%08x len=%04d\n",title ? title : "Dump of ", a, len);
printf("Ofs-00-01-02-03-04-05-06-07-08-09-0A-0B-0C-0D-0E-0F ASCII\n");
i = (len/STEP)*STEP;
for (j=0; j < i; j+=STEP)
{
printf("%02x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %c%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c\n",
j,
ad[j], ad[j+1], ad[j+2], ad[j+3] , ad[j+4], ad[j+5], ad[j+6], ad[j+7],
ad[j+8], ad[j+9], ad[j+10], ad[j+11] , ad[j+12], ad[j+13], ad[j+14], ad[j+15],
DC(ad[j]), DC(ad[j+1]), DC(ad[j+2]), DC(ad[j+3]) , DC(ad[j+4]), DC(ad[j+5]), DC(ad[j+6]), DC(ad[j+7]),
DC(ad[j+8]), DC(ad[j+9]), DC(ad[j+10]), DC(ad[j+11]) , DC(ad[j+12]), DC(ad[j+13]), DC(ad[j+14]), DC(ad[j+15])
);
}
if (len%STEP==0) return;
sprintf(buffer,"%02x:", i);
for (j=0; j < STEP; j++) {
if (j<(len%STEP))
sprintf(str, " %02x", ad[i+j]);
else
strcpy(str, " " );
strncat(buffer, str, sizeof(buffer));
}
strncat(buffer," ", sizeof(buffer));
for (j=0; j < (len%STEP); j++) {
sprintf(str, "%c", DC(ad[i+j]));
strncat(buffer, str, sizeof(buffer));
}
printf("%s\n",buffer);
}
void dumpAllTablesOfType(int i)
{
char title[32];
struct DMIHeader * dmihdr;
for(dmihdr = FindFirstDmiTableOfType(i, 4);
dmihdr;
dmihdr = FindNextDmiTableOfType(i, 4)) {
sprintf(title,"Table (type %d) :" , i);
dumpPhysAddr(title, dmihdr, dmihdr->length+32);
}
}
const char * getDMIString(struct DMIHeader * dmihdr, uint8_t strNum)
{
const char * ret =NULL;
const char * startAddr = (const char *) dmihdr;
const char * limit = NULL;
if (!dmihdr || dmihdr->length<4 || strNum==0) return NULL;
startAddr += dmihdr->length;
limit = startAddr + 256;
for(; strNum; strNum--) {
if ((*startAddr)==0 && *(startAddr+1)==0) break;
if (*startAddr && strNum<=1) {
ret = startAddr; // current str
break;
}
while(*startAddr && startAddr<limit) startAddr++;
if (startAddr==limit) break; // no terminator found
else if((*startAddr==0) && *(startAddr+1)==0) break;
else startAddr++;
}
return ret;
}
void scan_memory(PlatformInfo_t *p)
{
int i=0;
struct DMIHeader * dmihdr = NULL;
struct DMIMemoryModuleInfo* memInfo[MAX_RAM_SLOTS]; // 6
struct DMIPhysicalMemoryArray* physMemArray; // 16
struct DMIMemoryDevice* memDev[MAX_RAM_SLOTS]; //17
/* We mainly don't use obsolete tables 5,6 because most of computers don't handle it anymore */
Platform.DMI.MemoryModules = 0;
/* Now lets peek info rom table 16,17 as for some bios, table 5 & 6 are not used */
physMemArray = (struct DMIPhysicalMemoryArray*) FindFirstDmiTableOfType(16, 4);
Platform.DMI.MaxMemorySlots = physMemArray ? physMemArray->numberOfMemoryDevices : 0;
i = 0;
for(dmihdr = FindFirstDmiTableOfType(17, 4);
dmihdr;
dmihdr = FindNextDmiTableOfType(17, 4) ) {
memDev[i] = (struct DMIMemoryDevice*) dmihdr;
if (memDev[i]->size !=0 ) Platform.DMI.MemoryModules++;
if (memDev[i]->speed>0) Platform.RAM.DIMM[i].Frequency = memDev[i]->speed; // take it here for now but we'll check spd and dmi table 6 as well
i++;
}
// for table 6, we only have a look at the current speed
i = 0;
for(dmihdr = FindFirstDmiTableOfType(6, 4);
dmihdr;
dmihdr = FindNextDmiTableOfType(6, 4) ) {
memInfo[i] = (struct DMIMemoryModuleInfo*) dmihdr;
if (memInfo[i]->currentSpeed > Platform.RAM.DIMM[i].Frequency)
Platform.RAM.DIMM[i].Frequency = memInfo[i]->currentSpeed; // favor real overclocked speed if any
i++;
}
#if 0
dumpAllTablesOfType(17);
getc();
#endif
}
branches/Chimera/i386/libsaio/mem.h
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/*
* Copyright 2010 AsereBLN. All rights reserved. <aserebln@googlemail.com>
*
* mem.h
*/
#ifndef __LIBSAIO_MEM_H
#define __LIBSAIO_MEM_H
#include "platform.h"
extern void scan_memory(PlatformInfo_t *);
#endif/* __LIBSAIO_MEM_H */
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#include "sl.h"
#include "xml.h"
string_ref *ref_strings = NULL;
/// TODO: remove below
static char* buffer_start = NULL;
// TODO: redo the next two functions
void SaveRefString(char* string, int id)
{
//printf("Adding Ref String %d (%s)\n", id, string);
string_ref* tmp = ref_strings;
while(tmp)
{
if(tmp->id == id)
{
tmp->string = malloc(strlen(string)+1);
sprintf(tmp->string, "%s", string);
return;
}
tmp = tmp->next;
}
string_ref* new_ref = malloc(sizeof(string_ref));
new_ref->string = malloc(strlen(string)+1);
sprintf(new_ref->string, "%s", string);
new_ref->id = id;
new_ref->next = ref_strings;
ref_strings = new_ref;
}
char* GetRefString(int id)
{
string_ref* tmp = ref_strings;
while(tmp)
{
if(tmp->id == id) return tmp->string;
tmp = tmp->next;
}
//verbose("Unable to locate Ref String %d\n", id);
return "";
}
struct Module {
struct Module *nextModule;
long willLoad;
unsigned long signature1;
unsigned long signature2;
unsigned long length;
unsigned long alder32;
unsigned long adler32;
unsigned long version;
unsigned long numDrivers;
unsigned long reserved1;
return 0;
}
// XMLGetTag(int index)
// XMLTagCount( TagPtr dict )
int XMLTagCount( TagPtr dict )
{
int count = 0;
TagPtr tagList, tag;
if (dict->type != kTagTypeDict && dict->type != kTagTypeArray) return 0;
tag = 0;
tagList = dict->tag;
while (tagList)
{
tag = tagList;
tagList = tag->tagNext;
if (((tag->type != kTagTypeKey) && ((tag->string == 0) || (tag->string[0] == 0)))
&& (dict->type != kTagTypeArray)// If we are an array, any element is valid
) continue;
if(tag->type == kTagTypeKey) printf("Located key %s\n", tag->string);
count++;
}
return count;
}
TagPtr XMLGetElement( TagPtr dict, int id )
{
if(dict->type != kTagTypeArray) return 0;
int element = 0;
TagPtr tmp = dict->tag;
while(element < id)
{
element++;
tmp = tmp->tagNext;
}
return tmp;
}
/* Function for basic XML character entities parsing */
char*
return out;
}
#if UNUSED
//#if UNUSED
//==========================================================================
// XMLParseFile
// Expects to see one dictionary in the XML file.
// Expects to see one dictionary in the XML file, the final pos will be returned
// If the pos is not equal to the strlen, then there are multiple dicts
// Puts the first dictionary it finds in the
// tag pointer and returns 0, or returns -1 if not found.
// tag pointer and returns the end of the dic, or returns -1 if not found.
//
long
XMLParseFile( char * buffer, TagPtr * dict )
long length, pos;
TagPtr tag;
pos = 0;
char *configBuffer;
configBuffer = malloc(strlen(buffer)+1);
strcpy(configBuffer, buffer);
buffer_start = configBuffer;
while (1)
{
length = XMLParseNextTag(buffer + pos, &tag);
length = XMLParseNextTag(configBuffer + pos, &tag);
if (length == -1) break;
pos += length;
XMLFreeTag(tag);
}
if (length < 0) {
free(configBuffer);
if (length < 0) {
return -1;
}
*dict = tag;
return 0;
return pos;
}
#endif /* UNUSED */
//#endif /* UNUSED */
//==========================================================================
// ParseNextTag
// TODO: cleanup
long
XMLParseNextTag( char * buffer, TagPtr * tag )
{
length = GetNextTag(buffer, &tagName, 0);
if (length == -1) return -1;
pos = length;
if (!strncmp(tagName, kXMLTagPList, 6))
{
length = 0;
}
/***** dict ****/
else if (!strcmp(tagName, kXMLTagDict))
{
length = ParseTagList(buffer + pos, tag, kTagTypeDict, 0);
}
else if (!strcmp(tagName, kXMLTagDict "/"))
else if (!strncmp(tagName, kXMLTagDict, strlen(kXMLTagDict)) && tagName[strlen(tagName)-1] == '/')
{
length = ParseTagList(buffer + pos, tag, kTagTypeDict, 1);
}
else if (!strncmp(tagName, kXMLTagDict " ", strlen(kXMLTagDict " ")))
{
length = ParseTagList(buffer + pos, tag, kTagTypeDict, 0);
}
/***** key ****/
else if (!strcmp(tagName, kXMLTagKey))
{
length = ParseTagKey(buffer + pos, tag);
}
/***** string ****/
else if (!strcmp(tagName, kXMLTagString))
{
length = ParseTagString(buffer + pos, tag);
}
else if (!strncmp(tagName, kXMLTagString " ", strlen(kXMLTagString " ")))
{
// TODO: save tag if if found
if(!strncmp(tagName + strlen(kXMLTagString " "), kXMLStringID, strlen(kXMLStringID)))
{
// ID=
int id = 0;
int cnt = strlen(kXMLTagString " " kXMLStringID "\"") + 1;
while ((tagName[cnt] != '\0') && (tagName[cnt] != '"')) cnt++;
tagName[cnt] = 0;
char* val = tagName + strlen(kXMLTagString " " kXMLStringID "\"");
while(*val)
{
if ((*val >= '0' && *val <= '9'))// 0 - 9
{
id = (id * 10) + (*val++ - '0');
}
else
{
printf("ParseStringID error (0x%x)\n", *val);
getc();
return -1;
}
}
length = ParseTagString(buffer + pos, tag);
SaveRefString(buffer + pos, id);
}
else if(!strncmp(tagName + strlen(kXMLTagString " "), kXMLStringIDRef, strlen(kXMLStringIDRef)))
{
// IDREF=
int id = 0;
int cnt = strlen(kXMLTagString " " kXMLStringIDRef "\"") + 1;
while ((tagName[cnt] != '\0') && (tagName[cnt] != '"')) cnt++;
tagName[cnt] = 0;
char* val = tagName + strlen(kXMLTagString " " kXMLStringIDRef "\"");
while(*val)
{
if ((*val >= '0' && *val <= '9'))// 0 - 9
{
id = (id * 10) + (*val++ - '0');
}
else
{
printf("ParseStringIDREF error (0x%x)\n", *val);
getc();
return -1;
}
}
char* str = GetRefString(id);
TagPtr tmpTag = NewTag();
tmpTag->type = kTagTypeString;
tmpTag->string = str;
tmpTag->tag = 0;
tmpTag->tagNext = 0;
tmpTag->offset = buffer_start ? buffer - buffer_start + pos : 0;
*tag = tmpTag;
length = 0;
//printf("Located IDREF, id = %d, string = %s\n", id, str);
}
}
/***** integer ****/
else if (!strcmp(tagName, kXMLTagInteger))
{
length = ParseTagInteger(buffer + pos, tag);
}
else if (!strncmp(tagName, kXMLTagInteger " ", strlen(kXMLTagInteger " ")))
{
if(!strncmp(tagName + strlen(kXMLTagInteger " "), kXMLStringID, strlen(kXMLStringID)))
{
// ID=
int id = 0;
int cnt = strlen(kXMLTagInteger " " kXMLStringID "\"") + 1;
while ((tagName[cnt] != '\0') && (tagName[cnt] != '"')) cnt++;
tagName[cnt] = 0;
char* val = tagName + strlen(kXMLTagInteger " " kXMLStringID "\"");
while(*val)
{
if ((*val >= '0' && *val <= '9'))// 0 - 9
{
id = (id * 10) + (*val++ - '0');
}
else
{
printf("ParseIntegerID error (0x%x)\n", *val);
getc();
return -1;
}
}
length = ParseTagInteger(buffer + pos, tag);
SaveRefString((*tag)->string, id);
}
else if(!strncmp(tagName + strlen(kXMLTagInteger " "), kXMLStringIDRef, strlen(kXMLStringIDRef)))
{
// IDREF=
int id = 0;
int cnt = strlen(kXMLTagInteger " " kXMLStringIDRef "\"") + 1;
while ((tagName[cnt] != '\0') && (tagName[cnt] != '"')) cnt++;
tagName[cnt] = 0;
char* val = tagName + strlen(kXMLTagInteger " " kXMLStringIDRef "\"");
while(*val)
{
if ((*val >= '0' && *val <= '9'))// 0 - 9
{
id = (id * 10) + (*val++ - '0');
}
else
{
printf("ParseStringIDREF error (0x%x)\n", *val);
getc();
return -1;
}
}
int integer = (int)GetRefString(id);
TagPtr tmpTag = NewTag();
tmpTag->type = kTagTypeInteger;
tmpTag->string = (char*) integer;
tmpTag->tag = 0;
tmpTag->tagNext = 0;
tmpTag->offset = buffer_start ? buffer - buffer_start + pos : 0;
*tag = tmpTag;
length = 0;
//printf("Located IDREF, id = %d, string = %s\n", id, str);
}
else
{
length = ParseTagInteger(buffer + pos, tag);
}
}
/***** data ****/
else if (!strcmp(tagName, kXMLTagData))
{
length = ParseTagData(buffer + pos, tag);
}
else if (!strncmp(tagName, kXMLTagData " ", strlen(kXMLTagData " ")))
{
length = ParseTagData(buffer + pos, tag);
}
else if (!strcmp(tagName, kXMLTagDate))
{
length = ParseTagDate(buffer + pos, tag);
}
/***** date ****/
else if (!strncmp(tagName, kXMLTagDate " ", strlen(kXMLTagDate " ")))
{
length = ParseTagDate(buffer + pos, tag);
}
/***** false ****/
else if (!strcmp(tagName, kXMLTagFalse))
{
length = ParseTagBoolean(buffer + pos, tag, kTagTypeFalse);
}
/***** true ****/
else if (!strcmp(tagName, kXMLTagTrue))
{
length = ParseTagBoolean(buffer + pos, tag, kTagTypeTrue);
}
/***** array ****/
else if (!strcmp(tagName, kXMLTagArray))
{
length = ParseTagList(buffer + pos, tag, kTagTypeArray, 0);
}
else if (!strncmp(tagName, kXMLTagArray " ", strlen(kXMLTagArray " ")))
{
length = ParseTagList(buffer + pos, tag, kTagTypeArray, 0);
}
else if (!strcmp(tagName, kXMLTagArray "/"))
{
length = ParseTagList(buffer + pos, tag, kTagTypeArray, 1);
}
/***** unknown ****/
else
{
*tag = 0;
length = 0;
}
if (length == -1) return -1;
return pos + length;
tmpTag->type = type;
tmpTag->string = 0;
tmpTag->offset = buffer_start ? buffer - buffer_start : 0;
tmpTag->tag = tagList;
tmpTag->tagNext = 0;
tmpTag->type = kTagTypeKey;
tmpTag->string = string;
tmpTag->tag = subTag;
tmpTag->offset = buffer_start ? buffer - buffer_start: 0;
tmpTag->tagNext = 0;
*tag = tmpTag;
{
long length;
char * string;
TagPtr tmpTag;
length = FixDataMatchingTag(buffer, kXMLTagString);
if (length == -1) return -1;
tmpTag = NewTag();
TagPtr tmpTag = NewTag();
if (tmpTag == 0) return -1;
string = NewSymbol(buffer);
tmpTag->type = kTagTypeString;
tmpTag->string = string;
tmpTag->tag = 0;
tmpTag->offset = buffer_start ? buffer - buffer_start: 0;
tmpTag->tagNext = 0;
*tag = tmpTag;
ParseTagInteger( char * buffer, TagPtr * tag )
{
long length, integer;
bool negative = false;
TagPtr tmpTag;
length = FixDataMatchingTag(buffer, kXMLTagInteger);
char* val = buffer;
int size;
if(buffer[0] == '<')
{
printf("Warning integer is non existant\n");
getc();
tmpTag = NewTag();
tmpTag->type = kTagTypeInteger;
tmpTag->string = 0;
tmpTag->tag = 0;
tmpTag->offset = 0;
tmpTag->tagNext = 0;
*tag = tmpTag;
return 0;
}
size = length = FixDataMatchingTag(buffer, kXMLTagInteger);
if (length == -1) return -1;
tmpTag = NewTag();
if (tmpTag == 0) return -1;
integer = 0;
if(size > 1 && (val[1] == 'x' || val[1] == 'X'))// Hex value
{
val += 2;
while(*val)
{
if ((*val >= '0' && *val <= '9'))// 0 - 9
{
integer = (integer * 16) + (*val++ - '0');
}
else if ((*val >= 'a' && *val <= 'f'))// a - f
{
integer = (integer * 16) + (*val++ - 'a' + 10);
}
else if ((*val >= 'A' && *val <= 'F'))// A - F
{
integer = (integer * 16) + (*val++ - 'a' + 10);
}
else
{
printf("ParseTagInteger hex error (0x%x) in buffer %s\n", *val, buffer);
getc();
return -1;
}
}
}
else if ( size )// Decimal value
{
if (*val == '-')
{
negative = true;
val++;
size--;
}
for (integer = 0; size > 0; size--)
{
if(*val) // UGLY HACK, fix me.
{
if (*val < '0' || *val > '9')
{
printf("ParseTagInteger decimal error (0x%x) in buffer %s\n", *val, buffer);
getc();
return -1;
}
integer = (integer * 10) + (*val++ - '0');
}
}
if (negative)
integer = -integer;
}
tmpTag->type = kTagTypeInteger;
tmpTag->string = (char *)integer;
tmpTag->tag = 0;
tmpTag->string = (char *)integer;
tmpTag->tag = 0;
tmpTag->offset = buffer_start ? buffer - buffer_start: 0;
tmpTag->tagNext = 0;
*tag = tmpTag;
return length;
}
{
long length;
TagPtr tmpTag;
length = FixDataMatchingTag(buffer, kXMLTagData);
if (length == -1) return -1;
tmpTag = NewTag();
if (tmpTag == 0) return -1;
//printf("ParseTagData unimplimented\n");
//printf("Data: %s\n", buffer);
//getc();
// TODO: base64 decode
char* string = NewSymbol(buffer);
tmpTag->type = kTagTypeData;
tmpTag->string = 0;
tmpTag->string = string;
tmpTag->tag = 0;
tmpTag->offset = buffer_start ? buffer - buffer_start: 0;
tmpTag->tagNext = 0;
*tag = tmpTag;
tmpTag = NewTag();
if (tmpTag == 0) return -1;
printf("ParseTagDate unimplimented\n");
getc();
tmpTag->type = kTagTypeDate;
tmpTag->string = 0;
tmpTag->tag = 0;
tmpTag->offset = buffer_start ? buffer - buffer_start: 0;
tmpTag->tagNext = 0;
*tag = tmpTag;
tmpTag->type = type;
tmpTag->string = 0;
tmpTag->tag = 0;
tmpTag->offset = buffer_start ? buffer - buffer_start: 0;
tmpTag->tagNext = 0;
*tag = tmpTag;
tag->type = kTagTypeNone;
tag->string = 0;
tag->tag = 0;
tag->offset = 0;
tag->tagNext = gTagsFree;
gTagsFree = tag;
#else
return symbol;
}
bool XMLIsType(TagPtr dict, enum xmltype type)
{
if(!dict) return (type == kTagTypeNone);
return (dict->type == type);
}
/*** Cast functions ***/
TagPtr XMLCastArray(TagPtr dict)
{
if(!dict) return NULL;
if(dict->type == kTagTypeArray) return dict;
else return NULL;
}
TagPtr XMLCastDict(TagPtr dict)
{
if(!dict) return NULL;
if(dict->type == kTagTypeDict) return dict;
else return NULL;
}
char* XMLCastString(TagPtr dict)
{
if(!dict) return NULL;
if((dict->type == kTagTypeString) ||
(dict->type == kTagTypeKey)) return dict->string;
return NULL;
}
long XMLCastStringOffset(TagPtr dict)
{
if(dict &&
((dict->type == kTagTypeString) ||
(dict->type == kTagTypeKey)))
{
return dict->offset;
}
else
{
return -1;
}
}
bool XMLCastBoolean(TagPtr dict)
{
if(!dict) return false;
if(dict->type == kTagTypeTrue) return true;
return false;
}
int XMLCastInteger(TagPtr dict)
{
if(!dict)
{
printf("XMLCastInteger: null dict\n");
return 0;
}
if(dict->type == kTagTypeInteger) return (int)(dict->string);
return 0;
}
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#ifndef __LIBSAIO_XML_H
#define __LIBSAIO_XML_H
enum {
enum xmltype {
kTagTypeNone = 0,
kTagTypeDict,
kTagTypeKey,
kTagTypeArray
};
struct string_ref
{
char* string;
int id;
struct string_ref* next;
};
typedef struct string_ref string_ref;
extern string_ref* ref_strings;
#define kXMLTagPList "plist "
#define kXMLTagDict "dict"
#define kXMLTagKey "key"
#define kXMLTagTrue "true/"
#define kXMLTagArray "array"
#define kXMLStringID"ID="
#define kXMLStringIDRef "IDREF="
#define kPropCFBundleIdentifier ("CFBundleIdentifier")
#define kPropCFBundleExecutable ("CFBundleExecutable")
#define kPropOSBundleRequired ("OSBundleRequired")
extern long gImageLastKernelAddr;
TagPtr XMLGetProperty( TagPtr dict, const char * key );
TagPtr XMLGetElement( TagPtr dict, int id );
int XMLTagCount( TagPtr dict );
bool XMLIsType(TagPtr dict, enum xmltype type);
bool XMLCastBoolean( TagPtr dict );
char* XMLCastString( TagPtr dict );
long XMLCastStringOffset(TagPtr dict);
int XMLCastInteger ( TagPtr dict );
TagPtr XMLCastDict ( TagPtr dict );
TagPtr XMLCastArray( TagPtr dict );
long XMLParseNextTag(char *buffer, TagPtr *tag);
void XMLFreeTag(TagPtr tag);
char* XMLDecode(const char *in);
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bootArgsPreLion->Version = kBootArgsPreLionVersion;
bootArgsPreLion->Revision = kBootArgsPreLionRevision;
init_done = 1;
}
bootArgsPreLion = (boot_args_pre_lion *)AllocateKernelMemory(sizeof(boot_args_pre_lion));
bcopy(oldAddr, bootArgsPreLion, sizeof(boot_args_pre_lion));
}
}
void
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char * configEnd; // pointer to end of config files
char config[CONFIG_SIZE];
config_file_t bootConfig; // boot.plist
config_file_t bootConfig; // boot.plist
config_file_t overrideConfig; // additional boot.plist which can override bootConfig keys
config_file_t themeConfig; // theme.plist
config_file_t smbiosConfig; // smbios.plist
config_file_t themeConfig; // theme.plist
config_file_t smbiosConfig; // smbios.plist
config_file_t helperConfig; // boot helper partition's boot.plist
config_file_t ramdiskConfig; // RAMDisk.plist
} PrivateBootInfo_t;
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{
switch (Platform.CPU.Model)
{
case CPU_MODEL_YONAH:// Intel Mobile Core Solo, Duo
case CPU_MODEL_MEROM:// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx
case CPU_MODEL_PENRYN:// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx
case CPU_MODEL_ATOM:// Intel Atom (45nm)
case 0x0D: // ?
case CPU_MODEL_YONAH: // Yonah
case CPU_MODEL_MEROM: // Merom
case CPU_MODEL_PENRYN: // Penryn
case CPU_MODEL_ATOM: // Intel Atom (45nm)
{
bool cpu_dynamic_fsb = false;
break;
}
case CPU_MODEL_FIELDS:// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
case CPU_MODEL_FIELDS:
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM:// Intel Core i3, i5 LGA1156 (32nm)
case CPU_MODEL_NEHALEM:// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
case CPU_MODEL_NEHALEM_EX:// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx
case CPU_MODEL_SANDY_BRIDGE:// Intel Core i3, i5, i7, Xeon E3 LGA1155 (32nm)
case CPU_MODEL_WESTMERE:// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_WESTMERE_EX:// Intel Xeon E7
case CPU_MODEL_DALES_32NM:
case CPU_MODEL_NEHALEM:
case CPU_MODEL_NEHALEM_EX:
case CPU_MODEL_WESTMERE:
case CPU_MODEL_WESTMERE_EX:
case CPU_MODEL_SANDY:
case CPU_MODEL_SANDY_XEON:
{
maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; // Seems it always contains maximum multiplier value (with turbo, that's we need)...
minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff;
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#include "pci.h"
#include "platform.h"
#include "spd.h"
#include "cpu.h"
#include "saio_internal.h"
#include "bootstruct.h"
#include "memvendors.h"
#if DEBUG_SPD
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#define DBG(x...)msglog(x)
#endif
static const char *spd_memory_types[] =
{
"RAM",/* 00h Undefined */
"FPM",/* 01h FPM */
"EDO",/* 02h EDO */
"",/* 03h PIPELINE NIBBLE */
"SDRAM",/* 04h SDRAM */
"",/* 05h MULTIPLEXED ROM */
"DDR SGRAM",/* 06h SGRAM DDR */
"DDR SDRAM",/* 07h SDRAM DDR */
"DDR2 SDRAM",/* 08h SDRAM DDR 2 */
"",/* 09h Undefined */
"",/* 0Ah Undefined */
"DDR3 SDRAM"/* 0Bh SDRAM DDR 3 */
"RAM", /* 00h Undefined */
"FPM", /* 01h FPM */
"EDO", /* 02h EDO */
"",/* 03h PIPELINE NIBBLE */
"SDRAM", /* 04h SDRAM */
"",/* 05h MULTIPLEXED ROM */
"DDR SGRAM",/* 06h SGRAM DDR */
"DDR SDRAM",/* 07h SDRAM DDR */
"DDR2 SDRAM", /* 08h SDRAM DDR 2 */
"",/* 09h Undefined */
"",/* 0Ah Undefined */
"DDR3 SDRAM" /* 0Bh SDRAM DDR 3 */
};
#define UNKNOWN_MEM_TYPE 2
static uint8_t spd_mem_to_smbios[] =
{
UNKNOWN_MEM_TYPE,/* 00h Undefined */
UNKNOWN_MEM_TYPE,/* 01h FPM */
UNKNOWN_MEM_TYPE,/* 02h EDO */
UNKNOWN_MEM_TYPE,/* 03h PIPELINE NIBBLE */
SMB_MEM_TYPE_SDRAM,/* 04h SDRAM */
SMB_MEM_TYPE_ROM,/* 05h MULTIPLEXED ROM */
SMB_MEM_TYPE_SGRAM,/* 06h SGRAM DDR */
SMB_MEM_TYPE_DDR,/* 07h SDRAM DDR */
SMB_MEM_TYPE_DDR2,/* 08h SDRAM DDR 2 */
UNKNOWN_MEM_TYPE,/* 09h Undefined */
UNKNOWN_MEM_TYPE,/* 0Ah Undefined */
SMB_MEM_TYPE_DDR3/* 0Bh SDRAM DDR 3 */
UNKNOWN_MEM_TYPE, /* 00h Undefined */
UNKNOWN_MEM_TYPE, /* 01h FPM */
UNKNOWN_MEM_TYPE, /* 02h EDO */
UNKNOWN_MEM_TYPE, /* 03h PIPELINE NIBBLE */
SMB_MEM_TYPE_SDRAM, /* 04h SDRAM */
SMB_MEM_TYPE_ROM, /* 05h MULTIPLEXED ROM */
SMB_MEM_TYPE_SGRAM, /* 06h SGRAM DDR */
SMB_MEM_TYPE_DDR, /* 07h SDRAM DDR */
SMB_MEM_TYPE_DDR2, /* 08h SDRAM DDR 2 */
UNKNOWN_MEM_TYPE, /* 09h Undefined */
UNKNOWN_MEM_TYPE, /* 0Ah Undefined */
SMB_MEM_TYPE_DDR3 /* 0Bh SDRAM DDR 3 */
};
#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))
outb(base + SMBHSTSTS, 0x1f);// reset SMBus Controller
outb(base + SMBHSTDAT, 0xff);
while( inb(base + SMBHSTSTS) & 0x01);// wait until ready
rdtsc(l1, h1);
while ( inb(base + SMBHSTSTS) & 0x01) // wait until read
{
rdtsc(l2, h2);
t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);
if (t > 5)
return 0xFF; // break
}
outb(base + SMBHSTCMD, cmd);
outb(base + SMBHSTADD, (adr << 1) | 0x01 );
}
return strdup(asciiPartNo);
return NULL;
}
int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};
{
int i, speed;
uint8_t spd_size, spd_type;
uint32_t base;
uint32_t base, mmio, hostc;
bool dump = false;
RamSlotInfo_t* slot;
uint16_t cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);
DBG("SMBus CmdReg: 0x%x\n", cmd);
pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);
mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;
base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;
DBG("Scanning smbus_dev <%04x, %04x> ...\n",smbus_dev->vendor_id, smbus_dev->device_id);
hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);
verbose("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n",
smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);
getBoolForKey("DumpSPD", &dump, &bootInfo->bootConfig);
bool fullBanks = // needed at least for laptops
Platform.DMI.MemoryModules == Platform.DMI.MaxMemorySlots;
// Search MAX_RAM_SLOTS slots
char spdbuf[256];
// needed at least for laptops
bool fullBanks = Platform.DMI.MemoryModules == Platform.DMI.CntMemorySlots;
char spdbuf[MAX_SPD_SIZE];
// Search MAX_RAM_SLOTS slots
for (i = 0; i < MAX_RAM_SLOTS; i++){
slot = &Platform.RAM.DIMM[i];
spd_size = smb_read_byte_intel(base, 0x50 + i, 0);
DBG("SPD[0] (size): %d @0x%x\n", spd_size, 0x50 + i);
// Check spd is present
if (spd_size && (spd_size != 0xff) ) {
if (spd_size && (spd_size != 0xff))
{
slot->spd = spdbuf;
slot->InUse = true;
//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);
init_spd(slot->spd, base, i);
switch (slot->spd[SPD_MEMORY_TYPE]) {
case SPD_MEMORY_TYPE_SDRAM_DDR2:
}
slot->Frequency = freq;
}
verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n",
i,
(int)slot->Type,
slot->Vendor,
slot->PartNo,
slot->SerialNo);
if(DEBUG_SPD) {
dumpPhysAddr("spd content: ",slot->spd, spd_size);
#if DEBUG_SPD
dumpPhysAddr("spd content: ", slot->spd, spd_size);
getc();
}
#endif
}
// laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:
Platform.DMI.DIMM[i]=
i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.MaxMemorySlots==2 ?
i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.CntMemorySlots == 2 ?
mapping[i] : i; // for laptops case, mapping setup would need to be more generic than this
slot->spd = NULL;
static struct smbus_controllers_t smbus_controllers[] = {
{0x8086, 0x269B, "ESB2", read_smb_intel },
{0x8086, 0x25A4, "6300ESB", read_smb_intel },
{0x8086, 0x24C3, "ICH4", read_smb_intel },
{0x8086, 0x24D3, "ICH5", read_smb_intel },
{0x8086, 0x266A, "ICH6", read_smb_intel },
{0x8086, 0x27DA, "ICH7", read_smb_intel },
{0x8086, 0x283E, "ICH8", read_smb_intel },
{0x8086, 0x2930, "ICH9", read_smb_intel },
{0x8086, 0x3A30, "ICH10R", read_smb_intel },
{0x8086, 0x3A60, "ICH10B", read_smb_intel },
{0x8086, 0x3B30, "5 Series", read_smb_intel },
{0x8086, 0x1C22, "6 Series", read_smb_intel },
{0x8086, 0x5032, "EP80579", read_smb_intel }
{0x8086, 0x269B, "ESB2", read_smb_intel },
{0x8086, 0x25A4, "6300ESB", read_smb_intel },
{0x8086, 0x24C3, "ICH4", read_smb_intel },
{0x8086, 0x24D3, "ICH5", read_smb_intel },
{0x8086, 0x266A, "ICH6", read_smb_intel },
{0x8086, 0x27DA, "ICH7", read_smb_intel },
{0x8086, 0x283E, "ICH8", read_smb_intel },
{0x8086, 0x2930, "ICH9", read_smb_intel },
{0x8086, 0x3A30, "ICH10R", read_smb_intel },
{0x8086, 0x3A60, "ICH10B", read_smb_intel },
{0x8086, 0x3B30, "P55", read_smb_intel },
{0x8086, 0x5032, "EP80579", read_smb_intel }
};
{
find_and_read_smbus_controller(root_pci_dev);
}
branches/Chimera/i386/libsaio/Makefile
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vbe.o nbp.o hfs.o hfs_compare.o \
xml.o ntfs.o msdos.o md5c.o device_tree.o \
cpu.o platform.o acpi_patcher.o \
smbios_patcher.o fake_efi.o ext2fs.o \
smbios.o smbios_getters.o smbios_decode.o \
fake_efi.o ext2fs.o \
hpet.o dram_controllers.o spd.o usb.o pci_setup.o \
device_inject.o nvidia.o ati.o pci_root.o \
convert.o mem.o aml_generator.o
convert.o aml_generator.o
SAIO_EXTERN_OBJS = console.o
#ranlib $(SYMROOT)/$@
libsaio.a: $(SAIO_EXTERN_OBJS) $(SAIO_OBJS)
rm -f $(SYMROOT)/$(@F)
ar q $(SYMROOT)/$(@F) $^
ranlib $(SYMROOT)/$(@F)
@echo "\t[RM] $(SYMROOT)/$(@F)"
@rm -f $(SYMROOT)/$(@F)
@echo "\t[AR] $@"
@ar q $(SYMROOT)/$(@F) $^ &> /dev/null
@echo "\t[RANLIB] $@"
@ranlib $(SYMROOT)/$(@F)
#saio_internal.h: saio_external.h
#saio_table.c: saio_external.h
#saio_defs.h: saio_external.h
branches/Chimera/i386/libsaio/SMBIOS.h
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/*
* Copyright (c) 1998-2006 Apple Computer, Inc. All rights reserved.
* Copyright (c) 1998-2009 Apple Computer, Inc. All rights reserved.
*
* @APPLE_LICENSE_HEADER_START@
*
* @APPLE_LICENSE_HEADER_END@
*/
/* This file is a stripped-down version of the one found in the AppleSMBIOS project.
* Changes:
* - Don't use pragma pack but instead use GCC's packed attribute
*/
#ifndef __LIBSAIO_SMBIOS_H
#define __LIBSAIO_SMBIOS_H
#ifndef _LIBSAIO_SMBIOS_H
#define _LIBSAIO_SMBIOS_H
//
// Based on System Management BIOS Reference Specification v2.5
//
/*
* Based on System Management BIOS Reference Specification v2.5
*/
typedef uint8_t SMBString;
typedef uint8_t SMBByte;
typedef uint16_t SMBWord;
typedef uint32_t SMBDWord;
typedef uint64_t SMBQWord;
typedef uint8_tSMBString;
typedef uint8_tSMBByte;
typedef uint16_tSMBWord;
typedef uint32_tSMBDWord;
typedef uint64_tSMBQWord;
struct DMIHeader {
SMBBytetype;
SMBBytelength;
SMBWordhandle;
} __attribute__((packed));
typedef struct DMIEntryPoint {
SMBByte anchor[5];
SMBByte checksum;
SMBWord tableLength;
SMBDWord tableAddress;
SMBWord structureCount;
SMBByte bcdRevision;
} __attribute__((packed)) DMIEntryPoint;
struct DMIEntryPoint {
SMBByteanchor[5];
SMBBytechecksum;
SMBWordtableLength;
SMBDWordtableAddress;
SMBWordstructureCount;
SMBBytebcdRevision;
} __attribute__((packed));
typedef struct SMBEntryPoint {
SMBByte anchor[4];
SMBByte checksum;
SMBByte entryPointLength;
SMBByte majorVersion;
SMBByte minorVersion;
SMBWord maxStructureSize;
SMBByte entryPointRevision;
SMBByte formattedArea[5];
DMIEntryPoint dmi;
} __attribute__((packed)) SMBEntryPoint;
struct SMBEntryPoint {
SMBByteanchor[4];
SMBBytechecksum;
SMBByteentryPointLength;
SMBBytemajorVersion;
SMBByteminorVersion;
SMBWordmaxStructureSize;
SMBByteentryPointRevision;
SMBByteformattedArea[5];
struct DMIEntryPointdmi;
} __attribute__((packed));
//
// Header common to all SMBIOS structures
//
struct DMIMemoryControllerInfo {/* 3.3.6 Memory Controller Information (Type 5) */
struct DMIHeaderdmiHeader;
SMBByteerrorDetectingMethod;
SMBByteerrorCorrectingCapability;
SMBBytesupportedInterleave;
SMBBytecurrentInterleave;
SMBBytemaxMemoryModuleSize;
SMBWordsupportedSpeeds;
SMBWordsupportedMemoryTypes;
SMBBytememoryModuleVoltage;
SMBBytenumberOfMemorySlots;
} __attribute__((packed));
typedef struct SMBStructHeader {
SMBByte type;
SMBByte length;
SMBWord handle;
} __attribute__((packed)) SMBStructHeader;
struct DMIMemoryModuleInfo {/* 3.3.7 Memory Module Information (Type 6) */
struct DMIHeaderdmiHeader;
SMBBytesocketDesignation;
SMBBytebankConnections;
SMBBytecurrentSpeed;
SMBWordcurrentMemoryType;
SMBByteinstalledSize;
SMBByteenabledSize;
SMBByteerrorStatus;
} __attribute__((packed));
#define SMB_STRUCT_HEADER SMBStructHeader header;
struct DMIPhysicalMemoryArray {/* 3.3.17 Physical Memory Array (Type 16) */
struct DMIHeaderdmiHeader;
SMBBytelocation;
SMBByteuse;
SMBBytememoryCorrectionError;
SMBDWordmaximumCapacity;
SMBWordmemoryErrorInformationHandle;
SMBWordnumberOfMemoryDevices;
} __attribute__((packed));
typedef struct SMBAnchor
{
const SMBStructHeader *header;
const uint8_t *next;
const uint8_t *end;
} SMBAnchor;
struct DMIMemoryDevice {/* 3.3.18 Memory Device (Type 17) */
struct DMIHeaderdmiHeader;
SMBWordphysicalMemoryArrayHandle;
SMBWordmemoryErrorInformationHandle;
SMBWordtotalWidth;
SMBWorddataWidth;
SMBWordsize;
SMBByteformFactor;
SMBBytedeviceSet;
SMBBytedeviceLocator;
SMBBytebankLocator;
SMBBytememoryType;
SMBWordtypeDetail;
SMBWord speed;
} __attribute__((packed));
#define SMB_ANCHOR_IS_VALID(x)\
((x) && ((x)->header) && ((x)->next) && ((x)->end))
#endif /* !_LIBSAIO_SMBIOS_H */
#define SMB_ANCHOR_RESET(x)\
bzero(x, sizeof(typedef struct SMBAnchor));
//
// SMBIOS structure types.
//
enum {
kSMBTypeBIOSInformation = 0,
kSMBTypeSystemInformation = 1,
kSMBTypeBaseBoard= 2,
kSMBTypeSystemEnclosure = 3,
kSMBTypeProcessorInformation = 4,
kSMBTypeMemoryModule = 6,
kSMBTypeCacheInformation = 7,
kSMBTypeSystemSlot = 9,
kSMBTypePhysicalMemoryArray = 16,
kSMBTypeMemoryDevice = 17,
kSMBType32BitMemoryErrorInfo = 18,
kSMBType64BitMemoryErrorInfo = 33,
kSMBTypeEndOfTable = 127,
/* Apple Specific Structures */
kSMBTypeFirmwareVolume = 128,
kSMBTypeMemorySPD = 130,
kSMBTypeOemProcessorType = 131,
kSMBTypeOemProcessorBusSpeed = 132
};
//
// BIOS Information (Type 0)
//
typedef struct SMBBIOSInformation {
SMB_STRUCT_HEADER // Type 0
SMBString vendor; // BIOS vendor name
SMBString version; // BIOS version
SMBWord startSegment; // BIOS segment start
SMBString releaseDate; // BIOS release date
SMBByte romSize; // (n); 64K * (n+1) bytes
SMBQWord characteristics; // supported BIOS functions
} __attribute__((packed)) SMBBIOSInformation;
//
// System Information (Type 1)
//
typedef struct SMBSystemInformation {
// 2.0+ spec (8 bytes)
SMB_STRUCT_HEADER // Type 1
SMBString manufacturer;
SMBString productName;
SMBString version;
SMBString serialNumber;
// 2.1+ spec (25 bytes)
SMBByte uuid[16]; // can be all 0 or all 1's
SMBByte wakeupReason; // reason for system wakeup
// 2.4+ spec (27 bytes)
SMBString skuNumber;
SMBString family;
} __attribute__((packed)) SMBSystemInformation;
//
// Base Board (Type 2)
//
typedef struct SMBBaseBoard {
SMB_STRUCT_HEADER // Type 2
SMBStringmanufacturer;
SMBStringproduct;
SMBStringversion;
SMBStringserialNumber;
SMBStringassetTagNumber;
SMBBytefeatureFlags;
SMBStringlocationInChassis;
SMBWordchassisHandle;
SMBByteboardType;
SMBBytenumberOfContainedHandles;
// 0 - 255 contained handles go here but we do not include
// them in our structure. Be careful to use numberOfContainedHandles
// times sizeof(SMBWord) when computing the actual record size,
// if you need it.
} __attribute__((packed)) SMBBaseBoard;
// Values for boardType in Type 2 records
enum {
kSMBBaseBoardUnknown= 0x01,
kSMBBaseBoardOther= 0x02,
kSMBBaseBoardServerBlade= 0x03,
kSMBBaseBoardConnectivitySwitch= 0x04,
kSMBBaseBoardSystemMgmtModule= 0x05,
kSMBBaseBoardProcessorModule= 0x06,
kSMBBaseBoardIOModule= 0x07,
kSMBBaseBoardMemoryModule= 0x08,
kSMBBaseBoardDaughter= 0x09,
kSMBBaseBoardMotherboard= 0x0A,
kSMBBaseBoardProcessorMemoryModule= 0x0B,
kSMBBaseBoardProcessorIOModule= 0x0C,
kSMBBaseBoardInterconnect= 0x0D,
};
//
// System Enclosure (Type 3)
//
typedef struct SMBSystemEnclosure {
SMB_STRUCT_HEADER // Type 3
SMBString manufacturer;
SMBByte type;
SMBString version;
SMBString serialNumber;
SMBString assetTagNumber;
SMBByte bootupState;
SMBByte powerSupplyState;
SMBByte thermalState;
SMBByte securityStatus;
SMBDWord oemDefined;
} __attribute__((packed)) SMBSystemEnclosure;
//
// Processor Information (Type 4)
//
typedef struct SMBProcessorInformation {
// 2.0+ spec (26 bytes)
SMB_STRUCT_HEADER // Type 4
SMBString socketDesignation;
SMBByte processorType; // CPU = 3
SMBByte processorFamily; // processor family enum
SMBString manufacturer;
SMBQWord processorID; // based on CPUID
SMBString processorVersion;
SMBByte voltage; // bit7 cleared indicate legacy mode
SMBWord externalClock; // external clock in MHz
SMBWord maximumClock; // max internal clock in MHz
SMBWord currentClock; // current internal clock in MHz
SMBByte status;
SMBByte processorUpgrade; // processor upgrade enum
// 2.1+ spec (32 bytes)
SMBWord L1CacheHandle;
SMBWord L2CacheHandle;
SMBWord L3CacheHandle;
// 2.3+ spec (35 bytes)
SMBString serialNumber;
SMBString assetTag;
SMBString partNumber;
} __attribute__((packed)) SMBProcessorInformation;
#define kSMBProcessorInformationMinSize 26
//
// Memory Module Information (Type 6)
// Obsoleted since SMBIOS version 2.1
//
typedef struct SMBMemoryModule {
SMB_STRUCT_HEADER // Type 6
SMBString socketDesignation;
SMBByte bankConnections;
SMBByte currentSpeed;
SMBWord currentMemoryType;
SMBByte installedSize;
SMBByte enabledSize;
SMBByte errorStatus;
} __attribute__((packed)) SMBMemoryModule;
#define kSMBMemoryModuleSizeNotDeterminable 0x7D
#define kSMBMemoryModuleSizeNotEnabled 0x7E
#define kSMBMemoryModuleSizeNotInstalled 0x7F
//
// Cache Information (Type 7)
//
typedef struct SMBCacheInformation {
SMB_STRUCT_HEADER // Type 7
SMBString socketDesignation;
SMBWord cacheConfiguration;
SMBWord maximumCacheSize;
SMBWord installedSize;
SMBWord supportedSRAMType;
SMBWord currentSRAMType;
SMBByte cacheSpeed;
SMBByte errorCorrectionType;
SMBByte systemCacheType;
SMBByte associativity;
} __attribute__((packed)) SMBCacheInformation;
typedef struct SMBSystemSlot {
// 2.0+ spec (12 bytes)
SMB_STRUCT_HEADER // Type 9
SMBString slotDesignation;
SMBByte slotType;
SMBByte slotDataBusWidth;
SMBByte currentUsage;
SMBByte slotLength;
SMBWord slotID;
SMBByte slotCharacteristics1;
// 2.1+ spec (13 bytes)
SMBByte slotCharacteristics2;
} __attribute__((packed)) SMBSystemSlot;
//
// Physical Memory Array (Type 16)
//
typedef struct SMBPhysicalMemoryArray {
// 2.1+ spec (15 bytes)
SMB_STRUCT_HEADER // Type 16
SMBByte physicalLocation; // physical location
SMBByte arrayUse; // the use for the memory array
SMBByte errorCorrection; // error correction/detection method
SMBDWord maximumCapacity; // maximum memory capacity in kilobytes
SMBWord errorHandle; // handle of a previously detected error
SMBWord numMemoryDevices; // number of memory slots or sockets
} __attribute__((packed)) SMBPhysicalMemoryArray;
// Memory Array - Use
enum {
kSMBMemoryArrayUseOther = 0x01,
kSMBMemoryArrayUseUnknown = 0x02,
kSMBMemoryArrayUseSystemMemory = 0x03,
kSMBMemoryArrayUseVideoMemory = 0x04,
kSMBMemoryArrayUseFlashMemory = 0x05,
kSMBMemoryArrayUseNonVolatileMemory = 0x06,
kSMBMemoryArrayUseCacheMemory = 0x07
};
// Memory Array - Error Correction Types
enum {
kSMBMemoryArrayErrorCorrectionTypeOther = 0x01,
kSMBMemoryArrayErrorCorrectionTypeUnknown = 0x02,
kSMBMemoryArrayErrorCorrectionTypeNone = 0x03,
kSMBMemoryArrayErrorCorrectionTypeParity = 0x04,
kSMBMemoryArrayErrorCorrectionTypeSingleBitECC = 0x05,
kSMBMemoryArrayErrorCorrectionTypeMultiBitECC = 0x06,
kSMBMemoryArrayErrorCorrectionTypeCRC = 0x07
};
//
// Memory Device (Type 17)
//
typedef struct SMBMemoryDevice {
// 2.1+ spec (21 bytes)
SMB_STRUCT_HEADER // Type 17
SMBWord arrayHandle; // handle of the parent memory array
SMBWord errorHandle; // handle of a previously detected error
SMBWord totalWidth; // total width in bits; including ECC bits
SMBWord dataWidth; // data width in bits
SMBWord memorySize; // bit15 is scale, 0 = MB, 1 = KB
SMBByte formFactor; // memory device form factor
SMBByte deviceSet; // parent set of identical memory devices
SMBString deviceLocator; // labeled socket; e.g. "SIMM 3"
SMBString bankLocator; // labeled bank; e.g. "Bank 0" or "A"
SMBByte memoryType; // type of memory
SMBWord memoryTypeDetail; // additional detail on memory type
// 2.3+ spec (27 bytes)
SMBWord memorySpeed; // speed of device in MHz (0 for unknown)
SMBString manufacturer;
SMBString serialNumber;
SMBString assetTag;
SMBString partNumber;
} __attribute__((packed)) SMBMemoryDevice;
//
// Firmware Volume Description (Apple Specific - Type 128)
//
enum {
FW_REGION_RESERVED = 0,
FW_REGION_RECOVERY = 1,
FW_REGION_MAIN = 2,
FW_REGION_NVRAM = 3,
FW_REGION_CONFIG = 4,
FW_REGION_DIAGVAULT = 5,
NUM_FLASHMAP_ENTRIES = 8
};
typedef struct FW_REGION_INFO
{
SMBDWord StartAddress;
SMBDWord EndAddress;
} __attribute__((packed)) FW_REGION_INFO;
typedef struct SMBFirmwareVolume {
SMB_STRUCT_HEADER // Type 128
SMBByte RegionCount;
SMBByte Reserved[3];
SMBDWord FirmwareFeatures;
SMBDWord FirmwareFeaturesMask;
SMBByte RegionType[ NUM_FLASHMAP_ENTRIES ];
FW_REGION_INFO FlashMap[ NUM_FLASHMAP_ENTRIES ];
} __attribute__((packed)) SMBFirmwareVolume;
//
// Memory SPD Data (Apple Specific - Type 130)
//
typedef struct SMBMemorySPD {
SMB_STRUCT_HEADER // Type 130
SMBWord Type17Handle;
SMBWord Offset;
SMBWord Size;
SMBWord Data[];
} __attribute__((packed)) SMBMemorySPD;
static const char *
SMBMemoryDeviceTypes[] =
{
"RAM", /* 00h Undefined */
"RAM", /* 01h Other */
"RAM", /* 02h Unknown */
"DRAM", /* 03h DRAM */
"EDRAM", /* 04h EDRAM */
"VRAM", /* 05h VRAM */
"SRAM", /* 06h SRAM */
"RAM", /* 07h RAM */
"ROM", /* 08h ROM */
"FLASH", /* 09h FLASH */
"EEPROM", /* 0Ah EEPROM */
"FEPROM", /* 0Bh FEPROM */
"EPROM", /* 0Ch EPROM */
"CDRAM", /* 0Dh CDRAM */
"3DRAM", /* 0Eh 3DRAM */
"SDRAM", /* 0Fh SDRAM */
"SGRAM", /* 10h SGRAM */
"RDRAM", /* 11h RDRAM */
"DDR SDRAM", /* 12h DDR */
"DDR2 SDRAM", /* 13h DDR2 */
"DDR2 FB-DIMM", /* 14h DDR2 FB-DIMM */
"RAM",/* 15h unused */
"RAM",/* 16h unused */
"RAM",/* 17h unused */
"DDR3",/* 18h DDR3, chosen in [5776134] */
};
static const int
kSMBMemoryDeviceTypeCount = sizeof(SMBMemoryDeviceTypes) /
sizeof(SMBMemoryDeviceTypes[0]);
//
// OEM Processor Type (Apple Specific - Type 131)
//
typedef struct SMBOemProcessorType {
SMB_STRUCT_HEADER
SMBWord ProcessorType;
} __attribute__((packed)) SMBOemProcessorType;
//
// OEM Processor Bus Speed (Apple Specific - Type 132)
//
typedef struct SMBOemProcessorBusSpeed {
SMB_STRUCT_HEADER
SMBWord ProcessorBusSpeed; // MT/s unit
} __attribute__((packed)) SMBOemProcessorBusSpeed;
//----------------------------------------------------------------------------------------------------------
/* From Foundation/Efi/Guid/Smbios/SmBios.h */
/* Modified to wrap Data4 array init with {} */
#define EFI_SMBIOS_TABLE_GUID {0xeb9d2d31, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}}
#define SMBIOS_ORIGINAL0
#define SMBIOS_PATCHED1
extern void *getSmbios(int which);
extern void readSMBIOSInfo(SMBEntryPoint *eps);
extern void setupSMBIOSTable(void);
extern void decodeSMBIOSTable(SMBEntryPoint *eps);
#endif /* !__LIBSAIO_SMBIOS_H */
branches/Chimera/i386/libsaio/memvendors.h
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} VenIdName;
VenIdName vendorMap[] = {
{ 0, 0x01, "AMD"},
{ 0, 0x01, "AMD"},
{ 0, 0x02, "AMI"},
{ 0, 0x83, "Fairchild"},
{ 0, 0x04, "Fujitsu"},
branches/Chimera/i386/libsaio/table.c
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/* 0x8 : boot protected mode 32-bit code segment
byte granularity, 1MB limit, MEMBASE offset */
{0xFFFF, MEMBASE, 0x00, 0x9E, 0x4F, 0x00},
//{0xFFFF, MEMBASE, 0x00, 0x9E, 0x4F, 0x00},
{0xFFFF, 0x0000, 0x00, 0x9E, 0xCF, 0x00},
/* 0x10 : boot protected mode data segment
page granularity, 4GB limit, MEMBASE offset */
branches/Chimera/i386/libsaio/fdisk.h
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#ifndef __LIBSAIO_FDISK_H
#define __LIBSAIO_FDISK_H
#define DISK_BLK00/* blkno of boot block */
#define DISK_BLK0SZ512/* size of boot block */
#define DISK_BOOTSZ446/* size of boot code in boot block */
#define DISK_SIGNATURE0xAA55/* signature of the boot record */
#define FDISK_NPART4/* number of entries in fdisk table */
#define FDISK_ACTIVE0x80/* indicator of active partition */
#define FDISK_NEXTNAME0xA7/* indicator of NeXT partition */
#define FDISK_DOS120x01/* 12-bit fat < 10MB dos partition */
#define FDISK_DOS16S0x04/* 16-bit fat < 32MB dos partition */
#define FDISK_DOSEXT0x05/* extended dos partition */
#define FDISK_DOS16B0x06/* 16-bit fat >= 32MB dos partition */
#define FDISK_NTFS0x07/* NTFS partition */
#define FDISK_SMALLFAT320x0b/* FAT32 partition */
#define FDISK_FAT320x0c/* FAT32 partition */
#define FDISK_DOS16SLBA0x0e
#define FDISK_LINUX0x83
#define FDISK_UFS0xa8/* Apple UFS partition */
#define FDISK_HFS0xaf/* Apple HFS partition */
#define FDISK_BOOTER0xab/* Apple booter partition */
#define DISK_BLK0 0 /* blkno of boot block */
#define DISK_BLK0SZ 512 /* size of boot block */
#define DISK_BOOTSZ 446 /* size of boot code in boot block */
#define DISK_SIGNATURE 0xAA55 /* signature of the boot record */
#define FDISK_NPART 4 /* number of entries in fdisk table */
#define FDISK_ACTIVE 0x80 /* indicator of active partition */
#define FDISK_NEXTNAME 0xA7 /* indicator of NeXT partition */
#define FDISK_DOS12 0x01 /* 12-bit fat < 10MB dos partition */
#define FDISK_DOS16S 0x04 /* 16-bit fat < 32MB dos partition */
#define FDISK_DOSEXT 0x05 /* extended dos partition */
#define FDISK_DOS16B 0x06 /* 16-bit fat >= 32MB dos partition */
#define FDISK_NTFS 0x07 /* NTFS partition */
#define FDISK_SMALLFAT32 0x0b /* FAT32 partition */
#define FDISK_FAT32 0x0c /* FAT32 partition */
#define FDISK_DOS16SLBA 0x0e
#define FDISK_LINUX0x83
#define FDISK_UFS 0xa8 /* Apple UFS partition */
#define FDISK_HFS 0xaf /* Apple HFS partition */
#define FDISK_BOOTER 0xab /* Apple booter partition */
/*
* Format of fdisk partion entry (if present).
*/
struct fdisk_part {
unsigned char bootid;/* bootable or not */
unsigned char beghead;/* begining head, sector, cylinder */
unsigned char begsect;/* begcyl is a 10-bit number */
unsigned char begcyl;/* High 2 bits are in begsect */
unsigned char systid;/* OS type */
unsigned char endhead;/* ending head, sector, cylinder */
unsigned char endsect;/* endcyl is a 10-bit number */
unsigned char endcyl;/* High 2 bits are in endsect */
unsigned long relsect;/* partion physical offset on disk */
unsigned long numsect;/* number of sectors in partition */
unsigned char bootid; /* bootable or not */
unsigned char beghead; /* begining head, sector, cylinder */
unsigned char begsect; /* begcyl is a 10-bit number */
unsigned char begcyl; /* High 2 bits are in begsect */
unsigned char systid; /* OS type */
unsigned char endhead; /* ending head, sector, cylinder */
unsigned char endsect; /* endcyl is a 10-bit number */
unsigned char endcyl; /* High 2 bits are in endsect */
unsigned long relsect; /* partion physical offset on disk */
unsigned long numsect; /* number of sectors in partition */
} __attribute__((packed));
/*
branches/Chimera/i386/libsaio/nvidia.c
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#define DBG(x...)
#endif
#define NVIDIA_ROM_SIZE 0x20000
#define NVIDIA_ROM_SIZE 0x10000
#define PATCH_ROM_SUCCESS 1
#define PATCH_ROM_SUCCESS_HAS_LVDS 2
#define PATCH_ROM_FAILED 0
const char *nvidia_device_type_0[]={ "@0,device_type","display" };
const char *nvidia_device_type_1[]={ "@1,device_type","display" };
const char *nvidia_device_type[]={ "device_type","NVDA,Parent" };
const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
const char *nvidia_slot_name[]={ "AAPL,slot-name","Slot-1" };
static uint8_t default_dcfg_0[]={0xff, 0xff, 0xff, 0xff};
static uint8_t default_dcfg_1[]={0xff, 0xff, 0xff, 0xff};
static uint8_t default_NVCAP[]= {
0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
0x00, 0x00, 0x00, 0x00
};
static uint8_t default_NVPM[]= {
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
};
#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )
#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )
#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )
static struct nv_chipsets_t NVKnownChipsets[] = {
{ 0x00000000, "Unknown" },
// 0040 - 004F
{ 0x10DE0040, "GeForce 6800 Ultra" },
{ 0x10DE0041, "GeForce 6800" },
{ 0x10DE0042, "GeForce 6800 LE" },
{ 0x10DE0046, "GeForce 6800 GT" },
{ 0x10DE0047, "GeForce 6800 GS" },
{ 0x10DE0048, "GeForce 6800 XT" },
{ 0x10DE004D, "Quadro FX 3400" },
{ 0x10DE004E, "Quadro FX 4000" },
// 0050 - 005F
// 0060 - 006F
// 0070 - 007F
// 0080 - 008F
// 0090 - 009F
{ 0x10DE0090, "GeForce 7800 GTX" },
{ 0x10DE0091, "GeForce 7800 GTX" },
{ 0x10DE0092, "GeForce 7800 GT" },
{ 0x10DE0098, "GeForce Go 7800" },
{ 0x10DE0099, "GeForce Go 7800 GTX" },
{ 0x10DE009D, "Quadro FX 4500" },
// 00A0 - 00AF
// 00B0 - 00BF
// 00C0 - 00CF
{ 0x10DE00C0, "GeForce 6800 GS" },
{ 0x10DE00C1, "GeForce 6800" },
{ 0x10DE00C2, "GeForce 6800 LE" },
{ 0x10DE00CC, "Quadro FX Go1400" },
{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },
{ 0x10DE00CE, "Quadro FX 1400" },
// 00D0 - 00DF
// 00E0 - 00EF
// 00F0 - 00FF
{ 0x10DE00F1, "GeForce 6600 GT" },
{ 0x10DE00F2, "GeForce 6600" },
{ 0x10DE00F3, "GeForce 6200" },
{ 0x10DE00F4, "GeForce 6600 LE" },
{ 0x10DE00F5, "GeForce 7800 GS" },
{ 0x10DE00F6, "GeForce 6800 GS/XT" },
{ 0x10DE00F8, "Quadro FX 3400/4400" },
{ 0x10DE00F9, "GeForce 6800 Series GPU" },
// 0100 - 010F
// 0110 - 011F
// 0120 - 012F
// 0130 - 013F
// 0140 - 014F
{ 0x10DE0140, "GeForce 6600 GT" },
{ 0x10DE0141, "GeForce 6600" },
{ 0x10DE0142, "GeForce 6600 LE" },
{ 0x10DE0147, "GeForce 6700 XL" },
{ 0x10DE0148, "GeForce Go 6600" },
{ 0x10DE0149, "GeForce Go 6600 GT" },
{ 0x10DE014A, "Quadro NVS 440" },
{ 0x10DE014C, "Quadro FX 550" },
{ 0x10DE014D, "Quadro FX 550" },
{ 0x10DE014E, "Quadro FX 540" },
{ 0x10DE014F, "GeForce 6200" },
// 0150 - 015F
// 0160 - 016F
{ 0x10DE0160, "GeForce 6500" },
{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },
{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },
{ 0x10DE0168, "GeForce Go 6400" },
{ 0x10DE0169, "GeForce 6250" },
{ 0x10DE016A, "GeForce 7100 GS" },
// 0170 - 017F
// 0180 - 018F
// 0190 - 019F
{ 0x10DE0191, "GeForce 8800 GTX" },
{ 0x10DE0193, "GeForce 8800 GTS" },
{ 0x10DE0194, "GeForce 8800 Ultra" },
{ 0x10DE0197, "Tesla C870" },
{ 0x10DE019D, "Quadro FX 5600" },
{ 0x10DE019E, "Quadro FX 4600" },
// 01A0 - 01AF
// 01B0 - 01BF
// 01C0 - 01CF
// 01D0 - 01DF
{ 0x10DE01D0, "GeForce 7350 LE" },
{ 0x10DE01D1, "GeForce 7300 LE" },
{ 0x10DE01D2, "GeForce 7550 LE" },
{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },
{ 0x10DE01D3, "GeForce 7300 SE" },
{ 0x10DE01D6, "GeForce Go 7200" },
{ 0x10DE01D7, "GeForce Go 7300" },
{ 0x10DE01D8, "GeForce Go 7400" },
{ 0x10DE01DD, "GeForce 7500 LE" },
{ 0x10DE01DE, "Quadro FX 350" },
{ 0x10DE01DF, "GeForce 7300 GS" },
// 01E0 - 01EF
// 01F0 - 01FF
// 0200 - 020F
// 0210 - 021F
{ 0x10DE0211, "GeForce 6800" },
{ 0x10DE0212, "GeForce 6800 LE" },
{ 0x10DE0215, "GeForce 6800 GT" },
{ 0x10DE0218, "GeForce 6800 XT" },
// 0220 - 022F
{ 0x10DE0221, "GeForce 6200" },
{ 0x10DE0222, "GeForce 6200 A-LE" },
// 0230 - 023F
// 0240 - 024F
{ 0x10DE0240, "GeForce 6150" },
{ 0x10DE0241, "GeForce 6150 LE" },
{ 0x10DE0242, "GeForce 6100" },
{ 0x10DE0244, "GeForce Go 6150" },
{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },
{ 0x10DE0247, "GeForce Go 6100" },
// 0250 - 025F
// 0260 - 026F
// 0270 - 027F
// 0280 - 028F
// 0290 - 029F
{ 0x10DE0290, "GeForce 7900 GTX" },
{ 0x10DE0291, "GeForce 7900 GT/GTO" },
{ 0x10DE0291, "GeForce 7900 GT" },
{ 0x10DE0292, "GeForce 7900 GS" },
{ 0x10DE0293, "GeForce 7950 GX2" },
{ 0x10DE0294, "GeForce 7950 GX2" },
{ 0x10DE0295, "GeForce 7950 GT" },
{ 0x10DE0298, "GeForce Go 7900 GS" },
{ 0x10DE0299, "GeForce Go 7900 GTX" },
{ 0x10DE029A, "Quadro FX 2500M" },
{ 0x10DE029D, "Quadro FX 3500" },
{ 0x10DE029E, "Quadro FX 1500" },
{ 0x10DE029F, "Quadro FX 4500 X2" },
// 02A0 - 02AF
// 02B0 - 02BF
// 02C0 - 02CF
// 02D0 - 02DF
// 02E0 - 02EF
{ 0x10DE02E0, "GeForce 7600 GT" },
{ 0x10DE02E1, "GeForce 7600 GS" },
{ 0x10DE02E2, "GeForce 7300 GT" },
{ 0x10DE02E3, "GeForce 7900 GS" },
{ 0x10DE02E4, "GeForce 7950 GT" },
// 02F0 - 02FF
// 0300 - 030F
{ 0x10DE0301, "GeForce FX 5800 Ultra" },
{ 0x10DE0302, "GeForce FX 5800" },
{ 0x10DE0308, "Quadro FX 2000" },
{ 0x10DE0309, "Quadro FX 1000" },
// 0310 - 031F
{ 0x10DE0311, "GeForce FX 5600 Ultra" },
{ 0x10DE0312, "GeForce FX 5600" },
{ 0x10DE0314, "GeForce FX 5600XT" },
{ 0x10DE031A, "GeForce FX Go5600" },
{ 0x10DE031B, "GeForce FX Go5650" },
{ 0x10DE031C, "Quadro FX Go700" },
// 0320 - 032F
{ 0x10DE0324, "GeForce FX Go5200" },
{ 0x10DE0325, "GeForce FX Go5250" },
{ 0x10DE0326, "GeForce FX 5500" },
{ 0x10DE032B, "Quadro FX 500/600 PCI" },
{ 0x10DE032C, "GeForce FX Go53xx Series" },
{ 0x10DE032D, "GeForce FX Go5100" },
// 0330 - 033F
{ 0x10DE0330, "GeForce FX 5900 Ultra" },
{ 0x10DE0331, "GeForce FX 5900" },
{ 0x10DE0332, "GeForce FX 5900XT" },
{ 0x10DE0334, "GeForce FX 5900ZT" },
{ 0x10DE0338, "Quadro FX 3000" },
{ 0x10DE033F, "Quadro FX 700" },
// 0340 - 034F
{ 0x10DE0341, "GeForce FX 5700 Ultra" },
{ 0x10DE0342, "GeForce FX 5700" },
{ 0x10DE0343, "GeForce FX 5700LE" },
{ 0x10DE0348, "GeForce FX Go5700" },
{ 0x10DE034C, "Quadro FX Go1000" },
{ 0x10DE034E, "Quadro FX 1100" },
// 0350 - 035F
// 0360 - 036F
// 0370 - 037F
// 0380 - 038F
{ 0x10DE038B, "GeForce 7650 GS" },
// 0390 - 039F
{ 0x10DE0390, "GeForce 7650 GS" },
{ 0x10DE0391, "GeForce 7600 GT" },
{ 0x10DE0392, "GeForce 7600 GS" },
{ 0x10DE0393, "GeForce 7300 GT" },
{ 0x10DE039B, "GeForce Go 7900 SE" },
{ 0x10DE039C, "Quadro FX 550M" },
{ 0x10DE039E, "Quadro FX 560" },
// 03A0 - 03AF
// 03B0 - 03BF
// 03C0 - 03CF
// 03D0 - 03DF
{ 0x10DE03D0, "GeForce 6150SE nForce 430" },
{ 0x10DE03D1, "GeForce 6100 nForce 405" },
{ 0x10DE03D2, "GeForce 6100 nForce 400" },
{ 0x10DE03D5, "GeForce 6100 nForce 420" },
{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },
// 03E0 - 03EF
// 03F0 - 03FF
// 0400 - 040F
{ 0x10DE0400, "GeForce 8600 GTS" },
{ 0x10DE0401, "GeForce 8600 GT" },
{ 0x10DE0402, "GeForce 8600 GT" },
{ 0x10DE0403, "GeForce 8600 GS" },
{ 0x10DE0404, "GeForce 8400 GS" },
{ 0x10DE0405, "GeForce 9500M GS" },
{ 0x10DE0406, "GeForce 8300 GS" },
{ 0x10DE0407, "GeForce 8600M GT" },
{ 0x10DE0408, "GeForce 9650M GS" },
{ 0x10DE0409, "GeForce 8700M GT" },
{ 0x10DE040D, "Quadro FX 1600M" },
{ 0x10DE040E, "Quadro FX 570" },
{ 0x10DE040F, "Quadro FX 1700" },
// 0410 - 041F
{ 0x10DE0410, "GeForce GT 330" },
// 0420 - 042F
{ 0x10DE0420, "GeForce 8400 SE" },
{ 0x10DE0421, "GeForce 8500 GT" },
{ 0x10DE0422, "GeForce 8400 GS" },
{ 0x10DE042D, "Quadro FX 360M" },
{ 0x10DE042E, "GeForce 9300M G" },
{ 0x10DE042F, "Quadro NVS 290" },
// 0430 - 043F
// 0440 - 044F
// 0450 - 045F
// 0460 - 046F
// 0470 - 047F
// 0480 - 048F
// 0490 - 049F
// 04A0 - 04AF
// 04B0 - 04BF
// 04C0 - 04CF
// 04D0 - 04DF
// 04E0 - 04EF
// 04F0 - 04FF
// 0500 - 050F
// 0510 - 051F
// 0520 - 052F
// 0530 - 053F
{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },
{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },
{ 0x10DE053E, "GeForce 7025 / nForce 630a" },
// 0540 - 054F
// 0550 - 055F
// 0560 - 056F
// 0570 - 057F
// 0580 - 058F
// 0590 - 059F
// 05A0 - 05AF
// 05B0 - 05BF
// 05C0 - 05CF
// 05D0 - 05DF
// 05E0 - 05EF
{ 0x10DE05E0, "GeForce GTX 295" },
{ 0x10DE05E1, "GeForce GTX 280" },
{ 0x10DE05E2, "GeForce GTX 260" },
{ 0x10DE05E6, "GeForce GTX 275" },
{ 0x10DE05EA, "GeForce GTX 260" },
{ 0x10DE05EB, "GeForce GTX 295" },
{ 0x10DE05ED, "Quadroplex 2200 D2" },
// 05F0 - 05FF
{ 0x10DE05F8, "Quadroplex 2200 S4" },
{ 0x10DE05F9, "Quadro CX" },
{ 0x10DE05FD, "Quadro FX 5800" },
{ 0x10DE05FE, "Quadro FX 4800" },
{ 0x10DE05FF, "Quadro FX 3800" },
// 0600 - 060F
{ 0x10DE0600, "GeForce 8800 GTS 512" },
{ 0x10DE0601, "GeForce 9800 GT" },
{ 0x10DE0602, "GeForce 8800 GT" },
{ 0x10DE0603, "GeForce GT 230" },
{ 0x10DE0604, "GeForce 9800 GX2" },
{ 0x10DE0605, "GeForce 9800 GT" },
{ 0x10DE0606, "GeForce 8800 GS" },
{ 0x10DE060B, "GeForce 9800M GT" },
{ 0x10DE060C, "GeForce 8800M GTX" },
{ 0x10DE060D, "GeForce 8800 GS" },
{ 0x10DE060F, "GeForce GTX 285M" },
// 0610 - 061F
{ 0x10DE0610, "GeForce 9600 GSO" },
{ 0x10DE0611, "GeForce 8800 GT" },
{ 0x10DE0612, "GeForce 9800 GTX" },
{ 0x10DE0614, "GeForce 9800 GT" },
{ 0x10DE0615, "GeForce GTS 250" },
{ 0x10DE0617, "GeForce 9800M GTX" },
{ 0x10DE0618, "GeForce GTX 260M" },
{ 0x10DE0619, "Quadro FX 4700 X2" },
{ 0x10DE0618, "GeForce GTX 260M" },
{ 0x10DE061A, "Quadro FX 3700" },
{ 0x10DE061B, "Quadro VX 200" },
{ 0x10DE061C, "Quadro FX 3600M" },
{ 0x10DE061D, "Quadro FX 2800M" },
{ 0x10DE061F, "Quadro FX 3800M" },
// 0620 - 062F
{ 0x10DE0622, "GeForce 9600 GT" },
{ 0x10DE0623, "GeForce 9600 GS" },
{ 0x10DE0625, "GeForce 9600 GSO 512"},
{ 0x10DE0628, "GeForce 9800M GTS" },
{ 0x10DE062A, "GeForce 9700M GTS" },
{ 0x10DE062C, "GeForce 9800M GTS" },
{ 0x10DE062D, "GeForce 9600 GT" },
{ 0x10DE062E, "GeForce 9600 GT" },
// 0630 - 063F
{ 0x10DE0631, "GeForce GTS 160M" },
{ 0x10DE0632, "GeForce GTS 150M" },
{ 0x10DE0635, "GeForce 9600 GSO" },
{ 0x10DE0637, "GeForce 9600 GT" },
{ 0x10DE0638, "Quadro FX 1800" },
{ 0x10DE063A, "Quadro FX 2700M" },
// 0640 - 064F
{ 0x10DE0640, "GeForce 9500 GT" },
{ 0x10DE0641, "GeForce 9400 GT" },
{ 0x10DE0642, "GeForce 8400 GS" },
{ 0x10DE064A, "GeForce 9700M GT" },
{ 0x10DE064B, "GeForce 9500M G" },
{ 0x10DE064C, "GeForce 9650M GT" },
// 0650 - 065F
{ 0x10DE0651, "GeForce G 110M" },
{ 0x10DE0652, "GeForce GT 130M" },
{ 0x10DE0653, "GeForce GT 120M" },
{ 0x10DE0654, "GeForce GT 220M" },
{ 0x10DE0656, "GeForce 9650 S" },
{ 0x10DE0658, "Quadro FX 380" },
{ 0x10DE0659, "Quadro FX 580" },
{ 0x10DE065A, "Quadro FX 1700M" },
{ 0x10DE065B, "GeForce 9400 GT" },
{ 0x10DE065C, "Quadro FX 770M" },
{ 0x10DE065F, "GeForce G210" },
// 0660 - 066F
// 0670 - 067F
// 0680 - 068F
// 0690 - 069F
// 06A0 - 06AF
// 06B0 - 06BF
// 06C0 - 06CF
{ 0x10DE06C0, "GeForce GTX 480" },
{ 0x10DE06C3, "GeForce GTX D12U" },
{ 0x10DE06C4, "GeForce GTX 465" },
{ 0x10DE06CA, "GeForce GTX 480M" },
{ 0x10DE06CD, "GeForce GTX 470" },
// 06D0 - 06DF
{ 0x10DE06D1, "Tesla C2050" },// TODO: sub-device id: 0x0771
{ 0x10DE06D1, "Tesla C2070" },// TODO: sub-device id: 0x0772
{ 0x10DE06D2, "Tesla M2070" },
{ 0x10DE06D8, "Quadro 6000" },
{ 0x10DE06D9, "Quadro 5000" },
{ 0x10DE06DA, "Quadro 5000M" },
{ 0x10DE06DC, "Quadro 6000" },
{ 0x10DE06DE, "Tesla M2050" },// TODO: sub-device id: 0x0846
{ 0x10DE06DE, "Tesla M2070" },// TODO: sub-device id: ?
// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070
{ 0x10DE06DD, "Quadro 4000" },
{ 0x10DE06DE, "Tesla M2050" },// TODO: sub-device id: 0x0846
{ 0x10DE06DE, "Tesla M2070" },// TODO: sub-device id: ?
// 06E0 - 06EF
{ 0x10DE06E0, "GeForce 9300 GE" },
{ 0x10DE06E1, "GeForce 9300 GS" },
{ 0x10DE06E2, "GeForce 8400" },
{ 0x10DE06E3, "GeForce 8400 SE" },
{ 0x10DE06E4, "GeForce 8400 GS" },
{ 0x10DE06E5, "GeForce 9300M GS" },
{ 0x10DE06E6, "GeForce G100" },
{ 0x10DE06E7, "GeForce 9300 SE" },
{ 0x10DE06E8, "GeForce 9200M GS" },
{ 0x10DE06E9, "GeForce 9300M GS" },
{ 0x10DE06EA, "Quadro NVS 150M" },
{ 0x10DE06EB, "Quadro NVS 160M" },
{ 0x10DE06EC, "GeForce G 105M" },
{ 0x10DE06EF, "GeForce G 103M" },
// 06F0 - 06FF
{ 0x10DE06F8, "Quadro NVS 420" },
{ 0x10DE06F9, "Quadro FX 370 LP" },
{ 0x10DE06FA, "Quadro NVS 450" },
{ 0x10DE06FB, "Quadro FX 370M" },
{ 0x10DE06FD, "Quadro NVS 295" },
// 0700 - 070F
// 0710 - 071F
// 0720 - 072F
// 0730 - 073F
// 0740 - 074F
// 0750 - 075F
// 0760 - 076F
// 0770 - 077F
// 0780 - 078F
// 0790 - 079F
// 07A0 - 07AF
// 07B0 - 07BF
// 07C0 - 07CF
// 07D0 - 07DF
// 07E0 - 07EF
{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },
{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },
{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },
{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },
{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },
// 07F0 - 07FF
// 0800 - 080F
// 0810 - 081F
// 0820 - 082F
// 0830 - 083F
// 0840 - 084F
{ 0x10DE0844, "GeForce 9100M G" },
{ 0x10DE0845, "GeForce 8200M G" },
{ 0x10DE0846, "GeForce 9200" },
{ 0x10DE0847, "GeForce 9100" },
{ 0x10DE0848, "GeForce 8300" },
{ 0x10DE0849, "GeForce 8200" },
{ 0x10DE084A, "nForce 730a" },
{ 0x10DE084B, "GeForce 9200" },
{ 0x10DE084C, "nForce 980a/780a SLI" },
{ 0x10DE084D, "nForce 750a SLI" },
{ 0x10DE084F, "GeForce 8100 / nForce 720a" },
// 0850 - 085F
// 0860 - 086F
{ 0x10DE0860, "GeForce 9400" },
{ 0x10DE0861, "GeForce 9400" },
{ 0x10DE0862, "GeForce 9400M G" },
{ 0x10DE0863, "GeForce 9400M" },
{ 0x10DE0864, "GeForce 9300" },
{ 0x10DE0865, "ION" },
{ 0x10DE0866, "GeForce 9400M G" },
{ 0x10DE0867, "GeForce 9400" },
{ 0x10DE0868, "nForce 760i SLI" },
{ 0x10DE086A, "GeForce 9400" },
{ 0x10DE086C, "GeForce 9300 / nForce 730i" },
{ 0x10DE086D, "GeForce 9200" },
{ 0x10DE086E, "GeForce 9100M G" },
{ 0x10DE086F, "GeForce 8200M G" },
// 0870 - 087F
{ 0x10DE0870, "GeForce 9400M" },
{ 0x10DE0871, "GeForce 9200" },
{ 0x10DE0872, "GeForce G102M" },
{ 0x10DE0873, "GeForce G102M" },
{ 0x10DE0874, "ION 9300M" },
{ 0x10DE0876, "ION" },
{ 0x10DE087A, "GeForce 9400" },
{ 0x10DE086C, "GeForce 9300/nForce 730i" },
{ 0x10DE087D, "ION 9400M" },
{ 0x10DE087E, "ION LE" },
{ 0x10DE087F, "ION LE" },
// 0880 - 088F
// 0890 - 089F
// 08A0 - 08AF
// 08B0 - 08BF
// 08C0 - 08CF
// 08D0 - 08DF
// 08E0 - 08EF
// 08F0 - 08FF
// 0900 - 090F
// 0910 - 091F
// 0920 - 092F
// 0930 - 093F
// 0940 - 094F
// 0950 - 095F
// 0960 - 096F
// 0970 - 097F
// 0980 - 098F
// 0990 - 099F
// 09A0 - 09AF
// 09B0 - 09BF
// 09C0 - 09CF
// 09D0 - 09DF
// 09E0 - 09EF
// 09F0 - 09FF
// 0A00 - 0A0F
// 0A10 - 0A1F
// 0A20 - 0A2F
{ 0x10DE0A20, "GeForce GT220" },
{ 0x10DE0A22, "GeForce 315" },
{ 0x10DE0A23, "GeForce 210" },
{ 0x10DE0A28, "GeForce GT 230M" },
{ 0x10DE0A29, "GeForce GT 330M" },
{ 0x10DE0A2A, "GeForce GT 230M" },
{ 0x10DE0A2B, "GeForce GT 330M" },
{ 0x10DE0A2C, "NVS 5100M" },
{ 0x10DE0A2D, "GeForce GT 320M" },
// 0A30 - 0A3F
{ 0x10DE0A34, "GeForce GT 240M" },
{ 0x10DE0A35, "GeForce GT 325M" },
{ 0x10DE0A3C, "Quadro FX 880M" },
// 0A40 - 0A4F
// 0A50 - 0A5F
// 0A60 - 0A6F
{ 0x10DE0A60, "GeForce G210" },
{ 0x10DE0A62, "GeForce 205" },
{ 0x10DE0A63, "GeForce 310" },
{ 0x10DE0A64, "ION" },
{ 0x10DE0A65, "GeForce 210" },
{ 0x10DE0A66, "GeForce 310" },
{ 0x10DE0A67, "GeForce 315" },
{ 0x10DE0A68, "GeForce G105M" },
{ 0x10DE0A69, "GeForce G105M" },
{ 0x10DE0A6A, "NVS 2100M" },
{ 0x10DE0A6C, "NVS 3100M" },
{ 0x10DE0A6E, "GeForce 305M" },
{ 0x10DE0A6F, "ION" },
// 0A70 - 0A7F
{ 0x10DE0A70, "GeForce 310M" },
{ 0x10DE0A71, "GeForce 305M" },
{ 0x10DE0A72, "GeForce 310M" },
{ 0x10DE0A73, "GeForce 305M" },
{ 0x10DE0A74, "GeForce G210M" },
{ 0x10DE0A75, "GeForce G310M" },
{ 0x10DE0A78, "Quadro FX 380 LP" },
{ 0x10DE0A7C, "Quadro FX 380M" },
// 0A80 - 0A8F
// 0A90 - 0A9F
// 0AA0 - 0AAF
// 0AB0 - 0ABF
// 0AC0 - 0ACF
// 0AD0 - 0ADF
// 0AE0 - 0AEF
// 0AF0 - 0AFF
// 0B00 - 0B0F
// 0B10 - 0B1F
// 0B20 - 0B2F
// 0B30 - 0B3F
// 0B40 - 0B4F
// 0B50 - 0B5F
// 0B60 - 0B6F
// 0B70 - 0B7F
// 0B80 - 0B8F
// 0B90 - 0B9F
// 0BA0 - 0BAF
// 0BB0 - 0BBF
// 0BC0 - 0BCF
// 0BD0 - 0BDF
// 0BE0 - 0BEF
// 0BF0 - 0BFF
// 0C00 - 0C0F
// 0C10 - 0C1F
// 0C20 - 0C2F
// 0C30 - 0C3F
// 0C40 - 0C4F
// 0C50 - 0C5F
// 0C60 - 0C6F
// 0C70 - 0C7F
// 0C80 - 0C8F
// 0C90 - 0C9F
// 0CA0 - 0CAF
{ 0x10DE0CA0, "GeForce GT 330 " },
{ 0x10DE0CA2, "GeForce GT 320" },
{ 0x10DE0CA3, "GeForce GT 240" },
{ 0x10DE0CA4, "GeForce GT 340" },
{ 0x10DE0CA7, "GeForce GT 330" },
{ 0x10DE0CA8, "GeForce GTS 260M" },
{ 0x10DE0CA9, "GeForce GTS 250M" },
{ 0x10DE0CAC, "GeForce 315" },
{ 0x10DE0CAF, "GeForce GT 335M" },
// 0CB0 - 0CBF
{ 0x10DE0CB0, "GeForce GTS 350M" },
{ 0x10DE0CB1, "GeForce GTS 360M" },
{ 0x10DE0CBC, "Quadro FX 1800M" },
// 0CC0 - 0CCF
// 0CD0 - 0CDF
// 0CE0 - 0CEF
// 0CF0 - 0CFF
// 0D00 - 0D0F
// 0D10 - 0D1F
// 0D20 - 0D2F
// 0D30 - 0D3F
// 0D40 - 0D4F
// 0D50 - 0D5F
// 0D60 - 0D6F
// 0D70 - 0D7F
// 0D80 - 0D8F
// 0D90 - 0D9F
// 0DA0 - 0DAF
// 0DB0 - 0DBF
// 0DC0 - 0DCF
{ 0x10DE0CA3, "GeForce GT240" },
// 06C0 - 06DFF
{ 0x10DE06C0, "GeForce GTX 480" },
{ 0x10DE06C3, "GeForce GTX D12U" },
{ 0x10DE06C4, "GeForce GTX 465" },
{ 0x10DE06CA, "GeForce GTX 480M" },
{ 0x10DE06CD, "GeForce GTX 470" },
{ 0x10DE06D1, "Tesla C2050" },// TODO: sub-device id: 0x0771
{ 0x10DE06D1, "Tesla C2070" },// TODO: sub-device id: 0x0772
{ 0x10DE06D2, "Tesla M2070" },
{ 0x10DE06D8, "Quadro 6000" },
{ 0x10DE06D9, "Quadro 5000" },
{ 0x10DE06DA, "Quadro 5000M" },
{ 0x10DE06DC, "Quadro 6000" },
{ 0x10DE06DE, "Tesla M2050" },// TODO: sub-device id: 0x0846
{ 0x10DE06DE, "Tesla M2070" },// TODO: sub-device id: ?
// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070
{ 0x10DE06DD, "Quadro 4000" },
// 0DC0 - 0DFF
{ 0x10DE0DC0, "GeForce GT 440" },
{ 0x10DE0DC1, "D12-P1-35" },
{ 0x10DE0DC2, "D12-P1-35" },
{ 0x10DE0DC5, "GeForce GTS 450" },
{ 0x10DE0DC6, "GeForce GTS 450" },
{ 0x10DE0DCA, "GF10x" },
// 0DD0 - 0DDF
{ 0x10DE0DD1, "GeForce GTX 460M" },
{ 0x10DE0DD2, "GeForce GT 445M" },
{ 0x10DE0DD3, "GeForce GT 435M" },
{ 0x10DE0DD8, "Quadro 2000" },
{ 0x10DE0DDE, "GF106-ES" },
{ 0x10DE0DDF, "GF106-INT" },
// 0DE0 - 0DEF
{ 0x10DE0DE1, "GeForce GT 430" },
{ 0x10DE0DE2, "GeForce GT 420" },
{ 0x10DE0DEB, "GeForce GT 555M" },
{ 0x10DE0DEE, "GeForce GT 415M" },
// 0DF0 - 0DFF
{ 0x10DE0DF0, "GeForce GT 425M" },
{ 0x10DE0DF1, "GeForce GT 420M" },
{ 0x10DE0DF2, "GeForce GT 435M" },
{ 0x10DE0DF8, "Quadro 600" },
{ 0x10DE0DFE, "GF108 ES" },
{ 0x10DE0DFF, "GF108 INT" },
// 0E00 - 0E0F
// 0E10 - 0E1F
// 0E20 - 0E2F
// 0E20 - 0E3F
{ 0x10DE0E21, "D12U-25" },
{ 0x10DE0E22, "GeForce GTX 460" },
{ 0x10DE0E23, "GeForce GTX 460 SE" },
{ 0x10DE0E24, "GeForce GTX 460" },
{ 0x10DE0E25, "D12U-50" },
// 0E30 - 0E3F
{ 0x10DE0E30, "GeForce GTX 470M" },
{ 0x10DE0E38, "GF104GL" },
{ 0x10DE0E3E, "GF104-ES" },
{ 0x10DE0E3F, "GF104-INT" },
// 0E40 - 0E4F
// 0E50 - 0E5F
// 0E60 - 0E6F
// 0E70 - 0E7F
// 0E80 - 0E8F
// 0E90 - 0E9F
// 0EA0 - 0EAF
// 0EB0 - 0EBF
// 0EC0 - 0ECF
// 0ED0 - 0EDF
// 0EE0 - 0EEF
// 0EF0 - 0EFF
// 0F00 - 0F0F
// 0F10 - 0F1F
// 0F20 - 0F2F
// 0F30 - 0F3F
// 0F40 - 0F4F
// 0F50 - 0F5F
// 0F60 - 0F6F
// 0F70 - 0F7F
// 0F80 - 0F8F
// 0F90 - 0F9F
// 0FA0 - 0FAF
// 0FB0 - 0FBF
// 0FC0 - 0FCF
// 0FD0 - 0FDF
// 0FE0 - 0FEF
// 0FF0 - 0FFF
// 1000 - 100F
// 1010 - 101F
// 1020 - 102F
// 1030 - 103F
// 1040 - 104F
// 1050 - 105F
// 1060 - 106F
// 1070 - 107F
// 1080 - 108F
// 0EE0 - 0EFF: none yet
// 0F00 - 0F3F: none yet
// 1040 - 107F: none yet
// 1080 - 109F
{ 0x10DE1080, "GeForce GTX 580" },
{ 0x10DE1081, "GeForce GTX 570" },
{ 0x10DE1081, "D13U" },
{ 0x10DE1082, "D13U" },
{ 0x10DE1083, "D13U" },
{ 0x10DE1088, "GeForce GTX 590" },
// 1090 - 109F
{ 0x10DE1098, "D13U" },
{ 0x10DE109A, "N12E-Q5" },
// 10A0 - 10AF
// 10B0 - 10BF
// 10C0 - 10CF
{ 0x10DE10C3, "GeForce 8400 GS" },
// 1200 -
{ 0x10DE1200, "GeForce GTX 560 Ti" }
};
static uint16_t swap16(uint16_t x)
unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)
{
unsigned long long vram_size = 0;
if (nvCardType < NV_ARCH_50) {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
}
else if (nvCardType >= NV_ARCH_C0) {
vram_size = REG32(NVC0_MEM_CTRLR_COUNT) << 20;
vram_size *= REG32(NVC0_MEM_CTRLR_RAM_AMOUNT);
}
else {
else if (nvCardType < NV_ARCH_C0) {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size |= (vram_size & 0xff) << 32;
vram_size &= 0xffffffff00ll;
}
// workaround code for gt 430 & 9600M GT
switch (nvda_dev->device_id)
{
case 0x0DE1: vram_size = 1024*1024*1024; break; // gt 430
case 0x0649: vram_size = 512*1024*1024; break; // 9600M GT
default: break;
else { // >= NV_ARCH_C0
vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;
vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);
}
return vram_size;
}
{
struct DevPropDevice*device;
char*devicepath;
struct pci_rom_pci_header_t*rom_pci_header;
option_rom_pci_header_t*rom_pci_header;
volatile uint8_t*regs;
uint8_t*rom;
uint8_t*nvRom;
if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {
printf("ERROR: nVidia ROM Patching Failed!\n");
return false;
//return false;
}
rom_pci_header = (struct pci_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);
rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);
// check for 'PCIR' sig
if (rom_pci_header->signature == 0x50434952) {
default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);
#endif
if (getValueForKey(kdcfg0, &value, &len, &bootInfo->bootConfig) && len == DCFG0_LEN * 2)
{
uint8_tnew_dcfg0[DCFG0_LEN];
if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)
{
verbose("Using user supplied @0,display-cfg\n");
memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);
}
}
#if DEBUG_dcfg0
printf("@0,display-cfg: %02x%02x%02x%02x\n",
default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3], default_dcfg_0[4]);
#endif
if (getValueForKey(kdcfg1, &value, &len, &bootInfo->bootConfig) && len == DCFG1_LEN * 2)
{
uint8_tnew_dcfg1[DCFG1_LEN];
if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)
{
verbose("Using user supplied @1,display-cfg\n");
memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);
}
}
#if DEBUG_dcfg1
printf("@1,display-cfg: %02x%02x%02x%02x\n",
default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3], default_dcfg_1[4]);
#endif
devprop_add_nvidia_template(device);
devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);
devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);
devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);
devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);
devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);
devprop_add_value(device, "NVPM", default_NVPM, 28);
if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit) {
devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));
}
branches/Chimera/i386/libsaio/ati.c
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CHIP_FAMILY_RS690,
CHIP_FAMILY_RS740,
/* R600 */
CHIP_FAMILY_R600,
CHIP_FAMILY_R600,
CHIP_FAMILY_RV610,
CHIP_FAMILY_RV630,
CHIP_FAMILY_RV670,
"Redwood",// RV830
"Juniper",// RV840
"Cypress",// RV870
"Hemlock",
"Hemlock",
/* Northern Islands */
"Barts",
"Caicos",
{ 0x94C3,0x22471787,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 LE",kNull},
{ 0x94C3,0x01011A93,CHIP_FAMILY_RV610,"Qimonda Radeon HD 2400 PRO",kNull},
{ 0x9501,0x30001002,CHIP_FAMILY_RV670,"ATI Radeon HD 3690",kNull},
{ 0x9501,0x25421002,CHIP_FAMILY_RV670,"ATI Radeon HD 3870",kNull},
{ 0x9501,0x4750174B,CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x68F9,0x5470174B,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5470",kNull},
{ 0x68F9,0x5490174B,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5490",kNull},
{ 0x68F9,0x5530174B,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5530",kNull},
/* Northen Islands */
{ 0x6718,0x0B001002,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970",kBulrushes},
{ 0x6718,0x31301682,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970",kBulrushes},
{ 0x6718,0x67181002,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970",kBulrushes},
{ 0x6718,0x0B001002,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970",kNull},
{ 0x6718,0x31301682,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970",kNull},
{ 0x6718,0x67181002,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970",kNull},
{ 0x6738,0x67381002,CHIP_FAMILY_BARTS,"AMD Radeon HD 6870",kDuckweed},
{ 0x6739,0x67391002,CHIP_FAMILY_BARTS,"AMD Radeon HD 6850",kDuckweed},
{ 0x6759,0xE193174B,CHIP_FAMILY_TURKS,"AMD Radeon HD 6570",kNull},
/* standard/default models */
{ 0x9400,0x00000000,CHIP_FAMILY_R600,"ATI Radeon HD 2900 XT",kNull},
{ 0x9710,0x00000000,CHIP_FAMILY_RS880,"ATI Radeon HD 4200",kNull},
{ 0x9715,0x00000000,CHIP_FAMILY_RS880,"ATI Radeon HD 4250",kNull},
{ 0x9714,0x00000000,CHIP_FAMILY_RS880,"ATI Radeon HD 4290",kNull},
{ 0x6718,0x00000000,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970 Series",kBulrushes},
{ 0x6738,0x00000000,CHIP_FAMILY_BARTS,"AMD Radeon HD 6870 Series",kDuckweed},
{ 0x6739,0x00000000,CHIP_FAMILY_BARTS,"AMD Radeon HD 6850 Series",kDuckweed},
{ 0x6758,0x00000000,CHIP_FAMILY_TURKS,"AMD Radeon HD 6670 Series",kNull},
{ 0x6759,0x00000000,CHIP_FAMILY_TURKS,"AMD Radeon HD 6500 Series",kNull},
{ 0x6770,0x00000000,CHIP_FAMILY_CAICOS,"AMD Radeon HD 6400 Series",kNull},
{ 0x6779,0x00000000,CHIP_FAMILY_CAICOS,"AMD Radeon HD 6450 Series",kNull},
{ 0x68F9,0x00000000,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5400 Series",kNull},
/* Evergreen */
{ 0x688D,0x00000000,CHIP_FAMILY_CYPRESS,"AMD FireStream 9350",kUakari},
{ 0x6898,0x00000000,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5800 Series",kUakari},
{ 0x6899,0x00000000,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5800 Series",kUakari},
{ 0x689E,0x00000000,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5800 Series",kUakari},
{ 0x689C,0x00000000,CHIP_FAMILY_HEMLOCK,"ATI Radeon HD 5900 Series",kUakari},
{ 0x68B9,0x00000000,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5600 Series",kVervet},
{ 0x68D9,0x00000000,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5500 Series",kBaboon},
{ 0x68DA,0x00000000,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5500 Series",kBaboon},
{ 0x68F9,0x00000000,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5400 Series",kNull},
{ 0x6718,0x00000000,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6900 Series",kNull},
/* Northen Islands */
{ 0x6758,0x00000000,CHIP_FAMILY_TURKS,"AMD Radeon HD 6670",kNull},
{ 0x6759,0x00000000,CHIP_FAMILY_TURKS,"AMD Radeon HD 6500 Series",kNull},
{ 0x6770,0x00000000,CHIP_FAMILY_CAICOS,"AMD Radeon HD 6400 Series",kNull},
{ 0x6779,0x00000000,CHIP_FAMILY_CAICOS,"AMD Radeon HD 6450 Series",kNull},
{ 0x68F9,0x00000000,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5400 Series",kNull},
{ 0x0000,0x00000000,CHIP_FAMILY_UNKNOW,NULL,kNull}
};
if (!val->data)
return false;
memcpy(val->data, rev, val->size);
return true;
else
{
if (devprop_list[i].default_val.type != kNul)
devprop_add_value(card->device, devprop_list[i].name,
devprop_list[i].default_val.type == kCst ?
(uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data,
devprop_add_value(card->device, devprop_list[i].name,
devprop_list[i].default_val.type == kCst ?
(uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data,
devprop_list[i].default_val.size);
if (devprop_list[i].all_ports)
if (devprop_list[i].default_val.type != kNul)
{
devprop_list[i].name[1] = 0x30 + pnum; // convert to ascii
devprop_add_value(card->device, devprop_list[i].name,
devprop_list[i].default_val.type == kCst ?
(uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data,
devprop_add_value(card->device, devprop_list[i].name,
devprop_list[i].default_val.type == kCst ?
(uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data,
devprop_list[i].default_val.size);
}
}
}
bool validate_rom(pci_rom_header_t *rom_header, pci_dt_t *pci_dev)
bool validate_rom(option_rom_header_t *rom_header, pci_dt_t *pci_dev)
{
struct pci_rom_pci_header_t *rom_pci_header;
option_rom_pci_header_t *rom_pci_header;
if (rom_header->signature != 0xaa55)
return false;
rom_pci_header = (struct pci_rom_pci_header_t *)((uint8_t *)rom_header + rom_header->pci_header_offset);
rom_pci_header = (option_rom_pci_header_t *)((uint8_t *)rom_header + rom_header->pci_header_offset);
if (rom_pci_header->signature != 0x52494350)
return false;
return false;
read(fd, (char *)card->rom, card->rom_size);
if (!validate_rom((pci_rom_header_t *)card->rom, card->pci_dev))
if (!validate_rom((option_rom_header_t *)card->rom, card->pci_dev))
{
card->rom_size = 0;
card->rom = 0;
return false;
}
card->rom_size = ((pci_rom_header_t *)card->rom)->rom_size * 512;
card->rom_size = ((option_rom_header_t *)card->rom)->rom_size * 512;
close(fd);
bool read_vbios(bool from_pci)
{
pci_rom_header_t *rom_addr;
option_rom_header_t *rom_addr;
if (from_pci)
{
rom_addr = (pci_rom_header_t *)(pci_config_read32(card->pci_dev->dev.addr, PCI_ROM_ADDRESS) & ~0x7ff);
rom_addr = (option_rom_header_t *)(pci_config_read32(card->pci_dev->dev.addr, PCI_ROM_ADDRESS) & ~0x7ff);
verbose(" @0x%x", rom_addr);
}
else
rom_addr = (pci_rom_header_t *)0xc0000;
rom_addr = (option_rom_header_t *)0xc0000;
if (!validate_rom(rom_addr, card->pci_dev))
return false;
if (radeon_cards[i].device_id == pci_dev->device_id)
{
card->info = &radeon_cards[i];
if ((radeon_cards[i].subsys_id == 0x00000000) ||
if ((radeon_cards[i].subsys_id == 0x00000000) ||
(radeon_cards[i].subsys_id == pci_dev->subsys_id.subsys_id))
break;
}
card->mmio= (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_2) & ~0x0f);
card->io= (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_4) & ~0x03);
verbose("Framebuffer @0x%08X MMIO @0x%08X I/O Port @0x%08X ROM Addr @0x%08X\n",
verbose("Framebuffer @0x%08X MMIO @0x%08X I/O Port @0x%08X ROM Addr @0x%08X\n",
card->fb, card->mmio, card->io, pci_config_read32(pci_dev->dev.addr, PCI_ROM_ADDRESS));
card->posted= radeon_card_posted();
verbose("ATI card %s, ", card->posted ? "POSTed" : "non-POSTed");
get_vram_size();
getBoolForKey(kATYbinimage, &add_vbios, &bootInfo->bootConfig);
stringlength = string->length;
/* ------------------------------------------------- */
verbose("ATI %s %s %dMB (%s) [%04x:%04x] (subsys [%04x:%04x]):: %s\n",
chip_family_name[card->info->chip_family], card->info->model_name,
(uint32_t)(card->vram_size / (1024 * 1024)), card_configs[card->info->cfg_name].name,
verbose("ATI %s %s %dMB (%s) [%04x:%04x] (subsys [%04x:%04x]):: %s\n",
chip_family_name[card->info->chip_family], card->info->model_name,
(uint32_t)(card->vram_size / (1024 * 1024)), card_configs[card->info->cfg_name].name,
ati_dev->vendor_id, ati_dev->device_id,
ati_dev->subsys_id.subsys.vendor_id, ati_dev->subsys_id.subsys.device_id,
ati_dev->subsys_id.subsys.vendor_id, ati_dev->subsys_id.subsys.device_id,
devicepath);
free(card);
branches/Chimera/i386/libsaio/load.c
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(vmaddr + vmsize) <= (HIB_ADDR + HIB_LEN)))) {
stop("Kernel overflows available space");
}
if (vmsize && ((strcmp(segname, "__PRELINK_INFO") == 0) || (strcmp(segname, "__PRELINK") == 0)))
if (vmsize && ((strcmp(segname, "__PRELINK_INFO") == 0) || (strcmp(segname, "__PRELINK") == 0)))
gHaveKernelCache = true;
// Copy from file load area.
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#include "platform.h"
#include "cpu.h"
#include "mem.h"
#include "spd.h"
#include "dram_controllers.h"
if (dram_controller_dev!=NULL) {
scan_dram_controller(dram_controller_dev); // Rek: pci dev ram controller direct and fully informative scan ...
}
scan_memory(&Platform); // unfortunately still necesary for some comp where spd cant read correct speed
scan_spd(&Platform);
//getc();
}
done = true;
}
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#include "libsaio.h"
#include "platform.h"
#include "cpu.h"
#include "bootstruct.h"
#include "boot.h"
#ifndef DEBUG_CPU
#define DEBUG_CPU 0
{
uint64_ttscFrequency, fsbFrequency, cpuFrequency;
uint64_tmsr, flex_ratio;
uint8_tmaxcoef, maxdiv, currcoef, currdiv;
maxcoef = maxdiv = currcoef = currdiv = 0;
uint8_tmaxcoef, maxdiv, currcoef, bus_ratio_max, currdiv;
const char *newratio;
int len, myfsb;
uint8_t bus_ratio_min;
uint32_t max_ratio, min_ratio;
max_ratio = min_ratio = myfsb = bus_ratio_min = 0;
maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;
/* get cpuid values */
do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);
do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);
if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {
do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);
}
#if DEBUG_CPU
{
inti;
p->CPU.ExtModel= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);
p->CPU.ExtFamily= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);
p->CPU.Model += (p->CPU.ExtModel << 4);
if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && (p->CPU.Family == 0x06) && (p->CPU.Model >= 0x1a)){
msr = rdmsr64(MSR_CORE_THREAD_COUNT);// Undocumented MSR in Nehalem and newer CPUs
p->CPU.NoCores= bitfield((uint32_t)msr, 31, 16);// Using undocumented MSR to get actual values
p->CPU.NoThreads= bitfield((uint32_t)msr, 15, 0);// Using undocumented MSR to get actual values
p->CPU.Model += (p->CPU.ExtModel << 4);
if (p->CPU.Vendor == 0x756E6547 /* Intel */ && p->CPU.Family == 0x06 && p->CPU.Model >= 0x1a){
msr = rdmsr64(MSR_CORE_THREAD_COUNT);// Undocumented MSR in Nehalem and newer CPUs
p->CPU.NoCores= bitfield((uint32_t)msr, 31, 16);// Using undocumented MSR to get actual values
p->CPU.NoThreads= bitfield((uint32_t)msr, 15, 0);// Using undocumented MSR to get actual values
} else {
p->CPU.NoThreads= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);// Use previous method for Cores and Threads
p->CPU.NoCores= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;
p->CPU.NoThreads= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);// Use previous method for Cores and Threads
p->CPU.NoCores= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;
}
/* get brand string (if supported) */
/* Copyright: from Apple's XNU cpuid.c */
if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {
p->CPU.BrandString[0] = '\0';
}
}
/* setup features */
p->CPU.Features |= (CPU_FEATURE_MMX | CPU_FEATURE_SSE | CPU_FEATURE_SSE2 | CPU_FEATURE_MSR | CPU_FEATURE_APIC | CPU_FEATURE_TM1 | CPU_FEATURE_ACPI) & p->CPU.CPUID[CPUID_1][3];
p->CPU.Features |= (CPU_FEATURE_SSE3 | CPU_FEATURE_SSE41 | CPU_FEATURE_SSE42 | CPU_FEATURE_EST | CPU_FEATURE_TM2 | CPU_FEATURE_SSSE3 | CPU_FEATURE_xAPIC) & p->CPU.CPUID[CPUID_1][2];
p->CPU.Features |= (CPU_FEATURE_EM64T | CPU_FEATURE_XD) & p->CPU.CPUID[CPUID_81][3];
p->CPU.Features |= (CPU_FEATURE_LAHF) & p->CPU.CPUID[CPUID_81][2];
if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {
p->CPU.Features |= CPU_FEATURE_MMX;
}
if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {
p->CPU.Features |= CPU_FEATURE_SSE;
}
if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {
p->CPU.Features |= CPU_FEATURE_SSE2;
}
if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {
p->CPU.Features |= CPU_FEATURE_SSE3;
}
if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {
p->CPU.Features |= CPU_FEATURE_SSE41;
}
if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {
p->CPU.Features |= CPU_FEATURE_SSE42;
}
if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {
p->CPU.Features |= CPU_FEATURE_EM64T;
}
if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {
p->CPU.Features |= CPU_FEATURE_MSR;
}
//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {
if (p->CPU.NoThreads > p->CPU.NoCores) {
p->CPU.Features |= CPU_FEATURE_HTT;
}
cpuFrequency = 0;
if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {
int intelCPU = p->CPU.Model;
if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {
/* Nehalem CPU model */
if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM || p->CPU.Model == CPU_MODEL_FIELDS
|| p->CPU.Model == CPU_MODEL_DALES || p->CPU.Model == CPU_MODEL_DALES_32NM || p->CPU.Model == CPU_MODEL_SANDY_BRIDGE
|| p->CPU.Model == CPU_MODEL_WESTMERE || p->CPU.Model == CPU_MODEL_NEHALEM_EX)) {
if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM ||
p->CPU.Model == CPU_MODEL_FIELDS ||
p->CPU.Model == CPU_MODEL_DALES ||
p->CPU.Model == CPU_MODEL_DALES_32NM ||
p->CPU.Model == CPU_MODEL_WESTMERE ||
p->CPU.Model == CPU_MODEL_NEHALEM_EX ||
p->CPU.Model == CPU_MODEL_WESTMERE_EX ||
p->CPU.Model == CPU_MODEL_SANDY ||
p->CPU.Model == CPU_MODEL_SANDY_XEON)) {
msr = rdmsr64(MSR_PLATFORM_INFO);
DBG("msr(%d): platform_info %08x\n", __LINE__, msr & 0xffffffff);
currcoef = (msr >> 8) & 0xff;
bus_ratio_max = (msr >> 8) & 0xff;
bus_ratio_min = (msr >> 40) & 0xff; //valv: not sure about this one (Remarq.1)
msr = rdmsr64(MSR_FLEX_RATIO);
DBG("msr(%d): flex_ratio %08x\n", __LINE__, msr & 0xffffffff);
if ((msr >> 16) & 0x01) {
flex_ratio = (msr >> 8) & 0xff;
if (currcoef > flex_ratio) {
currcoef = flex_ratio;
/* bcc9: at least on the gigabyte h67ma-ud2h,
where the cpu multipler can't be changed to
allow overclocking, the flex_ratio msr has unexpected (to OSX)
contents. These contents cause mach_kernel to
fail to compute the bus ratio correctly, instead
causing the system to crash since tscGranularity
is inadvertently set to 0.
*/
if (flex_ratio == 0) {
/* Clear bit 16 (evidently the
presence bit) */
wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));
msr = rdmsr64(MSR_FLEX_RATIO);
verbose("Unusable flex ratio detected. Patched MSR now %08x\n", msr & 0xffffffff);
} else {
if (bus_ratio_max > flex_ratio) {
bus_ratio_max = flex_ratio;
}
}
}
if (currcoef) {
fsbFrequency = (tscFrequency / currcoef);
if (bus_ratio_max) {
fsbFrequency = (tscFrequency / bus_ratio_max);
}
cpuFrequency = tscFrequency;
//valv: Turbo Ratio Limit
if ((intelCPU != 0x2e) && (intelCPU != 0x2f)) {
msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);
cpuFrequency = bus_ratio_max * fsbFrequency;
max_ratio = bus_ratio_max * 10;
} else {
cpuFrequency = tscFrequency;
}
if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->bootConfig)) && (len <= 4)) {
max_ratio = atoi(newratio);
max_ratio = (max_ratio * 10);
if (len >= 3) max_ratio = (max_ratio + 5);
verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);
// extreme overclockers may love 320 ;)
if ((max_ratio >= min_ratio) && (max_ratio <= 320)) {
cpuFrequency = (fsbFrequency * max_ratio) / 10;
if (len >= 3) maxdiv = 1;
else maxdiv = 0;
} else {
max_ratio = (bus_ratio_max * 10);
}
}
//valv: to be uncommented if Remarq.1 didn't stick
/*if(bus_ratio_max > 0) bus_ratio = flex_ratio;*/
p->CPU.MaxRatio = max_ratio;
p->CPU.MinRatio = min_ratio;
myfsb = fsbFrequency / 1000000;
verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio);
currcoef = bus_ratio_max;
} else {
msr = rdmsr64(MSR_IA32_PERF_STATUS);
DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, msr & 0xffffffff);
}
}
}
/* Mobile CPU */
if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28)) {
/* Mobile CPU ? */
if (rdmsr64(0x17) & (1<<28)) {
p->CPU.Features |= CPU_FEATURE_MOBILE;
}
}
p->CPU.FSBFrequency = fsbFrequency;
p->CPU.CPUFrequency = cpuFrequency;
DBG("CPU: Brand String: %s\n",p->CPU.BrandString);
DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n",p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);
DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n",p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);
DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n",p->CPU.MaxCoef, p->CPU.CurrCoef);
DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n",p->CPU.MaxDiv, p->CPU.CurrDiv);
DBG("CPU: TSCFreq: %dMHz\n",p->CPU.TSCFrequency / 1000000);
DBG("CPU: FSBFreq: %dMHz\n",p->CPU.FSBFrequency / 1000000);
DBG("CPU: CPUFreq: %dMHz\n",p->CPU.CPUFrequency / 1000000);
DBG("CPU: NoCores/NoThreads: %d/%d\n",p->CPU.NoCores, p->CPU.NoThreads);
DBG("CPU: Features: 0x%08x\n",p->CPU.Features);
DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel);
DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily);
DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);
DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);
DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);
DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);
DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);
DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);
DBG("CPU: Features: 0x%08x\n", p->CPU.Features);
#if DEBUG_CPU
pause();
#endif
branches/Chimera/i386/libsaio/platform.h
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extern void scan_platform(void);
extern void dumpPhysAddr(const char * title, void * a, int len);
#define bit(n)(1UL << (n))
#define bitmask(h,l)((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
#define bitfield(x,h,l)(((x) & bitmask(h,l)) >> l)
/* CPUID index into cpuid_raw */
#define CPUID_00
#define CPUID_11
#define CPUID_816
#define CPUID_MAX7
#define CPU_MODEL_YONAH0x0E// Sossaman, Yonah
#define CPU_MODEL_MEROM0x0F// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom
#define CPU_MODEL_PENRYN0x17// Wolfdale, Yorkfield, Harpertown, Penryn
#define CPU_MODEL_NEHALEM0x1A// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown
#define CPU_MODEL_ATOM0x1C// Atom
#define CPU_MODEL_DUNNINGTON0x1D// Dunnington
#define CPU_MODEL_FIELDS0x1E// Lynnfield, Clarksfield, Jasper Forest
#define CPU_MODEL_DALES0x1F// Havendale, Auburndale
#define CPU_MODEL_DALES_32NM0x25// Clarkdale, Arrandale: Dual core
#define CPU_MODEL_SANDY_BRIDGE0x2A// Sandy Bridge
#define CPU_MODEL_WESTMERE0x2C// Gulftown, Westmere-EP, Westmere-WS
#define CPU_MODEL_NEHALEM_EX0x2E// Beckton
#define CPU_MODEL_YONAH0x0E
#define CPU_MODEL_MEROM0x0F
#define CPU_MODEL_PENRYN0x17
#define CPU_MODEL_NEHALEM0x1A
#define CPU_MODEL_ATOM0x1C
#define CPU_MODEL_FIELDS0x1E/* Lynnfield, Clarksfield, Jasper */
#define CPU_MODEL_DALES0x1F/* Havendale, Auburndale */
#define CPU_MODEL_DALES_32NM0x25/* Clarkdale, Arrandale */
#define CPU_MODEL_SANDY0x2a/* Sandy bridge */
#define CPU_MODEL_WESTMERE0x2C/* Gulftown, Westmere-EP, Westmere-WS */
#define CPU_MODEL_SANDY_XEON0x2D
#define CPU_MODEL_NEHALEM_EX0x2E
#define CPU_MODEL_WESTMERE_EX0x2F
/* CPU Features */
// NOTE: These are currently mapped to the actual bit in the cpuid value
#define CPU_FEATURE_MMXbit(23)// MMX Instruction Set
#define CPU_FEATURE_SSEbit(25)// SSE Instruction Set
#define CPU_FEATURE_SSE2bit(26)// SSE2 Instruction Set
#define CPU_FEATURE_SSE3bit(0)// SSE3 Instruction Set
#define CPU_FEATURE_SSE41bit(19)// SSE41 Instruction Set
#define CPU_FEATURE_SSE42bit(20)// SSE42 Instruction Set
#define CPU_FEATURE_EM64Tbit(29)// 64Bit Support
#define CPU_FEATURE_HTTbit(28)// HyperThreading
#define CPU_FEATURE_MSRbit(5)// MSR Support
#define CPU_FEATURE_APICbit(9)// On-chip APIC Hardware
#define CPU_FEATURE_ESTbit(7)// Enhanced Intel SpeedStep
#define CPU_FEATURE_TM2bit(8)// Thermal Monitor 2
#define CPU_FEATURE_TM1bit(29)// Thermal Monitor 1
#define CPU_FEATURE_SSSE3bit(9)// Supplemental SSE3 Instruction Set
#define CPU_FEATURE_xAPICbit(21)// Extended APIC Mode
#define CPU_FEATURE_ACPIbit(22)// Thermal Monitor and Software Controlled Clock
#define CPU_FEATURE_LAHFbit(20)// LAHF/SAHF Instructions
#define CPU_FEATURE_XDbit(20)// Execute Disable
#define CPU_FEATURE_MMX0x00000001// MMX Instruction Set
#define CPU_FEATURE_SSE0x00000002// SSE Instruction Set
#define CPU_FEATURE_SSE20x00000004// SSE2 Instruction Set
#define CPU_FEATURE_SSE30x00000008// SSE3 Instruction Set
#define CPU_FEATURE_SSE410x00000010// SSE41 Instruction Set
#define CPU_FEATURE_SSE420x00000020// SSE42 Instruction Set
#define CPU_FEATURE_EM64T0x00000040// 64Bit Support
#define CPU_FEATURE_HTT0x00000080// HyperThreading
#define CPU_FEATURE_MOBILE0x00000100// Mobile CPU
#define CPU_FEATURE_MSR0x00000200// MSR Support
// NOTE: Determine correct bit for below (28 is already in use)
#define CPU_FEATURE_MOBILEbit(1)// Mobile CPU
/* SMBIOS Memory Types */
#define SMB_MEM_TYPE_UNDEFINED0
#define SMB_MEM_TYPE_OTHER1
#define SMB_MEM_TYPE_DDR18
#define SMB_MEM_TYPE_DDR219
#define SMB_MEM_TYPE_FBDIMM20
#define SMB_MEM_TYPE_DDR324// Supported in 10.5.6+ AppleSMBIOS
#define SMB_MEM_TYPE_DDR324// Supported in 10.5.6+ AppleSMBIOS
/* Memory Configuration Types */
#define SMB_MEM_CHANNEL_UNKNOWN0
#define UUID_LEN16
typedef struct _RamSlotInfo_t {
uint32_tModuleSize;// Size of Module in MB
uint32_tFrequency;// in Mhz
uint32_tModuleSize;// Size of Module in MB
uint32_tFrequency; // in Mhz
const char*Vendor;
const char*PartNo;
const char*SerialNo;
char*spd;// SPD Dump
char*spd;// SPD Dump
boolInUse;
uint8_tType;
uint8_tBankConnections;// table type 6, see (3.3.7)
uint8_tBankConnections; // table type 6, see (3.3.7)
uint8_tBankConnCnt;
} RamSlotInfo_t;
typedef struct _PlatformInfo_t {
struct CPU {
uint32_tFeatures;// CPU Features like MMX, SSE2, VT, MobileCPU
uint32_tVendor;// Vendor
uint32_tSignature;// Signature
uint32_tStepping;// Stepping
uint32_tModel;// Model
uint32_tExtModel;// Extended Model
uint32_tFamily;// Family
uint32_tExtFamily;// Extended Family
uint32_tNoCores;// No Cores per Package
uint32_tNoThreads;// Threads per Package
uint8_tMaxCoef;// Max Multiplier
uint32_tFeatures;// CPU Features like MMX, SSE2, VT, MobileCPU
uint32_tVendor;// Vendor
uint32_tSignature;// Signature
uint32_tStepping;// Stepping
uint32_tModel;// Model
uint32_tExtModel;// Extended Model
uint32_tFamily;// Family
uint32_tExtFamily;// Extended Family
uint32_tNoCores;// No Cores per Package
uint32_tNoThreads;// Threads per Package
uint8_tMaxCoef;// Max Multiplier
uint8_tMaxDiv;
uint8_tCurrCoef;// Current Multiplier
uint8_tCurrCoef;// Current Multiplier
uint8_tCurrDiv;
uint64_tTSCFrequency;// TSC Frequency Hz
uint64_tFSBFrequency;// FSB Frequency Hz
uint64_tCPUFrequency;// CPU Frequency Hz
charBrandString[48];// 48 Byte Branding String
uint64_tTSCFrequency;// TSC Frequency Hz
uint64_tFSBFrequency;// FSB Frequency Hz
uint64_tCPUFrequency;// CPU Frequency Hz
uint32_tMaxRatio;// Max Bus Ratio
uint32_tMinRatio;// Min Bus Ratio
charBrandString[48];// 48 Byte Branding String
uint32_tCPUID[CPUID_MAX][4];// CPUID 0..4, 80..81 Raw Values
} CPU;
} RAM;
struct DMI {
intMaxMemorySlots;// number of memory slots polulated by SMBIOS
intCntMemorySlots;// number of memory slots counted
intMemoryModules;// number of memory modules installed
intDIMM[MAX_RAM_SLOTS];// Information and SPD mapping for each slot
intMaxMemorySlots;// number of memory slots polulated by SMBIOS
intCntMemorySlots;// number of memory slots counted
intMemoryModules;// number of memory modules installed
intDIMM[MAX_RAM_SLOTS];// Information and SPD mapping for each slot
} DMI;
uint8_tType;// System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)
uint8_tType;// System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)
uint8_t*UUID;
} PlatformInfo_t;
extern PlatformInfo_t Platform;
branches/Chimera/i386/libsaio/pci_setup.c
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#include "boot.h"
#include "bootstruct.h"
#include "pci.h"
#include "nvidia.h"
extern bool setup_nvidia_devprop(pci_dt_t *nvda_dev);
extern bool setup_ati_devprop(pci_dt_t *ati_dev);
extern void set_eth_builtin(pci_dt_t *eth_dev);
extern void notify_usb_dev(pci_dt_t *pci_dev);
switch (current->vendor_id)
{
case PCI_VENDOR_ID_ATI:
verbose("ATI VGA Controller [%04x:%04x] :: %s \n",
current->vendor_id, current->device_id, devicepath);
setup_ati_devprop(current);
break;
branches/Chimera/i386/libsaio/cpu.h
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extern void scan_cpu(PlatformInfo_t *);
#define bit(n)(1UL << (n))
#define bit(n)(1UL << (n))
#define bitmask(h,l)((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
#define bitfield(x,h,l)(((x) & bitmask(h,l)) >> l)
#define CPU_STRING_UNKNOWN"Unknown CPU Typ"
#define CPU_STRING_UNKNOWN"Unknown CPU Typ"
#define MSR_CORE_THREAD_COUNT0x35// Undocumented
#define MSR_EBC_FREQUENCY_ID0x2C// valv
#define MSR_EBL_CR_POWERON0x2A// valv
#define MSR_FLEX_RATIO0x194
#define MSR_FSB_FREQ0xCD// valv
#define MSR_IA32_CLOCK_MODULATION0x19A// valv
#define MSR_IA32_EXT_CONFIG0xEE
#define MSR_IA32_MISC_ENABLE0x1A0// valv
#define MSR_IA32_PERF_CONTROL0x199
#defineMSR_IA32_PERF_STATUS0x198
#define MSR_IA32_PLATFORM_ID0x17// valv
#defineMSR_PLATFORM_INFO0xCE
#define MSR_THERMAL_STATUS0x19C// valv
#define MSR_THERMAL_TARGET0x1A2// valv
#define MSR_TURBO_RATIO_LIMIT0x1AD// valv
#define MSR_MISC_PWR_MGMT0x1AA// valv
#defineMSR_IA32_PERF_STATUS0x198
#define MSR_IA32_PERF_CONTROL0x199
#define MSR_IA32_EXT_CONFIG0x00EE
#define MSR_FLEX_RATIO0x194
#define MSR_TURBO_RATIO_LIMIT0x1AD
#defineMSR_PLATFORM_INFO0xCE
#define MSR_CORE_THREAD_COUNT0x35// Undocumented
#define K8_FIDVID_STATUS0xC0010042
#define K10_COFVID_STATUS0xC0010071
#defineMSR_AMD_10H_11H_LIMIT0xc0010061// valv
#defineAMD_10H_11H_CONFIG0xc0010064// valv
#define K8_FIDVID_STATUS0xC0010042
#define K10_COFVID_STATUS0xC0010071
#define DEFAULT_FSB100000/* for now, hardcoding 100MHz for old CPUs */
#define DEFAULT_FSB100000 /* for now, hardcoding 100MHz for old CPUs */
// DFE: This constant comes from older xnu:
#define CLKNUM1193182/* formerly 1193167 */
#define CLKNUM1193182/* formerly 1193167 */
// DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM
#define CALIBRATE_TIME_MSEC30/* 30 msecs */
#define CALIBRATE_LATCH((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)
#define CALIBRATE_TIME_MSEC30/* 30 msecs */
#define CALIBRATE_LATCH((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)
static inline uint64_t rdtsc64(void)
{
__asm__ volatile("wrmsr" : : "c" (msr), "A" (val));
}
typedef struct msr_struct
{
unsigned lo;
unsigned hi;
} msr_t;
static inline __attribute__((always_inline)) msr_t rdmsr(unsigned val)
{
msr_t ret;
__asm__ volatile(
"rdmsr"
: "=a" (ret.lo), "=d" (ret.hi)
: "c" (val)
);
return ret;
}
static inline __attribute__((always_inline)) void wrmsr(unsigned val, msr_t msr)
{
__asm__ __volatile__ (
"wrmsr"
: /* No outputs */
: "c" (val), "a" (msr.lo), "d" (msr.hi)
);
}
static inline void intel_waitforsts(void) {
uint32_t inline_timeout = 100000;
while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; }
{
/* Enable gate, disable speaker */
__asm__ volatile(
" inb $0x61,%%al \n\t"
" and $0xFC,%%al \n\t" /* & ~0x03 */
" or $1,%%al \n\t"
" outb %%al,$0x61 \n\t"
" inb $0x61,%%al \n\t"
" and $0xFC,%%al \n\t" /* & ~0x03 */
" or $1,%%al \n\t"
" outb %%al,$0x61 \n\t"
: : : "%al" );
}
{
/* Disable gate and output to speaker */
__asm__ volatile(
" inb $0x61,%%al \n\t"
" and $0xFC,%%al \n\t"/* & ~0x03 */
" outb %%al,$0x61 \n\t"
" inb $0x61,%%al \n\t"
" and $0xFC,%%al \n\t"/* & ~0x03 */
" outb %%al,$0x61 \n\t"
: : : "%al" );
}
static inline void set_PIT2_mode0(uint16_t value)
{
__asm__ volatile(
" movb $0xB0,%%al \n\t"
" outb%%al,$0x43 \n\t"
" movb%%dl,%%al \n\t"
" outb%%al,$0x42 \n\t"
" movb%%dh,%%al \n\t"
" movb $0xB0,%%al \n\t"
" outb%%al,$0x43\n\t"
" movb%%dl,%%al\n\t"
" outb%%al,$0x42\n\t"
" movb%%dh,%%al\n\t"
" outb%%al,$0x42"
: : "d"(value) /*: no clobber */ );
}
branches/Chimera/i386/libsaio/pci.c
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}
new = (pci_dt_t*)malloc(sizeof(pci_dt_t));
bzero(new, sizeof(pci_dt_t));
new->dev.addr= pci_addr;
new->vendor_id= id & 0xffff;
new->device_id= (id >> 16) & 0xffff;
new->subsys_id.subsys_id = pci_config_read32(pci_addr, PCI_SUBSYSTEM_VENDOR_ID);
new->class_id= pci_config_read16(pci_addr, PCI_CLASS_DEVICE);
new->dev.addr= pci_addr;
new->vendor_id= id & 0xffff;
new->device_id= (id >> 16) & 0xffff;
new->subsys_id.subsys_id= pci_config_read32(pci_addr, PCI_SUBSYSTEM_VENDOR_ID);
new->class_id= pci_config_read16(pci_addr, PCI_CLASS_DEVICE);
new->parent= start;
header_type = pci_config_read8(pci_addr, PCI_HEADER_TYPE);
bzero(root_pci_dev, sizeof(pci_dt_t));
enable_pci_devs();
scan_pci_bus(root_pci_dev, 0);
#if DEBUG_PCI
dump_pci_dt(root_pci_dev->children);
pause();
current = pci_dt;
while (current) {
printf("%02x:%02x.%x [%04x] [%04x:%04x] (subsys [%04x:%04x]):: %s\n",
printf("%02x:%02x.%x [%04x] [%04x:%04x] (subsys [%04x:%04x]):: %s\n",
current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func,
current->class_id, current->vendor_id, current->device_id,
current->subsys_id.subsys.vendor_id, current->subsys_id.subsys.device_id,
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} pci_dev_t;
typedef struct pci_dt_t {
pci_dev_tdev;
pci_dev_tdev;
uint16_tvendor_id;
uint16_tdevice_id;
uint16_tvendor_id;
uint16_tdevice_id;
union {
struct {
uint16_tvendor_id;
uint16_tdevice_id;
} subsys;
}subsys;
uint32_tsubsys_id;
} subsys_id;
uint16_tclass_id;
}subsys_id;
struct pci_dt_t*parent;
struct pci_dt_t*children;
struct pci_dt_t*next;
uint16_tclass_id;
struct pci_dt_t*parent;
struct pci_dt_t*children;
struct pci_dt_t*next;
} pci_dt_t;
#define PCIADDR(bus, dev, func)(1 << 31) | (bus << 16) | (dev << 11) | (func << 8)
extern uint8_tpci_config_read8(uint32_t, uint8_t);
extern uint16_tpci_config_read16(uint32_t, uint8_t);
extern uint32_tpci_config_read32(uint32_t, uint8_t);
extern voidpci_config_write8(uint32_t, uint8_t, uint8_t);
extern voidpci_config_write16(uint32_t, uint8_t, uint16_t);
extern voidpci_config_write32(uint32_t, uint8_t, uint32_t);
extern char*get_pci_dev_path(pci_dt_t *);
extern voidbuild_pci_dt(void);
extern voiddump_pci_dt(pci_dt_t *);
extern voidpci_config_write8(uint32_t, uint8_t, uint8_t);
extern voidpci_config_write16(uint32_t, uint8_t, uint16_t);
extern voidpci_config_write32(uint32_t, uint8_t, uint32_t);
extern char*get_pci_dev_path(pci_dt_t *);
extern voidbuild_pci_dt(void);
extern voiddump_pci_dt(pci_dt_t *);
//-----------------------------------------------------------------------------
// added by Kabyl, name changed to follow trunk naming scheme
/* Option ROM header */
typedef struct {
uint16_tsignature;// 0xAA55
uint8_treserved[15];
uint16_tpci_header_offset;
uint16_texpansion_header_offset;
} pci_rom_header_t;
} option_rom_header_t;
/* Option ROM PCI Data Structure */
typedef struct {
uint32_tsignature;// 0x52494350'PCIR'
uint16_tvendor_id;
uint16_tdevice_id;
uint16_tvital_product_data_offset;
uint16_tstructure_length;
uint8_tstructure_revision;
uint8_tclass_code[3];
uint16_timage_length;
uint16_timage_revision;
uint8_tcode_type;
uint8_tindicator;
uint16_treserved;
} option_rom_pci_header_t;
//-----------------------------------------------------------------------------
// added by iNDi
struct pci_rom_pci_header_t {
uint32_tsignature;// 0x50434952 'PCIR'
uint16_tvendor_id;
uint16_tdevice_id;
uint16_tproduct;
uint16_tlength;
uint8_trevision;// 0 = PCI 2.1
uint8_tclass[3];
uint16_trom_size;
uint16_tcode_revision;
uint8_tcode_type;// 0 = x86
uint8_tlast_image;// 0x80
uint16_treserverd;
};
struct pci_rom_pnp_header_t {
typedef struct {
uint32_tsignature;// 0x24506E50 '$PnP'
uint8_trevision;// 1
uint8_tlength;//
uint16_tbootstrap_vector;
uint16_treserved;
uint16_tresource_vector;
};
} option_rom_pnp_header_t;
struct pci_rom_bios_t {
uint16_tsignature;// 0x55AA
uint8_tsize;// Multiples of 512
uint8_tchecksum;// 0x00
uint16_tpci_header;
uint16_tpnp_header;
};
/*
* Under PCI, each device has 256 bytes of configuration address space,
* of which the first 64 bytes are standardized as follows:
branches/Chimera/i386/libsaio/saio_types.h
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struct Tag {
long type;
char *string;
long offset;
struct Tag *tag;
struct Tag *tagNext;
};
unsigned char dev_path[8];
unsigned char reserved3;
unsigned char checksum;
} params __attribute__((packed));
} params;
struct drive_dpte {
unsigned short io_port_base;
unsigned short control_port_base;
unsigned short reserved;
unsigned char revision;
unsigned char checksum;
} dpte __attribute__((packed));
} dpte;
} __attribute__((packed));
typedef struct boot_drive_info boot_drive_info_t;
enum {
kNetworkDeviceType = kBIOSDevTypeNetwork,
kBlockDeviceType = kBIOSDevTypeHardDrive
} gBootFileType_t;
}; //gBootFileType_t;
enum {
kCursorTypeHidden = 0x0100,
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* edited for clarity and style only.
*/
#include <sys/types.h>
#include "libsaio.h"
#ifdef KERNEL
#include <sys/systm.h>
#else
#include <string.h>
#endif
#if MAC_OS_X_VERSION_MAX_ALLOWED >= MAC_OS_X_VERSION_10_5
# include <Kernel/libkern/crypto/md5.h>
#else
#endif
#ifdef KERNEL
#define memset(x,y,z)bzero(x,z);
#define memcpy(x,y,z)bcopy(y, x, z)
#endif
#if defined(__i386__) || defined(__alpha__)
#define Encode memcpy
#define Decode memcpy
#else /* __i386__ */
/*
* Encodes input (u_int32_t) into output (unsigned char). Assumes len is
* a multiple of 4.
*/
/* XXX not prototyped, and not compatible with memcpy(). */
static void
Encode (output, input, len)
unsigned char *output;
u_int32_t *input;
unsigned int len;
{
unsigned int i, j;
for (i = 0, j = 0; j < len; i++, j += 4) {
output[j] = (unsigned char)(input[i] & 0xff);
output[j+1] = (unsigned char)((input[i] >> 8) & 0xff);
output[j+2] = (unsigned char)((input[i] >> 16) & 0xff);
output[j+3] = (unsigned char)((input[i] >> 24) & 0xff);
}
}
/*
* Decodes input (unsigned char) into output (u_int32_t). Assumes len is
* a multiple of 4.
*/
static void
Decode (output, input, len)
u_int32_t *output;
const unsigned char *input;
unsigned int len;
{
unsigned int i, j;
for (i = 0, j = 0; j < len; i++, j += 4)
output[i] = ((u_int32_t)input[j]) | (((u_int32_t)input[j+1]) << 8) |
(((u_int32_t)input[j+2]) << 16) | (((u_int32_t)input[j+3]) << 24);
}
#endif /* i386 */
static unsigned char PADDING[64] = {
0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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#include "efi_tables.h"
#include "platform.h"
#include "acpi_patcher.h"
#include "smbios_patcher.h"
#include "smbios.h"
#include "device_inject.h"
#include "convert.h"
#include "pci.h"
#include "sl.h"
extern struct SMBEntryPoint * getSmbios(int which); // now cached
extern void setup_pci_devs(pci_dt_t *pci_dt);
/*
*/
/* Identify ourselves as the EFI firmware vendor */
static EFI_CHAR16 const FIRMWARE_VENDOR[] = {'A','p','p','l','e'};
static EFI_UINT32 const FIRMWARE_REVISION = 0x0001000a;
//static EFI_CHAR16 const FIRMWARE_VENDOR[] = {'C','h','i','m','e','r','a','_','1','.','1', 0};
//static EFI_UINT32 const FIRMWARE_REVISION = 132; /* FIXME: Find a constant for this. */
static EFI_CHAR16 const FIRMWARE_VENDOR[] = {'C','h','a','m','e','l','e','o','n','_','2','.','0', 0};
static EFI_UINT32 const FIRMWARE_REVISION = 132; /* FIXME: Find a constant for this. */
/* Default platform system_id (fix by IntVar) */
static EFI_CHAR8 const SYSTEM_ID[] = "0123456789ABCDEF"; //random value gen by uuidgen
//Azi: crc32 done in place, on the cases were it wasn't.
/*static inline void fixupEfiSystemTableCRC32(EFI_SYSTEM_TABLE_64 *efiSystemTable)
{
efiSystemTable->Hdr.CRC32 = 0;
efiSystemTable->Hdr.CRC32 = crc32(0L, efiSystemTable, efiSystemTable->Hdr.HeaderSize);
}*/
{
efiSystemTable->Hdr.CRC32 = 0;
efiSystemTable->Hdr.CRC32 = crc32(0L, efiSystemTable, efiSystemTable->Hdr.HeaderSize);
}*/
/*
* What we do here is simply allocate a fake EFI system table and a fake EFI
#define SMBIOS_ANCHOR_UINT32_LE 0x5f4d535f
#define EFI_ACPI_TABLE_GUID \
{ \
0xeb9d2d30, 0x2d88, 0x11d3, { 0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
}
{ \
0xeb9d2d30, 0x2d88, 0x11d3, { 0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
}
#define EFI_ACPI_20_TABLE_GUID \
{ \
0x8868e871, 0xe4f1, 0x11d3, { 0xbc, 0x22, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
{ \
0x8868e871, 0xe4f1, 0x11d3, { 0xbc, 0x22, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
EFI_GUID gEfiAcpiTableGuid = EFI_ACPI_TABLE_GUID;
EFI_GUID gEfiAcpi20TableGuid = EFI_ACPI_20_TABLE_GUID;
static const char const MODEL_PROP[] = "Model";
static const char const BOARDID_PROP[] = "board-id";
/*
* Get an smbios option string option to convert to EFI_CHAR16 string
*/
{
static EFI_CHAR8 uuid[UUID_LEN];
int i, isZero, isOnes;
struct SMBEntryPoint*smbios;
SMBByte*p;
smbios = getSmbios(SMBIOS_PATCHED); // checks for _SM_ anchor and table header checksum
if (smbios==NULL) return 0; // getSmbios() return a non null value if smbios is found
p = (SMBByte*)Platform.UUID;
p = (SMBByte*) FindFirstDmiTableOfType(1, 0x19); // Type 1: (3.3.2) System Information
if (p==NULL) return NULL;
verbose("Found SMBIOS System Information Table 1\n");
p += 8;
for (i=0, isZero=1, isOnes=1; i<UUID_LEN; i++)
{
if (p[i] != 0x00) isZero = 0;
// belong to smbios config only ...
const char *sysId = getStringForKey(kSystemID, &bootInfo->bootConfig);
EFI_CHAR8*ret = getUUIDFromString(sysId);
if (!sysId || !ret) // try bios dmi info UUID extraction
{
ret = getSmbiosUUID();
{
DT__AddProperty(runtimeServicesNode, "table", sizeof(uint64_t), &gST64->RuntimeServices);
}
// Set up the /efi/configuration-table node which will eventually have several child nodes for
// all of the configuration tables needed by various kernel extensions.
gEfiConfigurationTableNode = DT__AddChild(node, "configuration-table");
// Export system-id. Can be disabled with SystemId=No in com.apple.Boot.plist
if ((ret=getSystemID()))
DT__AddProperty(efiPlatformNode, SYSTEM_ID_PROP, UUID_LEN, (EFI_UINT32*) ret);
// Export SystemSerialNumber if present
// Export SystemSerialNumber if present
if ((ret16=getSmbiosChar16("SMserial", &len)))
DT__AddProperty(efiPlatformNode, SYSTEM_SERIAL_PROP, len, ret16);
void setupBoardId()
{
Node *node;
node = DT__FindNode("/", false);
if (node == 0) {
stop("Couldn't get root node");
}
const char *boardid = getStringForKey("SMboardproduct", &bootInfo->smbiosConfig);
if (boardid)
DT__AddProperty(node, BOARDID_PROP, strlen(boardid)+1, (EFI_CHAR16*)boardid);
}
Node *node;
node = DT__FindNode("/", false);
if (node == 0) {
stop("Couldn't get root node");
}
const char *boardid = getStringForKey("SMboardproduct", &bootInfo->smbiosConfig);
if (boardid)
DT__AddProperty(node, BOARDID_PROP, strlen(boardid)+1, (EFI_CHAR16*)boardid);
}
/*
* Load the smbios.plist override config file if any
err = loadConfigFile(dirSpecSMBIOS, &bootInfo->smbiosConfig);
}
}
if (err)
{
verbose("No SMBIOS replacement found.\n");
}
// get a chance to scan mem dynamically if user asks for it while having the config options loaded as well,
// as opposed to when it was in scan_platform(); also load the orig. smbios so that we can access dmi info without
// patching the smbios yet
getSmbios(SMBIOS_ORIGINAL);
scan_mem();
smbios_p = (EFI_PTR32)getSmbios(SMBIOS_PATCHED);// process smbios asap
}
/*
addConfigurationTable(&gEfiSmbiosTableGuid, &smbios_p, NULL);
setupBoardId(); //need to be called after getSmbios
// Setup ACPI with DSDT overrides (mackerintel's patch)
setupAcpi();
}
}
void saveOriginalSMBIOS(void)
{
Node *node;
SMBEntryPoint *origeps;
void *tableAddress;
node = DT__FindNode("/efi/platform", false);
if (!node)
{
verbose("/efi/platform node not found\n");
return;
}
origeps = getSmbios(SMBIOS_ORIGINAL);
if (!origeps)
{
return;
}
tableAddress = (void *)AllocateKernelMemory(origeps->dmi.tableLength);
if (!tableAddress)
{
return;
}
memcpy(tableAddress, (void *)origeps->dmi.tableAddress, origeps->dmi.tableLength);
DT__AddProperty(node, "SMBIOS", origeps->dmi.tableLength, tableAddress);
}
/*
* Entrypoint from boot.c
*/
{
// Generate efi device strings
setup_pci_devs(root_pci_dev);
readSMBIOSInfo(getSmbios(SMBIOS_ORIGINAL));
// load smbios.plist file if any
setupSmbiosConfigFile("SMBIOS.plist");
setupSmbiosConfigFile("smbios.plist");
setupSMBIOSTable();
// Initialize the base table
if (archCpuType == CPU_TYPE_I386)
{
// Initialize the device tree
setupEfiDeviceTree();
saveOriginalSMBIOS();
// Add configuration table entries to both the services table and the device tree
setupEfiConfigurationTable();
}
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DIR = boot0
include ../MakePaths.dir
NASM = /Developer/usr/bin/nasm
#NASM = /Developer/usr/bin/nasm
NASM =$(shell which nasm)
INSTALLDIR = $(DSTROOT)/usr/standalone/i386
DIRS_NEEDED = $(SYMROOT)
all embedtheme: $(DIRS_NEEDED) boot0 boot0hfs chain0
boot0: boot0.s Makefile $(NASM)
$(NASM) boot0.s -o $(SYMROOT)/$@
boot0: boot0.s
@echo "\t[NASM] $@"
@$(NASM) boot0.s -o $(SYMROOT)/$@
boot0hfs: boot0.s Makefile $(NASM)
$(NASM) boot0.s -DHFSFIRST -o $(SYMROOT)/$@
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chain0: chain0.s Makefile $(NASM)
$(NASM) chain0.s -o $(SYMROOT)/$@
@echo "\t[NASM] $@"
@$(NASM) chain0.s -o $(SYMROOT)/$@
install_i386:: all $(INSTALLDIR)
cp $(SYMROOT)/boot0 $(SYMROOT)/chain0 $(INSTALLDIR)
branches/Chimera/i386/MakeInc.dir
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MKDIRS = /bin/mkdir -p
endif
CPP = g++ -fno-exceptions -fno-rtti
# Toggle this as to whether you want a frame pointer (%ebp) to be used. It is
# invaluable for debugging the booter. For example using GDB attached to VMware.
# In fact, it's so invaluable that it's now the default. Not only that but the
.SUFFIXES: .s .i .c .o .o32 .o64
.c.o32:
$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) -arch i386 $< -o $(OBJROOT)/$*.o32 \
@echo "\t[CC32] $<"
@$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) -arch i386 $< -o $(OBJROOT)/$*.o32 \
-MD -dependency-file $(OBJROOT)/$*.d
md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
@md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
.c.o64:
$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) -arch x86_64 $< -o $(OBJROOT)/$*.o64 \
@echo "\t[CC64] $<"
@$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) -arch x86_64 $< -o $(OBJROOT)/$*.o64 \
-MD -dependency-file $(OBJROOT)/$*.d
md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
@md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
.c.o .m.o:
$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) $< -o $(OBJROOT)/$*.o \
@echo "\t[CC] $<"
@$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) $< -o $(OBJROOT)/$*.o \
-MD -dependency-file $(OBJROOT)/$*.d
md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
@md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
$(OBJROOT)/%.o: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) $< -o $(OBJROOT)/$*.o \
@echo "\t[CC] $<"
@$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) $< -o $(OBJROOT)/$*.o \
-MD -dependency-file $(OBJROOT)/$*.d
md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
@md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
$(OBJROOT)/%.o32: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) -arch i386 $< -o $(OBJROOT)/$*.o32 \
@echo "\t[CC32] $<"
@$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) -arch i386 $< -o $(OBJROOT)/$*.o32 \
-MD -dependency-file $(OBJROOT)/$*.d
md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
@md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
$(OBJROOT)/%.o64: %.c
$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) -arch x86_64 $< -o $(OBJROOT)/$*.o64 \
@echo "\t[CC64] $<"
@$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) -arch x86_64 $< -o $(OBJROOT)/$*.o64 \
-MD -dependency-file $(OBJROOT)/$*.d
md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
@md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
$(OBJROOT)/%.o: %.m
$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) $< -o $(OBJROOT)/$*.o \
@echo "\t[CC] $<"
@$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c $(INC) $< -o $(OBJROOT)/$*.o \
-MD -dependency-file $(OBJROOT)/$*.d
md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
@md -u $(OBJROOT)/Makedep -f -d $(OBJROOT)/$*.d
#.s.o:
#cc $(INC) -E $< > $(OBJROOT)/$*.o2
#$(AS) -o $(OBJROOT)/$@ $(OBJROOT)/$*.o2
.s.o:
cc $(CPPFLAGS) -c $(INC) -arch i386 -o $(OBJROOT)/$(@F) $<
@echo "\t[AS] $<"
@cc $(CPPFLAGS) -c $(INC) -arch i386 -o $(OBJROOT)/$(@F) $<
boot2.o:
cc $(CPPFLAGS) -Wa,-n -c $(INC) -arch i386 -o $(OBJROOT)/$(@F) boot2.s
@echo "\t[AS] boot2.s"
@cc $(CPPFLAGS) -Wa,-n -c $(INC) -arch i386 -o $(OBJROOT)/$(@F) boot2.s
$(OBJROOT)/%.o: %.s
cc $(CPPFLAGS) -c $(INC) -arch i386 -o $(OBJROOT)/$(@F) $<
@echo "\t[CC] $<"
@cc $(CPPFLAGS) -c $(INC) -arch i386 -o $(OBJROOT)/$(@F) $<
$(DIRS_NEEDED) $(INSTALLDIR) $(SRCROOT):
$(MKDIRS) $@
@echo "\t[MKDIR] $@"
@$(MKDIRS) $@
branches/Chimera/i386/boot1/Makefile
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INSTALLDIR = $(DSTROOT)/usr/standalone/i386
DIRS_NEEDED = $(OBJROOT) $(SYMROOT)
NASM = /Developer/usr/bin/nasm
#NASM = /Developer/usr/bin/nasm
NASM = $(shell which nasm)
VERSIONED_FILES = boot1h
all embedtheme: $(DIRS_NEEDED) $(VERSIONED_FILES)
boot1h: boot1.s Makefile
$(NASM) boot1.s -o $(SYMROOT)/boot1h
$(NASM) boot1hp.s -o $(SYMROOT)/boot1hp
$(NASM) boot1he.s -o $(SYMROOT)/boot1he
$(NASM) boot1f32.s -o $(SYMROOT)/boot1f32
@echo "\t[NASM] boot1.s"
@$(NASM) boot1.s -o $(SYMROOT)/boot1h
@echo "\t[NASM] boot1hp.s"
@$(NASM) boot1hp.s -o $(SYMROOT)/boot1hp
@echo "\t[NASM] boot1he.s"
@$(NASM) boot1he.s -o $(SYMROOT)/boot1he
@echo "\t[NASM] boot1f32.s"
@$(NASM) boot1f32.s -o $(SYMROOT)/boot1f32
install_i386:: all $(INSTALLDIR)
cp $(SYMROOT)/boot1h $(INSTALLDIR)/
branches/Chimera/i386/boot2/boot.c
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#include "ramdisk.h"
#include "gui.h"
#include "platform.h"
#include "modules.h"
long gBootMode; /* defaults to 0 == kBootModeNormal */
bool gOverrideKernel;
int ret;
bootArgs->kaddr = bootArgs->ksize = 0;
execute_hook("ExecKernel", (void*)binary, NULL, NULL, NULL);
ret = DecodeKernel(binary,
&kernelEntry,
// Reserve space for boot args
reserveKernBootStruct();
// Notify modules that the kernel has been decoded
execute_hook("DecodedKernel", (void*)binary, NULL, NULL, NULL);
// Load boot drivers from the specifed root path.
if (!gHaveKernelCache)
if (!gHaveKernelCache)
LoadDrivers("/");
clearActivityIndicator();
if (gErrors) {
usb_loop();
execute_hook("Kernel Start", (void*)kernelEntry, (void*)bootArgs, NULL, NULL);// Notify modules that the kernel is about to be started
// If we were in text mode, switch to graphics mode.
// This will draw the boot graphics unless we are in
// verbose mode.
setupBooterLog();
finalizeBootStruct();
finalizeBootStruct();
if (checkOSVersion("10.7")) {
startprog( kernelEntry, bootArgsPreLion );
}
// Not reached
return 0;
gBootVolume = selectBootVolume(bvChain);
// Intialize module system
init_module_system();
#if DEBUG
printf(" Default: %d, ->biosdev: %d, ->part_no: %d ->flags: %d\n", gBootVolume, gBootVolume->biosdev, gBootVolume->part_no, gBootVolume->flags);
printf(" bt(0,0): %d, ->biosdev: %d, ->part_no: %d ->flags: %d\n", gBIOSBootVolume, gBIOSBootVolume->biosdev, gBIOSBootVolume->part_no, gBIOSBootVolume->flags);
}
}
// Notify moduals that we are attempting to boot
execute_hook("PreBoot", NULL, NULL, NULL, NULL);
if (!getBoolForKey (kWake, &tryresume, &bootInfo->bootConfig)) {
tryresume = true;
tryresumedefault = true;
}
}
}
// Check for cache file.
trycache = (usecache &&
((gBootMode & kBootModeSafe) == 0) &&
break;
}
} while (0);
do {
if (trycache) {
bootFile = gBootKernelCacheFile;
verbose("Loading kernel cache %s\n", bootFile);
verbose("Loading kernel cache %s\n", bootFile);
if (checkOSVersion("10.7")) {
ret = LoadThinFatFile(bootFile, &binary);
}
if (checkOSVersion("10.7"))
{
// Lion, dont load kernel if you have cache
//Lion, dont load kernel if haz cache
if (!trycache) {
verbose("Loading kernel %s\n", bootFileSpec);
ret = LoadThinFatFile(bootFileSpec, &binary);
else ret = 1;
}
else {
// Snow Leopard or older
//Snow leopard or older
verbose("Loading kernel %s\n", bootFileSpec);
ret = LoadThinFatFile(bootFileSpec, &binary);
if (ret <= 0 && archCpuType == CPU_TYPE_X86_64) {
archCpuType = CPU_TYPE_I386;
ret = LoadThinFatFile(bootFileSpec, &binary);
}
}
}
} while (0);
clearActivityIndicator();
config_file_t systemVersion;
const char *val;
int len;
if (!loadConfigFile("System/Library/CoreServices/SystemVersion.plist", &systemVersion))
{
valid = true;
{
valid = true;
}
if (valid)
{
if (getValueForKey(kProductVersion, &val, &len, &systemVersion))
else
valid = false;
}
return valid;
}
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#define kWaitForKeypressKey"Wait"
#define kUseAtiROM"UseAtiROM"/* ati.c */
/* Kabyl: added these keys */
#define kAtiConfig"AtiConfig"/* ati.c */
#define kATYbinimage"ATYbinimage"/* ati.c */
#define kDSDT"DSDT"/* acpi_patcher.c */
#define kDropSSDT"DropSSDT"/* acpi_patcher.c */
#define kRestartFix"RestartFix"/* acpi_patcher.c */
/* Mojodojo: added these keys */
#define kGeneratePStates"GeneratePStates"/* acpi_patcher.c */
#define kGenerateCStates"GenerateCStates"/* acpi_patcher.c */
#define kEnableC2States"EnableC2State"/* acpi_patcher.c */
#define kUseNvidiaROM"UseNvidiaROM"/* nvidia.c */
#define kVBIOS"VBIOS"/* nvidia.c */
/* valv: added these keys */
#define kdcfg0"display_0"/* nvidia.c */
#define kdcfg1"display_1"/* nvidia.c */
#define kPCIRootUID"PCIRootUID"/* pci_root.c */
#define kEthernetBuiltIn"EthernetBuiltIn"/* pci_setup.c */
#define kGraphicsEnabler"GraphicsEnabler"/* pci_setup.c */
#define kForceHPET"ForceHPET"/* pci_setup.c */
#define kUHCIreset"UHCIreset"/* usb.c */
#define kLegacyOff"USBLegacyOff"/* usb.c */
#define kEHCIhard"EHCIhard"/* usb.c */
#define kDefaultPartition"Default Partition"/* sys.c */
#define kMD0Image"md0"/* ramdisk.h */
#define kbusratio"busratio"/* cpu.c */
/*
* Flags to the booter or kernel
branches/Chimera/i386/boot2/drivers.c
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unsigned long signature1;
unsigned long signature2;
unsigned long length;
unsigned long alder32;
unsigned long adler32;
unsigned long version;
unsigned long numDrivers;
unsigned long reserved1;
long (*LoadExtraDrivers_p)(FileLoadDrivers_t FileLoadDrivers_p);
static unsigned long Alder32( unsigned char * buffer, long length );
/*static*/ unsigned long Adler32( unsigned char * buffer, long length );
static long FileLoadDrivers(char *dirSpec, long plugin);
static long NetLoadDrivers(char *dirSpec);
static char * gTempSpec;
static char * gFileName;
static unsigned long
Alder32( unsigned char * buffer, long length )
/*static*/ unsigned long
Adler32( unsigned char * buffer, long length )
{
long cnt;
unsigned long result, lowHalf, highHalf;
if (( GetPackageElement(signature1) != kDriverPackageSignature1) ||
( GetPackageElement(signature2) != kDriverPackageSignature2) ||
( GetPackageElement(length) > kLoadSize ) ||
( GetPackageElement(alder32) !=
Alder32((unsigned char *)&package->version, GetPackageElement(length) - 0x10) ) )
( GetPackageElement(adler32) !=
Adler32((unsigned char *)&package->version, GetPackageElement(length) - 0x10) ) )
{
return -1;
}
return -1;
}
if (OSSwapBigToHostInt32(kernel_header->adler32) !=
Alder32(binary, uncompressed_size)) {
Adler32(binary, uncompressed_size)) {
printf("adler mismatch\n");
return -1;
}
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// Get us in to low memory so we can run everything
// We cannot possibly be more than 383.5k and copying extra won't really hurt anything
// We cannot possibly be more than 447k and copying extra won't really hurt anything
// We use the address of the assembly entrypoint to get our starting location.
memcpy(&boot2_sym, (char*)&boot2_sym + OFFSET_1MEG, 0x5fe00 /* 383.5k */);
memcpy(&boot2_sym, (char*)&boot2_sym + OFFSET_1MEG, BOOT2_MAX_LENGTH /* 447k */);
// This is a little assembler routine that returns to us in the correct selector
// instead of the kernel selector we're running in now and at the correct
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#include "vers.h"
char bootBanner[] = "\nDarwin/x86 boot v" I386BOOT_VERSION " - Chimera v" I386BOOT_CHAMELEONVERSION " r" I386BOOT_CHAMELEONREVISION "\n"
char bootBanner[] = "\nDarwin/x86 boot v" I386BOOT_VERSION " - Chameleon v" I386BOOT_CHAMELEONVERSION " r" I386BOOT_CHAMELEONREVISION "\n"
"Build date: " I386BOOT_BUILDDATE "\n"
"%dMB memory\n";
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# The ordering is important;
# boot2.o must be first.
OBJS = boot2.o boot.o graphics.o drivers.o prompt.o options.o lzss.o mboot.o \
ramdisk.o picopng.o resume.o bmdecompress.o graphic_utils.o gui.o
ramdisk.o picopng.o resume.o bmdecompress.o graphic_utils.o gui.o modules.o modules_support.o
# button.o browser.o scrollbar.o == NOTYET
UTILDIR = ../util
SFILES = boot2.s
CFILES = boot.c graphics.c drivers.c prompt.c options.c mboot.c picopng.c
HFILES = boot.h appleClut8.h appleboot.h mboot.h multiboot.h picopng.h
CFILES = boot.c graphics.c drivers.c prompt.c options.c mboot.c picopng.c modules.c
HFILES = boot.h appleClut8.h appleboot.h mboot.h multiboot.h picopng.h modules.h
OTHERFILES = Makefile
ALLSRC = $(FOREIGNSRC) $(FOREIGNBIN) $(SFILES) $(CFILES) \
$(HFILES) $(OTHERFILES)
BOOT2ADDR = 20200
MAXBOOTSIZE = 458240
#
# Strings used to retrieve the start location for the Symbols.dylib module
#
SYMBOLS_MODULE = Symbols.dylib
SYMBOL_START= _symbols_module_start
SYMBOL_ADDR = $(shell printf "%d" 0x`nm -s __DATA __data $(SYMROOT)/boot.sys | grep " $(SYMBOL_START)$$" | cut -f 1 -d " "`)
DATA_OFFSET = $(shell otool -l $(SYMROOT)/boot.sys | grep __data -A 4 | grep __DATA -A 3 | tail -n 1 | cut -f 6 -d " ")
DATA_ADDR = $(shell printf "%d" `otool -l $(SYMROOT)/boot.sys | grep __data -A 4 | grep __DATA -A 3 | head -n 2 | tail -n 1 | cut -f 8 -d " "`)
PATCH_ADDR = $(shell echo ${SYMBOL_ADDR}-${DATA_ADDR}+${DATA_OFFSET} | bc)
all: $(DIRS_NEEDED) boot
embedtheme: CFLAGS += -DEMBED_THEME
embedtheme: art.h all
boot: machOconv embedded.h $(OBJS) $(LIBDEP)
$(LD) -static -Wl,-preload -Wl,-segaddr,__INIT,$(BOOT2ADDR) \
@echo "\t[LD] boot.sys"
@$(LD) -static -Wl,-preload -Wl,-segaddr,__INIT,$(BOOT2ADDR) \
-nostdlib -arch i386 -Wl,-segalign,20 \
-o $(SYMROOT)/boot.sys $(filter %.o,$^) $(LIBS) -lcc_kext
machOconv $(SYMROOT)/boot.sys $(SYMROOT)/boot
size $(SYMROOT)/boot.sys
ls -l $(SYMROOT)/boot
@cp $(SYMROOT)/boot.sys $(SYMROOT)/boot2.sys
@# Generate the Symbols.dylib file
@echo "\t[dyldsymboltool] Symbols.dylib"
@$(SYMROOT)/dyldsymboltool $(SYMROOT)/boot.sys $(SYMROOT)/${SYMBOLS_MODULE}
@echo "\t[LD] boot.sys"
@$(LD) -static -Wl,-preload -Wl,-segaddr,__INIT,$(BOOT2ADDR) \
-nostdlib -arch i386 -Wl,-segalign,20 \
-Wl,-sectcreate,__DATA,__Symbols,$(SYMROOT)/Symbols.dylib \
-o $(SYMROOT)/boot.sys $(filter %.o,$^) $(LIBS) -lcc_kext
@# Second pass, fixup global var locations
@${RM} $(SYMROOT)/${SYMBOLS_MODULE}
@# Generate the Symbols.dylib file
@echo "\t[dyldsymboltool] Symbols.dylib"
@$(SYMROOT)/dyldsymboltool $(SYMROOT)/boot.sys $(SYMROOT)/${SYMBOLS_MODULE}
@${RM} $(SYMROOT)/boot.sys
@echo "\t[LD] boot.sys"
@$(LD) -static -Wl,-preload -Wl,-segaddr,__INIT,$(BOOT2ADDR) \
-nostdlib -arch i386 -Wl,-segalign,20 \
-Wl,-sectcreate,__DATA,__Symbols,$(SYMROOT)/Symbols.dylib \
-o $(SYMROOT)/boot.sys $(filter %.o,$^) $(LIBS) -lcc_kext
@ld -arch i386 \
-undefined dynamic_lookup \
-dylib -read_only_relocs suppress \
-S -x -Z -dead_strip_dylibs \
-no_uuid \
-final_output Symbols \
$(filter %.o,$^) $(LIBS) \
-o $(OBJROOT)/Symbols_LINKER_ONLY.dylib
@make embed_symbols# this is done in a sub process after boot.sys exists so the strings are populated correctly
@${RM} $(SYMROOT)/boot2.sys
@##size $(SYMROOT)/boot.sys
@ls -l $(SYMROOT)/boot
@( size=`ls -l $(SYMROOT)/boot | awk '{ print $$5}'` ; \
if expr "$$size" ">" "$(MAXBOOTSIZE)" > /dev/null ;\
then \
exit 1;\
fi)
embed_symbols: machOconv
@echo ================= Embedding Symbols.dylib =================
@echo "\t[MACHOCONV] boot"
@$(SYMROOT)/machOconv $(SYMROOT)/boot2.sys $(SYMROOT)/boot &> /dev/null
@echo "\t******* Patching at $(PATCH_ADDR) ******"
@stat -f%z $(SYMROOT)/boot | perl -ane "print pack('V',@F[0]);" | dd conv=notrunc of=${SYMROOT}/boot.sys bs=1 count=4 seek=$(PATCH_ADDR) &> /dev/null
@echo "\t[MACHOCONV] boot"
@$(SYMROOT)/machOconv $(SYMROOT)/boot.sys $(SYMROOT)/boot
prompt.o: vers.h
vers.h:
@echo "#define I386BOOT_VERSION \"5.0.132\"" > $(SYMROOT)/vers.h
@echo "#define I386BOOT_BUILDDATE \"`date \"+%Y-%m-%d %H:%M:%S\"`\"" >> $(SYMROOT)/vers.h
@echo "#define I386BOOT_CHAMELEONVERSION \"`cat ../../version`\"" >> $(SYMROOT)/vers.h
#@echo "#define I386BOOT_CHAMELEONREVISION \"`svnversion -n | tr -d [:alpha:]`\"" >> $(SYMROOT)/vers.h
# Following is only when using git instead of svn
@echo "#define I386BOOT_CHAMELEONREVISION \"`cat ../../revision`\"" >> $(SYMROOT)/vers.h
@echo "#define I386BOOT_CHAMELEONREVISION \"`svnversion -n | tr -d [:alpha:]`\"" >> $(SYMROOT)/vers.h
art.h:
@if [ "$(PNGCRUSH)" ]; then\
branches/Chimera/i386/doc/README
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For DOS compatibility reason, one extra stage of boot is required if
the boot device is a hard disk. The first sector of the hard disk will
contain the MS-DOS boot code and a boot record partition table.
contain the MOS-DOS boot code and a boot record partition table.
When this sector is loaded into 0000:7C00H, it will relocate itself
to somewhere else and then load the first sector of the active
partition into 0000:7C00H. Both UNIX and DOS use the command "fdisk"
stage bootstrap loader "boot2()". In order to be able to load the
big kernel image (bigger than 512K or 640K, depends on the memory
configuration), the second stage boot loader will run on the protected
mode. This bootstrap loader does not have any stand alone device
mode. This bootstarp loader does not have any stand alone device
drivers, all the I/O's are through the BIOS calls. Since the first
stage boot code will no longer be used at this moment, the memory
location of the first stage boot code (0000:1000H to 0000:1200H) will
and boot data segments must not be greater than 64K.
The boot loader loads the kernel image at memory location above 1 MB
to skip the memory hole between 512K/640K and 1MB. After the kernel
to skip the memory hole between 521K/640K and 1MB. After the kernel
is loaded, the boot loader stores the information in the stack and
then passes control to kernel. Currently, the three information passed
from the boot loader to the kernel are type of the boot device, size
branches/Chimera/i386/cdboot/Makefile
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DIR = cdboot
include ../MakePaths.dir
NASM = /Developer/usr/bin/nasm
NASM = $(shell which nasm)
#/Developer/usr/bin/nasm
INSTALLDIR = $(DSTROOT)/usr/standalone/i386
DIRS_NEEDED = $(SYMROOT)
all embedtheme: $(DIRS_NEEDED) cdboot
all embedtheme optionrom: $(DIRS_NEEDED) cdboot
cdboot: cdboot.s $(SYMROOT)/boot Makefile $(NASM)
$(NASM) cdboot.s -o $(SYMROOT)/cdboot
dd if=$(SYMROOT)/boot of=$(SYMROOT)/cdboot conv=sync bs=2k seek=1
@echo "\t[NASM] cdboot.s"
@$(NASM) cdboot.s -o $(SYMROOT)/cdboot
@dd if=$(SYMROOT)/boot of=$(SYMROOT)/cdboot conv=sync bs=2k seek=1 &> /dev/null
# Update cdboot with boot file size info
stat -f%z $(SYMROOT)/boot \
@# Update cdboot with boot file size info
@stat -f%z $(SYMROOT)/boot \
| perl -ane "print pack('V',@F[0]);" \
| dd of=$(SYMROOT)/cdboot bs=1 count=4 seek=2044 conv=notrunc
| dd of=$(SYMROOT)/cdboot bs=1 count=4 seek=2044 conv=notrunc &> /dev/null
install_i386:: all $(INSTALLDIR)
cp $(SYMROOT)/cdboot $(INSTALLDIR)
branches/Chimera/i386/libsa/Makefile
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all embedtheme: $(DIRS_NEEDED) $(LIBS)
libsa.a: $(SA_OBJS)
rm -f $(SYMROOT)/$(@F)
ar q $(SYMROOT)/$(@F) $^
ranlib $(SYMROOT)/$(@F)
@echo "\t[RM] $(SYMROOT)/$(@F)"
@rm -f $(SYMROOT)/$(@F)
@echo "\t[AR] $@"
@ar q $(SYMROOT)/$(@F) $^ &> /dev/null
@echo "\t[RANLIB] $@"
@ranlib $(SYMROOT)/$(@F)
$(INSTALL_SA_DIR) $(INSTALL_MD_DIR):
$(MKDIRS) $@
branches/Chimera/i386/libsa/memory.h
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# define BASE_SEG BOOT2_SEG
#endif
#define STACK_SEG 0x1000// zef: old STACK_SEG 0x5000
#define STACK_OFS 0xFFF0// stack pointer
#define STACK_SEG 0x1000// zef: old STACK_SEG 0x5000
#define STACK_OFS 0xFFF0 // stack pointer
#define BOOT1U_SEG 0x1000
#define BOOT1U_OFS 0x0200
#define BOOT2_SEG 0x2000
#define BOOT2_OFS 0x0200// 512 byte disk sector offset
#define BOOT2_OFS 0x0200 // 512 byte disk sector offset
#define BIOS_ADDR 0x8000// BIOS disk I/O buffer
#define BIOS_LEN 0x8000// 32K - divisible by 512 and 2048
#define BOOT2_MAX_LENGTH 0x6FE00 // Maximum size for boot2 is currentl 447kb
#define BOOT0_ADDR 0x7E00// boot0 gets loaded here
#define BIOS_ADDR 0x8000 // BIOS disk I/O buffer
#define BIOS_LEN 0x8000 // 32K - divisible by 512 and 2048
#define BOOT0_ADDR 0x7E00 // boot0 gets loaded here
/* These are all "virtual" addresses...
* which are physical addresses plus MEMBASE.
*/
#define MEMBASE 0x0
#define BOOTSTRUCT_ADDR 0x00011000// it's slightly smaller
#define BOOTSTRUCT_ADDR 0x00011000 // it's slightly smaller
#define BOOTSTRUCT_LEN 0x0000F000
#define BASE_ADDR ADDR32(BASE_SEG, 0)
#define BOOT2_ADDR ADDR32(BOOT2_SEG, BOOT2_OFS)
// TODO: BOOT_ADDR ?
#define HIB_ADDR 0x00040000// special hibernation area
#define HIB_ADDR 0x00040000 // special hibernation area
#define HIB_LEN 0x00060000
#define VIDEO_ADDR 0x000A0000// unusable space
#define VIDEO_ADDR 0x000A0000 // unusable space
#define VIDEO_LEN 0x00060000
#define KERNEL_ADDR 0x00100000// 128M kernel + drivers
#define KERNEL_ADDR 0x00100000 // 128M kernel + drivers
#define KERNEL_LEN 0x08000000
#define ZALLOC_ADDR 0x08100000// 256M zalloc area
#define ZALLOC_ADDR 0x08100000 // 256M zalloc area
#define ZALLOC_LEN 0x10000000
#define LOAD_ADDR 0x18100000// 64M File load buffer
#define LOAD_ADDR 0x18100000 // 64M File load buffer
#define LOAD_LEN 0x04000000
// Location of data fed to boot2 by the prebooter
#define PREBOOT_DATA 0x1C100000// Still have enough room for a 63M ramdisk image
// in case of 512MB system memory.
#define PREBOOT_DATA 0x1C100000 // Still have enough room for a 63M ramdisk image
// in case of 512MB system memory.
#define TFTP_ADDR LOAD_ADDR// tftp download buffer
#define TFTP_ADDR LOAD_ADDR // tftp download buffer
#define TFTP_LEN LOAD_LEN
#define kLoadAddr LOAD_ADDR
#define kLoadSize LOAD_LEN
#define CONVENTIONAL_LEN 0x0A0000// 640k
#define EXTENDED_ADDR 0x100000// 1024k
#define CONVENTIONAL_LEN 0x0A0000 // 640k
#define EXTENDED_ADDR 0x100000 // 1024k
#define ptov(paddr) ((paddr) - MEMBASE)
#define vtop(vaddr) ((vaddr) + MEMBASE)
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VPATH = $(OBJROOT):$(SYMROOT)
# The order of building is important.
SUBDIRS = util libsa libsaio boot2 boot1 boot0 cdboot
SUBDIRS = util libsa libsaio boot2 boot1 boot0 cdboot modules
all embedtheme tags debug install installhdrs:
@for i in ${SUBDIRS}; \
branches/Chimera/i386/util/Makefile
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CFILES = machOconv.c
ALLSRC = $(CFILES) $(MFILES) $(HFILES) $(EXPORT_HFILES)
PROGRAMS = machOconv bdmesg
PROGRAMS = machOconv bdmesg dyldsymboltool
OUTFILES = $(PROGRAMS)
all embedtheme: $(DIRS_NEEDED) $(PROGRAMS)
dyldsymboltool: dyldsymboltool.o32 dyldsymboltool.o64
@echo "\t[LD32] $@_32"
@$(CC) $(CFLAGS) $(LDFLAGS) $(DEFINES) -arch i386 -o $(SYMROOT)/$(@F)_32 $(OBJROOT)/$(@F).o32
@echo "\t[LD64] $@_64"
@$(CC) $(CFLAGS) $(LDFLAGS) $(DEFINES) -arch x86_64 -o $(SYMROOT)/$(@F)_64 $(OBJROOT)/$(@F).o64
@echo "\t[LIPO] $@"
@lipo -create -arch i386 $(SYMROOT)/$(@F)_32 -arch x86_64 $(SYMROOT)/$(@F)_64 -output $(SYMROOT)/$(@F)
@$(RM) $(SYMROOT)/$(@F)_32 $(SYMROOT)/$(@F)_64
machOconv: machOconv.o32 machOconv.o64
$(CC) $(CFLAGS) $(LDFLAGS) $(DEFINES) -arch i386 -o $(SYMROOT)/$(@F)_32 $(OBJROOT)/$(@F).o32
$(CC) $(CFLAGS) $(LDFLAGS) $(DEFINES) -arch x86_64 -o $(SYMROOT)/$(@F)_64 $(OBJROOT)/$(@F).o64
lipo -create -arch i386 $(SYMROOT)/$(@F)_32 -arch x86_64 $(SYMROOT)/$(@F)_64 -output $(SYMROOT)/$(@F)
$(RM) $(SYMROOT)/$(@F)_32 $(SYMROOT)/$(@F)_64
@echo "\t[LD32] $@_32"
@$(CC) $(CFLAGS) $(LDFLAGS) $(DEFINES) -arch i386 -o $(SYMROOT)/$(@F)_32 $(OBJROOT)/$(@F).o32
@echo "\t[LD64] $@_64"
@$(CC) $(CFLAGS) $(LDFLAGS) $(DEFINES) -arch x86_64 -o $(SYMROOT)/$(@F)_64 $(OBJROOT)/$(@F).o64
@echo "\t[LIPO] $@"
@lipo -create -arch i386 $(SYMROOT)/$(@F)_32 -arch x86_64 $(SYMROOT)/$(@F)_64 -output $(SYMROOT)/$(@F)
@$(RM) $(SYMROOT)/$(@F)_32 $(SYMROOT)/$(@F)_64
bdmesg: bdmesg.o32 bdmesg.o64
$(CC) $(CFLAGS) $(LDFLAGS) -framework IOKit -framework CoreFoundation -mmacosx-version-min=10.5 \
@echo "\t[LD32] $@_32"
@$(CC) $(CFLAGS) $(LDFLAGS) -framework IOKit -framework CoreFoundation -mmacosx-version-min=10.5 \
-arch i386 -o $(SYMROOT)/$(@F)_32 $(OBJROOT)/$(@F).o32
$(CC) $(CFLAGS) $(LDFLAGS) -framework IOKit -framework CoreFoundation -mmacosx-version-min=10.5 \
@echo "\t[LD64] $@_64"
@$(CC) $(CFLAGS) $(LDFLAGS) -framework IOKit -framework CoreFoundation -mmacosx-version-min=10.5 \
-arch x86_64 -o $(SYMROOT)/$(@F)_64 $(OBJROOT)/$(@F).o64
lipo -create -arch i386 $(SYMROOT)/$(@F)_32 -arch x86_64 $(SYMROOT)/$(@F)_64 -output $(SYMROOT)/$(@F)
$(RM) $(SYMROOT)/$(@F)_32 $(SYMROOT)/$(@F)_64
@echo "\t[LIPO] $@"
@lipo -create -arch i386 $(SYMROOT)/$(@F)_32 -arch x86_64 $(SYMROOT)/$(@F)_64 -output $(SYMROOT)/$(@F)
@$(RM) $(SYMROOT)/$(@F)_32 $(SYMROOT)/$(@F)_64
include ../MakeInc.dir
#dependencies
-include $(OBJROOT)/Makedep
-include $(OBJROOT)/Makedep
branches/Chimera/CREDITS
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Turbo
valv
zef
cparm
Thanks to:
---------
branches/Chimera/revision
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TODO List for Chameleon Boot Loader
====================================
- Fix the module system when booting chameleon with multiboot. Cleanup the xcode 4 fix.
- Integrate Prasys current work on options and quick shortcut modified version of 18seven
- Add auto-detection of efi string algorithm to enable graphics enabler to be enabled by default while not conflicting with other efi string overridden content
- Add autodetection of efistring algorythm to enabke graphics enabler to beanbled by default while not conflicting whith other efi string overriden content
(original idea of Galaxy)
- Add a more sophisticated acpi loading mechanism to enable loading custom acpi tables when dsdtdrop=y
Now for each acpi file found, we should compare the name with an existing acpi table found in the system that
we would normally load and replace this usual injection by the content of the file.
Once DropDSDT=y is set, no other acpi table than dsdt is loaded, then it is the responsibility of user
Once DropDSDT=y is set, no other acpi table than dsdt is loaded, then it is the responsability of user
to provide any other acpi table.
- Add a new module capable of writing proprietary Chameleon data to ioreg:
Using the DT__xxx() API, we will create a set of functions to write
Using the DT__xxx() API, we will creat e a set of functions to write
to log info, chameleon boot info to be retrieved by helper applications...
the only public function for log info purpose of this module would be:
logMessageToIOREG(...); // var args printf style format
getc();
}
- Case insensitive parsing for the bootConfig options:
- Case unsensitive parsing for the bootConfig options:
should help the common/novice user to setup more easily.
branches/Chimera/doc/BootHelp.txt
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"Legacy Logo"=Yes|No Use the legacy grey apple logo (disabled by default).
PciRoot=<value> Use an alternate value for PciRoot (default value 0).
UseKernelCache=Yes|No Default is No. Yes will load pre-linked kernel and will
ignore /E/E and /S/L/E/Extensions.mkext.
GraphicsEnabler=Yes|No Automatic device-properties generation for gfx cards.
AtiConfig=<cardcfg> Use a different card config
UseAtiROM=Yes|No Use an alternate Ati ROM image
(path: /Extra/<vendorid>_<devid>_<subsysid>.rom)
UseNvidiaROM=Yes|No Use an alternate Nvidia ROM image
(path: /Extra/<vendorid>_<devid>.rom)
VBIOS=Yes|No Inject NVIDIA VBIOS into device-properties.
display_0=<value> Inject alternate display-cfg value into
NVDA,Display-A@0
display_1=<value> Inject alternate display-cfg value into
NVDA,Display-B@1
UseAtiROM=Yes|No Use an alternate Ati ROM image
(path: /Extra/<vendorid>_<devid>_<subsysid>.rom)
UseNvidiaROM=Yes|No Use an alternate Nvidia ROM image
(path: /Extra/<vendorid>_<devid>.rom)
VBIOS=Yes|No Inject VBIOS to device-properties.
AtiConfig=<cardcfg> Use a different card config (the list can be found in ati.c).
EthernetBuiltIn=Yes|No Automatic "built-in"=yes device-properties generation
for ethernet interfaces.
(default paths:
/DSDT.aml /Extra/DSDT.aml bt(0,0)/Extra/DSDT.aml).
GenerateCStates=Yes Enable auto generation of processor idle sleep states
(C-States).
GeneratePStates=Yes Enable auto generation of processor power performance
states (P-States).
GenerateCStates=Yes Enable auto generation of Processor (C-States) and/or
GeneratePStates=Yes Performance (P-States) power states.
EnableC2State=Yes Enable specific Processor power state, C2.
EnableC3State=Yes Enable specific Processor power state, C3.
EnableC4State=Yes Enable specific Processor power state, C4.
EnableC2State=Yes Enable specific Processor power states, C2,
EnableC3State=Yes C3
EnableC4State=Yes and C4.
SMBIOS=<file> Use an alternate SMBIOS.plist file
(default path:
(default paths:
/Extra/SMBIOS.plist bt(0,0)/Extra/SMBIOS.plist).
SMBIOSdefaults=No Don't use the Default values for SMBIOS overriding
branches/Chimera/CHANGES
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- Added the BOOT2_MAX_LENGTH constant in memory.h. This is now used in moot.c to relocate the correct number of bytes for boot2.
- Added new ATi/AMD Graphics Card Enabler.
- Added new SMBIOS patcher.
- Added module system.
- Added automatic P-States & C-States generation for native power management.
- Added Booter Log Dump Tool
- Added Booter message Logging (":/boot-log" ioreg property)
branches/Chimera/Makefile
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@tar -cjf $(SYMROOT)/$(PRODUCT)-src.tar.bz2 ${EXCLUDE} .
clean:
rm -rf sym obj dst
rm -rf sym obj dst revision i386/modules/module_includes
#distclean: clean
#@rm -f $(SYMROOT)/$(PRODUCT)-src.*

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Revision: 849