Chameleon

Chameleon Commit Details

Date:2011-05-21 10:09:30 (12 years 10 months ago)
Author:Kabyl
Commit:861
Parents: 860
Message:Added support for Sandy Bridge SMBus scanning, check for CPU model before adding SMBOemProcessorBusSpeed, leave original SMBIOS memory info, if nothing is specified by the user or read from the SPD
Changes:
M/trunk/i386/libsaio/spd.c
M/trunk/i386/libsaio/smbios_getters.c
M/trunk/i386/libsaio/smbios.c

File differences

trunk/i386/libsaio/spd.c
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␊
static struct smbus_controllers_t smbus_controllers[] = {␊
␊
␉{0x8086, 0x269B, "ESB2", read_smb_intel },␊
␉{0x8086, 0x25A4, "6300ESB", read_smb_intel },␊
␉{0x8086, 0x24C3, "ICH4", read_smb_intel },␊
␉{0x8086, 0x24D3, "ICH5", read_smb_intel },␊
␉{0x8086, 0x266A, "ICH6", read_smb_intel },␊
␉{0x8086, 0x27DA, "ICH7", read_smb_intel },␊
␉{0x8086, 0x283E, "ICH8", read_smb_intel },␊
␉{0x8086, 0x2930, "ICH9", read_smb_intel },␉␊
␉{0x8086, 0x3A30, "ICH10R", read_smb_intel },␊
␉{0x8086, 0x3A60, "ICH10B", read_smb_intel },␊
␉{0x8086, 0x3B30, "P55", read_smb_intel },␊
␉{0x8086, 0x5032, "EP80579", read_smb_intel }␊
␉{0x8086, 0x269B, "ESB2",␉␉read_smb_intel },␊
␉{0x8086, 0x25A4, "6300ESB",␉␉read_smb_intel },␊
␉{0x8086, 0x24C3, "ICH4",␉␉read_smb_intel },␊
␉{0x8086, 0x24D3, "ICH5",␉␉read_smb_intel },␊
␉{0x8086, 0x266A, "ICH6",␉␉read_smb_intel },␊
␉{0x8086, 0x27DA, "ICH7",␉␉read_smb_intel },␊
␉{0x8086, 0x283E, "ICH8",␉␉read_smb_intel },␊
␉{0x8086, 0x2930, "ICH9",␉␉read_smb_intel },␉␊
␉{0x8086, 0x3A30, "ICH10R",␉␉read_smb_intel },␊
␉{0x8086, 0x3A60, "ICH10B",␉␉read_smb_intel },␊
␉{0x8086, 0x3B30, "5 Series",␉read_smb_intel },␊
␉{0x8086, 0x1C22, "6 Series",␉read_smb_intel },␊
␉{0x8086, 0x5032, "EP80579",␉␉read_smb_intel }␊
␊
};␊
␊
trunk/i386/libsaio/smbios.c
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{␊
␉SMBOemProcessorBusSpeed *p = (SMBOemProcessorBusSpeed *)structPtr->new;␊
␊
␉switch (Platform.CPU.Family) ␊
␉{␊
␉␉case 0x06:␊
␉␉{␊
␉␉␉switch (Platform.CPU.Model)␊
␉␉␉{␊
␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊
␉␉␉␉case CPU_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊
␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5, i7 LGA1156 (32nm)␊
␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊
␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7 LGA1366 (32nm) 6 Core␊
␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
␉␉␉␉␉break;␊
␊
␉␉␉␉default:␊
␉␉␉␉␉return;␊
␉␉␉}␊
␉␉}␊
␉}␊
␊
␉p->header.type␉␉= kSMBTypeOemProcessorBusSpeed;␊
␉p->header.length␉= sizeof(SMBOemProcessorBusSpeed);␊
␉p->header.handle␉= handle++;␊
trunk/i386/libsaio/smbios_getters.c
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␉␉␉␉␉␉return false;␊
␊
␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
␉␉␉␉␉case CPU_MODEL_SANDY:␉␉// Intel Core i5, i7 LGA1155 sandy bridge␊
case CPU_MODEL_SANDY_XEON: ␊
␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊
␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊
␉␉␉␉␉case CPU_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊
␉␉}␊
␉}␊
␊
//␉return false;␊
␉value->string = NOT_AVAILABLE;␊
␉return true;␊
␉return false;␊
//␉value->string = NOT_AVAILABLE;␊
//␉return true;␊
}␊
␉␊
bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
␉␉}␊
␉}␊
␊
//␉return false;␊
␉value->string = NOT_AVAILABLE;␊
␉return true;␊
␉return false;␊
//␉value->string = NOT_AVAILABLE;␊
//␉return true;␊
}␊
␊
bool getSMBMemoryDevicePartNumber(returnType *value)␊
␉␉}␊
␉}␊
␊
//␉return false;␊
␉value->string = NOT_AVAILABLE;␊
␉return true;␊
␉return false;␊
//␉value->string = NOT_AVAILABLE;␊
//␉return true;␊
}␊
␊
␊

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Revision: 861