Chameleon

Chameleon Commit Details

Date:2011-05-22 11:38:18 (8 years 4 months ago)
Author:Azimutz
Commit:868
Parents: 867
Message:- Restructure GraphicsEnabler module, into individual ones (per graphics vendor). - Rename ATIEnablerLegacy to match the others; modules naming should be close to final. Kabyl's suggestions/opinions/advices are included; thanks for putting up with the noob.
Changes:
D/branches/azimutz/Cleancut/i386/modules/GraphicsEnabler
D/branches/azimutz/Cleancut/i386/modules/ATiGraphicsEnabler/ATIEnablerLegacy.c
R/branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy → /branches/azimutz/Cleancut/i386/modules/ATiGraphicsEnabler
C/branches/azimutz/Cleancut/i386/modules/ATIEnablerLegacy/ATIEnablerLegacy.c → /branches/azimutz/Cleancut/i386/modules/ATiGraphicsEnabler/ATiGraphicsEnabler.c
A/branches/azimutz/Cleancut/i386/modules/AMDGraphicsEnabler/ati.c
A/branches/azimutz/Cleancut/i386/modules/IntelGraphicsEnabler/gma.c
A/branches/azimutz/Cleancut/i386/modules/AMDGraphicsEnabler
A/branches/azimutz/Cleancut/i386/modules/AMDGraphicsEnabler/ati_reg.h
A/branches/azimutz/Cleancut/i386/modules/NVIDIAGraphicsEnabler/nvidia.c
A/branches/azimutz/Cleancut/i386/modules/IntelGraphicsEnabler/gma.h
A/branches/azimutz/Cleancut/i386/modules/NVIDIAGraphicsEnabler/nvidia.h
A/branches/azimutz/Cleancut/i386/modules/NVIDIAGraphicsEnabler
A/branches/azimutz/Cleancut/i386/modules/IntelGraphicsEnabler
A/branches/azimutz/Cleancut/i386/modules/AMDGraphicsEnabler/Readme.txt
A/branches/azimutz/Cleancut/i386/modules/AMDGraphicsEnabler/Makefile
A/branches/azimutz/Cleancut/i386/modules/NVIDIAGraphicsEnabler/NVIDIAGraphicsEnabler.c
A/branches/azimutz/Cleancut/i386/modules/IntelGraphicsEnabler/IntelGraphicsEnabler.c
A/branches/azimutz/Cleancut/i386/modules/NVIDIAGraphicsEnabler/Readme.txt
A/branches/azimutz/Cleancut/i386/modules/IntelGraphicsEnabler/Readme.txt
A/branches/azimutz/Cleancut/i386/modules/NVIDIAGraphicsEnabler/Makefile
A/branches/azimutz/Cleancut/i386/modules/IntelGraphicsEnabler/Makefile
A/branches/azimutz/Cleancut/i386/modules/AMDGraphicsEnabler/AMDGraphicsEnabler.c
M/branches/azimutz/Cleancut/i386/modules/Makefile
M/branches/azimutz/Cleancut/i386/modules/ATiGraphicsEnabler/ati.c
M/branches/azimutz/Cleancut/i386/modules/ATiGraphicsEnabler/Readme.txt
M/branches/azimutz/Cleancut/i386/modules/ATiGraphicsEnabler/Makefile

File differences

branches/azimutz/Cleancut/i386/modules/NVIDIAGraphicsEnabler/nvidia.h
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/*
* NVidia injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi
*
* NVidia injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* NVidia driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
/*
* DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
*
*
* Copyright 2005-2006 Erik Waling
* Copyright 2006 Stephane Marchesin
* Copyright 2007-2009 Stuart Bennett
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __LIBSAIO_NVIDIA_H
#define __LIBSAIO_NVIDIA_H
bool setup_nvidia_devprop(pci_dt_t *nvda_dev);
struct nv_chipsets_t {
unsigned device;
char *name;
};
#define DCB_MAX_NUM_ENTRIES 16
#define DCB_MAX_NUM_I2C_ENTRIES 16
#define DCB_LOC_ON_CHIP 0
struct bios {
uint16_tsignature;/* 0x55AA */
uint8_tsize;/* Size in multiples of 512 */
};
#define NV_PROM_OFFSET0x300000
#define NV_PROM_SIZE0x0000ffff
#define NV_PRAMIN_OFFSET0x00700000
#define NV_PRAMIN_SIZE0x00100000
#define NV04_PFB_FIFO_DATA0x0010020c
#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK0xfff00000
#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT20
#define NVC0_MEM_CTRLR_COUNT0x00121c74
#define NVC0_MEM_CTRLR_RAM_AMOUNT0x0010f20c
#define NV_PBUS_PCI_NV_200x00001850
#define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED(0 << 0)
#define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED(1 << 0)
#define REG8(reg) ((volatile uint8_t *)regs)[(reg)]
#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1]
#define REG32(reg) ((volatile uint32_t *)regs)[(reg) >> 2]
#define NV_ARCH_03 0x03
#define NV_ARCH_04 0x04
#define NV_ARCH_10 0x10
#define NV_ARCH_20 0x20
#define NV_ARCH_30 0x30
#define NV_ARCH_40 0x40
#define NV_ARCH_50 0x50
#define NV_ARCH_C0 0xC0
#define CHIPSET_NV03 0x0010
#define CHIPSET_NV04 0x0020
#define CHIPSET_NV10 0x0100
#define CHIPSET_NV11 0x0110
#define CHIPSET_NV15 0x0150
#define CHIPSET_NV17 0x0170
#define CHIPSET_NV18 0x0180
#define CHIPSET_NFORCE 0x01A0
#define CHIPSET_NFORCE2 0x01F0
#define CHIPSET_NV20 0x0200
#define CHIPSET_NV25 0x0250
#define CHIPSET_NV28 0x0280
#define CHIPSET_NV30 0x0300
#define CHIPSET_NV31 0x0310
#define CHIPSET_NV34 0x0320
#define CHIPSET_NV35 0x0330
#define CHIPSET_NV36 0x0340
#define CHIPSET_NV40 0x0040
#define CHIPSET_NV41 0x00C0
#define CHIPSET_NV43 0x0140
#define CHIPSET_NV44 0x0160
#define CHIPSET_NV44A 0x0220
#define CHIPSET_NV45 0x0210
#define CHIPSET_NV50 0x0190
#define CHIPSET_NV84 0x0400
#define CHIPSET_MISC_BRIDGED 0x00F0
#define CHIPSET_G70 0x0090
#define CHIPSET_G71 0x0290
#define CHIPSET_G72 0x01D0
#define CHIPSET_G73 0x0390
// integrated GeForces (6100, 6150)
#define CHIPSET_C51 0x0240
// variant of C51, seems based on a G70 design
#define CHIPSET_C512 0x03D0
#define CHIPSET_G73_BRIDGED 0x02E0
#endif /* !__LIBSAIO_NVIDIA_H */
branches/azimutz/Cleancut/i386/modules/NVIDIAGraphicsEnabler/NVIDIAGraphicsEnabler.c
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/*
* GraphicsEnabler Module
*Enabled many nvidia and ati cards to be used out of the box in
*OS X. This was converted from boot2 code to a boot2 module.
*
*/
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "nvidia.h"
#include "modules.h"
#define kGraphicsEnablerKey"GraphicsEnabler"
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4);
void NVIDIAGraphicsEnabler_start()
{
register_hook_callback("PCIDevice", &GraphicsEnabler_hook);
}
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4)
{
pci_dt_t* current = arg1;
if (current->class_id != PCI_CLASS_DISPLAY_VGA) return;
char *devicepath = get_pci_dev_path(current);
bool do_gfx_devprop = true;
getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->bootConfig);
//Azi: check "fail" code...
if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_NVIDIA))
{
verbose("NVIDIA VGA Controller [%04x:%04x] :: %s \n",
current->vendor_id, current->device_id, devicepath);
setup_nvidia_devprop(current); // ---
}
else
verbose("Not a NVIDIA VGA Controller.\n"); // ---
}
branches/azimutz/Cleancut/i386/modules/NVIDIAGraphicsEnabler/Readme.txt
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Module:GraphicsEnabler
Description: the GraphicsEnabler nVidia code ported to a module.
Based on Meklort's work.
Dependencies: none
Keys: GraphicsEnabler(enabled by default)
UseNvidiaROM(disabled by default)
VBIOS...
TODO: ---
branches/azimutz/Cleancut/i386/modules/NVIDIAGraphicsEnabler/nvidia.c
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/*
* NVidia injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi
*
* NVidia injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* NVidia driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
/*
* DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
*
*
* Copyright 2005-2006 Erik Waling
* Copyright 2006 Stephane Marchesin
* Copyright 2007-2009 Stuart Bennett
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#include "device_inject.h"
#include "nvidia.h"
#ifndef DEBUG_NVIDIA
#define DEBUG_NVIDIA 0
#endif
#if DEBUG_NVIDIA
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
#define kUseNvidiaROM"UseNvidiaROM"
#define kVBIOS"VBIOS"
#define NVIDIA_ROM_SIZE 0x10000
#define PATCH_ROM_SUCCESS 1
#define PATCH_ROM_SUCCESS_HAS_LVDS 2
#define PATCH_ROM_FAILED 0
#define MAX_NUM_DCB_ENTRIES 16
#define TYPE_GROUPED 0xff
extern uint32_t devices_number;
const char *nvidia_compatible_0[]={ "@0,compatible","NVDA,NVMac" };
const char *nvidia_compatible_1[]={ "@1,compatible","NVDA,NVMac" };
const char *nvidia_device_type_0[]={ "@0,device_type","display" };
const char *nvidia_device_type_1[]={ "@1,device_type","display" };
const char *nvidia_device_type[]={ "device_type","NVDA,Parent" };
const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
const char *nvidia_slot_name[]={ "AAPL,slot-name","Slot-1" };
static uint8_t default_NVCAP[]= {
0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
0x00, 0x00, 0x00, 0x00
};
#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )
static struct nv_chipsets_t NVKnownChipsets[] = {
{ 0x00000000, "Unknown" },
{ 0x10DE0040, "GeForce 6800 Ultra" },
{ 0x10DE0041, "GeForce 6800" },
{ 0x10DE0042, "GeForce 6800 LE" },
{ 0x10DE0043, "GeForce 6800 XE" },
{ 0x10DE0044, "GeForce 6800 XT" },
{ 0x10DE0045, "GeForce 6800 GT" },
{ 0x10DE0046, "GeForce 6800 GT" },
{ 0x10DE0047, "GeForce 6800 GS" },
{ 0x10DE0048, "GeForce 6800 XT" },
{ 0x10DE004E, "Quadro FX 4000" },
{ 0x10DE0090, "GeForce 7800 GTX" },
{ 0x10DE0091, "GeForce 7800 GTX" },
{ 0x10DE0092, "GeForce 7800 GT" },
{ 0x10DE0093, "GeForce 7800 GS" },
{ 0x10DE0095, "GeForce 7800 SLI" },
{ 0x10DE0098, "GeForce Go 7800" },
{ 0x10DE0099, "GeForce Go 7800 GTX" },
{ 0x10DE009D, "Quadro FX 4500" },
{ 0x10DE00C0, "GeForce 6800 GS" },
{ 0x10DE00C1, "GeForce 6800" },
{ 0x10DE00C2, "GeForce 6800 LE" },
{ 0x10DE00C3, "GeForce 6800 XT" },
{ 0x10DE00C8, "GeForce Go 6800" },
{ 0x10DE00C9, "GeForce Go 6800 Ultra" },
{ 0x10DE00CC, "Quadro FX Go1400" },
{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },
{ 0x10DE00CE, "Quadro FX 1400" },
{ 0x10DE0140, "GeForce 6600 GT" },
{ 0x10DE0141, "GeForce 6600" },
{ 0x10DE0142, "GeForce 6600 LE" },
{ 0x10DE0143, "GeForce 6600 VE" },
{ 0x10DE0144, "GeForce Go 6600" },
{ 0x10DE0145, "GeForce 6610 XL" },
{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },
{ 0x10DE0147, "GeForce 6700 XL" },
{ 0x10DE0148, "GeForce Go 6600" },
{ 0x10DE0149, "GeForce Go 6600 GT" },
{ 0x10DE014C, "Quadro FX 550" },
{ 0x10DE014D, "Quadro FX 550" },
{ 0x10DE014E, "Quadro FX 540" },
{ 0x10DE014F, "GeForce 6200" },
{ 0x10DE0160, "GeForce 6500" },
{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },
{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },
{ 0x10DE0163, "GeForce 6200 LE" },
{ 0x10DE0164, "GeForce Go 6200" },
{ 0x10DE0165, "Quadro NVS 285" },
{ 0x10DE0166, "GeForce Go 6400" },
{ 0x10DE0167, "GeForce Go 6200" },
{ 0x10DE0168, "GeForce Go 6400" },
{ 0x10DE0169, "GeForce 6250" },
{ 0x10DE016A, "GeForce 7100 GS" },
{ 0x10DE0191, "GeForce 8800 GTX" },
{ 0x10DE0193, "GeForce 8800 GTS" },
{ 0x10DE0194, "GeForce 8800 Ultra" },
{ 0x10DE019D, "Quadro FX 5600" },
{ 0x10DE019E, "Quadro FX 4600" },
{ 0x10DE01D1, "GeForce 7300 LE" },
{ 0x10DE01D3, "GeForce 7300 SE" },
{ 0x10DE01D6, "GeForce Go 7200" },
{ 0x10DE01D7, "GeForce Go 7300" },
{ 0x10DE01D8, "GeForce Go 7400" },
{ 0x10DE01D9, "GeForce Go 7400 GS" },
{ 0x10DE01DA, "Quadro NVS 110M" },
{ 0x10DE01DB, "Quadro NVS 120M" },
{ 0x10DE01DC, "Quadro FX 350M" },
{ 0x10DE01DD, "GeForce 7500 LE" },
{ 0x10DE01DE, "Quadro FX 350" },
{ 0x10DE01DF, "GeForce 7300 GS" },
{ 0x10DE0211, "GeForce 6800" },
{ 0x10DE0212, "GeForce 6800 LE" },
{ 0x10DE0215, "GeForce 6800 GT" },
{ 0x10DE0218, "GeForce 6800 XT" },
{ 0x10DE0221, "GeForce 6200" },
{ 0x10DE0222, "GeForce 6200 A-LE" },
{ 0x10DE0240, "GeForce 6150" },
{ 0x10DE0241, "GeForce 6150 LE" },
{ 0x10DE0242, "GeForce 6100" },
{ 0x10DE0244, "GeForce Go 6150" },
{ 0x10DE0247, "GeForce Go 6100" },
{ 0x10DE0290, "GeForce 7900 GTX" },
{ 0x10DE0291, "GeForce 7900 GT" },
{ 0x10DE0292, "GeForce 7900 GS" },
{ 0x10DE0298, "GeForce Go 7900 GS" },
{ 0x10DE0299, "GeForce Go 7900 GTX" },
{ 0x10DE029A, "Quadro FX 2500M" },
{ 0x10DE029B, "Quadro FX 1500M" },
{ 0x10DE029C, "Quadro FX 5500" },
{ 0x10DE029D, "Quadro FX 3500" },
{ 0x10DE029E, "Quadro FX 1500" },
{ 0x10DE029F, "Quadro FX 4500 X2" },
{ 0x10DE0301, "GeForce FX 5800 Ultra" },
{ 0x10DE0302, "GeForce FX 5800" },
{ 0x10DE0308, "Quadro FX 2000" },
{ 0x10DE0309, "Quadro FX 1000" },
{ 0x10DE0311, "GeForce FX 5600 Ultra" },
{ 0x10DE0312, "GeForce FX 5600" },
{ 0x10DE0314, "GeForce FX 5600XT" },
{ 0x10DE031A, "GeForce FX Go5600" },
{ 0x10DE031B, "GeForce FX Go5650" },
{ 0x10DE031C, "Quadro FX Go700" },
{ 0x10DE0324, "GeForce FX Go5200" },
{ 0x10DE0325, "GeForce FX Go5250" },
{ 0x10DE0326, "GeForce FX 5500" },
{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },
{ 0x10DE032A, "Quadro NVS 55/280 PCI" },
{ 0x10DE032B, "Quadro FX 500/600 PCI" },
{ 0x10DE032C, "GeForce FX Go53xx Series" },
{ 0x10DE032D, "GeForce FX Go5100" },
{ 0x10DE0330, "GeForce FX 5900 Ultra" },
{ 0x10DE0331, "GeForce FX 5900" },
{ 0x10DE0332, "GeForce FX 5900XT" },
{ 0x10DE0333, "GeForce FX 5950 Ultra" },
{ 0x10DE0334, "GeForce FX 5900ZT" },
{ 0x10DE0338, "Quadro FX 3000" },
{ 0x10DE033F, "Quadro FX 700" },
{ 0x10DE0341, "GeForce FX 5700 Ultra" },
{ 0x10DE0342, "GeForce FX 5700" },
{ 0x10DE0343, "GeForce FX 5700LE" },
{ 0x10DE0344, "GeForce FX 5700VE" },
{ 0x10DE0347, "GeForce FX Go5700" },
{ 0x10DE0348, "GeForce FX Go5700" },
{ 0x10DE034C, "Quadro FX Go1000" },
{ 0x10DE034E, "Quadro FX 1100" },
{ 0x10DE0391, "GeForce 7600 GT" },
{ 0x10DE0392, "GeForce 7600 GS" },
{ 0x10DE0393, "GeForce 7300 GT" },
{ 0x10DE0394, "GeForce 7600 LE" },
{ 0x10DE0395, "GeForce 7300 GT" },
{ 0x10DE0397, "GeForce Go 7700" },
{ 0x10DE0398, "GeForce Go 7600" },
{ 0x10DE0399, "GeForce Go 7600 GT"},
{ 0x10DE039A, "Quadro NVS 300M" },
{ 0x10DE039B, "GeForce Go 7900 SE" },
{ 0x10DE039C, "Quadro FX 550M" },
{ 0x10DE039E, "Quadro FX 560" },
{ 0x10DE0400, "GeForce 8600 GTS" },
{ 0x10DE0401, "GeForce 8600 GT" },
{ 0x10DE0402, "GeForce 8600 GT" },
{ 0x10DE0403, "GeForce 8600 GS" },
{ 0x10DE0404, "GeForce 8400 GS" },
{ 0x10DE0405, "GeForce 9500M GS" },
{ 0x10DE0407, "GeForce 8600M GT" },
{ 0x10DE0408, "GeForce 9650M GS" },
{ 0x10DE0409, "GeForce 8700M GT" },
{ 0x10DE040A, "Quadro FX 370" },
{ 0x10DE040B, "Quadro NVS 320M" },
{ 0x10DE040C, "Quadro FX 570M" },
{ 0x10DE040D, "Quadro FX 1600M" },
{ 0x10DE040E, "Quadro FX 570" },
{ 0x10DE040F, "Quadro FX 1700" },
{ 0x10DE0420, "GeForce 8400 SE" },
{ 0x10DE0421, "GeForce 8500 GT" },
{ 0x10DE0422, "GeForce 8400 GS" },
{ 0x10DE0423, "GeForce 8300 GS" },
{ 0x10DE0424, "GeForce 8400 GS" },
{ 0x10DE0425, "GeForce 8600M GS" },
{ 0x10DE0426, "GeForce 8400M GT" },
{ 0x10DE0427, "GeForce 8400M GS" },
{ 0x10DE0428, "GeForce 8400M G" },
{ 0x10DE0429, "Quadro NVS 140M" },
{ 0x10DE042A, "Quadro NVS 130M" },
{ 0x10DE042B, "Quadro NVS 135M" },
{ 0x10DE042C, "GeForce 9400 GT" },
{ 0x10DE042D, "Quadro FX 360M" },
{ 0x10DE042E, "GeForce 9300M G" },
{ 0x10DE042F, "Quadro NVS 290" },
{ 0x10DE05E0, "GeForce GTX 295" },
{ 0x10DE05E1, "GeForce GTX 280" },
{ 0x10DE05E2, "GeForce GTX 260" },
{ 0x10DE05E3, "GeForce GTX 285" },
{ 0x10DE05E6, "GeForce GTX 275" },
{ 0x10DE05EA, "GeForce GTX 260" },
{ 0x10DE05EB, "GeForce GTX 295" },
{ 0x10DE05F9, "Quadro CX" },
{ 0x10DE05FD, "Quadro FX 5800" },
{ 0x10DE05FE, "Quadro FX 4800" },
{ 0x10DE0600, "GeForce 8800 GTS 512" },
{ 0x10DE0602, "GeForce 8800 GT" },
{ 0x10DE0604, "GeForce 9800 GX2" },
{ 0x10DE0605, "GeForce 9800 GT" },
{ 0x10DE0606, "GeForce 8800 GS" },
{ 0x10DE0607, "GeForce GTS 240" },
{ 0x10DE0608, "GeForce 9800M GTX" },
{ 0x10DE0609, "GeForce 8800M GTS" },
{ 0x10DE060A, "GeForce GTX 280M" },
{ 0x10DE060B, "GeForce 9800M GT" },
{ 0x10DE060C, "GeForce 8800M GTX" },
{ 0x10DE060D, "GeForce 8800 GS" },
{ 0x10DE0610, "GeForce 9600 GSO" },
{ 0x10DE0611, "GeForce 8800 GT" },
{ 0x10DE0612, "GeForce 9800 GTX" },
{ 0x10DE0613, "GeForce 9800 GTX+" },
{ 0x10DE0614, "GeForce 9800 GT" },
{ 0x10DE0615, "GeForce GTS 250" },
{ 0x10DE0617, "GeForce 9800M GTX" },
{ 0x10DE0618, "GeForce GTX 260M" },
{ 0x10DE061A, "Quadro FX 3700" },
{ 0x10DE061C, "Quadro FX 3600M" },
{ 0x10DE061D, "Quadro FX 2800M" },
{ 0x10DE061F, "Quadro FX 3800M" },
{ 0x10DE0622, "GeForce 9600 GT" },
{ 0x10DE0623, "GeForce 9600 GS" },
{ 0x10DE0625, "GeForce 9600 GSO 512"},
{ 0x10DE0626, "GeForce GT 130" },
{ 0x10DE0627, "GeForce GT 140" },
{ 0x10DE0628, "GeForce 9800M GTS" },
{ 0x10DE062A, "GeForce 9700M GTS" },
{ 0x10DE062C, "GeForce 9800M GTS" },
{ 0x10DE0640, "GeForce 9500 GT" },
{ 0x10DE0641, "GeForce 9400 GT" },
{ 0x10DE0642, "GeForce 8400 GS" },
{ 0x10DE0643, "GeForce 9500 GT" },
{ 0x10DE0644, "GeForce 9500 GS" },
{ 0x10DE0645, "GeForce 9500 GS" },
{ 0x10DE0646, "GeForce GT 120" },
{ 0x10DE0647, "GeForce 9600M GT" },
{ 0x10DE0648, "GeForce 9600M GS" },
{ 0x10DE0649, "GeForce 9600M GT" },
{ 0x10DE064A, "GeForce 9700M GT" },
{ 0x10DE064B, "GeForce 9500M G" },
{ 0x10DE064C, "GeForce 9650M GT" },
{ 0x10DE0652, "GeForce GT 130M" },
{ 0x10DE0658, "Quadro FX 380" },
{ 0x10DE0659, "Quadro FX 580" },
{ 0x10DE065A, "Quadro FX 1700M" },
{ 0x10DE065B, "GeForce 9400 GT" },
{ 0x10DE065C, "Quadro FX 770M" },
{ 0x10DE06E0, "GeForce 9300 GE" },
{ 0x10DE06E1, "GeForce 9300 GS" },
{ 0x10DE06E4, "GeForce 8400 GS" },
{ 0x10DE06E5, "GeForce 9300M GS" },
{ 0x10DE06E8, "GeForce 9200M GS" },
{ 0x10DE06E9, "GeForce 9300M GS" },
{ 0x10DE06EA, "Quadro NVS 150M" },
{ 0x10DE06EB, "Quadro NVS 160M" },
{ 0x10DE06EC, "GeForce G 105M" },
{ 0x10DE06EF, "GeForce G 103M" },
{ 0x10DE06F8, "Quadro NVS 420" },
{ 0x10DE06F9, "Quadro FX 370 LP" },
{ 0x10DE06FA, "Quadro NVS 450" },
{ 0x10DE06FD, "Quadro NVS 295" },
{ 0x10DE086A, "GeForce 9400" },
{ 0x10DE0874, "ION 9300M" },
{ 0x10DE086C, "GeForce 9300/nForce 730i" },
{ 0x10DE087D, "ION 9400M" },
{ 0x10DE087E, "ION LE" },
{ 0x10DE0A20, "GeForce GT220" },
{ 0x10DE0A23, "GeForce 210" },
{ 0x10DE0A28, "GeForce GT 230M" },
{ 0x10DE0A29, "GeForce GT 330M" },
{ 0x10DE0A2A, "GeForce GT 230M" },
{ 0x10DE0A34, "GeForce GT 240M" },
{ 0x10DE0A60, "GeForce G210" },
{ 0x10DE0A62, "GeForce 205" },
{ 0x10DE0A63, "GeForce 310" },
{ 0x10DE0A65, "GeForce 210" },
{ 0x10DE0A66, "GeForce 310" },
{ 0x10DE0A74, "GeForce G210M" },
{ 0x10DE0A75, "GeForce G310M" },
{ 0x10DE0A78, "Quadro FX 380 LP" },
{ 0x10DE0CA3, "GeForce GT 240" },
{ 0x10DE0CA8, "GeForce GTS 260M" },
{ 0x10DE0CA9, "GeForce GTS 250M" },
{ 0x10DE0CB1, "GeForce GTS 360M" },
{ 0x10DE0CA3, "GeForce GT240" },
// 06C0 - 06DFF
{ 0x10DE06C0, "GeForce GTX 480" },
{ 0x10DE06C3, "GeForce GTX D12U" },
{ 0x10DE06C4, "GeForce GTX 465" },
{ 0x10DE06CA, "GeForce GTX 480M" },
{ 0x10DE06CD, "GeForce GTX 470" },
{ 0x10DE06D1, "Tesla C2050" },// TODO: sub-device id: 0x0771
{ 0x10DE06D1, "Tesla C2070" },// TODO: sub-device id: 0x0772
{ 0x10DE06D2, "Tesla M2070" },
{ 0x10DE06D8, "Quadro 6000" },
{ 0x10DE06D9, "Quadro 5000" },
{ 0x10DE06DA, "Quadro 5000M" },
{ 0x10DE06DC, "Quadro 6000" },
{ 0x10DE06DE, "Tesla M2050" },// TODO: sub-device id: 0x0846
{ 0x10DE06DE, "Tesla M2070" },// TODO: sub-device id: ?
// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070
{ 0x10DE06DD, "Quadro 4000" },
// 0DC0 - 0DFF
{ 0x10DE0DC0, "GeForce GT 440" },
{ 0x10DE0DC1, "D12-P1-35" },
{ 0x10DE0DC2, "D12-P1-35" },
{ 0x10DE0DC4, "GeForce GTS 450" },
{ 0x10DE0DC5, "GeForce GTS 450" },
{ 0x10DE0DC6, "GeForce GTS 450" },
{ 0x10DE0DCA, "GF10x" },
{ 0x10DE0DD1, "GeForce GTX 460M" },
{ 0x10DE0DD2, "GeForce GT 445M" },
{ 0x10DE0DD3, "GeForce GT 435M" },
{ 0x10DE0DD8, "Quadro 2000" },
{ 0x10DE0DDE, "GF106-ES" },
{ 0x10DE0DDF, "GF106-INT" },
{ 0x10DE0DE1, "GeForce GT 430" },
{ 0x10DE0DE2, "GeForce GT 420" },
{ 0x10DE0DEB, "GeForce GT 555M" },
{ 0x10DE0DEE, "GeForce GT 415M" },
{ 0x10DE0DF0, "GeForce GT 425M" },
{ 0x10DE0DF1, "GeForce GT 420M" },
{ 0x10DE0DF2, "GeForce GT 435M" },
{ 0x10DE0DF3, "GeForce GT 420M" },
{ 0x10DE0DF8, "Quadro 600" },
{ 0x10DE0DFE, "GF108 ES" },
{ 0x10DE0DFF, "GF108 INT" },
// 0E20 - 0E3F
{ 0x10DE0E21, "D12U-25" },
{ 0x10DE0E22, "GeForce GTX 460" },
{ 0x10DE0E23, "GeForce GTX 460 SE" },
{ 0x10DE0E24, "GeForce GTX 460" },
{ 0x10DE0E25, "D12U-50" },
{ 0x10DE0E30, "GeForce GTX 470M" },
{ 0x10DE0E38, "GF104GL" },
{ 0x10DE0E3E, "GF104-ES" },
{ 0x10DE0E3F, "GF104-INT" },
// 0EE0 - 0EFF: none yet
// 0F00 - 0F3F: none yet
// 1040 - 107F: none yet
// 1080 - 109F
{ 0x10DE1080, "GeForce GTX 580" },
{ 0x10DE1081, "D13U" },
{ 0x10DE1082, "D13U" },
{ 0x10DE1083, "D13U" },
{ 0x10DE1098, "D13U" },
{ 0x10DE109A, "N12E-Q5" },
};
static uint16_t swap16(uint16_t x)
{
return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));
}
static uint16_t read16(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[2];
ret[0] = ptr[offset+1];
ret[1] = ptr[offset];
return *((uint16_t*)&ret);
}
#if 0
static uint32_t swap32(uint32_t x)
{
return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);
}
static uint8_t read8(uint8_t *ptr, uint16_t offset)
{
return ptr[offset];
}
static uint32_t read32(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[4];
ret[0] = ptr[offset+3];
ret[1] = ptr[offset+2];
ret[2] = ptr[offset+1];
ret[3] = ptr[offset];
return *((uint32_t*)&ret);
}
#endif
static int patch_nvidia_rom(uint8_t *rom)
{
if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {
printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);
return PATCH_ROM_FAILED;
}
uint16_t dcbptr = swap16(read16(rom, 0x36));
if(!dcbptr) {
printf("no dcb table found\n");
return PATCH_ROM_FAILED;
}/* else
printf("dcb table at offset 0x%04x\n", dcbptr);
*/
uint8_t *dcbtable = &rom[dcbptr];
uint8_t dcbtable_version = dcbtable[0];
uint8_t headerlength = 0;
uint8_t recordlength = 0;
uint8_t numentries = 0;
if(dcbtable_version >= 0x20) {
uint32_t sig;
if(dcbtable_version >= 0x30) {
headerlength = dcbtable[1];
numentries = dcbtable[2];
recordlength = dcbtable[3];
sig = *(uint32_t *)&dcbtable[6];
} else {
sig = *(uint32_t *)&dcbtable[4];
headerlength = 8;
}
if (sig != 0x4edcbdcb) {
printf("bad display config block signature (0x%8x)\n", sig);
return PATCH_ROM_FAILED;
}
} else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */
char sig[8] = { 0 };
strncpy(sig, (char *)&dcbtable[-7], 7);
recordlength = 10;
if (strcmp(sig, "DEV_REC")) {
printf("Bad Display Configuration Block signature (%s)\n", sig);
return PATCH_ROM_FAILED;
}
} else {
printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);
return PATCH_ROM_FAILED;
}
if(numentries >= MAX_NUM_DCB_ENTRIES)
numentries = MAX_NUM_DCB_ENTRIES;
uint8_t num_outputs = 0, i=0;
struct dcbentry {
uint8_t type;
uint8_t index;
uint8_t *heads;
} entries[numentries];
for (i = 0; i < numentries; i++) {
uint32_t connection;
connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];
/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
continue;
if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */
continue;
if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */
continue;
entries[num_outputs].type = connection & 0xf;
entries[num_outputs].index = num_outputs;
entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);
}
int has_lvds = false;
uint8_t channel1 = 0, channel2 = 0;
for(i=0; i<num_outputs; i++) {
if(entries[i].type == 3) {
has_lvds = true;
//printf("found LVDS\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
}
// if we have a LVDS output, we group the rest to the second channel
if(has_lvds) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
continue;
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
} else {
//
int x;
// we loop twice as we need to generate two channels
for(x=0; x<=1; x++) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
continue;
// if type is TMDS, the prior output is ANALOG
// we always group ANALOG and TMDS
// if there is a TV output after TMDS, we group it to that channel as well
if(i && entries[i].type == 0x2) {
switch (x) {
case 0:
//printf("group channel 1\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if((entries[i-1].type == 0x0)) {
channel1 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
//printf("group tv1\n");
channel1 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
case 1:
//printf("group channel 2 : %d\n", i);
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if((entries[i-1].type == 0x0)) {
channel2 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
//printf("group tv2\n");
channel2 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
}
break;
}
}
}
}
// if we have left ungrouped outputs merge them to the empty channel
uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);
togroup = &channel2;
for(i=0; i<num_outputs;i++)
if(entries[i].type != TYPE_GROUPED) {
//printf("%d not grouped\n", i);
if(togroup)
*togroup |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
if(channel1 > channel2) {
uint8_t buff = channel1;
channel1 = channel2;
channel2 = buff;
}
default_NVCAP[6] = channel1;
default_NVCAP[8] = channel2;
// patching HEADS
for(i=0; i<num_outputs;i++) {
if(channel1 & (1 << i))
*entries[i].heads = 1;
else if(channel2 & (1 << i))
*entries[i].heads = 2;
}
return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);
}
static char *get_nvidia_model(uint32_t id) {
inti;
for (i=1; i< (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {
if (NVKnownChipsets[i].device == id) {
return NVKnownChipsets[i].name;
}
}
return NVKnownChipsets[0].name;
}
static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)
{
intfd;
intsize;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {
return 0;
}
size = file_size(fd);
if (size > bufsize) {
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);
size = bufsize;
}
size = read(fd, (char *)buf, size);
close(fd);
return size > 0 ? size : 0;
}
static int devprop_add_nvidia_template(struct DevPropDevice *device)
{
chartmp[16];
if(!device)
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_name_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_name_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type))
return 0;
// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!
// len = sprintf(tmp, "Slot-%x", devices_number);
sprintf(tmp, "Slot-%x",devices_number);
devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));
devices_number++;
return 1;
}
int hex2bin(const char *hex, uint8_t *bin, int len)
{
char*p;
inti;
charbuf[3];
if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {
printf("[ERROR] bin2hex input error\n");
return -1;
}
buf[2] = '\0';
p = (char *) hex;
for (i=0; i<len; i++) {
if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {
printf("[ERROR] bin2hex '%s' syntax error\n", hex);
return -2;
}
buf[0] = *p++;
buf[1] = *p++;
bin[i] = (unsigned char) strtoul(buf, NULL, 16);
}
return 0;
}
unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)
{
unsigned long long vram_size = 0;
if (nvCardType < NV_ARCH_50) {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
}
else if (nvCardType < NV_ARCH_C0) {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size |= (vram_size & 0xff) << 32;
vram_size &= 0xffffffff00ll;
}
else { // >= NV_ARCH_C0
vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;
vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);
}
return vram_size;
}
bool setup_nvidia_devprop(pci_dt_t *nvda_dev)
{
struct DevPropDevice*device;
char*devicepath;
option_rom_pci_header_t*rom_pci_header;
volatile uint8_t*regs;
uint8_t*rom;
uint8_t*nvRom;
uint8_tnvCardType;
unsigned long longvideoRam;
uint32_tnvBiosOveride;
uint32_tbar[7];
uint32_tboot_display;
intnvPatch;
intlen;
charbiosVersion[32];
charnvFilename[32];
charkNVCAP[12];
char*model;
const char*value;
booldoit;
devicepath = get_pci_dev_path(nvda_dev);
bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );
regs = (uint8_t *) (bar[0] & ~0x0f);
// get card type
nvCardType = (REG32(0) >> 20) & 0x1ff;
// Amount of VRAM in kilobytes
videoRam = mem_detect(regs, nvCardType, nvda_dev);
model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);
verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",
model, (uint32_t)(videoRam / 1024 / 1024),
(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,
devicepath);
rom = malloc(NVIDIA_ROM_SIZE);
sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id);
if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit) {
verbose("Looking for nvidia video bios file %s\n", nvFilename);
nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);
if (nvBiosOveride > 0) {
verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);
DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);
} else {
printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);
return false;
}
} else {
// Otherwise read bios from card
nvBiosOveride = 0;
// TODO: we should really check for the signature before copying the rom, i think.
// PRAMIN first
nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];
bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
// PROM next
// Enable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;
nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];
bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// disable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
// 0xC0000 last
bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
printf("ERROR: Unable to locate nVidia Video BIOS\n");
return false;
} else {
DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
} else {
DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
} else {
DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
}
if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {
printf("ERROR: nVidia ROM Patching Failed!\n");
//return false;
}
rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);
// check for 'PCIR' sig
if (rom_pci_header->signature == 0x50434952) {
if (rom_pci_header->device_id != nvda_dev->device_id) {
// Get Model from the OpROM
model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);
} else {
printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);
}
}
if (!string) {
string = devprop_create_string();
}
device = devprop_add_device(string, devicepath);
/* FIXME: for primary graphics card only */
boot_display = 1;
devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
if(nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {
uint8_t built_in = 0x01;
devprop_add_value(device, "@0,built-in", &built_in, 1);
}
// get bios version
const int MAX_BIOS_VERSION_LENGTH = 32;
char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);
memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);
int i, version_start;
int crlf_count = 0;
// only search the first 384 bytes
for(i = 0; i < 0x180; i++) {
if(rom[i] == 0x0D && rom[i+1] == 0x0A) {
crlf_count++;
// second 0x0D0A was found, extract bios version
if(crlf_count == 2) {
if(rom[i-1] == 0x20) i--; // strip last " "
for(version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--) {
// find start
if(rom[version_start] == 0x00) {
version_start++;
// strip "Version "
if(strncmp((const char*)rom+version_start, "Version ", 8) == 0) {
version_start += 8;
}
strncpy(version_str, (const char*)rom+version_start, i-version_start);
break;
}
}
break;
}
}
}
sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);
sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);
if (getValueForKey(kNVCAP, &value, &len, &bootInfo->bootConfig) && len == NVCAP_LEN * 2) {
uint8_tnew_NVCAP[NVCAP_LEN];
if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) {
verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);
memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);
}
}
#if DEBUG_NVCAP
printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",
default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],
default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],
default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],
default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],
default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);
#endif
devprop_add_nvidia_template(device);
devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);
devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);
devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);
if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit) {
devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));
}
stringdata = malloc(sizeof(uint8_t) * string->length);
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
branches/azimutz/Cleancut/i386/modules/NVIDIAGraphicsEnabler/Makefile
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MODULE_NAME = NVIDIAGraphicsEnabler
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = _$(MODULE_NAME)_start
MODULE_DEPENDENCIES =
DIR = NVIDIAGraphicsEnabler
MODULE_OBJS = nvidia.o NVIDIAGraphicsEnabler.o
OPTIM = -Os -Oz
DEBUG = -DNOTHING
#DEBUG = -DDEBUG_HELLO_WORLD=1
CFLAGS= $(RC_CFLAGS) $(OPTIM) $(MORECPP) -arch i386 -g -Wmost \
-D__ARCHITECTURE__=\"i386\" -DSAIO_INTERNAL_USER \
-DRCZ_COMPRESSED_FILE_SUPPORT $(DEBUG) \
-fno-builtin $(OMIT_FRAME_POINTER_CFLAG) \
-mpreferred-stack-boundary=2 -fno-align-functions -fno-stack-protector \
-march=pentium4 -msse2 -mfpmath=sse -msoft-float -fno-common
DEFINES=
CONFIG = hd
INC = -I. -I.. -I$(SYMROOT) -I$(UTILDIR) -I$(LIBSADIR) -I$(LIBSAIODIR) -I$(BOOT2DIR)
LIBS=
VPATH = $(OBJROOT):$(SYMROOT)
SFILES =
CFILES =
HFILES =
EXPORTED_HFILES =
INSTALLED_HFILES =
OTHERFILES = Makefile
ALLSRC = $(SFILES) $(CFILES) \
$(HFILES) $(OTHERFILES)
DIRS_NEEDED = $(OBJROOT) $(SYMROOT)
all embedtheme optionrom: dylib
include ../MakeInc.dir
branches/azimutz/Cleancut/i386/modules/IntelGraphicsEnabler/gma.c
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/**
Original patch by nawcom
http://forum.voodooprojects.org/index.php/topic,1029.msg4427.html#msg4427
**/
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#include "device_inject.h"
#include "gma.h"
#ifndef DEBUG_GMA
#define DEBUG_GMA 0
#endif
#if DEBUG_GMA
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
uint8_t GMAX3100_vals[22][4] = {
{ 0x01,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x08 },
{ 0x64,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x08 },
{ 0x01,0x00,0x00,0x00 },
{ 0x20,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x20,0x03,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x08,0x52,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x3B,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 }
};
uint8_t reg_TRUE[] = { 0x01 ,0x00 ,0x00 ,0x00 };
uint8_t reg_FALSE[] = { 0x00,0x00,0x00,0x00 };
static struct gma_gpu_t KnownGPUS[] = {
{ 0x00000000, "Unknown" },
{ 0x808627A2, "Mobile GMA950" },
{ 0x808627AE, "Mobile GMA950" },
{ 0x808627A6, "Mobile GMA950" },
{ 0x80862772, "Desktop GMA950" }, //Azi: never worked with mine.
{ 0x80862776, "Desktop GMA950" },
{ 0x80862A02, "GMAX3100" },
{ 0x80862A03, "GMAX3100" },
{ 0x80862A12, "GMAX3100" },
{ 0x80862A13, "GMAX3100" },
};
char *get_gma_model(uint32_t id) {
int i=0;
for(i = 0; i < (sizeof(KnownGPUS) / sizeof(KnownGPUS[0])); i++) {
if(KnownGPUS[i].device == id)
return KnownGPUS[i].name;
}
return KnownGPUS[0].name;
}
bool setup_gma_devprop(pci_dt_t *gma_dev)
{
//intlen;
char *devicepath;
volatile uint8_t *regs;
uint32_t bar[7];
char *model;
uint8_t BuiltIn = 0x00;
uint8_t ClassFix[4] = { 0x00, 0x00, 0x03, 0x00 };
devicepath = get_pci_dev_path(gma_dev);
bar[0] = pci_config_read32(gma_dev->dev.addr, 0x10);
regs = (uint8_t *) (bar[0] & ~0x0f);
model = get_gma_model((gma_dev->vendor_id << 16) | gma_dev->device_id);
verbose("Intel %s [%04x:%04x] :: %s\n",
model, gma_dev->vendor_id, gma_dev->device_id, devicepath);
if (!string)
string = devprop_create_string();
struct DevPropDevice *device = malloc(sizeof(struct DevPropDevice));
device = devprop_add_device(string, devicepath);
if(!device)
{
printf("Failed initializing dev-prop string dev-entry, press any key...\n");
getc();
return false;
}
devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1));
devprop_add_value(device, "device_type", (uint8_t*)"display", 8);
if (model == (char *)"Mobile GMA950") {
devprop_add_value(device, "AAPL,HasPanel", reg_TRUE, 4);
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
} else if (model == (char *)"Desktop GMA950") {
BuiltIn = 0x01;
devprop_add_value(device, "built-in", &BuiltIn, 1);
} else if (model == (char *)"GMAX3100") {
devprop_add_value(device, "AAPL,HasPanel",GMAX3100_vals[0], 4);
devprop_add_value(device, "AAPL,SelfRefreshSupported",GMAX3100_vals[1], 4);
devprop_add_value(device, "AAPL,aux-power-connected",GMAX3100_vals[2], 4);
devprop_add_value(device, "AAPL,backlight-control",GMAX3100_vals[3], 4);
devprop_add_value(device, "AAPL00,blackscreen-preferences",GMAX3100_vals[4], 4);
devprop_add_value(device, "AAPL01,BacklightIntensity",GMAX3100_vals[5], 4);
devprop_add_value(device, "AAPL01,blackscreen-preferences",GMAX3100_vals[6], 4);
devprop_add_value(device, "AAPL01,DataJustify",GMAX3100_vals[7], 4);
devprop_add_value(device, "AAPL01,Depth",GMAX3100_vals[8], 4);
devprop_add_value(device, "AAPL01,Dither",GMAX3100_vals[9], 4);
devprop_add_value(device, "AAPL01,DualLink",GMAX3100_vals[10], 4);
devprop_add_value(device, "AAPL01,Height",GMAX3100_vals[11], 4);
devprop_add_value(device, "AAPL01,Interlace",GMAX3100_vals[12], 4);
devprop_add_value(device, "AAPL01,Inverter",GMAX3100_vals[13], 4);
devprop_add_value(device, "AAPL01,InverterCurrent",GMAX3100_vals[14], 4);
devprop_add_value(device, "AAPL01,InverterCurrency",GMAX3100_vals[15], 4);
devprop_add_value(device, "AAPL01,LinkFormat",GMAX3100_vals[16], 4);
devprop_add_value(device, "AAPL01,LinkType",GMAX3100_vals[17], 4);
devprop_add_value(device, "AAPL01,Pipe",GMAX3100_vals[18], 4);
devprop_add_value(device, "AAPL01,PixelFormat",GMAX3100_vals[19], 4);
devprop_add_value(device, "AAPL01,Refresh",GMAX3100_vals[20], 4);
devprop_add_value(device, "AAPL01,Stretch",GMAX3100_vals[21], 4);
}
stringdata = malloc(sizeof(uint8_t) * string->length);
if(!stringdata)
{
printf("no stringdata press a key...\n");
getc();
return false;
}
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
branches/azimutz/Cleancut/i386/modules/IntelGraphicsEnabler/IntelGraphicsEnabler.c
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/*
* IntelGraphicsEnabler Module ---
* Enables "some" Intel cards to be used out of the box ?? in OS X.
* This was converted from ... // AutoResolution reminder ---
*
*/
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "gma.h"
#include "modules.h"
#define kGraphicsEnablerKey"GraphicsEnabler"
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4);
void IntelGraphicsEnabler_start()
{
register_hook_callback("PCIDevice", &GraphicsEnabler_hook);
}
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4)
{
pci_dt_t* current = arg1;
if (current->class_id != PCI_CLASS_DISPLAY_VGA) return;
char *devicepath = get_pci_dev_path(current);
bool do_gfx_devprop = true;
getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->bootConfig);
//Azi: check "fail" code...
if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_INTEL))
{
verbose("Intel VGA Controller [%04x:%04x] :: %s \n",
current->vendor_id, current->device_id, devicepath);
setup_gma_devprop(current);
}
else
verbose("Not a Intel VGA Controller.\n"); // ---
}
branches/azimutz/Cleancut/i386/modules/IntelGraphicsEnabler/gma.h
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#ifndef __LIBSAIO_GMA_H
#define __LIBSAIO_GMA_H
bool setup_gma_devprop(pci_dt_t *gma_dev);
struct gma_gpu_t {
unsigned device;
char *name;
};
#define REG8(reg) ((volatile uint8_t *)regs)[(reg)]
#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1]
#define REG32(reg) ((volatile uint32_t *)regs)[(reg) >> 2]
#endif /* !__LIBSAIO_GMA_H */
branches/azimutz/Cleancut/i386/modules/IntelGraphicsEnabler/Readme.txt
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Module:IntelGraphicsEnabler
Description: Enables "some" Intel cards to be used out of the box ?? in OS X.
This was converted from ...
Dependencies: none
Keys: GraphicsEnabler (enabled by default)
TODO: ---
branches/azimutz/Cleancut/i386/modules/IntelGraphicsEnabler/Makefile
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MODULE_NAME = IntelGraphicsEnabler
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = _$(MODULE_NAME)_start
MODULE_DEPENDENCIES =
DIR = IntelGraphicsEnabler
MODULE_OBJS = gma.o IntelGraphicsEnabler.o
OPTIM = -Os -Oz
DEBUG = -DNOTHING
#DEBUG = -DDEBUG_HELLO_WORLD=1
CFLAGS= $(RC_CFLAGS) $(OPTIM) $(MORECPP) -arch i386 -g -Wmost \
-D__ARCHITECTURE__=\"i386\" -DSAIO_INTERNAL_USER \
-DRCZ_COMPRESSED_FILE_SUPPORT $(DEBUG) \
-fno-builtin $(OMIT_FRAME_POINTER_CFLAG) \
-mpreferred-stack-boundary=2 -fno-align-functions -fno-stack-protector \
-march=pentium4 -msse2 -mfpmath=sse -msoft-float -fno-common
DEFINES=
CONFIG = hd
INC = -I. -I.. -I$(SYMROOT) -I$(UTILDIR) -I$(LIBSADIR) -I$(LIBSAIODIR) -I$(BOOT2DIR)
LIBS=
VPATH = $(OBJROOT):$(SYMROOT)
SFILES =
CFILES =
HFILES =
EXPORTED_HFILES =
INSTALLED_HFILES =
OTHERFILES = Makefile
ALLSRC = $(SFILES) $(CFILES) \
$(HFILES) $(OTHERFILES)
DIRS_NEEDED = $(OBJROOT) $(SYMROOT)
all embedtheme optionrom: dylib
include ../MakeInc.dir
branches/azimutz/Cleancut/i386/modules/ATiGraphicsEnabler/pci_old.h
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/*
*
* Copyright 2008 by Islam M. Ahmed Zaid. All rights reserved.
*
*/
#ifndef __PCI_OLD_H
#define __PCI_OLD_H
typedef struct {
uint32_t:2;
uint32_treg:6;
uint32_tfunc:3;
uint32_tdev:5;
uint32_tbus:8;
uint32_t:7;
uint32_teb:1;
} pci_addr_t;
typedef union {
pci_addr_tbits;
uint32_taddr;
} pci_dev_t;
typedef struct pci_dt_t {
pci_dev_tdev;
uint16_tvendor_id;
uint16_tdevice_id;
union {
struct {
uint16_tvendor_id;
uint16_tdevice_id;
} subsys;
uint32_t subsys_id;
} subsys_id;
uint16_tclass_id;
struct pci_dt_t*parent;
struct pci_dt_t*children;
struct pci_dt_t*next;
} pci_dt_t;
#define PCIADDR(bus, dev, func)(1 << 31) | (bus << 16) | (dev << 11) | (func << 8)
#define PCI_ADDR_REG0xcf8
#define PCI_DATA_REG0xcfc
extern pci_dt_t*root_pci_dev;
extern uint8_tpci_config_read8(uint32_t, uint8_t);
extern uint16_tpci_config_read16(uint32_t, uint8_t);
extern uint32_tpci_config_read32(uint32_t, uint8_t);
extern voidpci_config_write8(uint32_t, uint8_t, uint8_t);
extern voidpci_config_write16(uint32_t, uint8_t, uint16_t);
extern voidpci_config_write32(uint32_t, uint8_t, uint32_t);
extern char*get_pci_dev_path(pci_dt_t *);
extern voidbuild_pci_dt(void);
extern voiddump_pci_dt(pci_dt_t *);
//-----------------------------------------------------------------------------
// added by iNDi
struct pci_rom_pci_header_t {
uint32_tsignature;// 0x50434952 'PCIR'
uint16_tvendor;
uint16_tdevice;
uint16_tproduct;
uint16_tlength;
uint8_trevision;// 0 = PCI 2.1
uint8_tclass[3];
uint16_trom_size;
uint16_tcode_revision;
uint8_tcode_type;// 0 = x86
uint8_tlast_image;// 0x80
uint16_treserverd;
};
struct pci_rom_pnp_header_t {
uint32_tsignature;// 0x24506E50 '$PnP'
uint8_trevision;// 1
uint8_tlength;//
uint16_toffset;
uint8_tchecksum;
uint32_tidentifier;
uint16_tmanufacturer;
uint16_tproduct;
uint8_tclass[3];
uint8_tindicators;
uint16_tboot_vector;
uint16_tdisconnect_vector;
uint16_tbootstrap_vector;
uint16_treserved;
uint16_tresource_vector;
};
struct pci_rom_bios_t {
uint16_tsignature;// 0x55AA
uint8_tsize;// Multiples of 512
uint8_tchecksum;// 0x00
uint16_tpci_header;
uint16_tpnp_header;
};
/*
* Under PCI, each device has 256 bytes of configuration address space,
* of which the first 64 bytes are standardized as follows:
*/
#define PCI_VENDOR_ID0x00/* 16 bits */
#define PCI_DEVICE_ID0x02/* 16 bits */
#define PCI_COMMAND0x04/* 16 bits */
#define PCI_COMMAND_IO0x1/* Enable response in I/O space */
#define PCI_COMMAND_MEMORY0x2/* Enable response in Memory space */
#define PCI_COMMAND_MASTER0x4/* Enable bus mastering */
#define PCI_COMMAND_SPECIAL0x8/* Enable response to special cycles */
#define PCI_COMMAND_INVALIDATE0x10/* Use memory write and invalidate */
#define PCI_COMMAND_VGA_PALETTE0x20/* Enable palette snooping */
#define PCI_COMMAND_PARITY0x40/* Enable parity checking */
#define PCI_COMMAND_WAIT0x80/* Enable address/data stepping */
#define PCI_COMMAND_SERR0x100/* Enable SERR */
#define PCI_COMMAND_FAST_BACK0x200/* Enable back-to-back writes */
#define PCI_COMMAND_DISABLE_INTx0x400/* PCIE: Disable INTx interrupts */
#define PCI_STATUS0x06/* 16 bits */
#define PCI_STATUS_INTx0x08/* PCIE: INTx interrupt pending */
#define PCI_STATUS_CAP_LIST0x10/* Support Capability List */
#define PCI_STATUS_66MHZ0x20/* Support 66 Mhz PCI 2.1 bus */
#define PCI_STATUS_UDF0x40/* Support User Definable Features [obsolete] */
#define PCI_STATUS_FAST_BACK0x80/* Accept fast-back to back */
#define PCI_STATUS_PARITY0x100/* Detected parity error */
#define PCI_STATUS_DEVSEL_MASK0x600/* DEVSEL timing */
#define PCI_STATUS_DEVSEL_FAST0x000
#define PCI_STATUS_DEVSEL_MEDIUM0x200
#define PCI_STATUS_DEVSEL_SLOW0x400
#define PCI_STATUS_SIG_TARGET_ABORT 0x800/* Set on target abort */
#define PCI_STATUS_REC_TARGET_ABORT 0x1000/* Master ack of " */
#define PCI_STATUS_REC_MASTER_ABORT 0x2000/* Set on master abort */
#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000/* Set when we drive SERR */
#define PCI_STATUS_DETECTED_PARITY0x8000/* Set on parity error */
#define PCI_CLASS_REVISION0x08/* High 24 bits are class, low 8 revision */
#define PCI_REVISION_ID0x08 /* Revision ID */
#define PCI_CLASS_PROG0x09 /* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE0x0a /* Device class */
#define PCI_CACHE_LINE_SIZE0x0c/* 8 bits */
#define PCI_LATENCY_TIMER0x0d/* 8 bits */
#define PCI_HEADER_TYPE0x0e/* 8 bits */
#define PCI_HEADER_TYPE_NORMAL0
#define PCI_HEADER_TYPE_BRIDGE1
#define PCI_HEADER_TYPE_CARDBUS2
#define PCI_BIST0x0f/* 8 bits */
#define PCI_BIST_CODE_MASK0x0f/* Return result */
#define PCI_BIST_START0x40/* 1 to start BIST, 2 secs or less */
#define PCI_BIST_CAPABLE0x80/* 1 if BIST capable */
/*
* Base addresses specify locations in memory or I/O space.
* Decoded size can be determined by writing a value of
* 0xffffffff to the register, and reading it back. Only
* 1 bits are decoded.
*/
#define PCI_BASE_ADDRESS_00x10/* 32 bits */
#define PCI_BASE_ADDRESS_10x14/* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_20x18/* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_30x1c/* 32 bits */
#define PCI_BASE_ADDRESS_40x20/* 32 bits */
#define PCI_BASE_ADDRESS_50x24/* 32 bits */
#define PCI_BASE_ADDRESS_SPACE0x01/* 0 = memory, 1 = I/O */
#define PCI_BASE_ADDRESS_SPACE_IO0x01
#define PCI_BASE_ADDRESS_SPACE_MEMORY0x00
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK0x06
#define PCI_BASE_ADDRESS_MEM_TYPE_320x00/* 32 bit address */
#define PCI_BASE_ADDRESS_MEM_TYPE_1M0x02/* Below 1M [obsolete] */
#define PCI_BASE_ADDRESS_MEM_TYPE_640x04/* 64 bit address */
#define PCI_BASE_ADDRESS_MEM_PREFETCH0x08/* prefetchable? */
#define PCI_BASE_ADDRESS_MEM_MASK(~(pciaddr_t)0x0f)
#define PCI_BASE_ADDRESS_IO_MASK(~(pciaddr_t)0x03)
/* bit 1 is reserved if address_space = 1 */
/* Header type 0 (normal devices) */
#define PCI_CARDBUS_CIS0x28
#define PCI_SUBSYSTEM_VENDOR_ID0x2c
#define PCI_SUBSYSTEM_ID0x2e
#define PCI_ROM_ADDRESS0x30/* Bits 31..11 are address, 10..1 reserved */
#define PCI_ROM_ADDRESS_ENABLE0x01
#define PCI_ROM_ADDRESS_MASK(~(pciaddr_t)0x7ff)
#define PCI_CAPABILITY_LIST0x34/* Offset of first capability list entry */
/* 0x35-0x3b are reserved */
#define PCI_INTERRUPT_LINE0x3c/* 8 bits */
#define PCI_INTERRUPT_PIN0x3d/* 8 bits */
#define PCI_MIN_GNT0x3e/* 8 bits */
#define PCI_MAX_LAT0x3f/* 8 bits */
/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_PRIMARY_BUS0x18/* Primary bus number */
#define PCI_SECONDARY_BUS0x19/* Secondary bus number */
#define PCI_SUBORDINATE_BUS0x1a/* Highest bus number behind the bridge */
#define PCI_SEC_LATENCY_TIMER0x1b/* Latency timer for secondary interface */
#define PCI_IO_BASE0x1c/* I/O range behind the bridge */
#define PCI_IO_LIMIT0x1d
#define PCI_IO_RANGE_TYPE_MASK0x0f/* I/O bridging type */
#define PCI_IO_RANGE_TYPE_160x00
#define PCI_IO_RANGE_TYPE_320x01
#define PCI_IO_RANGE_MASK~0x0f
#define PCI_SEC_STATUS0x1e/* Secondary status register */
#define PCI_MEMORY_BASE0x20/* Memory range behind */
#define PCI_MEMORY_LIMIT0x22
#define PCI_MEMORY_RANGE_TYPE_MASK0x0f
#define PCI_MEMORY_RANGE_MASK~0x0f
#define PCI_PREF_MEMORY_BASE0x24/* Prefetchable memory range behind */
#define PCI_PREF_MEMORY_LIMIT0x26
#define PCI_PREF_RANGE_TYPE_MASK0x0f
#define PCI_PREF_RANGE_TYPE_320x00
#define PCI_PREF_RANGE_TYPE_640x01
#define PCI_PREF_RANGE_MASK~0x0f
#define PCI_PREF_BASE_UPPER320x28/* Upper half of prefetchable memory range */
#define PCI_PREF_LIMIT_UPPER320x2c
#define PCI_IO_BASE_UPPER160x30/* Upper half of I/O addresses */
#define PCI_IO_LIMIT_UPPER160x32
/* 0x34 same as for htype 0 */
/* 0x35-0x3b is reserved */
#define PCI_ROM_ADDRESS10x38/* Same as PCI_ROM_ADDRESS, but for htype 1 */
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_BRIDGE_CONTROL0x3e
#define PCI_BRIDGE_CTL_PARITY0x01/* Enable parity detection on secondary interface */
#define PCI_BRIDGE_CTL_SERR0x02/* The same for SERR forwarding */
#define PCI_BRIDGE_CTL_NO_ISA0x04/* Disable bridging of ISA ports */
#define PCI_BRIDGE_CTL_VGA0x08/* Forward VGA addresses */
#define PCI_BRIDGE_CTL_MASTER_ABORT0x20/* Report master aborts */
#define PCI_BRIDGE_CTL_BUS_RESET0x40/* Secondary bus reset */
#define PCI_BRIDGE_CTL_FAST_BACK0x80/* Fast Back2Back enabled on secondary interface */
#define PCI_BRIDGE_CTL_PRI_DISCARD_TIMER 0x100/* PCI-X? */
#define PCI_BRIDGE_CTL_SEC_DISCARD_TIMER 0x200/* PCI-X? */
#define PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS 0x400/* PCI-X? */
#define PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800/* PCI-X? */
/* Header type 2 (CardBus bridges) */
/* 0x14-0x15 reserved */
#define PCI_CB_SEC_STATUS0x16/* Secondary status */
#define PCI_CB_PRIMARY_BUS0x18/* PCI bus number */
#define PCI_CB_CARD_BUS0x19/* CardBus bus number */
#define PCI_CB_SUBORDINATE_BUS0x1a/* Subordinate bus number */
#define PCI_CB_LATENCY_TIMER0x1b/* CardBus latency timer */
#define PCI_CB_MEMORY_BASE_00x1c
#define PCI_CB_MEMORY_LIMIT_00x20
#define PCI_CB_MEMORY_BASE_10x24
#define PCI_CB_MEMORY_LIMIT_10x28
#define PCI_CB_IO_BASE_00x2c
#define PCI_CB_IO_BASE_0_HI0x2e
#define PCI_CB_IO_LIMIT_00x30
#define PCI_CB_IO_LIMIT_0_HI0x32
#define PCI_CB_IO_BASE_10x34
#define PCI_CB_IO_BASE_1_HI0x36
#define PCI_CB_IO_LIMIT_10x38
#define PCI_CB_IO_LIMIT_1_HI0x3a
#define PCI_CB_IO_RANGE_MASK~0x03
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_CB_BRIDGE_CONTROL0x3e
#define PCI_CB_BRIDGE_CTL_PARITY0x01/* Similar to standard bridge control register */
#define PCI_CB_BRIDGE_CTL_SERR0x02
#define PCI_CB_BRIDGE_CTL_ISA0x04
#define PCI_CB_BRIDGE_CTL_VGA0x08
#define PCI_CB_BRIDGE_CTL_MASTER_ABORT0x20
#define PCI_CB_BRIDGE_CTL_CB_RESET0x40/* CardBus reset */
#define PCI_CB_BRIDGE_CTL_16BIT_INT0x80/* Enable interrupt for 16-bit cards */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100/* Prefetch enable for both memory regions */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
#define PCI_CB_BRIDGE_CTL_POST_WRITES0x400
#define PCI_CB_SUBSYSTEM_VENDOR_ID0x40
#define PCI_CB_SUBSYSTEM_ID0x42
#define PCI_CB_LEGACY_MODE_BASE0x44/* 16-bit PC Card legacy mode base address (ExCa) */
/* 0x48-0x7f reserved */
/* Capability lists */
#define PCI_CAP_LIST_ID0/* Capability ID */
#define PCI_CAP_ID_PM0x01/* Power Management */
#define PCI_CAP_ID_AGP0x02/* Accelerated Graphics Port */
#define PCI_CAP_ID_VPD0x03/* Vital Product Data */
#define PCI_CAP_ID_SLOTID0x04/* Slot Identification */
#define PCI_CAP_ID_MSI0x05/* Message Signaled Interrupts */
#define PCI_CAP_ID_CHSWP0x06/* CompactPCI HotSwap */
#define PCI_CAP_ID_PCIX0x07/* PCI-X */
#define PCI_CAP_ID_HT0x08/* HyperTransport */
#define PCI_CAP_ID_VNDR0x09/* Vendor specific */
#define PCI_CAP_ID_DBG0x0A/* Debug port */
#define PCI_CAP_ID_CCRC0x0B/* CompactPCI Central Resource Control */
#define PCI_CAP_ID_HOTPLUG0x0C/* PCI hot-plug */
#define PCI_CAP_ID_SSVID0x0D/* Bridge subsystem vendor/device ID */
#define PCI_CAP_ID_AGP30x0E/* AGP 8x */
#define PCI_CAP_ID_SECURE0x0F/* Secure device (?) */
#define PCI_CAP_ID_EXP0x10/* PCI Express */
#define PCI_CAP_ID_MSIX0x11/* MSI-X */
#define PCI_CAP_ID_SATA0x12/* Serial-ATA HBA */
#define PCI_CAP_ID_AF0x13/* Advanced features of PCI devices integrated in PCIe root cplx */
#define PCI_CAP_LIST_NEXT1/* Next capability in the list */
#define PCI_CAP_FLAGS2/* Capability defined flags (16 bits) */
#define PCI_CAP_SIZEOF4
/* Capabilities residing in the PCI Express extended configuration space */
#define PCI_EXT_CAP_ID_AER0x01/* Advanced Error Reporting */
#define PCI_EXT_CAP_ID_VC0x02/* Virtual Channel */
#define PCI_EXT_CAP_ID_DSN0x03/* Device Serial Number */
#define PCI_EXT_CAP_ID_PB0x04/* Power Budgeting */
#define PCI_EXT_CAP_ID_RCLINK0x05/* Root Complex Link Declaration */
#define PCI_EXT_CAP_ID_RCILINK0x06/* Root Complex Internal Link Declaration */
#define PCI_EXT_CAP_ID_RCECOLL0x07/* Root Complex Event Collector */
#define PCI_EXT_CAP_ID_MFVC0x08/* Multi-Function Virtual Channel */
#define PCI_EXT_CAP_ID_RBCB0x0a/* Root Bridge Control Block */
#define PCI_EXT_CAP_ID_VNDR0x0b/* Vendor specific */
#define PCI_EXT_CAP_ID_ACS0x0d/* Access Controls */
#define PCI_EXT_CAP_ID_ARI0x0e/* Alternative Routing-ID Interpretation */
#define PCI_EXT_CAP_ID_ATS0x0f/* Address Translation Service */
#define PCI_EXT_CAP_ID_SRIOV0x10/* Single Root I/O Virtualization */
/* Power Management Registers */
#define PCI_PM_CAP_VER_MASK0x0007/* Version (2=PM1.1) */
#define PCI_PM_CAP_PME_CLOCK0x0008/* Clock required for PME generation */
#define PCI_PM_CAP_DSI0x0020/* Device specific initialization required */
#define PCI_PM_CAP_AUX_C_MASK0x01c0/* Maximum aux current required in D3cold */
#define PCI_PM_CAP_D10x0200/* D1 power state support */
#define PCI_PM_CAP_D20x0400/* D2 power state support */
#define PCI_PM_CAP_PME_D00x0800/* PME can be asserted from D0 */
#define PCI_PM_CAP_PME_D10x1000/* PME can be asserted from D1 */
#define PCI_PM_CAP_PME_D20x2000/* PME can be asserted from D2 */
#define PCI_PM_CAP_PME_D3_HOT0x4000/* PME can be asserted from D3hot */
#define PCI_PM_CAP_PME_D3_COLD0x8000/* PME can be asserted from D3cold */
#define PCI_PM_CTRL4/* PM control and status register */
#define PCI_PM_CTRL_STATE_MASK0x0003/* Current power state (D0 to D3) */
#define PCI_PM_CTRL_PME_ENABLE0x0100/* PME pin enable */
#define PCI_PM_CTRL_DATA_SEL_MASK0x1e00/* PM table data index */
#define PCI_PM_CTRL_DATA_SCALE_MASK0x6000/* PM table data scaling factor */
#define PCI_PM_CTRL_PME_STATUS0x8000/* PME pin status */
#define PCI_PM_PPB_EXTENSIONS6/* PPB support extensions */
#define PCI_PM_PPB_B2_B30x40/* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */
#define PCI_PM_BPCC_ENABLE0x80/* Secondary bus is power managed */
#define PCI_PM_DATA_REGISTER7/* PM table contents read here */
#define PCI_PM_SIZEOF8
/* AGP registers */
#define PCI_AGP_VERSION2/* BCD version number */
#define PCI_AGP_RFU3/* Rest of capability flags */
#define PCI_AGP_STATUS4/* Status register */
#define PCI_AGP_STATUS_RQ_MASK0xff000000/* Maximum number of requests - 1 */
#define PCI_AGP_STATUS_ISOCH0x10000/* Isochronous transactions supported */
#define PCI_AGP_STATUS_ARQSZ_MASK0xe000/* log2(optimum async req size in bytes) - 4 */
#define PCI_AGP_STATUS_CAL_MASK0x1c00/* Calibration cycle timing */
#define PCI_AGP_STATUS_SBA0x0200/* Sideband addressing supported */
#define PCI_AGP_STATUS_ITA_COH0x0100/* In-aperture accesses always coherent */
#define PCI_AGP_STATUS_GART640x0080/* 64-bit GART entries supported */
#define PCI_AGP_STATUS_HTRANS0x0040/* If 0, core logic can xlate host CPU accesses thru aperture */
#define PCI_AGP_STATUS_64BIT0x0020/* 64-bit addressing cycles supported */
#define PCI_AGP_STATUS_FW0x0010/* Fast write transfers supported */
#define PCI_AGP_STATUS_AGP30x0008/* AGP3 mode supported */
#define PCI_AGP_STATUS_RATE40x0004/* 4x transfer rate supported (RFU in AGP3 mode) */
#define PCI_AGP_STATUS_RATE20x0002/* 2x transfer rate supported (8x in AGP3 mode) */
#define PCI_AGP_STATUS_RATE10x0001/* 1x transfer rate supported (4x in AGP3 mode) */
#define PCI_AGP_COMMAND8/* Control register */
#define PCI_AGP_COMMAND_RQ_MASK0xff000000 /* Master: Maximum number of requests */
#define PCI_AGP_COMMAND_ARQSZ_MASK0xe000/* log2(optimum async req size in bytes) - 4 */
#define PCI_AGP_COMMAND_CAL_MASK0x1c00/* Calibration cycle timing */
#define PCI_AGP_COMMAND_SBA0x0200/* Sideband addressing enabled */
#define PCI_AGP_COMMAND_AGP0x0100/* Allow processing of AGP transactions */
#define PCI_AGP_COMMAND_GART640x0080/* 64-bit GART entries enabled */
#define PCI_AGP_COMMAND_64BIT0x0020/* Allow generation of 64-bit addr cycles */
#define PCI_AGP_COMMAND_FW0x0010/* Enable FW transfers */
#define PCI_AGP_COMMAND_RATE40x0004/* Use 4x rate (RFU in AGP3 mode) */
#define PCI_AGP_COMMAND_RATE20x0002/* Use 2x rate (8x in AGP3 mode) */
#define PCI_AGP_COMMAND_RATE10x0001/* Use 1x rate (4x in AGP3 mode) */
#define PCI_AGP_SIZEOF12
/* Vital Product Data */
#define PCI_VPD_ADDR2/* Address to access (15 bits!) */
#define PCI_VPD_ADDR_MASK0x7fff/* Address mask */
#define PCI_VPD_ADDR_F0x8000/* Write 0, 1 indicates completion */
#define PCI_VPD_DATA4/* 32-bits of data returned here */
/* Slot Identification */
#define PCI_SID_ESR2/* Expansion Slot Register */
#define PCI_SID_ESR_NSLOTS0x1f/* Number of expansion slots available */
#define PCI_SID_ESR_FIC0x20/* First In Chassis Flag */
#define PCI_SID_CHASSIS_NR3/* Chassis Number */
/* Message Signaled Interrupts registers */
#define PCI_MSI_FLAGS2/* Various flags */
#define PCI_MSI_FLAGS_MASK_BIT0x100/* interrupt masking & reporting supported */
#define PCI_MSI_FLAGS_64BIT0x080/* 64-bit addresses allowed */
#define PCI_MSI_FLAGS_QSIZE0x070/* Message queue size configured */
#define PCI_MSI_FLAGS_QMASK0x00e/* Maximum queue size available */
#define PCI_MSI_FLAGS_ENABLE0x001/* MSI feature enabled */
#define PCI_MSI_RFU3/* Rest of capability flags */
#define PCI_MSI_ADDRESS_LO4/* Lower 32 bits */
#define PCI_MSI_ADDRESS_HI8/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
#define PCI_MSI_DATA_328/* 16 bits of data for 32-bit devices */
#define PCI_MSI_DATA_6412/* 16 bits of data for 64-bit devices */
#define PCI_MSI_MASK_BIT_3212/* per-vector masking for 32-bit devices */
#define PCI_MSI_MASK_BIT_6416/* per-vector masking for 64-bit devices */
#define PCI_MSI_PENDING_3216/* per-vector interrupt pending for 32-bit devices */
#define PCI_MSI_PENDING_6420/* per-vector interrupt pending for 64-bit devices */
/* PCI-X */
#define PCI_PCIX_COMMAND 2 /* Command register offset */
#define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */
#define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
#define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */
#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
#define PCI_PCIX_COMMAND_RESERVED 0xf80
#define PCI_PCIX_STATUS 4 /* Status register offset */
#define PCI_PCIX_STATUS_FUNCTION 0x00000007
#define PCI_PCIX_STATUS_DEVICE 0x000000f8
#define PCI_PCIX_STATUS_BUS 0x0000ff00
#define PCI_PCIX_STATUS_64BIT 0x00010000
#define PCI_PCIX_STATUS_133MHZ 0x00020000
#define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
#define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
#define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */
#define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
#define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000
#define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000
#define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */
#define PCI_PCIX_STATUS_266MHZ0x40000000 /* 266 MHz capable */
#define PCI_PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
#define PCI_PCIX_SIZEOF4
/* PCI-X Bridges */
#define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */
#define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001
#define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002
#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */
#define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */
#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */
#define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020
#define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0
#define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00
#define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */
#define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007
#define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8
#define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00
#define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000
#define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000
#define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
#define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
#define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */
#define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000
#define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000
#define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */
#define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */
#define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff
#define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000
#define PCI_PCIX_BRIDGE_SIZEOF 12
/* PCI Express */
#define PCI_EXP_FLAGS0x2/* Capabilities register */
#define PCI_EXP_FLAGS_VERS0x000f/* Capability version */
#define PCI_EXP_FLAGS_TYPE0x00f0/* Device/Port type */
#define PCI_EXP_TYPE_ENDPOINT0x0/* Express Endpoint */
#define PCI_EXP_TYPE_LEG_END0x1/* Legacy Endpoint */
#define PCI_EXP_TYPE_ROOT_PORT 0x4/* Root Port */
#define PCI_EXP_TYPE_UPSTREAM0x5/* Upstream Port */
#define PCI_EXP_TYPE_DOWNSTREAM 0x6/* Downstream Port */
#define PCI_EXP_TYPE_PCI_BRIDGE 0x7/* PCI/PCI-X Bridge */
#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8/* PCI/PCI-X to PCIE Bridge */
#define PCI_EXP_TYPE_ROOT_INT_EP 0x9/* Root Complex Integrated Endpoint */
#define PCI_EXP_TYPE_ROOT_EC 0xa/* Root Complex Event Collector */
#define PCI_EXP_FLAGS_SLOT0x0100/* Slot implemented */
#define PCI_EXP_FLAGS_IRQ0x3e00/* Interrupt message number */
#define PCI_EXP_DEVCAP0x4/* Device capabilities */
#define PCI_EXP_DEVCAP_PAYLOAD0x07/* Max_Payload_Size */
#define PCI_EXP_DEVCAP_PHANTOM0x18/* Phantom functions */
#define PCI_EXP_DEVCAP_EXT_TAG0x20/* Extended tags */
#define PCI_EXP_DEVCAP_L0S0x1c0/* L0s Acceptable Latency */
#define PCI_EXP_DEVCAP_L10xe00/* L1 Acceptable Latency */
#define PCI_EXP_DEVCAP_ATN_BUT0x1000/* Attention Button Present */
#define PCI_EXP_DEVCAP_ATN_IND0x2000/* Attention Indicator Present */
#define PCI_EXP_DEVCAP_PWR_IND0x4000/* Power Indicator Present */
#define PCI_EXP_DEVCAP_RBE0x8000/* Role-Based Error Reporting */
#define PCI_EXP_DEVCAP_PWR_VAL0x3fc0000 /* Slot Power Limit Value */
#define PCI_EXP_DEVCAP_PWR_SCL0xc000000 /* Slot Power Limit Scale */
#define PCI_EXP_DEVCAP_FLRESET0x10000000 /* Function-Level Reset */
#define PCI_EXP_DEVCTL0x8/* Device Control */
#define PCI_EXP_DEVCTL_CERE0x0001/* Correctable Error Reporting En. */
#define PCI_EXP_DEVCTL_NFERE0x0002/* Non-Fatal Error Reporting Enable */
#define PCI_EXP_DEVCTL_FERE0x0004/* Fatal Error Reporting Enable */
#define PCI_EXP_DEVCTL_URRE0x0008/* Unsupported Request Reporting En. */
#define PCI_EXP_DEVCTL_RELAXED0x0010/* Enable Relaxed Ordering */
#define PCI_EXP_DEVCTL_PAYLOAD0x00e0/* Max_Payload_Size */
#define PCI_EXP_DEVCTL_EXT_TAG0x0100/* Extended Tag Field Enable */
#define PCI_EXP_DEVCTL_PHANTOM0x0200/* Phantom Functions Enable */
#define PCI_EXP_DEVCTL_AUX_PME0x0400/* Auxiliary Power PM Enable */
#define PCI_EXP_DEVCTL_NOSNOOP0x0800/* Enable No Snoop */
#define PCI_EXP_DEVCTL_READRQ0x7000/* Max_Read_Request_Size */
#define PCI_EXP_DEVCTL_BCRE0x8000/* Bridge Configuration Retry Enable */
#define PCI_EXP_DEVCTL_FLRESET0x8000/* Function-Level Reset [bit shared with BCRE] */
#define PCI_EXP_DEVSTA0xa/* Device Status */
#define PCI_EXP_DEVSTA_CED0x01/* Correctable Error Detected */
#define PCI_EXP_DEVSTA_NFED0x02/* Non-Fatal Error Detected */
#define PCI_EXP_DEVSTA_FED0x04/* Fatal Error Detected */
#define PCI_EXP_DEVSTA_URD0x08/* Unsupported Request Detected */
#define PCI_EXP_DEVSTA_AUXPD0x10/* AUX Power Detected */
#define PCI_EXP_DEVSTA_TRPND0x20/* Transactions Pending */
#define PCI_EXP_LNKCAP0xc/* Link Capabilities */
#define PCI_EXP_LNKCAP_SPEED0x0000f/* Maximum Link Speed */
#define PCI_EXP_LNKCAP_WIDTH0x003f0/* Maximum Link Width */
#define PCI_EXP_LNKCAP_ASPM0x00c00/* Active State Power Management */
#define PCI_EXP_LNKCAP_L0S0x07000/* L0s Acceptable Latency */
#define PCI_EXP_LNKCAP_L10x38000/* L1 Acceptable Latency */
#define PCI_EXP_LNKCAP_CLOCKPM0x40000/* Clock Power Management */
#define PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
#define PCI_EXP_LNKCAP_DLLA0x100000 /* Data Link Layer Active Reporting */
#define PCI_EXP_LNKCAP_LBNC0x200000 /* Link Bandwidth Notification Capability */
#define PCI_EXP_LNKCAP_PORT0xff000000 /* Port Number */
#define PCI_EXP_LNKCTL0x10/* Link Control */
#define PCI_EXP_LNKCTL_ASPM0x0003/* ASPM Control */
#define PCI_EXP_LNKCTL_RCB0x0008/* Read Completion Boundary */
#define PCI_EXP_LNKCTL_DISABLE0x0010/* Link Disable */
#define PCI_EXP_LNKCTL_RETRAIN0x0020/* Retrain Link */
#define PCI_EXP_LNKCTL_CLOCK0x0040/* Common Clock Configuration */
#define PCI_EXP_LNKCTL_XSYNCH0x0080/* Extended Synch */
#define PCI_EXP_LNKCTL_CLOCKPM0x0100/* Clock Power Management */
#define PCI_EXP_LNKCTL_HWAUTWD0x0200/* Hardware Autonomous Width Disable */
#define PCI_EXP_LNKCTL_BWMIE0x0400/* Bandwidth Mgmt Interrupt Enable */
#define PCI_EXP_LNKCTL_AUTBWIE0x0800/* Autonomous Bandwidth Mgmt Interrupt Enable */
#define PCI_EXP_LNKSTA0x12/* Link Status */
#define PCI_EXP_LNKSTA_SPEED0x000f/* Negotiated Link Speed */
#define PCI_EXP_LNKSTA_WIDTH0x03f0/* Negotiated Link Width */
#define PCI_EXP_LNKSTA_TR_ERR0x0400/* Training Error (obsolete) */
#define PCI_EXP_LNKSTA_TRAIN0x0800/* Link Training */
#define PCI_EXP_LNKSTA_SL_CLK0x1000/* Slot Clock Configuration */
#define PCI_EXP_LNKSTA_DL_ACT0x2000/* Data Link Layer in DL_Active State */
#define PCI_EXP_LNKSTA_BWMGMT0x4000/* Bandwidth Mgmt Status */
#define PCI_EXP_LNKSTA_AUTBW0x8000/* Autonomous Bandwidth Mgmt Status */
#define PCI_EXP_SLTCAP0x14/* Slot Capabilities */
#define PCI_EXP_SLTCAP_ATNB0x0001/* Attention Button Present */
#define PCI_EXP_SLTCAP_PWRC0x0002/* Power Controller Present */
#define PCI_EXP_SLTCAP_MRL0x0004/* MRL Sensor Present */
#define PCI_EXP_SLTCAP_ATNI0x0008/* Attention Indicator Present */
#define PCI_EXP_SLTCAP_PWRI0x0010/* Power Indicator Present */
#define PCI_EXP_SLTCAP_HPS0x0020/* Hot-Plug Surprise */
#define PCI_EXP_SLTCAP_HPC0x0040/* Hot-Plug Capable */
#define PCI_EXP_SLTCAP_PWR_VAL0x00007f80 /* Slot Power Limit Value */
#define PCI_EXP_SLTCAP_PWR_SCL0x00018000 /* Slot Power Limit Scale */
#define PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
#define PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
#define PCI_EXP_SLTCAP_PSN0xfff80000 /* Physical Slot Number */
#define PCI_EXP_SLTCTL0x18/* Slot Control */
#define PCI_EXP_SLTCTL_ATNB0x0001/* Attention Button Pressed Enable */
#define PCI_EXP_SLTCTL_PWRF0x0002/* Power Fault Detected Enable */
#define PCI_EXP_SLTCTL_MRLS0x0004/* MRL Sensor Changed Enable */
#define PCI_EXP_SLTCTL_PRSD0x0008/* Presence Detect Changed Enable */
#define PCI_EXP_SLTCTL_CMDC0x0010/* Command Completed Interrupt Enable */
#define PCI_EXP_SLTCTL_HPIE0x0020/* Hot-Plug Interrupt Enable */
#define PCI_EXP_SLTCTL_ATNI0x00c0/* Attention Indicator Control */
#define PCI_EXP_SLTCTL_PWRI0x0300/* Power Indicator Control */
#define PCI_EXP_SLTCTL_PWRC0x0400/* Power Controller Control */
#define PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
#define PCI_EXP_SLTCTL_LLCHG0x1000/* Data Link Layer State Changed Enable */
#define PCI_EXP_SLTSTA0x1a/* Slot Status */
#define PCI_EXP_SLTSTA_ATNB0x0001/* Attention Button Pressed */
#define PCI_EXP_SLTSTA_PWRF0x0002/* Power Fault Detected */
#define PCI_EXP_SLTSTA_MRLS0x0004/* MRL Sensor Changed */
#define PCI_EXP_SLTSTA_PRSD0x0008/* Presence Detect Changed */
#define PCI_EXP_SLTSTA_CMDC0x0010/* Command Completed */
#define PCI_EXP_SLTSTA_MRL_ST0x0020/* MRL Sensor State */
#define PCI_EXP_SLTSTA_PRES0x0040/* Presence Detect State */
#define PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
#define PCI_EXP_SLTSTA_LLCHG0x0100/* Data Link Layer State Changed */
#define PCI_EXP_RTCTL0x1c/* Root Control */
#define PCI_EXP_RTCTL_SECEE0x0001/* System Error on Correctable Error */
#define PCI_EXP_RTCTL_SENFEE0x0002/* System Error on Non-Fatal Error */
#define PCI_EXP_RTCTL_SEFEE0x0004/* System Error on Fatal Error */
#define PCI_EXP_RTCTL_PMEIE0x0008/* PME Interrupt Enable */
#define PCI_EXP_RTCTL_CRSVIS0x0010/* Configuration Request Retry Status Visible to SW */
#define PCI_EXP_RTCAP0x1e/* Root Capabilities */
#define PCI_EXP_RTCAP_CRSVIS0x0010/* Configuration Request Retry Status Visible to SW */
#define PCI_EXP_RTSTA0x20/* Root Status */
#define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
#define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
#define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
#define PCI_EXP_DEVCAP20x24/* Device capabilities 2 */
#define PCI_EXP_DEVCTL20x28/* Device Control */
#define PCI_EXP_DEV2_TIMEOUT_RANGE(x)((x) & 0xf) /* Completion Timeout Ranges Supported */
#define PCI_EXP_DEV2_TIMEOUT_VALUE(x)((x) & 0xf) /* Completion Timeout Value */
#define PCI_EXP_DEV2_TIMEOUT_DIS0x0010/* Completion Timeout Disable Supported */
#define PCI_EXP_DEV2_ARI0x0020/* ARI Forwarding */
#define PCI_EXP_DEVSTA20x2a/* Device Status */
#define PCI_EXP_LNKCAP20x2c/* Link Capabilities */
#define PCI_EXP_LNKCTL20x30/* Link Control */
#define PCI_EXP_LNKCTL2_SPEED(x)((x) & 0xf) /* Target Link Speed */
#define PCI_EXP_LNKCTL2_CMPLNC0x0010/* Enter Compliance */
#define PCI_EXP_LNKCTL2_SPEED_DIS0x0020/* Hardware Autonomous Speed Disable */
#define PCI_EXP_LNKCTL2_DEEMPHASIS(x)(((x) >> 6) & 1) /* Selectable De-emphasis */
#define PCI_EXP_LNKCTL2_MARGIN(x)(((x) >> 7) & 7) /* Transmit Margin */
#define PCI_EXP_LNKCTL2_MOD_CMPLNC0x0400/* Enter Modified Compliance */
#define PCI_EXP_LNKCTL2_CMPLNC_SOS0x0800/* Compliance SOS */
#define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 1) /* Compliance De-emphasis */
#define PCI_EXP_LNKSTA20x32/* Link Status */
#define PCI_EXP_LINKSTA2_DEEMPHASIS(x)((x) & 1)/* Current De-emphasis Level */
#define PCI_EXP_SLTCAP20x34/* Slot Capabilities */
#define PCI_EXP_SLTCTL20x38/* Slot Control */
#define PCI_EXP_SLTSTA20x3a/* Slot Status */
/* MSI-X */
#define PCI_MSIX_ENABLE0x8000
#define PCI_MSIX_MASK0x4000
#define PCI_MSIX_TABSIZE0x03ff
#define PCI_MSIX_TABLE4
#define PCI_MSIX_PBA8
#define PCI_MSIX_BIR0x7
/* Subsystem vendor/device ID for PCI bridges */
#define PCI_SSVID_VENDOR4
#define PCI_SSVID_DEVICE6
/* Advanced Error Reporting */
#define PCI_ERR_UNCOR_STATUS4/* Uncorrectable Error Status */
#define PCI_ERR_UNC_TRAIN0x00000001/* Undefined in PCIe rev1.1 & 2.0 spec */
#define PCI_ERR_UNC_DLP0x00000010/* Data Link Protocol */
#define PCI_ERR_UNC_SDES0x00000020/* Surprise Down Error */
#define PCI_ERR_UNC_POISON_TLP0x00001000/* Poisoned TLP */
#define PCI_ERR_UNC_FCP0x00002000/* Flow Control Protocol */
#define PCI_ERR_UNC_COMP_TIME0x00004000/* Completion Timeout */
#define PCI_ERR_UNC_COMP_ABORT0x00008000/* Completer Abort */
#define PCI_ERR_UNC_UNX_COMP0x00010000/* Unexpected Completion */
#define PCI_ERR_UNC_RX_OVER0x00020000/* Receiver Overflow */
#define PCI_ERR_UNC_MALF_TLP0x00040000/* Malformed TLP */
#define PCI_ERR_UNC_ECRC0x00080000/* ECRC Error Status */
#define PCI_ERR_UNC_UNSUP0x00100000/* Unsupported Request */
#define PCI_ERR_UNC_ACS_VIOL0x00200000/* ACS Violation */
#define PCI_ERR_UNCOR_MASK8/* Uncorrectable Error Mask */
/* Same bits as above */
#define PCI_ERR_UNCOR_SEVER12/* Uncorrectable Error Severity */
/* Same bits as above */
#define PCI_ERR_COR_STATUS16/* Correctable Error Status */
#define PCI_ERR_COR_RCVR0x00000001/* Receiver Error Status */
#define PCI_ERR_COR_BAD_TLP0x00000040/* Bad TLP Status */
#define PCI_ERR_COR_BAD_DLLP0x00000080/* Bad DLLP Status */
#define PCI_ERR_COR_REP_ROLL0x00000100/* REPLAY_NUM Rollover */
#define PCI_ERR_COR_REP_TIMER0x00001000/* Replay Timer Timeout */
#define PCI_ERR_COR_REP_ANFE0x00002000/* Advisory Non-Fatal Error */
#define PCI_ERR_COR_MASK20/* Correctable Error Mask */
/* Same bits as above */
#define PCI_ERR_CAP24/* Advanced Error Capabilities */
#define PCI_ERR_CAP_FEP(x)((x) & 31)/* First Error Pointer */
#define PCI_ERR_CAP_ECRC_GENC0x00000020/* ECRC Generation Capable */
#define PCI_ERR_CAP_ECRC_GENE0x00000040/* ECRC Generation Enable */
#define PCI_ERR_CAP_ECRC_CHKC0x00000080/* ECRC Check Capable */
#define PCI_ERR_CAP_ECRC_CHKE0x00000100/* ECRC Check Enable */
#define PCI_ERR_HEADER_LOG28/* Header Log Register (16 bytes) */
#define PCI_ERR_ROOT_COMMAND44/* Root Error Command */
#define PCI_ERR_ROOT_STATUS48
#define PCI_ERR_ROOT_COR_SRC52
#define PCI_ERR_ROOT_SRC54
/* Virtual Channel */
#define PCI_VC_PORT_REG14
#define PCI_VC_PORT_REG28
#define PCI_VC_PORT_CTRL12
#define PCI_VC_PORT_STATUS14
#define PCI_VC_RES_CAP16
#define PCI_VC_RES_CTRL20
#define PCI_VC_RES_STATUS26
/* Power Budgeting */
#define PCI_PWR_DSR4/* Data Select Register */
#define PCI_PWR_DATA8/* Data Register */
#define PCI_PWR_DATA_BASE(x)((x) & 0xff) /* Base Power */
#define PCI_PWR_DATA_SCALE(x)(((x) >> 8) & 3) /* Data Scale */
#define PCI_PWR_DATA_PM_SUB(x)(((x) >> 10) & 7) /* PM Sub State */
#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
#define PCI_PWR_DATA_TYPE(x)(((x) >> 15) & 7) /* Type */
#define PCI_PWR_DATA_RAIL(x)(((x) >> 18) & 7) /* Power Rail */
#define PCI_PWR_CAP12/* Capability */
#define PCI_PWR_CAP_BUDGET(x)((x) & 1)/* Included in system budget */
/* Access Control Services */
#define PCI_ACS_CAP0x04/* ACS Capability Register */
#define PCI_ACS_CAP_VALID0x0001/* ACS Source Validation */
#define PCI_ACS_CAP_BLOCK0x0002/* ACS Translation Blocking */
#define PCI_ACS_CAP_REQ_RED0x0004/* ACS P2P Request Redirect */
#define PCI_ACS_CAP_CMPLT_RED0x0008/* ACS P2P Completion Redirect */
#define PCI_ACS_CAP_FORWARD0x0010/* ACS Upstream Forwarding */
#define PCI_ACS_CAP_EGRESS0x0020/* ACS P2P Egress Control */
#define PCI_ACS_CAP_TRANS0x0040/* ACS Direct Translated P2P */
#define PCI_ACS_CAP_VECTOR(x)(((x) >> 8) & 0xff) /* Egress Control Vector Size */
#define PCI_ACS_CTRL0x06/* ACS Control Register */
#define PCI_ACS_CTRL_VALID0x0001/* ACS Source Validation Enable */
#define PCI_ACS_CTRL_BLOCK0x0002/* ACS Translation Blocking Enable */
#define PCI_ACS_CTRL_REQ_RED0x0004/* ACS P2P Request Redirect Enable */
#define PCI_ACS_CTRL_CMPLT_RED0x0008/* ACS P2P Completion Redirect Enable */
#define PCI_ACS_CTRL_FORWARD0x0010/* ACS Upstream Forwarding Enable */
#define PCI_ACS_CTRL_EGRESS0x0020/* ACS P2P Egress Control Enable */
#define PCI_ACS_CTRL_TRANS0x0040/* ACS Direct Translated P2P Enable */
#define PCI_ACS_EGRESS_CTRL0x08/* Egress Control Vector */
/* Alternative Routing-ID Interpretation */
#define PCI_ARI_CAP0x04/* ARI Capability Register */
#define PCI_ARI_CAP_MFVC0x0001/* MFVC Function Groups Capability */
#define PCI_ARI_CAP_ACS0x0002/* ACS Function Groups Capability */
#define PCI_ARI_CAP_NFN(x)(((x) >> 8) & 0xff) /* Next Function Number */
#define PCI_ARI_CTRL0x06/* ARI Control Register */
#define PCI_ARI_CTRL_MFVC0x0001/* MFVC Function Groups Enable */
#define PCI_ARI_CTRL_ACS0x0002/* ACS Function Groups Enable */
#define PCI_ARI_CTRL_FG(x)(((x) >> 4) & 7) /* Function Group */
/* Address Translation Service */
#define PCI_ATS_CAP0x04/* ATS Capability Register */
#define PCI_ATS_CAP_IQD(x)((x) & 0x1f) /* Invalidate Queue Depth */
#define PCI_ATS_CTRL0x06/* ATS Control Register */
#define PCI_ATS_CTRL_STU(x)((x) & 0x1f) /* Smallest Translation Unit */
#define PCI_ATS_CTRL_ENABLE0x8000/* ATS Enable */
/* Single Root I/O Virtualization */
#define PCI_IOV_CAP0x04/* SR-IOV Capability Register */
#define PCI_IOV_CAP_VFM0x00000001 /* VF Migration Capable */
#define PCI_IOV_CAP_IMN(x)((x) >> 21) /* VF Migration Interrupt Message Number */
#define PCI_IOV_CTRL0x08/* SR-IOV Control Register */
#define PCI_IOV_CTRL_VFE0x0001/* VF Enable */
#define PCI_IOV_CTRL_VFME0x0002/* VF Migration Enable */
#define PCI_IOV_CTRL_VFMIE0x0004/* VF Migration Interrupt Enable */
#define PCI_IOV_CTRL_MSE0x0008/* VF MSE */
#define PCI_IOV_CTRL_ARI0x0010/* ARI Capable Hierarchy */
#define PCI_IOV_STATUS0x0a/* SR-IOV Status Register */
#define PCI_IOV_STATUS_MS0x0001/* VF Migration Status */
#define PCI_IOV_INITIALVF0x0c/* Number of VFs that are initially associated */
#define PCI_IOV_TOTALVF0x0e/* Maximum number of VFs that could be associated */
#define PCI_IOV_NUMVF0x10/* Number of VFs that are available */
#define PCI_IOV_FDL0x12/* Function Dependency Link */
#define PCI_IOV_OFFSET0x14/* First VF Offset */
#define PCI_IOV_STRIDE0x16/* Routing ID offset from one VF to the next one */
#define PCI_IOV_DID0x1a/* VF Device ID */
#define PCI_IOV_SUPPS0x1c/* Supported Page Sizes */
#define PCI_IOV_SYSPS0x20/* System Page Size */
#define PCI_IOV_BAR_BASE0x24/* VF BAR0, VF BAR1, ... VF BAR5 */
#define PCI_IOV_NUM_BAR6/* Number of VF BARs */
#define PCI_IOV_MSAO0x3c/* VF Migration State Array Offset */
#define PCI_IOV_MSA_BIR(x)((x) & 7) /* VF Migration State BIR */
#define PCI_IOV_MSA_OFFSET(x)((x) & 0xfffffff8) /* VF Migration State Offset */
/*
* The PCI interface treats multi-function devices as independent
* devices. The slot/function address of each device is encoded
* in a single byte as follows:
*
*7:3 = slot
*2:0 = function
*/
#define PCI_DEVFN(slot,func)((((slot) & 0x1f) << 3) | ((func) & 0x07))
#define PCI_SLOT(devfn)(((devfn) >> 3) & 0x1f)
#define PCI_FUNC(devfn)((devfn) & 0x07)
/* Device classes and subclasses */
#define PCI_CLASS_NOT_DEFINED0x0000
#define PCI_CLASS_NOT_DEFINED_VGA0x0001
#define PCI_BASE_CLASS_STORAGE0x01
#define PCI_CLASS_STORAGE_SCSI0x0100
#define PCI_CLASS_STORAGE_IDE0x0101
#define PCI_CLASS_STORAGE_FLOPPY0x0102
#define PCI_CLASS_STORAGE_IPI0x0103
#define PCI_CLASS_STORAGE_RAID0x0104
#define PCI_CLASS_STORAGE_ATA0x0105
#define PCI_CLASS_STORAGE_SATA0x0106
#define PCI_CLASS_STORAGE_SAS0x0107
#define PCI_CLASS_STORAGE_OTHER0x0180
#define PCI_BASE_CLASS_NETWORK0x02
#define PCI_CLASS_NETWORK_ETHERNET0x0200
#define PCI_CLASS_NETWORK_TOKEN_RING0x0201
#define PCI_CLASS_NETWORK_FDDI0x0202
#define PCI_CLASS_NETWORK_ATM0x0203
#define PCI_CLASS_NETWORK_ISDN0x0204
#define PCI_CLASS_NETWORK_OTHER0x0280
#define PCI_BASE_CLASS_DISPLAY0x03
#define PCI_CLASS_DISPLAY_VGA0x0300
#define PCI_CLASS_DISPLAY_XGA0x0301
#define PCI_CLASS_DISPLAY_3D0x0302
#define PCI_CLASS_DISPLAY_OTHER0x0380
#define PCI_BASE_CLASS_MULTIMEDIA0x04
#define PCI_CLASS_MULTIMEDIA_VIDEO0x0400
#define PCI_CLASS_MULTIMEDIA_AUDIO0x0401
#define PCI_CLASS_MULTIMEDIA_PHONE0x0402
#define PCI_CLASS_MULTIMEDIA_AUDIO_DEV0x0403
#define PCI_CLASS_MULTIMEDIA_OTHER0x0480
#define PCI_BASE_CLASS_MEMORY0x05
#define PCI_CLASS_MEMORY_RAM0x0500
#define PCI_CLASS_MEMORY_FLASH0x0501
#define PCI_CLASS_MEMORY_OTHER0x0580
#define PCI_BASE_CLASS_BRIDGE0x06
#define PCI_CLASS_BRIDGE_HOST0x0600
#define PCI_CLASS_BRIDGE_ISA0x0601
#define PCI_CLASS_BRIDGE_EISA0x0602
#define PCI_CLASS_BRIDGE_MC0x0603
#define PCI_CLASS_BRIDGE_PCI0x0604
#define PCI_CLASS_BRIDGE_PCMCIA0x0605
#define PCI_CLASS_BRIDGE_NUBUS0x0606
#define PCI_CLASS_BRIDGE_CARDBUS0x0607
#define PCI_CLASS_BRIDGE_RACEWAY0x0608
#define PCI_CLASS_BRIDGE_PCI_SEMI0x0609
#define PCI_CLASS_BRIDGE_IB_TO_PCI0x060a
#define PCI_CLASS_BRIDGE_OTHER0x0680
#define PCI_BASE_CLASS_COMMUNICATION0x07
#define PCI_CLASS_COMMUNICATION_SERIAL0x0700
#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
#define PCI_CLASS_COMMUNICATION_MSERIAL0x0702
#define PCI_CLASS_COMMUNICATION_MODEM0x0703
#define PCI_CLASS_COMMUNICATION_OTHER0x0780
#define PCI_BASE_CLASS_SYSTEM0x08
#define PCI_CLASS_SYSTEM_PIC0x0800
#define PCI_CLASS_SYSTEM_DMA0x0801
#define PCI_CLASS_SYSTEM_TIMER0x0802
#define PCI_CLASS_SYSTEM_RTC0x0803
#define PCI_CLASS_SYSTEM_PCI_HOTPLUG0x0804
#define PCI_CLASS_SYSTEM_OTHER0x0880
#define PCI_BASE_CLASS_INPUT0x09
#define PCI_CLASS_INPUT_KEYBOARD0x0900
#define PCI_CLASS_INPUT_PEN0x0901
#define PCI_CLASS_INPUT_MOUSE0x0902
#define PCI_CLASS_INPUT_SCANNER0x0903
#define PCI_CLASS_INPUT_GAMEPORT0x0904
#define PCI_CLASS_INPUT_OTHER0x0980
#define PCI_BASE_CLASS_DOCKING0x0a
#define PCI_CLASS_DOCKING_GENERIC0x0a00
#define PCI_CLASS_DOCKING_OTHER0x0a80
#define PCI_BASE_CLASS_PROCESSOR0x0b
#define PCI_CLASS_PROCESSOR_3860x0b00
#define PCI_CLASS_PROCESSOR_4860x0b01
#define PCI_CLASS_PROCESSOR_PENTIUM0x0b02
#define PCI_CLASS_PROCESSOR_ALPHA0x0b10
#define PCI_CLASS_PROCESSOR_POWERPC0x0b20
#define PCI_CLASS_PROCESSOR_MIPS0x0b30
#define PCI_CLASS_PROCESSOR_CO0x0b40
#define PCI_BASE_CLASS_SERIAL0x0c
#define PCI_CLASS_SERIAL_FIREWIRE0x0c00
#define PCI_CLASS_SERIAL_ACCESS0x0c01
#define PCI_CLASS_SERIAL_SSA0x0c02
#define PCI_CLASS_SERIAL_USB0x0c03
#define PCI_CLASS_SERIAL_FIBER0x0c04
#define PCI_CLASS_SERIAL_SMBUS0x0c05
#define PCI_CLASS_SERIAL_INFINIBAND0x0c06
#define PCI_BASE_CLASS_WIRELESS0x0d
#define PCI_CLASS_WIRELESS_IRDA0x0d00
#define PCI_CLASS_WIRELESS_CONSUMER_IR0x0d01
#define PCI_CLASS_WIRELESS_RF0x0d10
#define PCI_CLASS_WIRELESS_OTHER0x0d80
#define PCI_BASE_CLASS_INTELLIGENT0x0e
#define PCI_CLASS_INTELLIGENT_I2O0x0e00
#define PCI_BASE_CLASS_SATELLITE0x0f
#define PCI_CLASS_SATELLITE_TV0x0f00
#define PCI_CLASS_SATELLITE_AUDIO0x0f01
#define PCI_CLASS_SATELLITE_VOICE0x0f03
#define PCI_CLASS_SATELLITE_DATA0x0f04
#define PCI_BASE_CLASS_CRYPT0x10
#define PCI_CLASS_CRYPT_NETWORK0x1000
#define PCI_CLASS_CRYPT_ENTERTAINMENT0x1010
#define PCI_CLASS_CRYPT_OTHER0x1080
#define PCI_BASE_CLASS_SIGNAL0x11
#define PCI_CLASS_SIGNAL_DPIO0x1100
#define PCI_CLASS_SIGNAL_PERF_CTR0x1101
#define PCI_CLASS_SIGNAL_SYNCHRONIZER0x1110
#define PCI_CLASS_SIGNAL_OTHER0x1180
#define PCI_CLASS_OTHERS0xff
/* Several ID's we need in the library */
#define PCI_VENDOR_ID_APPLE0x106b
#define PCI_VENDOR_ID_AMD0x1002
#define PCI_VENDOR_ID_ATI0x1002
#define PCI_VENDOR_ID_INTEL0x8086
#define PCI_VENDOR_ID_NVIDIA0x10de
#define PCI_VENDOR_ID_REALTEK0x10ec
#define PCI_VENDOR_ID_TEXAS_INSTRUMENTS0x104c
#define PCI_VENDOR_ID_VIA0x1106
#endif /* !__PCI_OLD_H */
branches/azimutz/Cleancut/i386/modules/ATiGraphicsEnabler/ati.h
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/*
* ATI injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas
*
* ATI injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ATI driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with ATI injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
#ifndef __LIBSAIO_ATI_H
#define __LIBSAIO_ATI_H
bool setup_ati_devprop(pci_dt_t *ati_dev);
struct ati_chipsets_t {
unsigned device;
char *name;
};
struct ati_data_key {
uint32_t size;
char *name;
uint8_t data[];
};
#define REG8(reg) ((volatile uint8_t *)regs)[(reg)]
#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1]
#define REG32R(reg) ((volatile uint32_t *)regs)[(reg) >> 2]
#define REG32W(reg, val) ((volatile uint32_t *)regs)[(reg) >> 2] = (val)
#endif /* !__LIBSAIO_ATI_H */
branches/azimutz/Cleancut/i386/modules/ATiGraphicsEnabler/ATiGraphicsEnabler.c
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/*
* ATIGraphicsEnabler Module ---
* Enables many ati "legacy ??" cards to be used out of the box in OS X.
* This was converted from ( < r784) boot2 code to a boot2 module.
*
*/
#include "saio_internal.h"
#include "bootstruct.h"
#include "../modules/ATiGraphicsEnabler/pci_old.h"
#include "ati.h"
#include "modules.h"
#define kGraphicsEnablerKey"GraphicsEnabler" // change?
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4);
void ATiGraphicsEnabler_start()
{
register_hook_callback("PCIDevice", &GraphicsEnabler_hook);
}
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4)
{
pci_dt_t* current = arg1;
if (current->class_id != PCI_CLASS_DISPLAY_VGA) return;
char *devicepath = get_pci_dev_path(current);
bool do_gfx_devprop = true;
getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->bootConfig);
//Azi: check "fail" code...
if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_ATI))
{
verbose("ATI VGA Controller [%04x:%04x] :: %s \n",
current->vendor_id, current->device_id, devicepath);
setup_ati_devprop(current);
}
else
verbose("Not a ATI VGA Controller.\n"); // ---
}
branches/azimutz/Cleancut/i386/modules/ATiGraphicsEnabler/Readme.txt
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Module:ATiGraphicsEnabler
Description: the GraphicsEnabler ATI code ( < r784) ported to a module.
Support for "legacy" cards...
Based on Meklort's work.
Dependencies: none
Keys: GraphicsEnabler(enabled by default)
UseAtiROM(disabled by default)
TODO:
- naming: ATi or AMD ??
- eliminate the need for pci_old.h
- merge with
branches/azimutz/Cleancut/i386/modules/ATiGraphicsEnabler/Makefile
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MODULE_NAME = ATiGraphicsEnabler
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = _$(MODULE_NAME)_start
MODULE_DEPENDENCIES =
DIR = Enabler/ATiGraphicsEnabler
MODULE_OBJS = ati.o ATiGraphicsEnabler.o
OPTIM = -Os -Oz
DEBUG = -DNOTHING
#DEBUG = -DDEBUG_HELLO_WORLD=1
CFLAGS= $(RC_CFLAGS) $(OPTIM) $(MORECPP) -arch i386 -g -Wmost \
-D__ARCHITECTURE__=\"i386\" -DSAIO_INTERNAL_USER \
-DRCZ_COMPRESSED_FILE_SUPPORT $(DEBUG) \
-fno-builtin $(OMIT_FRAME_POINTER_CFLAG) \
-mpreferred-stack-boundary=2 -fno-align-functions -fno-stack-protector \
-march=pentium4 -msse2 -mfpmath=sse -msoft-float -fno-common
DEFINES=
CONFIG = hd
INC = -I. -I.. -I$(SYMROOT) -I$(UTILDIR) -I$(LIBSADIR) -I$(LIBSAIODIR) -I$(BOOT2DIR)
LIBS=
VPATH = $(OBJROOT):$(SYMROOT)
SFILES =
CFILES =
HFILES =
EXPORTED_HFILES =
INSTALLED_HFILES =
OTHERFILES = Makefile
ALLSRC = $(SFILES) $(CFILES) \
$(HFILES) $(OTHERFILES)
DIRS_NEEDED = $(OBJROOT) $(SYMROOT)
all embedtheme: dylib
include ../MakeInc.dir
branches/azimutz/Cleancut/i386/modules/ATiGraphicsEnabler/ati.c
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/*
* ATI injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas
*
* ATI injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ATI driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with ATI injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
#include "bootstruct.h"
#include "../modules/ATiGraphicsEnabler/pci_old.h"
#include "platform.h"
#include "device_inject.h"
#include "ati.h"
#ifndef DEBUG_ATI
#define DEBUG_ATI 0
#endif
#if DEBUG_ATI
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
#define kUseAtiROMKey"UseAtiROM"
#define MAX_NUM_DCB_ENTRIES 16
#define TYPE_GROUPED 0xff
extern uint32_t devices_number;
const char *ati_compatible_0[]= { "@0,compatible", "ATY,%s" };
const char *ati_compatible_1[]= { "@1,compatible", "ATY,%s" };
const char *ati_device_type_0[]= { "@0,device_type", "display" };
const char *ati_device_type_1[]= { "@1,device_type", "display" };
const char *ati_device_type[]= { "device_type", "ATY,%sParent" };
const char *ati_name_0[]= { "@0,name", "ATY,%s" };
const char *ati_name_1[]= { "@1,name", "ATY,%s" };
const char *ati_name[]= { "name", "ATY,%sParent" };
const char *ati_efidisplay_0[]= { "@0,ATY,EFIDisplay", "TMDSB" };
struct ati_data_key ati_connector_type_0= { 0x04, "@0,connector-type", {0x00, 0x04, 0x00, 0x00} };
struct ati_data_key ati_connector_type_1= { 0x04, "@1,connector-type", {0x04, 0x00, 0x00, 0x00} };
struct ati_data_key ati_display_con_fl_type_0= { 0x04, "@0,display-connect-flags", {0x00, 0x00, 0x04, 0x00} };
const char *ati_display_type_0[]= { "@0,display-type", "LCD" };
const char *ati_display_type_1[]= { "@1,display-type", "NONE" };
struct ati_data_key ati_aux_power_conn= { 0x04, "AAPL,aux-power-connected", {0x01, 0x00, 0x00, 0x00} };
struct ati_data_key ati_backlight_ctrl= { 0x04, "AAPL,backlight-control", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl01_coher= { 0x04, "AAPL01,Coherency", {0x01, 0x00, 0x00, 0x00} };
const char *ati_card_no[]= { "ATY,Card#", "109-B77101-00" };
const char *ati_copyright[]= { "ATY,Copyright", "Copyright AMD Inc. All Rights Reserved. 2005-2009" };
const char *ati_efi_compile_d[]= { "ATY,EFICompileDate", "Jan 26 2009" };
struct ati_data_key ati_efi_disp_conf= { 0x08, "ATY,EFIDispConfig", {0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} };
struct ati_data_key ati_efi_drv_type= { 0x01, "ATY,EFIDriverType", {0x02} };
struct ati_data_key ati_efi_enbl_mode= { 0x01, "ATY,EFIEnabledMode", {0x01} };
struct ati_data_key ati_efi_init_stat= { 0x04, "ATY,EFIHWInitStatus", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_efi_orientation= { 0x02, "ATY,EFIOrientation", {0x02, 0x00} };
const char *ati_efi_version[]= { "ATY,EFIVersion", "01.00.318" };
const char *ati_efi_versionB[]= { "ATY,EFIVersionB", "113-SBSJ1G04-00R-02" };
const char *ati_efi_versionE[]= { "ATY,EFIVersionE", "113-B7710A-318" };
struct ati_data_key ati_mclk= { 0x04, "ATY,MCLK", {0x70, 0x2e, 0x11, 0x00} };
struct ati_data_key ati_mem_rev_id= { 0x02, "ATY,MemRevisionID", {0x03, 0x00} };
struct ati_data_key ati_mem_vend_id= { 0x02, "ATY,MemVendorID", {0x02, 0x00} };
const char *ati_mrt[]= { "ATY,MRT", " " };
const char *ati_romno[]= { "ATY,Rom#", "113-B7710C-176" };
struct ati_data_key ati_sclk= { 0x04, "ATY,SCLK", {0x28, 0xdb, 0x0b, 0x00} };
struct ati_data_key ati_vendor_id= { 0x02, "ATY,VendorID", {0x02, 0x10} };
struct ati_data_key ati_platform_info= { 0x80, "ATY,PlatformInfo", {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_mvad= { 0x40, "MVAD", {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, 0x92, 0x20, 0x00, 0x03} };
struct ati_data_key ati_saved_config= { 0x100, "saved-config", {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, 0x92, 0x20, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xee, 0x02, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
///non 48xx keys
const char *ati_efidisplay_0_n4[]= { "@0,ATY,EFIDisplay", "TMDSA" };
struct ati_data_key ati_connector_type_0_n4= { 0x04, "@0,connector-type", {0x04, 0x00, 0x00, 0x00} };
struct ati_data_key ati_connector_type_1_n4= { 0x04, "@1,connector-type", {0x00, 0x02, 0x00, 0x00} };
struct ati_data_key ati_aapl_emc_disp_list_n4= { 0x40, "AAPL,EMC-Display-List", {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x1b, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x1c, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x21, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_fb_offset_n4= { 0x08, "ATY,FrameBufferOffset", {0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00} };
struct ati_data_key ati_hwgpio_n4= { 0x04, "ATY,HWGPIO", {0x23, 0xa8, 0x48, 0x00} };
struct ati_data_key ati_iospace_offset_n4= { 0x08, "ATY,IOSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00} };
struct ati_data_key ati_mclk_n4= { 0x04, "ATY,MCLK", {0x00, 0x35, 0x0c, 0x00} };
struct ati_data_key ati_sclk_n4= { 0x04, "ATY,SCLK", {0x60, 0xae, 0x0a, 0x00} };
struct ati_data_key ati_refclk_n4= { 0x04, "ATY,RefCLK", {0x8c, 0x0a, 0x00, 0x00} };
struct ati_data_key ati_regspace_offset_n4= { 0x08, "ATY,RegisterSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x90, 0xa2, 0x00, 0x00} };
struct ati_data_key ati_vram_memsize_0= { 0x08, "@0,VRAM,memsize", {0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_vram_memsize_1= { 0x08, "@1,VRAM,memsize", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl_blackscr_prefs_0_n4= { 0x04, "AAPL00,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl_blackscr_prefs_1_n4= { 0x04, "AAPL01,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_swgpio_info_n4= { 0x04, "ATY,SWGPIO Info", {0x00, 0x48, 0xa8, 0x23} };
struct ati_data_key ati_efi_orientation_n4= { 0x01, "ATY,EFIOrientation", {0x08} };
struct ati_data_key ati_mvad_n4= { 0x100, "MVAD", {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_saved_config_n4= { 0x100, "saved-config", {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct pcir_s {
uint32_t signature;
uint16_t vid;
uint16_t devid;
};
// Known cards as of 2008/08/26
static struct ati_chipsets_t ATIKnownChipsets[] = {
{ 0x00000000, "Unknown" } ,
//{ 0x10027181, "ATI Radeon 1300 Series"} ,
{ 0x10029589, "ATI Radeon 2600 Series"} ,
{ 0x10029588, "ATI Radeon 2600 Series"} ,
{ 0x100294C3, "ATI Radeon 2400 Series"} ,
{ 0x100294C4, "ATI Radeon 2400 Series"} ,
{ 0x100294C6, "ATI Radeon 2400 Series"} ,
{ 0x10029400, "ATI Radeon 2900 Series"} ,
{ 0x10029405, "ATI Radeon 2900GT Series"} ,
{ 0x10029581, "ATI Radeon 2600 Series"} ,
{ 0x10029583, "ATI Radeon 2600 Series"} ,
{ 0x10029586, "ATI Radeon 2600 Series"} ,
{ 0x10029587, "ATI Radeon 2600 Series"} ,
{ 0x100294C9, "ATI Radeon 2400 Series"} ,
{ 0x10029501, "ATI Radeon 3800 Series"} ,
{ 0x10029505, "ATI Radeon 3800 Series"} ,
{ 0x10029515, "ATI Radeon 3800 Series"} ,
{ 0x10029507, "ATI Radeon 3800 Series"} ,
{ 0x10029500, "ATI Radeon 3800 Series"} ,
{ 0x1002950F, "ATI Radeon 3800X2 Series"} ,
{ 0x100295C5, "ATI Radeon 3400 Series"} ,
{ 0x100295C7, "ATI Radeon 3400 Series"} ,
{ 0x100295C0, "ATI Radeon 3400 Series"} ,
{ 0x10029596, "ATI Radeon 3600 Series"} ,
{ 0x10029590, "ATI Radeon 3600 Series"} ,
{ 0x10029599, "ATI Radeon 3600 Series"} ,
{ 0x10029597, "ATI Radeon 3600 Series"} ,
{ 0x10029598, "ATI Radeon 3600 Series"} ,
{ 0x10029442, "ATI Radeon 4850 Series"} ,
{ 0x10029440, "ATI Radeon 4870 Series"} ,
{ 0x1002944C, "ATI Radeon 4830 Series"} ,
{ 0x10029460, "ATI Radeon 4890 Series"} ,
{ 0x10029462, "ATI Radeon 4890 Series"} ,
{ 0x10029441, "ATI Radeon 4870X2 Series"} ,
{ 0x10029443, "ATI Radeon 4850X2 Series"} ,
{ 0x10029444, "ATI Radeon 4800 Series"} ,
{ 0x10029446, "ATI Radeon 4800 Series"} ,
{ 0x1002944E, "ATI Radeon 4730 Series"} ,
{ 0x10029450, "ATI Radeon 4800 Series"} ,
{ 0x10029452, "ATI Radeon 4800 Series"} ,
{ 0x10029456, "ATI Radeon 4800 Series"} ,
{ 0x1002944A, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002945A, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002945B, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002944B, "ATI Radeon 4800 Mobility Series"} ,
{ 0x10029490, "ATI Radeon 4670 Series"} ,
{ 0x10029498, "ATI Radeon 4650 Series"} ,
{ 0x10029490, "ATI Radeon 4600 Series"} ,
{ 0x10029498, "ATI Radeon 4600 Series"} ,
{ 0x1002949E, "ATI Radeon 4600 Series"} ,
{ 0x10029480, "ATI Radeon 4600 Series"} ,
{ 0x10029488, "ATI Radeon 4600 Series"} ,
{ 0x10029540, "ATI Radeon 4500 Series"} ,
{ 0x10029541, "ATI Radeon 4500 Series"} ,
{ 0x1002954E, "ATI Radeon 4500 Series"} ,
{ 0x10029552, "ATI Radeon 4300 Mobility Series"} ,
{ 0x10029553, "ATI Radeon 4500 Mobility Series"} ,
{ 0x1002954F, "ATI Radeon 4300 Series"} ,
{ 0x100294B3, "ATI Radeon 4770 Series"} ,
{ 0x100294B5, "ATI Radeon 4770 Series"} ,
{ 0x100268B8, "ATI Radeon 5700 Series"} ,
{ 0x100268BE, "ATI Radeon 5700 Series"} ,
{ 0x10026898, "ATI Radeon 5800 Series"} ,
{ 0x10026899, "ATI Radeon 5800 Series"}
};
static struct ati_chipsets_t ATIKnownFramebuffers[] = {
{ 0x00000000, "Megalodon" },
//{ 0x10027181, "Caretta" },
{ 0x10029589, "Lamna"} ,
{ 0x10029588, "Lamna"} ,
{ 0x100294C3, "Iago"} ,
{ 0x100294C4, "Iago"} ,
{ 0x100294C6, "Iago"} ,
{ 0x10029400, "Franklin"} ,
{ 0x10029405, "Franklin"} ,
{ 0x10029581, "Hypoprion"} ,
{ 0x10029583, "Hypoprion"} ,
{ 0x10029586, "Hypoprion"} ,
{ 0x10029587, "Hypoprion"} ,
{ 0x100294C9, "Iago"} ,
{ 0x10029501, "Megalodon"} ,
{ 0x10029505, "Megalodon"} ,
{ 0x10029515, "Megalodon"} ,
{ 0x10029507, "Megalodon"} ,
{ 0x10029500, "Megalodon"} ,
{ 0x1002950F, "Triakis"} ,
{ 0x100295C5, "Iago"} ,
{ 0x100295C7, "Iago"} ,
{ 0x100295C0, "Iago"} ,
{ 0x10029596, "Megalodon"} ,
{ 0x10029590, "Megalodon"} ,
{ 0x10029599, "Megalodon"} ,
{ 0x10029597, "Megalodon"} ,
{ 0x10029598, "Megalodon"} ,
{ 0x10029442, "Motmot"} ,
{ 0x10029440, "Motmot"} ,
{ 0x1002944C, "Motmot"} ,
{ 0x10029460, "Motmot"} ,
{ 0x10029462, "Motmot"} ,
{ 0x10029441, "Motmot"} ,
{ 0x10029443, "Motmot"} ,
{ 0x10029444, "Motmot"} ,
{ 0x10029446, "Motmot"} ,
{ 0x1002944E, "Motmot"} ,
{ 0x10029450, "Motmot"} ,
{ 0x10029452, "Motmot"} ,
{ 0x10029456, "Motmot"} ,
{ 0x1002944A, "Motmot"} ,
{ 0x1002945A, "Motmot"} ,
{ 0x1002945B, "Motmot"} ,
{ 0x1002944B, "Motmot"} ,
{ 0x10029490, "Peregrine"} ,
{ 0x10029498, "Peregrine"} ,
{ 0x1002949E, "Peregrine"} ,
{ 0x10029480, "Peregrine"} ,
{ 0x10029488, "Peregrine"} ,
{ 0x10029540, "Peregrine"} ,
{ 0x10029541, "Peregrine"} ,
{ 0x1002954E, "Peregrine"} ,
{ 0x10029552, "Peregrine"} ,
{ 0x10029553, "Peregrine"} ,
{ 0x1002954F, "Peregrine"} ,
{ 0x100294B3, "Peregrine"},
{ 0x100294B5, "Peregrine"},
{ 0x100268B8, "Motmot"},
{ 0x100268BE, "Motmot"},
{ 0x10026898, "Motmot"},
{ 0x10026899, "Motmot"}
};
static uint32_t accessROM(pci_dt_t *ati_dev, unsigned int mode)
{
uint32_tbar[7];
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (uint32_t *) (bar[2] & ~0x0f);
if (mode) {
if (mode != 1) {
return 0xe00002c7;
}
REG32W(0x179c, 0x00080000);
REG32W(0x1798, 0x00080721);
REG32W(0x17a0, 0x00080621);
REG32W(0x1600, 0x14030300);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
REG32W(0x17a0, 0x21);
REG32W(0x1798, 0x21);
REG32W(0x1798, 0x21);
} else {
REG32W(0x1600, 0x14030302);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00080000);
REG32W(0x17a0, 0x00080621);
REG32W(0x1798, 0x00080721);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
REG32W(0x1604, 0x0400e9fc);
REG32W(0x161c, 0x00);
REG32W(0x1620, 0x9f);
REG32W(0x1618, 0x00040004);
REG32W(0x161c, 0x00);
REG32W(0x1604, 0xe9fc);
REG32W(0x179c, 0x00080000);
REG32W(0x1798, 0x00080721);
REG32W(0x17a0, 0x00080621);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
}
return 0;
}
static uint8_t *readAtomBIOS(pci_dt_t *ati_dev)
{
uint32_tbar[7];
uint32_t*BIOSBase;
uint32_tcounter;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (volatile uint32_t *) (bar[2] & ~0x0f);
accessROM(ati_dev, 0);
REG32W(0xa8, 0);
REG32R(0xac);
REG32W(0xa8, 0);
REG32R(0xac);
BIOSBase = malloc(0x10000);
REG32W(0xa8, 0);
BIOSBase[0] = REG32R(0xac);
counter = 4;
do {
REG32W(0xa8, counter);
BIOSBase[counter/4] = REG32R(0xac);
counter +=4;
} while (counter != 0x10000);
accessROM((pci_dt_t *)regs, 1);
if (*(uint16_t *)BIOSBase != 0xAA55) {
printf("Wrong BIOS signature: %04x\n", *(uint16_t *)BIOSBase);
return 0;
}
return (uint8_t *)BIOSBase;
}
#define R5XX_CONFIG_MEMSIZE0x00F8 //Azi:---
#define R6XX_CONFIG_MEMSIZE0x5428
uint32_t getvramsizekb(pci_dt_t *ati_dev)
{
uint32_tbar[7];
uint32_tsize;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (uint32_t *) (bar[2] & ~0x0f);
if (ati_dev->device_id < 0x9400) {
size = (REG32R(R5XX_CONFIG_MEMSIZE)) >> 10;
} else {
size = (REG32R(R6XX_CONFIG_MEMSIZE)) >> 10;
}
return size;
}
#define AVIVO_D1CRTC_CONTROL0x6080
#define AVIVO_CRTC_EN(1<<0)
#define AVIVO_D2CRTC_CONTROL0x6880
static bool radeon_card_posted(pci_dt_t *ati_dev)
{
// if devid matches biosimage(from legacy) devid - posted card, fails with X2/crossfire cards.
/*char *biosimage = 0xC0000;
if ((uint8_t)biosimage[0] == 0x55 && (uint8_t)biosimage[1] == 0xaa)
{
struct pci_rom_pci_header_t *rom_pci_header;
rom_pci_header = (struct pci_rom_pci_header_t*)(biosimage + (uint8_t)biosimage[24] + (uint8_t)biosimage[25]*256);
if (rom_pci_header->signature == 0x52494350)
{
if (rom_pci_header->device == ati_dev->device_id)
{
return true;
printf("Card was POSTed\n");
}
}
}
return false;
printf("Card was not POSTed\n");
*/
//fails yet
uint32_tbar[7];
uint32_tval;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18);
regs = (uint32_t *) (bar[2] & ~0x0f);
val = REG32R(AVIVO_D1CRTC_CONTROL) | REG32R(AVIVO_D2CRTC_CONTROL);
if (val & AVIVO_CRTC_EN) {
return true;
} else {
return false;
}
}
static uint32_t load_ati_bios_file(const char *filename, uint8_t *buf, int bufsize)
{
intfd;
intsize;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {
return 0;
}
size = file_size(fd);
if (size > bufsize) {
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);
size = bufsize;
}
size = read(fd, (char *)buf, size);
close(fd);
return size > 0 ? size : 0;
}
static char *get_ati_model(uint32_t id)
{
int i;
for (i = 0; i < (sizeof(ATIKnownChipsets) / sizeof(ATIKnownChipsets[0])); i++) {
if (ATIKnownChipsets[i].device == id) {
return ATIKnownChipsets[i].name;
}
}
return ATIKnownChipsets[0].name;
}
static char *get_ati_fb(uint32_t id)
{
inti;
for (i = 0; i < (sizeof(ATIKnownFramebuffers) / sizeof(ATIKnownFramebuffers[0])); i++) {
if (ATIKnownFramebuffers[i].device == id) {
return ATIKnownFramebuffers[i].name;
}
}
return ATIKnownFramebuffers[0].name;
}
static int devprop_add_iopciconfigspace(struct DevPropDevice *device, pci_dt_t *ati_dev)
{
inti;
uint8_t*config_space;
if (!device || !ati_dev) {
return 0;
}
verbose("dumping pci config space, 256 bytes\n");
config_space = malloc(256);
for (i=0; i<=255; i++) {
config_space[i] = pci_config_read8( ati_dev->dev.addr, i);
}
devprop_add_value(device, "ATY,PCIConfigSpace", config_space, 256);
free (config_space);
return 1;
}
static int devprop_add_ati_template_4xxx(struct DevPropDevice *device)
{
if(!device)
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_compatible_0))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_compatible_1))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_1))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_device_type))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name_0))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name_1))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_display_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_display_type_1))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_slot_name))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_card_no))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_copyright))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_version))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_mrt))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_romno))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_name_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_display_con_fl_type_0))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_disp_conf))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_init_stat))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config))
return 0;
return 1;
}
static int devprop_add_ati_template(struct DevPropDevice *device)
{
if(!device)
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0_n4))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_slot_name_n4))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_card_no))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_copyright))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_version))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_mrt))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_romno))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_name_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_emc_disp_list_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_fb_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_hwgpio_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_iospace_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_refclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_regspace_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_0_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_1_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_swgpio_info_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config_n4))
return 0;
return 1;
}
bool setup_ati_devprop(pci_dt_t *ati_dev)
{
struct DevPropDevice*device;
char*devicepath;
char*model;
char*framebuffer;
chartmp[64];
uint8_t*rom = NULL;
uint32_trom_size = 0;
uint8_t*bios;
uint32_tbios_size;
uint32_tvram_size;
uint32_tboot_display;
uint8_tcmd;
booldoit;
booltoFree;
devicepath = get_pci_dev_path(ati_dev);
cmd = pci_config_read8(ati_dev->dev.addr, 4);
verbose("old pci command - %x\n", cmd);
if (cmd == 0) {
pci_config_write8(ati_dev->dev.addr, 4, 6);
cmd = pci_config_read8(ati_dev->dev.addr, 4);
verbose("new pci command - %x\n", cmd);
}
model = get_ati_model((ati_dev->vendor_id << 16) | ati_dev->device_id);
framebuffer = get_ati_fb((ati_dev->vendor_id << 16) | ati_dev->device_id);
if (!string) {
string = devprop_create_string();
}
device = devprop_add_device(string, devicepath);
if (!device) {
printf("Failed initializing dev-prop string dev-entry, press any key...\n");
getc();
return false;
}
/* FIXME: for primary graphics card only */
if (radeon_card_posted(ati_dev)) {
boot_display = 1;
} else {
boot_display = 0;
}
verbose("boot display - %x\n", boot_display);
devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
if ((framebuffer[0] == 'M' && framebuffer[1] == 'o' && framebuffer[2] == 't') ||
(framebuffer[0] == 'S' && framebuffer[1] == 'h' && framebuffer[2] == 'r') ||
(framebuffer[0] == 'P' && framebuffer[1] == 'e' && framebuffer[2] == 'r')) //faster than strcmp ;)
devprop_add_ati_template_4xxx(device);
else {
devprop_add_ati_template(device);
vram_size = getvramsizekb(ati_dev) * 1024;
if ((vram_size > 0x80000000) || (vram_size == 0)) {
vram_size = 0x10000000;//vram reported wrong, defaulting to 256 mb
}
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&vram_size, 4);
ati_vram_memsize_0.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway
ati_vram_memsize_0.data[7] = (vram_size >> 24) & 0xFF;
ati_vram_memsize_1.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway
ati_vram_memsize_1.data[7] = (vram_size >> 24) & 0xFF;
DP_ADD_TEMP_VAL_DATA(device, ati_vram_memsize_0);
DP_ADD_TEMP_VAL_DATA(device, ati_vram_memsize_1);
devprop_add_iopciconfigspace(device, ati_dev);
}
devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1));
devprop_add_value(device, "ATY,DeviceID", (uint8_t*)&ati_dev->device_id, 2);
//fb setup
sprintf(tmp, "Slot-%x",devices_number);
devprop_add_value(device, "AAPL,slot-name", (uint8_t*)tmp, strlen(tmp) + 1);
devices_number++;
sprintf(tmp, ati_compatible_0[1], framebuffer);
devprop_add_value(device, (char *) ati_compatible_0[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_compatible_1[1], framebuffer);
devprop_add_value(device, (char *) ati_compatible_1[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_device_type[1], framebuffer);
devprop_add_value(device, (char *) ati_device_type[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name[1], framebuffer);
devprop_add_value(device, (char *) ati_name[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name_0[1], framebuffer);
devprop_add_value(device, (char *) ati_name_0[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name_1[1], framebuffer);
devprop_add_value(device, (char *) ati_name_1[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, "bt(0,0)/Extra/%04x_%04x.rom", (uint16_t)ati_dev->vendor_id, (uint16_t)ati_dev->device_id);
if (getBoolForKey(kUseAtiROMKey, &doit, &bootInfo->bootConfig) && doit) {
verbose("looking for ati video bios file %s\n", tmp);
rom = malloc(0x20000);
rom_size = load_ati_bios_file(tmp, rom, 0x20000);
if (rom_size > 0) {
verbose("Using ATI Video BIOS File %s (%d Bytes)\n", tmp, rom_size);
if (rom_size > 0x10000) {
rom_size = 0x10000; //we dont need rest anyway;
}
} else {
printf("ERROR: unable to open ATI Video BIOS File %s\n", tmp);
}
}
if (rom_size == 0) {
if (boot_display) {// no custom rom
bios = NULL;// try to dump from legacy space, otherwise can result in 100% fan speed
} else {
// readAtomBios result in bug on some cards (100% fan speed and black screen),
// not using it for posted card, reading from legacy space instead
bios = readAtomBIOS(ati_dev);
}
} else {
bios = rom;//going custom rom way
verbose("Using rom %s\n", tmp);
}
if (bios == NULL) {
bios = (uint8_t *)0x000C0000;
toFree = false;
verbose("Not going to use bios image file\n");
} else {
toFree = true;
}
if (bios[0] == 0x55 && bios[1] == 0xaa) {
verbose("Found bios image\n");
bios_size = bios[2] * 512;
struct pci_rom_pci_header_t *rom_pci_header;
rom_pci_header = (struct pci_rom_pci_header_t*)(bios + bios[24] + bios[25]*256);
if (rom_pci_header->signature == 0x52494350) {
if (rom_pci_header->device != ati_dev->device_id) {
verbose("Bios image (%x) doesnt match card (%x), ignoring\n", rom_pci_header->device, ati_dev->device_id);
} else {
if (toFree)
{
//Azi: mmio, Memory-mapped I/O - Kabyl's smbios patcher stuff reminder.
verbose("Adding binimage to card %x from mmio space with size %x\n", ati_dev->device_id, bios_size);
} else {
verbose("Adding binimage to card %x from legacy space with size %x\n", ati_dev->device_id, bios_size);
}
devprop_add_value(device, "ATY,bin_image", bios, bios_size);
}
} else {
verbose("Wrong pci header signature %x\n", rom_pci_header->signature);
}
} else {
verbose("Bios image not found at %x, content %x %x\n", bios, bios[0], bios[1]);
}
if (toFree) {
free(bios);
}
stringdata = malloc(sizeof(uint8_t) * string->length);
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
branches/azimutz/Cleancut/i386/modules/AMDGraphicsEnabler/ati_reg.h
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