Chameleon

Chameleon Commit Details

Date:2011-05-22 13:50:06 (12 years 10 months ago)
Author:Azimutz
Commit:872
Parents: 871
Message:Merge graphics modules from Cleancut.
Changes:
A/branches/azimutz/Chazi/i386/modules/AMDGraphicsEnabler/ati.c
A/branches/azimutz/Chazi/i386/modules/IntelGraphicsEnabler/gma.c
A/branches/azimutz/Chazi/i386/modules/AMDGraphicsEnabler
A/branches/azimutz/Chazi/i386/modules/AMDGraphicsEnabler/ati_reg.h
A/branches/azimutz/Chazi/i386/modules/IntelGraphicsEnabler/gma.h
A/branches/azimutz/Chazi/i386/modules/NVIDIAGraphicsEnabler/nvidia.c
A/branches/azimutz/Chazi/i386/modules/NVIDIAGraphicsEnabler/nvidia.h
A/branches/azimutz/Chazi/i386/modules/NVIDIAGraphicsEnabler
A/branches/azimutz/Chazi/i386/modules/ATiGraphicsEnabler/ati.c
A/branches/azimutz/Chazi/i386/modules/IntelGraphicsEnabler
A/branches/azimutz/Chazi/i386/modules/AMDGraphicsEnabler/Readme.txt
A/branches/azimutz/Chazi/i386/modules/ATiGraphicsEnabler/pci_old.h
A/branches/azimutz/Chazi/i386/modules/ATiGraphicsEnabler
A/branches/azimutz/Chazi/i386/modules/AMDGraphicsEnabler/Makefile
A/branches/azimutz/Chazi/i386/modules/NVIDIAGraphicsEnabler/NVIDIAGraphicsEnabler.c
A/branches/azimutz/Chazi/i386/modules/ATiGraphicsEnabler/ati.h
A/branches/azimutz/Chazi/i386/modules/IntelGraphicsEnabler/IntelGraphicsEnabler.c
A/branches/azimutz/Chazi/i386/modules/NVIDIAGraphicsEnabler/Readme.txt
A/branches/azimutz/Chazi/i386/modules/ATiGraphicsEnabler/ATiGraphicsEnabler.c
A/branches/azimutz/Chazi/i386/modules/IntelGraphicsEnabler/Readme.txt
A/branches/azimutz/Chazi/i386/modules/NVIDIAGraphicsEnabler/Makefile
A/branches/azimutz/Chazi/i386/modules/IntelGraphicsEnabler/Makefile
A/branches/azimutz/Chazi/i386/modules/ATiGraphicsEnabler/Readme.txt
A/branches/azimutz/Chazi/i386/modules/ATiGraphicsEnabler/Makefile
A/branches/azimutz/Chazi/i386/modules/AMDGraphicsEnabler/AMDGraphicsEnabler.c
M/branches/azimutz/Chazi/i386/modules/Makefile
M/branches/azimutz/Cleancut/i386/modules/ATiGraphicsEnabler/Readme.txt

File differences

branches/azimutz/Chazi/i386/modules/NVIDIAGraphicsEnabler/nvidia.h
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/*
* NVidia injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi
*
* NVidia injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* NVidia driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
/*
* DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
*
*
* Copyright 2005-2006 Erik Waling
* Copyright 2006 Stephane Marchesin
* Copyright 2007-2009 Stuart Bennett
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __LIBSAIO_NVIDIA_H
#define __LIBSAIO_NVIDIA_H
bool setup_nvidia_devprop(pci_dt_t *nvda_dev);
struct nv_chipsets_t {
unsigned device;
char *name;
};
#define DCB_MAX_NUM_ENTRIES 16
#define DCB_MAX_NUM_I2C_ENTRIES 16
#define DCB_LOC_ON_CHIP 0
struct bios {
uint16_tsignature;/* 0x55AA */
uint8_tsize;/* Size in multiples of 512 */
};
#define NV_PROM_OFFSET0x300000
#define NV_PROM_SIZE0x0000ffff
#define NV_PRAMIN_OFFSET0x00700000
#define NV_PRAMIN_SIZE0x00100000
#define NV04_PFB_FIFO_DATA0x0010020c
#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK0xfff00000
#define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT20
#define NVC0_MEM_CTRLR_COUNT0x00121c74
#define NVC0_MEM_CTRLR_RAM_AMOUNT0x0010f20c
#define NV_PBUS_PCI_NV_200x00001850
#define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED(0 << 0)
#define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED(1 << 0)
#define REG8(reg) ((volatile uint8_t *)regs)[(reg)]
#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1]
#define REG32(reg) ((volatile uint32_t *)regs)[(reg) >> 2]
#define NV_ARCH_03 0x03
#define NV_ARCH_04 0x04
#define NV_ARCH_10 0x10
#define NV_ARCH_20 0x20
#define NV_ARCH_30 0x30
#define NV_ARCH_40 0x40
#define NV_ARCH_50 0x50
#define NV_ARCH_C0 0xC0
#define CHIPSET_NV03 0x0010
#define CHIPSET_NV04 0x0020
#define CHIPSET_NV10 0x0100
#define CHIPSET_NV11 0x0110
#define CHIPSET_NV15 0x0150
#define CHIPSET_NV17 0x0170
#define CHIPSET_NV18 0x0180
#define CHIPSET_NFORCE 0x01A0
#define CHIPSET_NFORCE2 0x01F0
#define CHIPSET_NV20 0x0200
#define CHIPSET_NV25 0x0250
#define CHIPSET_NV28 0x0280
#define CHIPSET_NV30 0x0300
#define CHIPSET_NV31 0x0310
#define CHIPSET_NV34 0x0320
#define CHIPSET_NV35 0x0330
#define CHIPSET_NV36 0x0340
#define CHIPSET_NV40 0x0040
#define CHIPSET_NV41 0x00C0
#define CHIPSET_NV43 0x0140
#define CHIPSET_NV44 0x0160
#define CHIPSET_NV44A 0x0220
#define CHIPSET_NV45 0x0210
#define CHIPSET_NV50 0x0190
#define CHIPSET_NV84 0x0400
#define CHIPSET_MISC_BRIDGED 0x00F0
#define CHIPSET_G70 0x0090
#define CHIPSET_G71 0x0290
#define CHIPSET_G72 0x01D0
#define CHIPSET_G73 0x0390
// integrated GeForces (6100, 6150)
#define CHIPSET_C51 0x0240
// variant of C51, seems based on a G70 design
#define CHIPSET_C512 0x03D0
#define CHIPSET_G73_BRIDGED 0x02E0
#endif /* !__LIBSAIO_NVIDIA_H */
branches/azimutz/Chazi/i386/modules/NVIDIAGraphicsEnabler/NVIDIAGraphicsEnabler.c
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/*
* GraphicsEnabler Module
*Enabled many nvidia and ati cards to be used out of the box in
*OS X. This was converted from boot2 code to a boot2 module.
*
*/
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "nvidia.h"
#include "modules.h"
#define kGraphicsEnablerKey"GraphicsEnabler"
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4);
void NVIDIAGraphicsEnabler_start()
{
register_hook_callback("PCIDevice", &GraphicsEnabler_hook);
}
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4)
{
pci_dt_t* current = arg1;
if (current->class_id != PCI_CLASS_DISPLAY_VGA) return;
char *devicepath = get_pci_dev_path(current);
bool do_gfx_devprop = true;
getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->bootConfig);
//Azi: check "fail" code...
if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_NVIDIA))
{
verbose("NVIDIA VGA Controller [%04x:%04x] :: %s \n",
current->vendor_id, current->device_id, devicepath);
setup_nvidia_devprop(current); // ---
}
else
verbose("Not a NVIDIA VGA Controller.\n"); // ---
}
branches/azimutz/Chazi/i386/modules/NVIDIAGraphicsEnabler/Readme.txt
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Module:GraphicsEnabler
Description: the GraphicsEnabler nVidia code ported to a module.
Based on Meklort's work.
Dependencies: none
Keys: GraphicsEnabler(enabled by default)
UseNvidiaROM(disabled by default)
VBIOS...
TODO: ---
branches/azimutz/Chazi/i386/modules/NVIDIAGraphicsEnabler/nvidia.c
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/*
* NVidia injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi
*
* NVidia injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* NVidia driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
/*
* DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
*
*
* Copyright 2005-2006 Erik Waling
* Copyright 2006 Stephane Marchesin
* Copyright 2007-2009 Stuart Bennett
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#include "device_inject.h"
#include "nvidia.h"
#ifndef DEBUG_NVIDIA
#define DEBUG_NVIDIA 0
#endif
#if DEBUG_NVIDIA
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
#define kUseNvidiaROM"UseNvidiaROM"
#define kVBIOS"VBIOS"
#define NVIDIA_ROM_SIZE 0x10000
#define PATCH_ROM_SUCCESS 1
#define PATCH_ROM_SUCCESS_HAS_LVDS 2
#define PATCH_ROM_FAILED 0
#define MAX_NUM_DCB_ENTRIES 16
#define TYPE_GROUPED 0xff
extern uint32_t devices_number;
const char *nvidia_compatible_0[]={ "@0,compatible","NVDA,NVMac" };
const char *nvidia_compatible_1[]={ "@1,compatible","NVDA,NVMac" };
const char *nvidia_device_type_0[]={ "@0,device_type","display" };
const char *nvidia_device_type_1[]={ "@1,device_type","display" };
const char *nvidia_device_type[]={ "device_type","NVDA,Parent" };
const char *nvidia_name_0[]={ "@0,name","NVDA,Display-A" };
const char *nvidia_name_1[]={ "@1,name","NVDA,Display-B" };
const char *nvidia_slot_name[]={ "AAPL,slot-name","Slot-1" };
static uint8_t default_NVCAP[]= {
0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
0x00, 0x00, 0x00, 0x00
};
#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )
static struct nv_chipsets_t NVKnownChipsets[] = {
{ 0x00000000, "Unknown" },
{ 0x10DE0040, "GeForce 6800 Ultra" },
{ 0x10DE0041, "GeForce 6800" },
{ 0x10DE0042, "GeForce 6800 LE" },
{ 0x10DE0043, "GeForce 6800 XE" },
{ 0x10DE0044, "GeForce 6800 XT" },
{ 0x10DE0045, "GeForce 6800 GT" },
{ 0x10DE0046, "GeForce 6800 GT" },
{ 0x10DE0047, "GeForce 6800 GS" },
{ 0x10DE0048, "GeForce 6800 XT" },
{ 0x10DE004E, "Quadro FX 4000" },
{ 0x10DE0090, "GeForce 7800 GTX" },
{ 0x10DE0091, "GeForce 7800 GTX" },
{ 0x10DE0092, "GeForce 7800 GT" },
{ 0x10DE0093, "GeForce 7800 GS" },
{ 0x10DE0095, "GeForce 7800 SLI" },
{ 0x10DE0098, "GeForce Go 7800" },
{ 0x10DE0099, "GeForce Go 7800 GTX" },
{ 0x10DE009D, "Quadro FX 4500" },
{ 0x10DE00C0, "GeForce 6800 GS" },
{ 0x10DE00C1, "GeForce 6800" },
{ 0x10DE00C2, "GeForce 6800 LE" },
{ 0x10DE00C3, "GeForce 6800 XT" },
{ 0x10DE00C8, "GeForce Go 6800" },
{ 0x10DE00C9, "GeForce Go 6800 Ultra" },
{ 0x10DE00CC, "Quadro FX Go1400" },
{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },
{ 0x10DE00CE, "Quadro FX 1400" },
{ 0x10DE0140, "GeForce 6600 GT" },
{ 0x10DE0141, "GeForce 6600" },
{ 0x10DE0142, "GeForce 6600 LE" },
{ 0x10DE0143, "GeForce 6600 VE" },
{ 0x10DE0144, "GeForce Go 6600" },
{ 0x10DE0145, "GeForce 6610 XL" },
{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },
{ 0x10DE0147, "GeForce 6700 XL" },
{ 0x10DE0148, "GeForce Go 6600" },
{ 0x10DE0149, "GeForce Go 6600 GT" },
{ 0x10DE014C, "Quadro FX 550" },
{ 0x10DE014D, "Quadro FX 550" },
{ 0x10DE014E, "Quadro FX 540" },
{ 0x10DE014F, "GeForce 6200" },
{ 0x10DE0160, "GeForce 6500" },
{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },
{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },
{ 0x10DE0163, "GeForce 6200 LE" },
{ 0x10DE0164, "GeForce Go 6200" },
{ 0x10DE0165, "Quadro NVS 285" },
{ 0x10DE0166, "GeForce Go 6400" },
{ 0x10DE0167, "GeForce Go 6200" },
{ 0x10DE0168, "GeForce Go 6400" },
{ 0x10DE0169, "GeForce 6250" },
{ 0x10DE016A, "GeForce 7100 GS" },
{ 0x10DE0191, "GeForce 8800 GTX" },
{ 0x10DE0193, "GeForce 8800 GTS" },
{ 0x10DE0194, "GeForce 8800 Ultra" },
{ 0x10DE019D, "Quadro FX 5600" },
{ 0x10DE019E, "Quadro FX 4600" },
{ 0x10DE01D1, "GeForce 7300 LE" },
{ 0x10DE01D3, "GeForce 7300 SE" },
{ 0x10DE01D6, "GeForce Go 7200" },
{ 0x10DE01D7, "GeForce Go 7300" },
{ 0x10DE01D8, "GeForce Go 7400" },
{ 0x10DE01D9, "GeForce Go 7400 GS" },
{ 0x10DE01DA, "Quadro NVS 110M" },
{ 0x10DE01DB, "Quadro NVS 120M" },
{ 0x10DE01DC, "Quadro FX 350M" },
{ 0x10DE01DD, "GeForce 7500 LE" },
{ 0x10DE01DE, "Quadro FX 350" },
{ 0x10DE01DF, "GeForce 7300 GS" },
{ 0x10DE0211, "GeForce 6800" },
{ 0x10DE0212, "GeForce 6800 LE" },
{ 0x10DE0215, "GeForce 6800 GT" },
{ 0x10DE0218, "GeForce 6800 XT" },
{ 0x10DE0221, "GeForce 6200" },
{ 0x10DE0222, "GeForce 6200 A-LE" },
{ 0x10DE0240, "GeForce 6150" },
{ 0x10DE0241, "GeForce 6150 LE" },
{ 0x10DE0242, "GeForce 6100" },
{ 0x10DE0244, "GeForce Go 6150" },
{ 0x10DE0247, "GeForce Go 6100" },
{ 0x10DE0290, "GeForce 7900 GTX" },
{ 0x10DE0291, "GeForce 7900 GT" },
{ 0x10DE0292, "GeForce 7900 GS" },
{ 0x10DE0298, "GeForce Go 7900 GS" },
{ 0x10DE0299, "GeForce Go 7900 GTX" },
{ 0x10DE029A, "Quadro FX 2500M" },
{ 0x10DE029B, "Quadro FX 1500M" },
{ 0x10DE029C, "Quadro FX 5500" },
{ 0x10DE029D, "Quadro FX 3500" },
{ 0x10DE029E, "Quadro FX 1500" },
{ 0x10DE029F, "Quadro FX 4500 X2" },
{ 0x10DE0301, "GeForce FX 5800 Ultra" },
{ 0x10DE0302, "GeForce FX 5800" },
{ 0x10DE0308, "Quadro FX 2000" },
{ 0x10DE0309, "Quadro FX 1000" },
{ 0x10DE0311, "GeForce FX 5600 Ultra" },
{ 0x10DE0312, "GeForce FX 5600" },
{ 0x10DE0314, "GeForce FX 5600XT" },
{ 0x10DE031A, "GeForce FX Go5600" },
{ 0x10DE031B, "GeForce FX Go5650" },
{ 0x10DE031C, "Quadro FX Go700" },
{ 0x10DE0324, "GeForce FX Go5200" },
{ 0x10DE0325, "GeForce FX Go5250" },
{ 0x10DE0326, "GeForce FX 5500" },
{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },
{ 0x10DE032A, "Quadro NVS 55/280 PCI" },
{ 0x10DE032B, "Quadro FX 500/600 PCI" },
{ 0x10DE032C, "GeForce FX Go53xx Series" },
{ 0x10DE032D, "GeForce FX Go5100" },
{ 0x10DE0330, "GeForce FX 5900 Ultra" },
{ 0x10DE0331, "GeForce FX 5900" },
{ 0x10DE0332, "GeForce FX 5900XT" },
{ 0x10DE0333, "GeForce FX 5950 Ultra" },
{ 0x10DE0334, "GeForce FX 5900ZT" },
{ 0x10DE0338, "Quadro FX 3000" },
{ 0x10DE033F, "Quadro FX 700" },
{ 0x10DE0341, "GeForce FX 5700 Ultra" },
{ 0x10DE0342, "GeForce FX 5700" },
{ 0x10DE0343, "GeForce FX 5700LE" },
{ 0x10DE0344, "GeForce FX 5700VE" },
{ 0x10DE0347, "GeForce FX Go5700" },
{ 0x10DE0348, "GeForce FX Go5700" },
{ 0x10DE034C, "Quadro FX Go1000" },
{ 0x10DE034E, "Quadro FX 1100" },
{ 0x10DE0391, "GeForce 7600 GT" },
{ 0x10DE0392, "GeForce 7600 GS" },
{ 0x10DE0393, "GeForce 7300 GT" },
{ 0x10DE0394, "GeForce 7600 LE" },
{ 0x10DE0395, "GeForce 7300 GT" },
{ 0x10DE0397, "GeForce Go 7700" },
{ 0x10DE0398, "GeForce Go 7600" },
{ 0x10DE0399, "GeForce Go 7600 GT"},
{ 0x10DE039A, "Quadro NVS 300M" },
{ 0x10DE039B, "GeForce Go 7900 SE" },
{ 0x10DE039C, "Quadro FX 550M" },
{ 0x10DE039E, "Quadro FX 560" },
{ 0x10DE0400, "GeForce 8600 GTS" },
{ 0x10DE0401, "GeForce 8600 GT" },
{ 0x10DE0402, "GeForce 8600 GT" },
{ 0x10DE0403, "GeForce 8600 GS" },
{ 0x10DE0404, "GeForce 8400 GS" },
{ 0x10DE0405, "GeForce 9500M GS" },
{ 0x10DE0407, "GeForce 8600M GT" },
{ 0x10DE0408, "GeForce 9650M GS" },
{ 0x10DE0409, "GeForce 8700M GT" },
{ 0x10DE040A, "Quadro FX 370" },
{ 0x10DE040B, "Quadro NVS 320M" },
{ 0x10DE040C, "Quadro FX 570M" },
{ 0x10DE040D, "Quadro FX 1600M" },
{ 0x10DE040E, "Quadro FX 570" },
{ 0x10DE040F, "Quadro FX 1700" },
{ 0x10DE0420, "GeForce 8400 SE" },
{ 0x10DE0421, "GeForce 8500 GT" },
{ 0x10DE0422, "GeForce 8400 GS" },
{ 0x10DE0423, "GeForce 8300 GS" },
{ 0x10DE0424, "GeForce 8400 GS" },
{ 0x10DE0425, "GeForce 8600M GS" },
{ 0x10DE0426, "GeForce 8400M GT" },
{ 0x10DE0427, "GeForce 8400M GS" },
{ 0x10DE0428, "GeForce 8400M G" },
{ 0x10DE0429, "Quadro NVS 140M" },
{ 0x10DE042A, "Quadro NVS 130M" },
{ 0x10DE042B, "Quadro NVS 135M" },
{ 0x10DE042C, "GeForce 9400 GT" },
{ 0x10DE042D, "Quadro FX 360M" },
{ 0x10DE042E, "GeForce 9300M G" },
{ 0x10DE042F, "Quadro NVS 290" },
{ 0x10DE05E0, "GeForce GTX 295" },
{ 0x10DE05E1, "GeForce GTX 280" },
{ 0x10DE05E2, "GeForce GTX 260" },
{ 0x10DE05E3, "GeForce GTX 285" },
{ 0x10DE05E6, "GeForce GTX 275" },
{ 0x10DE05EA, "GeForce GTX 260" },
{ 0x10DE05EB, "GeForce GTX 295" },
{ 0x10DE05F9, "Quadro CX" },
{ 0x10DE05FD, "Quadro FX 5800" },
{ 0x10DE05FE, "Quadro FX 4800" },
{ 0x10DE0600, "GeForce 8800 GTS 512" },
{ 0x10DE0602, "GeForce 8800 GT" },
{ 0x10DE0604, "GeForce 9800 GX2" },
{ 0x10DE0605, "GeForce 9800 GT" },
{ 0x10DE0606, "GeForce 8800 GS" },
{ 0x10DE0607, "GeForce GTS 240" },
{ 0x10DE0608, "GeForce 9800M GTX" },
{ 0x10DE0609, "GeForce 8800M GTS" },
{ 0x10DE060A, "GeForce GTX 280M" },
{ 0x10DE060B, "GeForce 9800M GT" },
{ 0x10DE060C, "GeForce 8800M GTX" },
{ 0x10DE060D, "GeForce 8800 GS" },
{ 0x10DE0610, "GeForce 9600 GSO" },
{ 0x10DE0611, "GeForce 8800 GT" },
{ 0x10DE0612, "GeForce 9800 GTX" },
{ 0x10DE0613, "GeForce 9800 GTX+" },
{ 0x10DE0614, "GeForce 9800 GT" },
{ 0x10DE0615, "GeForce GTS 250" },
{ 0x10DE0617, "GeForce 9800M GTX" },
{ 0x10DE0618, "GeForce GTX 260M" },
{ 0x10DE061A, "Quadro FX 3700" },
{ 0x10DE061C, "Quadro FX 3600M" },
{ 0x10DE061D, "Quadro FX 2800M" },
{ 0x10DE061F, "Quadro FX 3800M" },
{ 0x10DE0622, "GeForce 9600 GT" },
{ 0x10DE0623, "GeForce 9600 GS" },
{ 0x10DE0625, "GeForce 9600 GSO 512"},
{ 0x10DE0626, "GeForce GT 130" },
{ 0x10DE0627, "GeForce GT 140" },
{ 0x10DE0628, "GeForce 9800M GTS" },
{ 0x10DE062A, "GeForce 9700M GTS" },
{ 0x10DE062C, "GeForce 9800M GTS" },
{ 0x10DE0640, "GeForce 9500 GT" },
{ 0x10DE0641, "GeForce 9400 GT" },
{ 0x10DE0642, "GeForce 8400 GS" },
{ 0x10DE0643, "GeForce 9500 GT" },
{ 0x10DE0644, "GeForce 9500 GS" },
{ 0x10DE0645, "GeForce 9500 GS" },
{ 0x10DE0646, "GeForce GT 120" },
{ 0x10DE0647, "GeForce 9600M GT" },
{ 0x10DE0648, "GeForce 9600M GS" },
{ 0x10DE0649, "GeForce 9600M GT" },
{ 0x10DE064A, "GeForce 9700M GT" },
{ 0x10DE064B, "GeForce 9500M G" },
{ 0x10DE064C, "GeForce 9650M GT" },
{ 0x10DE0652, "GeForce GT 130M" },
{ 0x10DE0658, "Quadro FX 380" },
{ 0x10DE0659, "Quadro FX 580" },
{ 0x10DE065A, "Quadro FX 1700M" },
{ 0x10DE065B, "GeForce 9400 GT" },
{ 0x10DE065C, "Quadro FX 770M" },
{ 0x10DE06E0, "GeForce 9300 GE" },
{ 0x10DE06E1, "GeForce 9300 GS" },
{ 0x10DE06E4, "GeForce 8400 GS" },
{ 0x10DE06E5, "GeForce 9300M GS" },
{ 0x10DE06E8, "GeForce 9200M GS" },
{ 0x10DE06E9, "GeForce 9300M GS" },
{ 0x10DE06EA, "Quadro NVS 150M" },
{ 0x10DE06EB, "Quadro NVS 160M" },
{ 0x10DE06EC, "GeForce G 105M" },
{ 0x10DE06EF, "GeForce G 103M" },
{ 0x10DE06F8, "Quadro NVS 420" },
{ 0x10DE06F9, "Quadro FX 370 LP" },
{ 0x10DE06FA, "Quadro NVS 450" },
{ 0x10DE06FD, "Quadro NVS 295" },
{ 0x10DE086A, "GeForce 9400" },
{ 0x10DE0874, "ION 9300M" },
{ 0x10DE086C, "GeForce 9300/nForce 730i" },
{ 0x10DE087D, "ION 9400M" },
{ 0x10DE087E, "ION LE" },
{ 0x10DE0A20, "GeForce GT220" },
{ 0x10DE0A23, "GeForce 210" },
{ 0x10DE0A28, "GeForce GT 230M" },
{ 0x10DE0A29, "GeForce GT 330M" },
{ 0x10DE0A2A, "GeForce GT 230M" },
{ 0x10DE0A34, "GeForce GT 240M" },
{ 0x10DE0A60, "GeForce G210" },
{ 0x10DE0A62, "GeForce 205" },
{ 0x10DE0A63, "GeForce 310" },
{ 0x10DE0A65, "GeForce 210" },
{ 0x10DE0A66, "GeForce 310" },
{ 0x10DE0A74, "GeForce G210M" },
{ 0x10DE0A75, "GeForce G310M" },
{ 0x10DE0A78, "Quadro FX 380 LP" },
{ 0x10DE0CA3, "GeForce GT 240" },
{ 0x10DE0CA8, "GeForce GTS 260M" },
{ 0x10DE0CA9, "GeForce GTS 250M" },
{ 0x10DE0CB1, "GeForce GTS 360M" },
{ 0x10DE0CA3, "GeForce GT240" },
// 06C0 - 06DFF
{ 0x10DE06C0, "GeForce GTX 480" },
{ 0x10DE06C3, "GeForce GTX D12U" },
{ 0x10DE06C4, "GeForce GTX 465" },
{ 0x10DE06CA, "GeForce GTX 480M" },
{ 0x10DE06CD, "GeForce GTX 470" },
{ 0x10DE06D1, "Tesla C2050" },// TODO: sub-device id: 0x0771
{ 0x10DE06D1, "Tesla C2070" },// TODO: sub-device id: 0x0772
{ 0x10DE06D2, "Tesla M2070" },
{ 0x10DE06D8, "Quadro 6000" },
{ 0x10DE06D9, "Quadro 5000" },
{ 0x10DE06DA, "Quadro 5000M" },
{ 0x10DE06DC, "Quadro 6000" },
{ 0x10DE06DE, "Tesla M2050" },// TODO: sub-device id: 0x0846
{ 0x10DE06DE, "Tesla M2070" },// TODO: sub-device id: ?
// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070
{ 0x10DE06DD, "Quadro 4000" },
// 0DC0 - 0DFF
{ 0x10DE0DC0, "GeForce GT 440" },
{ 0x10DE0DC1, "D12-P1-35" },
{ 0x10DE0DC2, "D12-P1-35" },
{ 0x10DE0DC4, "GeForce GTS 450" },
{ 0x10DE0DC5, "GeForce GTS 450" },
{ 0x10DE0DC6, "GeForce GTS 450" },
{ 0x10DE0DCA, "GF10x" },
{ 0x10DE0DD1, "GeForce GTX 460M" },
{ 0x10DE0DD2, "GeForce GT 445M" },
{ 0x10DE0DD3, "GeForce GT 435M" },
{ 0x10DE0DD8, "Quadro 2000" },
{ 0x10DE0DDE, "GF106-ES" },
{ 0x10DE0DDF, "GF106-INT" },
{ 0x10DE0DE1, "GeForce GT 430" },
{ 0x10DE0DE2, "GeForce GT 420" },
{ 0x10DE0DEB, "GeForce GT 555M" },
{ 0x10DE0DEE, "GeForce GT 415M" },
{ 0x10DE0DF0, "GeForce GT 425M" },
{ 0x10DE0DF1, "GeForce GT 420M" },
{ 0x10DE0DF2, "GeForce GT 435M" },
{ 0x10DE0DF3, "GeForce GT 420M" },
{ 0x10DE0DF8, "Quadro 600" },
{ 0x10DE0DFE, "GF108 ES" },
{ 0x10DE0DFF, "GF108 INT" },
// 0E20 - 0E3F
{ 0x10DE0E21, "D12U-25" },
{ 0x10DE0E22, "GeForce GTX 460" },
{ 0x10DE0E23, "GeForce GTX 460 SE" },
{ 0x10DE0E24, "GeForce GTX 460" },
{ 0x10DE0E25, "D12U-50" },
{ 0x10DE0E30, "GeForce GTX 470M" },
{ 0x10DE0E38, "GF104GL" },
{ 0x10DE0E3E, "GF104-ES" },
{ 0x10DE0E3F, "GF104-INT" },
// 0EE0 - 0EFF: none yet
// 0F00 - 0F3F: none yet
// 1040 - 107F: none yet
// 1080 - 109F
{ 0x10DE1080, "GeForce GTX 580" },
{ 0x10DE1081, "D13U" },
{ 0x10DE1082, "D13U" },
{ 0x10DE1083, "D13U" },
{ 0x10DE1098, "D13U" },
{ 0x10DE109A, "N12E-Q5" },
};
static uint16_t swap16(uint16_t x)
{
return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));
}
static uint16_t read16(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[2];
ret[0] = ptr[offset+1];
ret[1] = ptr[offset];
return *((uint16_t*)&ret);
}
#if 0
static uint32_t swap32(uint32_t x)
{
return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);
}
static uint8_t read8(uint8_t *ptr, uint16_t offset)
{
return ptr[offset];
}
static uint32_t read32(uint8_t *ptr, uint16_t offset)
{
uint8_t ret[4];
ret[0] = ptr[offset+3];
ret[1] = ptr[offset+2];
ret[2] = ptr[offset+1];
ret[3] = ptr[offset];
return *((uint32_t*)&ret);
}
#endif
static int patch_nvidia_rom(uint8_t *rom)
{
if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {
printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);
return PATCH_ROM_FAILED;
}
uint16_t dcbptr = swap16(read16(rom, 0x36));
if(!dcbptr) {
printf("no dcb table found\n");
return PATCH_ROM_FAILED;
}/* else
printf("dcb table at offset 0x%04x\n", dcbptr);
*/
uint8_t *dcbtable = &rom[dcbptr];
uint8_t dcbtable_version = dcbtable[0];
uint8_t headerlength = 0;
uint8_t recordlength = 0;
uint8_t numentries = 0;
if(dcbtable_version >= 0x20) {
uint32_t sig;
if(dcbtable_version >= 0x30) {
headerlength = dcbtable[1];
numentries = dcbtable[2];
recordlength = dcbtable[3];
sig = *(uint32_t *)&dcbtable[6];
} else {
sig = *(uint32_t *)&dcbtable[4];
headerlength = 8;
}
if (sig != 0x4edcbdcb) {
printf("bad display config block signature (0x%8x)\n", sig);
return PATCH_ROM_FAILED;
}
} else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */
char sig[8] = { 0 };
strncpy(sig, (char *)&dcbtable[-7], 7);
recordlength = 10;
if (strcmp(sig, "DEV_REC")) {
printf("Bad Display Configuration Block signature (%s)\n", sig);
return PATCH_ROM_FAILED;
}
} else {
printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);
return PATCH_ROM_FAILED;
}
if(numentries >= MAX_NUM_DCB_ENTRIES)
numentries = MAX_NUM_DCB_ENTRIES;
uint8_t num_outputs = 0, i=0;
struct dcbentry {
uint8_t type;
uint8_t index;
uint8_t *heads;
} entries[numentries];
for (i = 0; i < numentries; i++) {
uint32_t connection;
connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];
/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
if ((connection & 0x0000000f) == 0x0000000f) /* end of records */
continue;
if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */
continue;
if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */
continue;
entries[num_outputs].type = connection & 0xf;
entries[num_outputs].index = num_outputs;
entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);
}
int has_lvds = false;
uint8_t channel1 = 0, channel2 = 0;
for(i=0; i<num_outputs; i++) {
if(entries[i].type == 3) {
has_lvds = true;
//printf("found LVDS\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
}
// if we have a LVDS output, we group the rest to the second channel
if(has_lvds) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
continue;
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
} else {
//
int x;
// we loop twice as we need to generate two channels
for(x=0; x<=1; x++) {
for(i=0; i<num_outputs; i++) {
if(entries[i].type == TYPE_GROUPED)
continue;
// if type is TMDS, the prior output is ANALOG
// we always group ANALOG and TMDS
// if there is a TV output after TMDS, we group it to that channel as well
if(i && entries[i].type == 0x2) {
switch (x) {
case 0:
//printf("group channel 1\n");
channel1 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if((entries[i-1].type == 0x0)) {
channel1 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
//printf("group tv1\n");
channel1 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
case 1:
//printf("group channel 2 : %d\n", i);
channel2 |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
if((entries[i-1].type == 0x0)) {
channel2 |= ( 0x1 << entries[i-1].index);
entries[i-1].type = TYPE_GROUPED;
}
// group TV as well if there is one
if( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
//printf("group tv2\n");
channel2 |= ( 0x1 << entries[i+1].index);
entries[i+1].type = TYPE_GROUPED;
}
break;
}
break;
}
}
}
}
// if we have left ungrouped outputs merge them to the empty channel
uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);
togroup = &channel2;
for(i=0; i<num_outputs;i++)
if(entries[i].type != TYPE_GROUPED) {
//printf("%d not grouped\n", i);
if(togroup)
*togroup |= ( 0x1 << entries[i].index);
entries[i].type = TYPE_GROUPED;
}
if(channel1 > channel2) {
uint8_t buff = channel1;
channel1 = channel2;
channel2 = buff;
}
default_NVCAP[6] = channel1;
default_NVCAP[8] = channel2;
// patching HEADS
for(i=0; i<num_outputs;i++) {
if(channel1 & (1 << i))
*entries[i].heads = 1;
else if(channel2 & (1 << i))
*entries[i].heads = 2;
}
return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);
}
static char *get_nvidia_model(uint32_t id) {
inti;
for (i=1; i< (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {
if (NVKnownChipsets[i].device == id) {
return NVKnownChipsets[i].name;
}
}
return NVKnownChipsets[0].name;
}
static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)
{
intfd;
intsize;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {
return 0;
}
size = file_size(fd);
if (size > bufsize) {
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);
size = bufsize;
}
size = read(fd, (char *)buf, size);
close(fd);
return size > 0 ? size : 0;
}
static int devprop_add_nvidia_template(struct DevPropDevice *device)
{
chartmp[16];
if(!device)
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_name_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_name_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, nvidia_device_type))
return 0;
// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!
// len = sprintf(tmp, "Slot-%x", devices_number);
sprintf(tmp, "Slot-%x",devices_number);
devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));
devices_number++;
return 1;
}
int hex2bin(const char *hex, uint8_t *bin, int len)
{
char*p;
inti;
charbuf[3];
if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {
printf("[ERROR] bin2hex input error\n");
return -1;
}
buf[2] = '\0';
p = (char *) hex;
for (i=0; i<len; i++) {
if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {
printf("[ERROR] bin2hex '%s' syntax error\n", hex);
return -2;
}
buf[0] = *p++;
buf[1] = *p++;
bin[i] = (unsigned char) strtoul(buf, NULL, 16);
}
return 0;
}
unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)
{
unsigned long long vram_size = 0;
if (nvCardType < NV_ARCH_50) {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
}
else if (nvCardType < NV_ARCH_C0) {
vram_size = REG32(NV04_PFB_FIFO_DATA);
vram_size |= (vram_size & 0xff) << 32;
vram_size &= 0xffffffff00ll;
}
else { // >= NV_ARCH_C0
vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;
vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);
}
return vram_size;
}
bool setup_nvidia_devprop(pci_dt_t *nvda_dev)
{
struct DevPropDevice*device;
char*devicepath;
option_rom_pci_header_t*rom_pci_header;
volatile uint8_t*regs;
uint8_t*rom;
uint8_t*nvRom;
uint8_tnvCardType;
unsigned long longvideoRam;
uint32_tnvBiosOveride;
uint32_tbar[7];
uint32_tboot_display;
intnvPatch;
intlen;
charbiosVersion[32];
charnvFilename[32];
charkNVCAP[12];
char*model;
const char*value;
booldoit;
devicepath = get_pci_dev_path(nvda_dev);
bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );
regs = (uint8_t *) (bar[0] & ~0x0f);
// get card type
nvCardType = (REG32(0) >> 20) & 0x1ff;
// Amount of VRAM in kilobytes
videoRam = mem_detect(regs, nvCardType, nvda_dev);
model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);
verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",
model, (uint32_t)(videoRam / 1024 / 1024),
(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,
devicepath);
rom = malloc(NVIDIA_ROM_SIZE);
sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id);
if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit) {
verbose("Looking for nvidia video bios file %s\n", nvFilename);
nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);
if (nvBiosOveride > 0) {
verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);
DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);
} else {
printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);
return false;
}
} else {
// Otherwise read bios from card
nvBiosOveride = 0;
// TODO: we should really check for the signature before copying the rom, i think.
// PRAMIN first
nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];
bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
// PROM next
// Enable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;
nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];
bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);
// disable PROM access
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
// 0xC0000 last
bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);
// Valid Signature ?
if (rom[0] != 0x55 && rom[1] != 0xaa) {
printf("ERROR: Unable to locate nVidia Video BIOS\n");
return false;
} else {
DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
} else {
DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
} else {
DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
}
}
if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {
printf("ERROR: nVidia ROM Patching Failed!\n");
//return false;
}
rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);
// check for 'PCIR' sig
if (rom_pci_header->signature == 0x50434952) {
if (rom_pci_header->device_id != nvda_dev->device_id) {
// Get Model from the OpROM
model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);
} else {
printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);
}
}
if (!string) {
string = devprop_create_string();
}
device = devprop_add_device(string, devicepath);
/* FIXME: for primary graphics card only */
boot_display = 1;
devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
if(nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {
uint8_t built_in = 0x01;
devprop_add_value(device, "@0,built-in", &built_in, 1);
}
// get bios version
const int MAX_BIOS_VERSION_LENGTH = 32;
char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);
memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);
int i, version_start;
int crlf_count = 0;
// only search the first 384 bytes
for(i = 0; i < 0x180; i++) {
if(rom[i] == 0x0D && rom[i+1] == 0x0A) {
crlf_count++;
// second 0x0D0A was found, extract bios version
if(crlf_count == 2) {
if(rom[i-1] == 0x20) i--; // strip last " "
for(version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--) {
// find start
if(rom[version_start] == 0x00) {
version_start++;
// strip "Version "
if(strncmp((const char*)rom+version_start, "Version ", 8) == 0) {
version_start += 8;
}
strncpy(version_str, (const char*)rom+version_start, i-version_start);
break;
}
}
break;
}
}
}
sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);
sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);
if (getValueForKey(kNVCAP, &value, &len, &bootInfo->bootConfig) && len == NVCAP_LEN * 2) {
uint8_tnew_NVCAP[NVCAP_LEN];
if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) {
verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);
memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);
}
}
#if DEBUG_NVCAP
printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",
default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],
default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],
default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],
default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],
default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);
#endif
devprop_add_nvidia_template(device);
devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);
devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);
devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);
if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit) {
devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));
}
stringdata = malloc(sizeof(uint8_t) * string->length);
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
branches/azimutz/Chazi/i386/modules/NVIDIAGraphicsEnabler/Makefile
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MODULE_NAME = NVIDIAGraphicsEnabler
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = _$(MODULE_NAME)_start
MODULE_DEPENDENCIES =
DIR = NVIDIAGraphicsEnabler
MODULE_OBJS = nvidia.o NVIDIAGraphicsEnabler.o
OPTIM = -Os -Oz
DEBUG = -DNOTHING
#DEBUG = -DDEBUG_HELLO_WORLD=1
CFLAGS= $(RC_CFLAGS) $(OPTIM) $(MORECPP) -arch i386 -g -Wmost \
-D__ARCHITECTURE__=\"i386\" -DSAIO_INTERNAL_USER \
-DRCZ_COMPRESSED_FILE_SUPPORT $(DEBUG) \
-fno-builtin $(OMIT_FRAME_POINTER_CFLAG) \
-mpreferred-stack-boundary=2 -fno-align-functions -fno-stack-protector \
-march=pentium4 -msse2 -mfpmath=sse -msoft-float -fno-common
DEFINES=
CONFIG = hd
INC = -I. -I.. -I$(SYMROOT) -I$(UTILDIR) -I$(LIBSADIR) -I$(LIBSAIODIR) -I$(BOOT2DIR)
LIBS=
VPATH = $(OBJROOT):$(SYMROOT)
SFILES =
CFILES =
HFILES =
EXPORTED_HFILES =
INSTALLED_HFILES =
OTHERFILES = Makefile
ALLSRC = $(SFILES) $(CFILES) \
$(HFILES) $(OTHERFILES)
DIRS_NEEDED = $(OBJROOT) $(SYMROOT)
all embedtheme optionrom: dylib
include ../MakeInc.dir
branches/azimutz/Chazi/i386/modules/IntelGraphicsEnabler/gma.c
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/**
Original patch by nawcom
http://forum.voodooprojects.org/index.php/topic,1029.msg4427.html#msg4427
**/
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#include "device_inject.h"
#include "gma.h"
#ifndef DEBUG_GMA
#define DEBUG_GMA 0
#endif
#if DEBUG_GMA
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
uint8_t GMAX3100_vals[22][4] = {
{ 0x01,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x08 },
{ 0x64,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x08 },
{ 0x01,0x00,0x00,0x00 },
{ 0x20,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x20,0x03,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x08,0x52,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x01,0x00,0x00,0x00 },
{ 0x3B,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00 }
};
uint8_t reg_TRUE[] = { 0x01 ,0x00 ,0x00 ,0x00 };
uint8_t reg_FALSE[] = { 0x00,0x00,0x00,0x00 };
static struct gma_gpu_t KnownGPUS[] = {
{ 0x00000000, "Unknown" },
{ 0x808627A2, "Mobile GMA950" },
{ 0x808627AE, "Mobile GMA950" },
{ 0x808627A6, "Mobile GMA950" },
{ 0x80862772, "Desktop GMA950" }, //Azi: never worked with mine.
{ 0x80862776, "Desktop GMA950" },
{ 0x80862A02, "GMAX3100" },
{ 0x80862A03, "GMAX3100" },
{ 0x80862A12, "GMAX3100" },
{ 0x80862A13, "GMAX3100" },
};
char *get_gma_model(uint32_t id) {
int i=0;
for(i = 0; i < (sizeof(KnownGPUS) / sizeof(KnownGPUS[0])); i++) {
if(KnownGPUS[i].device == id)
return KnownGPUS[i].name;
}
return KnownGPUS[0].name;
}
bool setup_gma_devprop(pci_dt_t *gma_dev)
{
//intlen;
char *devicepath;
volatile uint8_t *regs;
uint32_t bar[7];
char *model;
uint8_t BuiltIn = 0x00;
uint8_t ClassFix[4] = { 0x00, 0x00, 0x03, 0x00 };
devicepath = get_pci_dev_path(gma_dev);
bar[0] = pci_config_read32(gma_dev->dev.addr, 0x10);
regs = (uint8_t *) (bar[0] & ~0x0f);
model = get_gma_model((gma_dev->vendor_id << 16) | gma_dev->device_id);
verbose("Intel %s [%04x:%04x] :: %s\n",
model, gma_dev->vendor_id, gma_dev->device_id, devicepath);
if (!string)
string = devprop_create_string();
struct DevPropDevice *device = malloc(sizeof(struct DevPropDevice));
device = devprop_add_device(string, devicepath);
if(!device)
{
printf("Failed initializing dev-prop string dev-entry, press any key...\n");
getc();
return false;
}
devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1));
devprop_add_value(device, "device_type", (uint8_t*)"display", 8);
if (model == (char *)"Mobile GMA950") {
devprop_add_value(device, "AAPL,HasPanel", reg_TRUE, 4);
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
} else if (model == (char *)"Desktop GMA950") {
BuiltIn = 0x01;
devprop_add_value(device, "built-in", &BuiltIn, 1);
} else if (model == (char *)"GMAX3100") {
devprop_add_value(device, "AAPL,HasPanel",GMAX3100_vals[0], 4);
devprop_add_value(device, "AAPL,SelfRefreshSupported",GMAX3100_vals[1], 4);
devprop_add_value(device, "AAPL,aux-power-connected",GMAX3100_vals[2], 4);
devprop_add_value(device, "AAPL,backlight-control",GMAX3100_vals[3], 4);
devprop_add_value(device, "AAPL00,blackscreen-preferences",GMAX3100_vals[4], 4);
devprop_add_value(device, "AAPL01,BacklightIntensity",GMAX3100_vals[5], 4);
devprop_add_value(device, "AAPL01,blackscreen-preferences",GMAX3100_vals[6], 4);
devprop_add_value(device, "AAPL01,DataJustify",GMAX3100_vals[7], 4);
devprop_add_value(device, "AAPL01,Depth",GMAX3100_vals[8], 4);
devprop_add_value(device, "AAPL01,Dither",GMAX3100_vals[9], 4);
devprop_add_value(device, "AAPL01,DualLink",GMAX3100_vals[10], 4);
devprop_add_value(device, "AAPL01,Height",GMAX3100_vals[11], 4);
devprop_add_value(device, "AAPL01,Interlace",GMAX3100_vals[12], 4);
devprop_add_value(device, "AAPL01,Inverter",GMAX3100_vals[13], 4);
devprop_add_value(device, "AAPL01,InverterCurrent",GMAX3100_vals[14], 4);
devprop_add_value(device, "AAPL01,InverterCurrency",GMAX3100_vals[15], 4);
devprop_add_value(device, "AAPL01,LinkFormat",GMAX3100_vals[16], 4);
devprop_add_value(device, "AAPL01,LinkType",GMAX3100_vals[17], 4);
devprop_add_value(device, "AAPL01,Pipe",GMAX3100_vals[18], 4);
devprop_add_value(device, "AAPL01,PixelFormat",GMAX3100_vals[19], 4);
devprop_add_value(device, "AAPL01,Refresh",GMAX3100_vals[20], 4);
devprop_add_value(device, "AAPL01,Stretch",GMAX3100_vals[21], 4);
}
stringdata = malloc(sizeof(uint8_t) * string->length);
if(!stringdata)
{
printf("no stringdata press a key...\n");
getc();
return false;
}
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
branches/azimutz/Chazi/i386/modules/IntelGraphicsEnabler/IntelGraphicsEnabler.c
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/*
* IntelGraphicsEnabler Module ---
* Enables "some" Intel cards to be used out of the box ?? in OS X.
* This was converted from ... // AutoResolution reminder ---
*
*/
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "gma.h"
#include "modules.h"
#define kGraphicsEnablerKey"GraphicsEnabler"
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4);
void IntelGraphicsEnabler_start()
{
register_hook_callback("PCIDevice", &GraphicsEnabler_hook);
}
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4)
{
pci_dt_t* current = arg1;
if (current->class_id != PCI_CLASS_DISPLAY_VGA) return;
char *devicepath = get_pci_dev_path(current);
bool do_gfx_devprop = true;
getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->bootConfig);
//Azi: check "fail" code...
if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_INTEL))
{
verbose("Intel VGA Controller [%04x:%04x] :: %s \n",
current->vendor_id, current->device_id, devicepath);
setup_gma_devprop(current);
}
else
verbose("Not a Intel VGA Controller.\n"); // ---
}
branches/azimutz/Chazi/i386/modules/IntelGraphicsEnabler/gma.h
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#ifndef __LIBSAIO_GMA_H
#define __LIBSAIO_GMA_H
bool setup_gma_devprop(pci_dt_t *gma_dev);
struct gma_gpu_t {
unsigned device;
char *name;
};
#define REG8(reg) ((volatile uint8_t *)regs)[(reg)]
#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1]
#define REG32(reg) ((volatile uint32_t *)regs)[(reg) >> 2]
#endif /* !__LIBSAIO_GMA_H */
branches/azimutz/Chazi/i386/modules/IntelGraphicsEnabler/Readme.txt
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Module:IntelGraphicsEnabler
Description: Enables "some" Intel cards to be used out of the box ?? in OS X.
This was converted from ...
Dependencies: none
Keys: GraphicsEnabler (enabled by default)
TODO: ---
branches/azimutz/Chazi/i386/modules/IntelGraphicsEnabler/Makefile
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MODULE_NAME = IntelGraphicsEnabler
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = _$(MODULE_NAME)_start
MODULE_DEPENDENCIES =
DIR = IntelGraphicsEnabler
MODULE_OBJS = gma.o IntelGraphicsEnabler.o
OPTIM = -Os -Oz
DEBUG = -DNOTHING
#DEBUG = -DDEBUG_HELLO_WORLD=1
CFLAGS= $(RC_CFLAGS) $(OPTIM) $(MORECPP) -arch i386 -g -Wmost \
-D__ARCHITECTURE__=\"i386\" -DSAIO_INTERNAL_USER \
-DRCZ_COMPRESSED_FILE_SUPPORT $(DEBUG) \
-fno-builtin $(OMIT_FRAME_POINTER_CFLAG) \
-mpreferred-stack-boundary=2 -fno-align-functions -fno-stack-protector \
-march=pentium4 -msse2 -mfpmath=sse -msoft-float -fno-common
DEFINES=
CONFIG = hd
INC = -I. -I.. -I$(SYMROOT) -I$(UTILDIR) -I$(LIBSADIR) -I$(LIBSAIODIR) -I$(BOOT2DIR)
LIBS=
VPATH = $(OBJROOT):$(SYMROOT)
SFILES =
CFILES =
HFILES =
EXPORTED_HFILES =
INSTALLED_HFILES =
OTHERFILES = Makefile
ALLSRC = $(SFILES) $(CFILES) \
$(HFILES) $(OTHERFILES)
DIRS_NEEDED = $(OBJROOT) $(SYMROOT)
all embedtheme optionrom: dylib
include ../MakeInc.dir
branches/azimutz/Chazi/i386/modules/ATiGraphicsEnabler/pci_old.h
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/*
*
* Copyright 2008 by Islam M. Ahmed Zaid. All rights reserved.
*
*/
#ifndef __PCI_OLD_H
#define __PCI_OLD_H
typedef struct {
uint32_t:2;
uint32_treg:6;
uint32_tfunc:3;
uint32_tdev:5;
uint32_tbus:8;
uint32_t:7;
uint32_teb:1;
} pci_addr_t;
typedef union {
pci_addr_tbits;
uint32_taddr;
} pci_dev_t;
typedef struct pci_dt_t {
pci_dev_tdev;
uint16_tvendor_id;
uint16_tdevice_id;
union {
struct {
uint16_tvendor_id;
uint16_tdevice_id;
} subsys;
uint32_t subsys_id;
} subsys_id;
uint16_tclass_id;
struct pci_dt_t*parent;
struct pci_dt_t*children;
struct pci_dt_t*next;
} pci_dt_t;
#define PCIADDR(bus, dev, func)(1 << 31) | (bus << 16) | (dev << 11) | (func << 8)
#define PCI_ADDR_REG0xcf8
#define PCI_DATA_REG0xcfc
extern pci_dt_t*root_pci_dev;
extern uint8_tpci_config_read8(uint32_t, uint8_t);
extern uint16_tpci_config_read16(uint32_t, uint8_t);
extern uint32_tpci_config_read32(uint32_t, uint8_t);
extern voidpci_config_write8(uint32_t, uint8_t, uint8_t);
extern voidpci_config_write16(uint32_t, uint8_t, uint16_t);
extern voidpci_config_write32(uint32_t, uint8_t, uint32_t);
extern char*get_pci_dev_path(pci_dt_t *);
extern voidbuild_pci_dt(void);
extern voiddump_pci_dt(pci_dt_t *);
//-----------------------------------------------------------------------------
// added by iNDi
struct pci_rom_pci_header_t {
uint32_tsignature;// 0x50434952 'PCIR'
uint16_tvendor;
uint16_tdevice;
uint16_tproduct;
uint16_tlength;
uint8_trevision;// 0 = PCI 2.1
uint8_tclass[3];
uint16_trom_size;
uint16_tcode_revision;
uint8_tcode_type;// 0 = x86
uint8_tlast_image;// 0x80
uint16_treserverd;
};
struct pci_rom_pnp_header_t {
uint32_tsignature;// 0x24506E50 '$PnP'
uint8_trevision;// 1
uint8_tlength;//
uint16_toffset;
uint8_tchecksum;
uint32_tidentifier;
uint16_tmanufacturer;
uint16_tproduct;
uint8_tclass[3];
uint8_tindicators;
uint16_tboot_vector;
uint16_tdisconnect_vector;
uint16_tbootstrap_vector;
uint16_treserved;
uint16_tresource_vector;
};
struct pci_rom_bios_t {
uint16_tsignature;// 0x55AA
uint8_tsize;// Multiples of 512
uint8_tchecksum;// 0x00
uint16_tpci_header;
uint16_tpnp_header;
};
/*
* Under PCI, each device has 256 bytes of configuration address space,
* of which the first 64 bytes are standardized as follows:
*/
#define PCI_VENDOR_ID0x00/* 16 bits */
#define PCI_DEVICE_ID0x02/* 16 bits */
#define PCI_COMMAND0x04/* 16 bits */
#define PCI_COMMAND_IO0x1/* Enable response in I/O space */
#define PCI_COMMAND_MEMORY0x2/* Enable response in Memory space */
#define PCI_COMMAND_MASTER0x4/* Enable bus mastering */
#define PCI_COMMAND_SPECIAL0x8/* Enable response to special cycles */
#define PCI_COMMAND_INVALIDATE0x10/* Use memory write and invalidate */
#define PCI_COMMAND_VGA_PALETTE0x20/* Enable palette snooping */
#define PCI_COMMAND_PARITY0x40/* Enable parity checking */
#define PCI_COMMAND_WAIT0x80/* Enable address/data stepping */
#define PCI_COMMAND_SERR0x100/* Enable SERR */
#define PCI_COMMAND_FAST_BACK0x200/* Enable back-to-back writes */
#define PCI_COMMAND_DISABLE_INTx0x400/* PCIE: Disable INTx interrupts */
#define PCI_STATUS0x06/* 16 bits */
#define PCI_STATUS_INTx0x08/* PCIE: INTx interrupt pending */
#define PCI_STATUS_CAP_LIST0x10/* Support Capability List */
#define PCI_STATUS_66MHZ0x20/* Support 66 Mhz PCI 2.1 bus */
#define PCI_STATUS_UDF0x40/* Support User Definable Features [obsolete] */
#define PCI_STATUS_FAST_BACK0x80/* Accept fast-back to back */
#define PCI_STATUS_PARITY0x100/* Detected parity error */
#define PCI_STATUS_DEVSEL_MASK0x600/* DEVSEL timing */
#define PCI_STATUS_DEVSEL_FAST0x000
#define PCI_STATUS_DEVSEL_MEDIUM0x200
#define PCI_STATUS_DEVSEL_SLOW0x400
#define PCI_STATUS_SIG_TARGET_ABORT 0x800/* Set on target abort */
#define PCI_STATUS_REC_TARGET_ABORT 0x1000/* Master ack of " */
#define PCI_STATUS_REC_MASTER_ABORT 0x2000/* Set on master abort */
#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000/* Set when we drive SERR */
#define PCI_STATUS_DETECTED_PARITY0x8000/* Set on parity error */
#define PCI_CLASS_REVISION0x08/* High 24 bits are class, low 8 revision */
#define PCI_REVISION_ID0x08 /* Revision ID */
#define PCI_CLASS_PROG0x09 /* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE0x0a /* Device class */
#define PCI_CACHE_LINE_SIZE0x0c/* 8 bits */
#define PCI_LATENCY_TIMER0x0d/* 8 bits */
#define PCI_HEADER_TYPE0x0e/* 8 bits */
#define PCI_HEADER_TYPE_NORMAL0
#define PCI_HEADER_TYPE_BRIDGE1
#define PCI_HEADER_TYPE_CARDBUS2
#define PCI_BIST0x0f/* 8 bits */
#define PCI_BIST_CODE_MASK0x0f/* Return result */
#define PCI_BIST_START0x40/* 1 to start BIST, 2 secs or less */
#define PCI_BIST_CAPABLE0x80/* 1 if BIST capable */
/*
* Base addresses specify locations in memory or I/O space.
* Decoded size can be determined by writing a value of
* 0xffffffff to the register, and reading it back. Only
* 1 bits are decoded.
*/
#define PCI_BASE_ADDRESS_00x10/* 32 bits */
#define PCI_BASE_ADDRESS_10x14/* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_20x18/* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_30x1c/* 32 bits */
#define PCI_BASE_ADDRESS_40x20/* 32 bits */
#define PCI_BASE_ADDRESS_50x24/* 32 bits */
#define PCI_BASE_ADDRESS_SPACE0x01/* 0 = memory, 1 = I/O */
#define PCI_BASE_ADDRESS_SPACE_IO0x01
#define PCI_BASE_ADDRESS_SPACE_MEMORY0x00
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK0x06
#define PCI_BASE_ADDRESS_MEM_TYPE_320x00/* 32 bit address */
#define PCI_BASE_ADDRESS_MEM_TYPE_1M0x02/* Below 1M [obsolete] */
#define PCI_BASE_ADDRESS_MEM_TYPE_640x04/* 64 bit address */
#define PCI_BASE_ADDRESS_MEM_PREFETCH0x08/* prefetchable? */
#define PCI_BASE_ADDRESS_MEM_MASK(~(pciaddr_t)0x0f)
#define PCI_BASE_ADDRESS_IO_MASK(~(pciaddr_t)0x03)
/* bit 1 is reserved if address_space = 1 */
/* Header type 0 (normal devices) */
#define PCI_CARDBUS_CIS0x28
#define PCI_SUBSYSTEM_VENDOR_ID0x2c
#define PCI_SUBSYSTEM_ID0x2e
#define PCI_ROM_ADDRESS0x30/* Bits 31..11 are address, 10..1 reserved */
#define PCI_ROM_ADDRESS_ENABLE0x01
#define PCI_ROM_ADDRESS_MASK(~(pciaddr_t)0x7ff)
#define PCI_CAPABILITY_LIST0x34/* Offset of first capability list entry */
/* 0x35-0x3b are reserved */
#define PCI_INTERRUPT_LINE0x3c/* 8 bits */
#define PCI_INTERRUPT_PIN0x3d/* 8 bits */
#define PCI_MIN_GNT0x3e/* 8 bits */
#define PCI_MAX_LAT0x3f/* 8 bits */
/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_PRIMARY_BUS0x18/* Primary bus number */
#define PCI_SECONDARY_BUS0x19/* Secondary bus number */
#define PCI_SUBORDINATE_BUS0x1a/* Highest bus number behind the bridge */
#define PCI_SEC_LATENCY_TIMER0x1b/* Latency timer for secondary interface */
#define PCI_IO_BASE0x1c/* I/O range behind the bridge */
#define PCI_IO_LIMIT0x1d
#define PCI_IO_RANGE_TYPE_MASK0x0f/* I/O bridging type */
#define PCI_IO_RANGE_TYPE_160x00
#define PCI_IO_RANGE_TYPE_320x01
#define PCI_IO_RANGE_MASK~0x0f
#define PCI_SEC_STATUS0x1e/* Secondary status register */
#define PCI_MEMORY_BASE0x20/* Memory range behind */
#define PCI_MEMORY_LIMIT0x22
#define PCI_MEMORY_RANGE_TYPE_MASK0x0f
#define PCI_MEMORY_RANGE_MASK~0x0f
#define PCI_PREF_MEMORY_BASE0x24/* Prefetchable memory range behind */
#define PCI_PREF_MEMORY_LIMIT0x26
#define PCI_PREF_RANGE_TYPE_MASK0x0f
#define PCI_PREF_RANGE_TYPE_320x00
#define PCI_PREF_RANGE_TYPE_640x01
#define PCI_PREF_RANGE_MASK~0x0f
#define PCI_PREF_BASE_UPPER320x28/* Upper half of prefetchable memory range */
#define PCI_PREF_LIMIT_UPPER320x2c
#define PCI_IO_BASE_UPPER160x30/* Upper half of I/O addresses */
#define PCI_IO_LIMIT_UPPER160x32
/* 0x34 same as for htype 0 */
/* 0x35-0x3b is reserved */
#define PCI_ROM_ADDRESS10x38/* Same as PCI_ROM_ADDRESS, but for htype 1 */
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_BRIDGE_CONTROL0x3e
#define PCI_BRIDGE_CTL_PARITY0x01/* Enable parity detection on secondary interface */
#define PCI_BRIDGE_CTL_SERR0x02/* The same for SERR forwarding */
#define PCI_BRIDGE_CTL_NO_ISA0x04/* Disable bridging of ISA ports */
#define PCI_BRIDGE_CTL_VGA0x08/* Forward VGA addresses */
#define PCI_BRIDGE_CTL_MASTER_ABORT0x20/* Report master aborts */
#define PCI_BRIDGE_CTL_BUS_RESET0x40/* Secondary bus reset */
#define PCI_BRIDGE_CTL_FAST_BACK0x80/* Fast Back2Back enabled on secondary interface */
#define PCI_BRIDGE_CTL_PRI_DISCARD_TIMER 0x100/* PCI-X? */
#define PCI_BRIDGE_CTL_SEC_DISCARD_TIMER 0x200/* PCI-X? */
#define PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS 0x400/* PCI-X? */
#define PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800/* PCI-X? */
/* Header type 2 (CardBus bridges) */
/* 0x14-0x15 reserved */
#define PCI_CB_SEC_STATUS0x16/* Secondary status */
#define PCI_CB_PRIMARY_BUS0x18/* PCI bus number */
#define PCI_CB_CARD_BUS0x19/* CardBus bus number */
#define PCI_CB_SUBORDINATE_BUS0x1a/* Subordinate bus number */
#define PCI_CB_LATENCY_TIMER0x1b/* CardBus latency timer */
#define PCI_CB_MEMORY_BASE_00x1c
#define PCI_CB_MEMORY_LIMIT_00x20
#define PCI_CB_MEMORY_BASE_10x24
#define PCI_CB_MEMORY_LIMIT_10x28
#define PCI_CB_IO_BASE_00x2c
#define PCI_CB_IO_BASE_0_HI0x2e
#define PCI_CB_IO_LIMIT_00x30
#define PCI_CB_IO_LIMIT_0_HI0x32
#define PCI_CB_IO_BASE_10x34
#define PCI_CB_IO_BASE_1_HI0x36
#define PCI_CB_IO_LIMIT_10x38
#define PCI_CB_IO_LIMIT_1_HI0x3a
#define PCI_CB_IO_RANGE_MASK~0x03
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_CB_BRIDGE_CONTROL0x3e
#define PCI_CB_BRIDGE_CTL_PARITY0x01/* Similar to standard bridge control register */
#define PCI_CB_BRIDGE_CTL_SERR0x02
#define PCI_CB_BRIDGE_CTL_ISA0x04
#define PCI_CB_BRIDGE_CTL_VGA0x08
#define PCI_CB_BRIDGE_CTL_MASTER_ABORT0x20
#define PCI_CB_BRIDGE_CTL_CB_RESET0x40/* CardBus reset */
#define PCI_CB_BRIDGE_CTL_16BIT_INT0x80/* Enable interrupt for 16-bit cards */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100/* Prefetch enable for both memory regions */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
#define PCI_CB_BRIDGE_CTL_POST_WRITES0x400
#define PCI_CB_SUBSYSTEM_VENDOR_ID0x40
#define PCI_CB_SUBSYSTEM_ID0x42
#define PCI_CB_LEGACY_MODE_BASE0x44/* 16-bit PC Card legacy mode base address (ExCa) */
/* 0x48-0x7f reserved */
/* Capability lists */
#define PCI_CAP_LIST_ID0/* Capability ID */
#define PCI_CAP_ID_PM0x01/* Power Management */
#define PCI_CAP_ID_AGP0x02/* Accelerated Graphics Port */
#define PCI_CAP_ID_VPD0x03/* Vital Product Data */
#define PCI_CAP_ID_SLOTID0x04/* Slot Identification */
#define PCI_CAP_ID_MSI0x05/* Message Signaled Interrupts */
#define PCI_CAP_ID_CHSWP0x06/* CompactPCI HotSwap */
#define PCI_CAP_ID_PCIX0x07/* PCI-X */
#define PCI_CAP_ID_HT0x08/* HyperTransport */
#define PCI_CAP_ID_VNDR0x09/* Vendor specific */
#define PCI_CAP_ID_DBG0x0A/* Debug port */
#define PCI_CAP_ID_CCRC0x0B/* CompactPCI Central Resource Control */
#define PCI_CAP_ID_HOTPLUG0x0C/* PCI hot-plug */
#define PCI_CAP_ID_SSVID0x0D/* Bridge subsystem vendor/device ID */
#define PCI_CAP_ID_AGP30x0E/* AGP 8x */
#define PCI_CAP_ID_SECURE0x0F/* Secure device (?) */
#define PCI_CAP_ID_EXP0x10/* PCI Express */
#define PCI_CAP_ID_MSIX0x11/* MSI-X */
#define PCI_CAP_ID_SATA0x12/* Serial-ATA HBA */
#define PCI_CAP_ID_AF0x13/* Advanced features of PCI devices integrated in PCIe root cplx */
#define PCI_CAP_LIST_NEXT1/* Next capability in the list */
#define PCI_CAP_FLAGS2/* Capability defined flags (16 bits) */
#define PCI_CAP_SIZEOF4
/* Capabilities residing in the PCI Express extended configuration space */
#define PCI_EXT_CAP_ID_AER0x01/* Advanced Error Reporting */
#define PCI_EXT_CAP_ID_VC0x02/* Virtual Channel */
#define PCI_EXT_CAP_ID_DSN0x03/* Device Serial Number */
#define PCI_EXT_CAP_ID_PB0x04/* Power Budgeting */
#define PCI_EXT_CAP_ID_RCLINK0x05/* Root Complex Link Declaration */
#define PCI_EXT_CAP_ID_RCILINK0x06/* Root Complex Internal Link Declaration */
#define PCI_EXT_CAP_ID_RCECOLL0x07/* Root Complex Event Collector */
#define PCI_EXT_CAP_ID_MFVC0x08/* Multi-Function Virtual Channel */
#define PCI_EXT_CAP_ID_RBCB0x0a/* Root Bridge Control Block */
#define PCI_EXT_CAP_ID_VNDR0x0b/* Vendor specific */
#define PCI_EXT_CAP_ID_ACS0x0d/* Access Controls */
#define PCI_EXT_CAP_ID_ARI0x0e/* Alternative Routing-ID Interpretation */
#define PCI_EXT_CAP_ID_ATS0x0f/* Address Translation Service */
#define PCI_EXT_CAP_ID_SRIOV0x10/* Single Root I/O Virtualization */
/* Power Management Registers */
#define PCI_PM_CAP_VER_MASK0x0007/* Version (2=PM1.1) */
#define PCI_PM_CAP_PME_CLOCK0x0008/* Clock required for PME generation */
#define PCI_PM_CAP_DSI0x0020/* Device specific initialization required */
#define PCI_PM_CAP_AUX_C_MASK0x01c0/* Maximum aux current required in D3cold */
#define PCI_PM_CAP_D10x0200/* D1 power state support */
#define PCI_PM_CAP_D20x0400/* D2 power state support */
#define PCI_PM_CAP_PME_D00x0800/* PME can be asserted from D0 */
#define PCI_PM_CAP_PME_D10x1000/* PME can be asserted from D1 */
#define PCI_PM_CAP_PME_D20x2000/* PME can be asserted from D2 */
#define PCI_PM_CAP_PME_D3_HOT0x4000/* PME can be asserted from D3hot */
#define PCI_PM_CAP_PME_D3_COLD0x8000/* PME can be asserted from D3cold */
#define PCI_PM_CTRL4/* PM control and status register */
#define PCI_PM_CTRL_STATE_MASK0x0003/* Current power state (D0 to D3) */
#define PCI_PM_CTRL_PME_ENABLE0x0100/* PME pin enable */
#define PCI_PM_CTRL_DATA_SEL_MASK0x1e00/* PM table data index */
#define PCI_PM_CTRL_DATA_SCALE_MASK0x6000/* PM table data scaling factor */
#define PCI_PM_CTRL_PME_STATUS0x8000/* PME pin status */
#define PCI_PM_PPB_EXTENSIONS6/* PPB support extensions */
#define PCI_PM_PPB_B2_B30x40/* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */
#define PCI_PM_BPCC_ENABLE0x80/* Secondary bus is power managed */
#define PCI_PM_DATA_REGISTER7/* PM table contents read here */
#define PCI_PM_SIZEOF8
/* AGP registers */
#define PCI_AGP_VERSION2/* BCD version number */
#define PCI_AGP_RFU3/* Rest of capability flags */
#define PCI_AGP_STATUS4/* Status register */
#define PCI_AGP_STATUS_RQ_MASK0xff000000/* Maximum number of requests - 1 */
#define PCI_AGP_STATUS_ISOCH0x10000/* Isochronous transactions supported */
#define PCI_AGP_STATUS_ARQSZ_MASK0xe000/* log2(optimum async req size in bytes) - 4 */
#define PCI_AGP_STATUS_CAL_MASK0x1c00/* Calibration cycle timing */
#define PCI_AGP_STATUS_SBA0x0200/* Sideband addressing supported */
#define PCI_AGP_STATUS_ITA_COH0x0100/* In-aperture accesses always coherent */
#define PCI_AGP_STATUS_GART640x0080/* 64-bit GART entries supported */
#define PCI_AGP_STATUS_HTRANS0x0040/* If 0, core logic can xlate host CPU accesses thru aperture */
#define PCI_AGP_STATUS_64BIT0x0020/* 64-bit addressing cycles supported */
#define PCI_AGP_STATUS_FW0x0010/* Fast write transfers supported */
#define PCI_AGP_STATUS_AGP30x0008/* AGP3 mode supported */
#define PCI_AGP_STATUS_RATE40x0004/* 4x transfer rate supported (RFU in AGP3 mode) */
#define PCI_AGP_STATUS_RATE20x0002/* 2x transfer rate supported (8x in AGP3 mode) */
#define PCI_AGP_STATUS_RATE10x0001/* 1x transfer rate supported (4x in AGP3 mode) */
#define PCI_AGP_COMMAND8/* Control register */
#define PCI_AGP_COMMAND_RQ_MASK0xff000000 /* Master: Maximum number of requests */
#define PCI_AGP_COMMAND_ARQSZ_MASK0xe000/* log2(optimum async req size in bytes) - 4 */
#define PCI_AGP_COMMAND_CAL_MASK0x1c00/* Calibration cycle timing */
#define PCI_AGP_COMMAND_SBA0x0200/* Sideband addressing enabled */
#define PCI_AGP_COMMAND_AGP0x0100/* Allow processing of AGP transactions */
#define PCI_AGP_COMMAND_GART640x0080/* 64-bit GART entries enabled */
#define PCI_AGP_COMMAND_64BIT0x0020/* Allow generation of 64-bit addr cycles */
#define PCI_AGP_COMMAND_FW0x0010/* Enable FW transfers */
#define PCI_AGP_COMMAND_RATE40x0004/* Use 4x rate (RFU in AGP3 mode) */
#define PCI_AGP_COMMAND_RATE20x0002/* Use 2x rate (8x in AGP3 mode) */
#define PCI_AGP_COMMAND_RATE10x0001/* Use 1x rate (4x in AGP3 mode) */
#define PCI_AGP_SIZEOF12
/* Vital Product Data */
#define PCI_VPD_ADDR2/* Address to access (15 bits!) */
#define PCI_VPD_ADDR_MASK0x7fff/* Address mask */
#define PCI_VPD_ADDR_F0x8000/* Write 0, 1 indicates completion */
#define PCI_VPD_DATA4/* 32-bits of data returned here */
/* Slot Identification */
#define PCI_SID_ESR2/* Expansion Slot Register */
#define PCI_SID_ESR_NSLOTS0x1f/* Number of expansion slots available */
#define PCI_SID_ESR_FIC0x20/* First In Chassis Flag */
#define PCI_SID_CHASSIS_NR3/* Chassis Number */
/* Message Signaled Interrupts registers */
#define PCI_MSI_FLAGS2/* Various flags */
#define PCI_MSI_FLAGS_MASK_BIT0x100/* interrupt masking & reporting supported */
#define PCI_MSI_FLAGS_64BIT0x080/* 64-bit addresses allowed */
#define PCI_MSI_FLAGS_QSIZE0x070/* Message queue size configured */
#define PCI_MSI_FLAGS_QMASK0x00e/* Maximum queue size available */
#define PCI_MSI_FLAGS_ENABLE0x001/* MSI feature enabled */
#define PCI_MSI_RFU3/* Rest of capability flags */
#define PCI_MSI_ADDRESS_LO4/* Lower 32 bits */
#define PCI_MSI_ADDRESS_HI8/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
#define PCI_MSI_DATA_328/* 16 bits of data for 32-bit devices */
#define PCI_MSI_DATA_6412/* 16 bits of data for 64-bit devices */
#define PCI_MSI_MASK_BIT_3212/* per-vector masking for 32-bit devices */
#define PCI_MSI_MASK_BIT_6416/* per-vector masking for 64-bit devices */
#define PCI_MSI_PENDING_3216/* per-vector interrupt pending for 32-bit devices */
#define PCI_MSI_PENDING_6420/* per-vector interrupt pending for 64-bit devices */
/* PCI-X */
#define PCI_PCIX_COMMAND 2 /* Command register offset */
#define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */
#define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
#define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */
#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
#define PCI_PCIX_COMMAND_RESERVED 0xf80
#define PCI_PCIX_STATUS 4 /* Status register offset */
#define PCI_PCIX_STATUS_FUNCTION 0x00000007
#define PCI_PCIX_STATUS_DEVICE 0x000000f8
#define PCI_PCIX_STATUS_BUS 0x0000ff00
#define PCI_PCIX_STATUS_64BIT 0x00010000
#define PCI_PCIX_STATUS_133MHZ 0x00020000
#define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
#define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
#define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */
#define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
#define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000
#define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000
#define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */
#define PCI_PCIX_STATUS_266MHZ0x40000000 /* 266 MHz capable */
#define PCI_PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
#define PCI_PCIX_SIZEOF4
/* PCI-X Bridges */
#define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */
#define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001
#define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002
#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */
#define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */
#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */
#define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020
#define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0
#define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00
#define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */
#define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007
#define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8
#define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00
#define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000
#define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000
#define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
#define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
#define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */
#define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000
#define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000
#define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */
#define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */
#define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff
#define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000
#define PCI_PCIX_BRIDGE_SIZEOF 12
/* PCI Express */
#define PCI_EXP_FLAGS0x2/* Capabilities register */
#define PCI_EXP_FLAGS_VERS0x000f/* Capability version */
#define PCI_EXP_FLAGS_TYPE0x00f0/* Device/Port type */
#define PCI_EXP_TYPE_ENDPOINT0x0/* Express Endpoint */
#define PCI_EXP_TYPE_LEG_END0x1/* Legacy Endpoint */
#define PCI_EXP_TYPE_ROOT_PORT 0x4/* Root Port */
#define PCI_EXP_TYPE_UPSTREAM0x5/* Upstream Port */
#define PCI_EXP_TYPE_DOWNSTREAM 0x6/* Downstream Port */
#define PCI_EXP_TYPE_PCI_BRIDGE 0x7/* PCI/PCI-X Bridge */
#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8/* PCI/PCI-X to PCIE Bridge */
#define PCI_EXP_TYPE_ROOT_INT_EP 0x9/* Root Complex Integrated Endpoint */
#define PCI_EXP_TYPE_ROOT_EC 0xa/* Root Complex Event Collector */
#define PCI_EXP_FLAGS_SLOT0x0100/* Slot implemented */
#define PCI_EXP_FLAGS_IRQ0x3e00/* Interrupt message number */
#define PCI_EXP_DEVCAP0x4/* Device capabilities */
#define PCI_EXP_DEVCAP_PAYLOAD0x07/* Max_Payload_Size */
#define PCI_EXP_DEVCAP_PHANTOM0x18/* Phantom functions */
#define PCI_EXP_DEVCAP_EXT_TAG0x20/* Extended tags */
#define PCI_EXP_DEVCAP_L0S0x1c0/* L0s Acceptable Latency */
#define PCI_EXP_DEVCAP_L10xe00/* L1 Acceptable Latency */
#define PCI_EXP_DEVCAP_ATN_BUT0x1000/* Attention Button Present */
#define PCI_EXP_DEVCAP_ATN_IND0x2000/* Attention Indicator Present */
#define PCI_EXP_DEVCAP_PWR_IND0x4000/* Power Indicator Present */
#define PCI_EXP_DEVCAP_RBE0x8000/* Role-Based Error Reporting */
#define PCI_EXP_DEVCAP_PWR_VAL0x3fc0000 /* Slot Power Limit Value */
#define PCI_EXP_DEVCAP_PWR_SCL0xc000000 /* Slot Power Limit Scale */
#define PCI_EXP_DEVCAP_FLRESET0x10000000 /* Function-Level Reset */
#define PCI_EXP_DEVCTL0x8/* Device Control */
#define PCI_EXP_DEVCTL_CERE0x0001/* Correctable Error Reporting En. */
#define PCI_EXP_DEVCTL_NFERE0x0002/* Non-Fatal Error Reporting Enable */
#define PCI_EXP_DEVCTL_FERE0x0004/* Fatal Error Reporting Enable */
#define PCI_EXP_DEVCTL_URRE0x0008/* Unsupported Request Reporting En. */
#define PCI_EXP_DEVCTL_RELAXED0x0010/* Enable Relaxed Ordering */
#define PCI_EXP_DEVCTL_PAYLOAD0x00e0/* Max_Payload_Size */
#define PCI_EXP_DEVCTL_EXT_TAG0x0100/* Extended Tag Field Enable */
#define PCI_EXP_DEVCTL_PHANTOM0x0200/* Phantom Functions Enable */
#define PCI_EXP_DEVCTL_AUX_PME0x0400/* Auxiliary Power PM Enable */
#define PCI_EXP_DEVCTL_NOSNOOP0x0800/* Enable No Snoop */
#define PCI_EXP_DEVCTL_READRQ0x7000/* Max_Read_Request_Size */
#define PCI_EXP_DEVCTL_BCRE0x8000/* Bridge Configuration Retry Enable */
#define PCI_EXP_DEVCTL_FLRESET0x8000/* Function-Level Reset [bit shared with BCRE] */
#define PCI_EXP_DEVSTA0xa/* Device Status */
#define PCI_EXP_DEVSTA_CED0x01/* Correctable Error Detected */
#define PCI_EXP_DEVSTA_NFED0x02/* Non-Fatal Error Detected */
#define PCI_EXP_DEVSTA_FED0x04/* Fatal Error Detected */
#define PCI_EXP_DEVSTA_URD0x08/* Unsupported Request Detected */
#define PCI_EXP_DEVSTA_AUXPD0x10/* AUX Power Detected */
#define PCI_EXP_DEVSTA_TRPND0x20/* Transactions Pending */
#define PCI_EXP_LNKCAP0xc/* Link Capabilities */
#define PCI_EXP_LNKCAP_SPEED0x0000f/* Maximum Link Speed */
#define PCI_EXP_LNKCAP_WIDTH0x003f0/* Maximum Link Width */
#define PCI_EXP_LNKCAP_ASPM0x00c00/* Active State Power Management */
#define PCI_EXP_LNKCAP_L0S0x07000/* L0s Acceptable Latency */
#define PCI_EXP_LNKCAP_L10x38000/* L1 Acceptable Latency */
#define PCI_EXP_LNKCAP_CLOCKPM0x40000/* Clock Power Management */
#define PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
#define PCI_EXP_LNKCAP_DLLA0x100000 /* Data Link Layer Active Reporting */
#define PCI_EXP_LNKCAP_LBNC0x200000 /* Link Bandwidth Notification Capability */
#define PCI_EXP_LNKCAP_PORT0xff000000 /* Port Number */
#define PCI_EXP_LNKCTL0x10/* Link Control */
#define PCI_EXP_LNKCTL_ASPM0x0003/* ASPM Control */
#define PCI_EXP_LNKCTL_RCB0x0008/* Read Completion Boundary */
#define PCI_EXP_LNKCTL_DISABLE0x0010/* Link Disable */
#define PCI_EXP_LNKCTL_RETRAIN0x0020/* Retrain Link */
#define PCI_EXP_LNKCTL_CLOCK0x0040/* Common Clock Configuration */
#define PCI_EXP_LNKCTL_XSYNCH0x0080/* Extended Synch */
#define PCI_EXP_LNKCTL_CLOCKPM0x0100/* Clock Power Management */
#define PCI_EXP_LNKCTL_HWAUTWD0x0200/* Hardware Autonomous Width Disable */
#define PCI_EXP_LNKCTL_BWMIE0x0400/* Bandwidth Mgmt Interrupt Enable */
#define PCI_EXP_LNKCTL_AUTBWIE0x0800/* Autonomous Bandwidth Mgmt Interrupt Enable */
#define PCI_EXP_LNKSTA0x12/* Link Status */
#define PCI_EXP_LNKSTA_SPEED0x000f/* Negotiated Link Speed */
#define PCI_EXP_LNKSTA_WIDTH0x03f0/* Negotiated Link Width */
#define PCI_EXP_LNKSTA_TR_ERR0x0400/* Training Error (obsolete) */
#define PCI_EXP_LNKSTA_TRAIN0x0800/* Link Training */
#define PCI_EXP_LNKSTA_SL_CLK0x1000/* Slot Clock Configuration */
#define PCI_EXP_LNKSTA_DL_ACT0x2000/* Data Link Layer in DL_Active State */
#define PCI_EXP_LNKSTA_BWMGMT0x4000/* Bandwidth Mgmt Status */
#define PCI_EXP_LNKSTA_AUTBW0x8000/* Autonomous Bandwidth Mgmt Status */
#define PCI_EXP_SLTCAP0x14/* Slot Capabilities */
#define PCI_EXP_SLTCAP_ATNB0x0001/* Attention Button Present */
#define PCI_EXP_SLTCAP_PWRC0x0002/* Power Controller Present */
#define PCI_EXP_SLTCAP_MRL0x0004/* MRL Sensor Present */
#define PCI_EXP_SLTCAP_ATNI0x0008/* Attention Indicator Present */
#define PCI_EXP_SLTCAP_PWRI0x0010/* Power Indicator Present */
#define PCI_EXP_SLTCAP_HPS0x0020/* Hot-Plug Surprise */
#define PCI_EXP_SLTCAP_HPC0x0040/* Hot-Plug Capable */
#define PCI_EXP_SLTCAP_PWR_VAL0x00007f80 /* Slot Power Limit Value */
#define PCI_EXP_SLTCAP_PWR_SCL0x00018000 /* Slot Power Limit Scale */
#define PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
#define PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
#define PCI_EXP_SLTCAP_PSN0xfff80000 /* Physical Slot Number */
#define PCI_EXP_SLTCTL0x18/* Slot Control */
#define PCI_EXP_SLTCTL_ATNB0x0001/* Attention Button Pressed Enable */
#define PCI_EXP_SLTCTL_PWRF0x0002/* Power Fault Detected Enable */
#define PCI_EXP_SLTCTL_MRLS0x0004/* MRL Sensor Changed Enable */
#define PCI_EXP_SLTCTL_PRSD0x0008/* Presence Detect Changed Enable */
#define PCI_EXP_SLTCTL_CMDC0x0010/* Command Completed Interrupt Enable */
#define PCI_EXP_SLTCTL_HPIE0x0020/* Hot-Plug Interrupt Enable */
#define PCI_EXP_SLTCTL_ATNI0x00c0/* Attention Indicator Control */
#define PCI_EXP_SLTCTL_PWRI0x0300/* Power Indicator Control */
#define PCI_EXP_SLTCTL_PWRC0x0400/* Power Controller Control */
#define PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
#define PCI_EXP_SLTCTL_LLCHG0x1000/* Data Link Layer State Changed Enable */
#define PCI_EXP_SLTSTA0x1a/* Slot Status */
#define PCI_EXP_SLTSTA_ATNB0x0001/* Attention Button Pressed */
#define PCI_EXP_SLTSTA_PWRF0x0002/* Power Fault Detected */
#define PCI_EXP_SLTSTA_MRLS0x0004/* MRL Sensor Changed */
#define PCI_EXP_SLTSTA_PRSD0x0008/* Presence Detect Changed */
#define PCI_EXP_SLTSTA_CMDC0x0010/* Command Completed */
#define PCI_EXP_SLTSTA_MRL_ST0x0020/* MRL Sensor State */
#define PCI_EXP_SLTSTA_PRES0x0040/* Presence Detect State */
#define PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
#define PCI_EXP_SLTSTA_LLCHG0x0100/* Data Link Layer State Changed */
#define PCI_EXP_RTCTL0x1c/* Root Control */
#define PCI_EXP_RTCTL_SECEE0x0001/* System Error on Correctable Error */
#define PCI_EXP_RTCTL_SENFEE0x0002/* System Error on Non-Fatal Error */
#define PCI_EXP_RTCTL_SEFEE0x0004/* System Error on Fatal Error */
#define PCI_EXP_RTCTL_PMEIE0x0008/* PME Interrupt Enable */
#define PCI_EXP_RTCTL_CRSVIS0x0010/* Configuration Request Retry Status Visible to SW */
#define PCI_EXP_RTCAP0x1e/* Root Capabilities */
#define PCI_EXP_RTCAP_CRSVIS0x0010/* Configuration Request Retry Status Visible to SW */
#define PCI_EXP_RTSTA0x20/* Root Status */
#define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
#define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
#define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
#define PCI_EXP_DEVCAP20x24/* Device capabilities 2 */
#define PCI_EXP_DEVCTL20x28/* Device Control */
#define PCI_EXP_DEV2_TIMEOUT_RANGE(x)((x) & 0xf) /* Completion Timeout Ranges Supported */
#define PCI_EXP_DEV2_TIMEOUT_VALUE(x)((x) & 0xf) /* Completion Timeout Value */
#define PCI_EXP_DEV2_TIMEOUT_DIS0x0010/* Completion Timeout Disable Supported */
#define PCI_EXP_DEV2_ARI0x0020/* ARI Forwarding */
#define PCI_EXP_DEVSTA20x2a/* Device Status */
#define PCI_EXP_LNKCAP20x2c/* Link Capabilities */
#define PCI_EXP_LNKCTL20x30/* Link Control */
#define PCI_EXP_LNKCTL2_SPEED(x)((x) & 0xf) /* Target Link Speed */
#define PCI_EXP_LNKCTL2_CMPLNC0x0010/* Enter Compliance */
#define PCI_EXP_LNKCTL2_SPEED_DIS0x0020/* Hardware Autonomous Speed Disable */
#define PCI_EXP_LNKCTL2_DEEMPHASIS(x)(((x) >> 6) & 1) /* Selectable De-emphasis */
#define PCI_EXP_LNKCTL2_MARGIN(x)(((x) >> 7) & 7) /* Transmit Margin */
#define PCI_EXP_LNKCTL2_MOD_CMPLNC0x0400/* Enter Modified Compliance */
#define PCI_EXP_LNKCTL2_CMPLNC_SOS0x0800/* Compliance SOS */
#define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 1) /* Compliance De-emphasis */
#define PCI_EXP_LNKSTA20x32/* Link Status */
#define PCI_EXP_LINKSTA2_DEEMPHASIS(x)((x) & 1)/* Current De-emphasis Level */
#define PCI_EXP_SLTCAP20x34/* Slot Capabilities */
#define PCI_EXP_SLTCTL20x38/* Slot Control */
#define PCI_EXP_SLTSTA20x3a/* Slot Status */
/* MSI-X */
#define PCI_MSIX_ENABLE0x8000
#define PCI_MSIX_MASK0x4000
#define PCI_MSIX_TABSIZE0x03ff
#define PCI_MSIX_TABLE4
#define PCI_MSIX_PBA8
#define PCI_MSIX_BIR0x7
/* Subsystem vendor/device ID for PCI bridges */
#define PCI_SSVID_VENDOR4
#define PCI_SSVID_DEVICE6
/* Advanced Error Reporting */
#define PCI_ERR_UNCOR_STATUS4/* Uncorrectable Error Status */
#define PCI_ERR_UNC_TRAIN0x00000001/* Undefined in PCIe rev1.1 & 2.0 spec */
#define PCI_ERR_UNC_DLP0x00000010/* Data Link Protocol */
#define PCI_ERR_UNC_SDES0x00000020/* Surprise Down Error */
#define PCI_ERR_UNC_POISON_TLP0x00001000/* Poisoned TLP */
#define PCI_ERR_UNC_FCP0x00002000/* Flow Control Protocol */
#define PCI_ERR_UNC_COMP_TIME0x00004000/* Completion Timeout */
#define PCI_ERR_UNC_COMP_ABORT0x00008000/* Completer Abort */
#define PCI_ERR_UNC_UNX_COMP0x00010000/* Unexpected Completion */
#define PCI_ERR_UNC_RX_OVER0x00020000/* Receiver Overflow */
#define PCI_ERR_UNC_MALF_TLP0x00040000/* Malformed TLP */
#define PCI_ERR_UNC_ECRC0x00080000/* ECRC Error Status */
#define PCI_ERR_UNC_UNSUP0x00100000/* Unsupported Request */
#define PCI_ERR_UNC_ACS_VIOL0x00200000/* ACS Violation */
#define PCI_ERR_UNCOR_MASK8/* Uncorrectable Error Mask */
/* Same bits as above */
#define PCI_ERR_UNCOR_SEVER12/* Uncorrectable Error Severity */
/* Same bits as above */
#define PCI_ERR_COR_STATUS16/* Correctable Error Status */
#define PCI_ERR_COR_RCVR0x00000001/* Receiver Error Status */
#define PCI_ERR_COR_BAD_TLP0x00000040/* Bad TLP Status */
#define PCI_ERR_COR_BAD_DLLP0x00000080/* Bad DLLP Status */
#define PCI_ERR_COR_REP_ROLL0x00000100/* REPLAY_NUM Rollover */
#define PCI_ERR_COR_REP_TIMER0x00001000/* Replay Timer Timeout */
#define PCI_ERR_COR_REP_ANFE0x00002000/* Advisory Non-Fatal Error */
#define PCI_ERR_COR_MASK20/* Correctable Error Mask */
/* Same bits as above */
#define PCI_ERR_CAP24/* Advanced Error Capabilities */
#define PCI_ERR_CAP_FEP(x)((x) & 31)/* First Error Pointer */
#define PCI_ERR_CAP_ECRC_GENC0x00000020/* ECRC Generation Capable */
#define PCI_ERR_CAP_ECRC_GENE0x00000040/* ECRC Generation Enable */
#define PCI_ERR_CAP_ECRC_CHKC0x00000080/* ECRC Check Capable */
#define PCI_ERR_CAP_ECRC_CHKE0x00000100/* ECRC Check Enable */
#define PCI_ERR_HEADER_LOG28/* Header Log Register (16 bytes) */
#define PCI_ERR_ROOT_COMMAND44/* Root Error Command */
#define PCI_ERR_ROOT_STATUS48
#define PCI_ERR_ROOT_COR_SRC52
#define PCI_ERR_ROOT_SRC54
/* Virtual Channel */
#define PCI_VC_PORT_REG14
#define PCI_VC_PORT_REG28
#define PCI_VC_PORT_CTRL12
#define PCI_VC_PORT_STATUS14
#define PCI_VC_RES_CAP16
#define PCI_VC_RES_CTRL20
#define PCI_VC_RES_STATUS26
/* Power Budgeting */
#define PCI_PWR_DSR4/* Data Select Register */
#define PCI_PWR_DATA8/* Data Register */
#define PCI_PWR_DATA_BASE(x)((x) & 0xff) /* Base Power */
#define PCI_PWR_DATA_SCALE(x)(((x) >> 8) & 3) /* Data Scale */
#define PCI_PWR_DATA_PM_SUB(x)(((x) >> 10) & 7) /* PM Sub State */
#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
#define PCI_PWR_DATA_TYPE(x)(((x) >> 15) & 7) /* Type */
#define PCI_PWR_DATA_RAIL(x)(((x) >> 18) & 7) /* Power Rail */
#define PCI_PWR_CAP12/* Capability */
#define PCI_PWR_CAP_BUDGET(x)((x) & 1)/* Included in system budget */
/* Access Control Services */
#define PCI_ACS_CAP0x04/* ACS Capability Register */
#define PCI_ACS_CAP_VALID0x0001/* ACS Source Validation */
#define PCI_ACS_CAP_BLOCK0x0002/* ACS Translation Blocking */
#define PCI_ACS_CAP_REQ_RED0x0004/* ACS P2P Request Redirect */
#define PCI_ACS_CAP_CMPLT_RED0x0008/* ACS P2P Completion Redirect */
#define PCI_ACS_CAP_FORWARD0x0010/* ACS Upstream Forwarding */
#define PCI_ACS_CAP_EGRESS0x0020/* ACS P2P Egress Control */
#define PCI_ACS_CAP_TRANS0x0040/* ACS Direct Translated P2P */
#define PCI_ACS_CAP_VECTOR(x)(((x) >> 8) & 0xff) /* Egress Control Vector Size */
#define PCI_ACS_CTRL0x06/* ACS Control Register */
#define PCI_ACS_CTRL_VALID0x0001/* ACS Source Validation Enable */
#define PCI_ACS_CTRL_BLOCK0x0002/* ACS Translation Blocking Enable */
#define PCI_ACS_CTRL_REQ_RED0x0004/* ACS P2P Request Redirect Enable */
#define PCI_ACS_CTRL_CMPLT_RED0x0008/* ACS P2P Completion Redirect Enable */
#define PCI_ACS_CTRL_FORWARD0x0010/* ACS Upstream Forwarding Enable */
#define PCI_ACS_CTRL_EGRESS0x0020/* ACS P2P Egress Control Enable */
#define PCI_ACS_CTRL_TRANS0x0040/* ACS Direct Translated P2P Enable */
#define PCI_ACS_EGRESS_CTRL0x08/* Egress Control Vector */
/* Alternative Routing-ID Interpretation */
#define PCI_ARI_CAP0x04/* ARI Capability Register */
#define PCI_ARI_CAP_MFVC0x0001/* MFVC Function Groups Capability */
#define PCI_ARI_CAP_ACS0x0002/* ACS Function Groups Capability */
#define PCI_ARI_CAP_NFN(x)(((x) >> 8) & 0xff) /* Next Function Number */
#define PCI_ARI_CTRL0x06/* ARI Control Register */
#define PCI_ARI_CTRL_MFVC0x0001/* MFVC Function Groups Enable */
#define PCI_ARI_CTRL_ACS0x0002/* ACS Function Groups Enable */
#define PCI_ARI_CTRL_FG(x)(((x) >> 4) & 7) /* Function Group */
/* Address Translation Service */
#define PCI_ATS_CAP0x04/* ATS Capability Register */
#define PCI_ATS_CAP_IQD(x)((x) & 0x1f) /* Invalidate Queue Depth */
#define PCI_ATS_CTRL0x06/* ATS Control Register */
#define PCI_ATS_CTRL_STU(x)((x) & 0x1f) /* Smallest Translation Unit */
#define PCI_ATS_CTRL_ENABLE0x8000/* ATS Enable */
/* Single Root I/O Virtualization */
#define PCI_IOV_CAP0x04/* SR-IOV Capability Register */
#define PCI_IOV_CAP_VFM0x00000001 /* VF Migration Capable */
#define PCI_IOV_CAP_IMN(x)((x) >> 21) /* VF Migration Interrupt Message Number */
#define PCI_IOV_CTRL0x08/* SR-IOV Control Register */
#define PCI_IOV_CTRL_VFE0x0001/* VF Enable */
#define PCI_IOV_CTRL_VFME0x0002/* VF Migration Enable */
#define PCI_IOV_CTRL_VFMIE0x0004/* VF Migration Interrupt Enable */
#define PCI_IOV_CTRL_MSE0x0008/* VF MSE */
#define PCI_IOV_CTRL_ARI0x0010/* ARI Capable Hierarchy */
#define PCI_IOV_STATUS0x0a/* SR-IOV Status Register */
#define PCI_IOV_STATUS_MS0x0001/* VF Migration Status */
#define PCI_IOV_INITIALVF0x0c/* Number of VFs that are initially associated */
#define PCI_IOV_TOTALVF0x0e/* Maximum number of VFs that could be associated */
#define PCI_IOV_NUMVF0x10/* Number of VFs that are available */
#define PCI_IOV_FDL0x12/* Function Dependency Link */
#define PCI_IOV_OFFSET0x14/* First VF Offset */
#define PCI_IOV_STRIDE0x16/* Routing ID offset from one VF to the next one */
#define PCI_IOV_DID0x1a/* VF Device ID */
#define PCI_IOV_SUPPS0x1c/* Supported Page Sizes */
#define PCI_IOV_SYSPS0x20/* System Page Size */
#define PCI_IOV_BAR_BASE0x24/* VF BAR0, VF BAR1, ... VF BAR5 */
#define PCI_IOV_NUM_BAR6/* Number of VF BARs */
#define PCI_IOV_MSAO0x3c/* VF Migration State Array Offset */
#define PCI_IOV_MSA_BIR(x)((x) & 7) /* VF Migration State BIR */
#define PCI_IOV_MSA_OFFSET(x)((x) & 0xfffffff8) /* VF Migration State Offset */
/*
* The PCI interface treats multi-function devices as independent
* devices. The slot/function address of each device is encoded
* in a single byte as follows:
*
*7:3 = slot
*2:0 = function
*/
#define PCI_DEVFN(slot,func)((((slot) & 0x1f) << 3) | ((func) & 0x07))
#define PCI_SLOT(devfn)(((devfn) >> 3) & 0x1f)
#define PCI_FUNC(devfn)((devfn) & 0x07)
/* Device classes and subclasses */
#define PCI_CLASS_NOT_DEFINED0x0000
#define PCI_CLASS_NOT_DEFINED_VGA0x0001
#define PCI_BASE_CLASS_STORAGE0x01
#define PCI_CLASS_STORAGE_SCSI0x0100
#define PCI_CLASS_STORAGE_IDE0x0101
#define PCI_CLASS_STORAGE_FLOPPY0x0102
#define PCI_CLASS_STORAGE_IPI0x0103
#define PCI_CLASS_STORAGE_RAID0x0104
#define PCI_CLASS_STORAGE_ATA0x0105
#define PCI_CLASS_STORAGE_SATA0x0106
#define PCI_CLASS_STORAGE_SAS0x0107
#define PCI_CLASS_STORAGE_OTHER0x0180
#define PCI_BASE_CLASS_NETWORK0x02
#define PCI_CLASS_NETWORK_ETHERNET0x0200
#define PCI_CLASS_NETWORK_TOKEN_RING0x0201
#define PCI_CLASS_NETWORK_FDDI0x0202
#define PCI_CLASS_NETWORK_ATM0x0203
#define PCI_CLASS_NETWORK_ISDN0x0204
#define PCI_CLASS_NETWORK_OTHER0x0280
#define PCI_BASE_CLASS_DISPLAY0x03
#define PCI_CLASS_DISPLAY_VGA0x0300
#define PCI_CLASS_DISPLAY_XGA0x0301
#define PCI_CLASS_DISPLAY_3D0x0302
#define PCI_CLASS_DISPLAY_OTHER0x0380
#define PCI_BASE_CLASS_MULTIMEDIA0x04
#define PCI_CLASS_MULTIMEDIA_VIDEO0x0400
#define PCI_CLASS_MULTIMEDIA_AUDIO0x0401
#define PCI_CLASS_MULTIMEDIA_PHONE0x0402
#define PCI_CLASS_MULTIMEDIA_AUDIO_DEV0x0403
#define PCI_CLASS_MULTIMEDIA_OTHER0x0480
#define PCI_BASE_CLASS_MEMORY0x05
#define PCI_CLASS_MEMORY_RAM0x0500
#define PCI_CLASS_MEMORY_FLASH0x0501
#define PCI_CLASS_MEMORY_OTHER0x0580
#define PCI_BASE_CLASS_BRIDGE0x06
#define PCI_CLASS_BRIDGE_HOST0x0600
#define PCI_CLASS_BRIDGE_ISA0x0601
#define PCI_CLASS_BRIDGE_EISA0x0602
#define PCI_CLASS_BRIDGE_MC0x0603
#define PCI_CLASS_BRIDGE_PCI0x0604
#define PCI_CLASS_BRIDGE_PCMCIA0x0605
#define PCI_CLASS_BRIDGE_NUBUS0x0606
#define PCI_CLASS_BRIDGE_CARDBUS0x0607
#define PCI_CLASS_BRIDGE_RACEWAY0x0608
#define PCI_CLASS_BRIDGE_PCI_SEMI0x0609
#define PCI_CLASS_BRIDGE_IB_TO_PCI0x060a
#define PCI_CLASS_BRIDGE_OTHER0x0680
#define PCI_BASE_CLASS_COMMUNICATION0x07
#define PCI_CLASS_COMMUNICATION_SERIAL0x0700
#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
#define PCI_CLASS_COMMUNICATION_MSERIAL0x0702
#define PCI_CLASS_COMMUNICATION_MODEM0x0703
#define PCI_CLASS_COMMUNICATION_OTHER0x0780
#define PCI_BASE_CLASS_SYSTEM0x08
#define PCI_CLASS_SYSTEM_PIC0x0800
#define PCI_CLASS_SYSTEM_DMA0x0801
#define PCI_CLASS_SYSTEM_TIMER0x0802
#define PCI_CLASS_SYSTEM_RTC0x0803
#define PCI_CLASS_SYSTEM_PCI_HOTPLUG0x0804
#define PCI_CLASS_SYSTEM_OTHER0x0880
#define PCI_BASE_CLASS_INPUT0x09
#define PCI_CLASS_INPUT_KEYBOARD0x0900
#define PCI_CLASS_INPUT_PEN0x0901
#define PCI_CLASS_INPUT_MOUSE0x0902
#define PCI_CLASS_INPUT_SCANNER0x0903
#define PCI_CLASS_INPUT_GAMEPORT0x0904
#define PCI_CLASS_INPUT_OTHER0x0980
#define PCI_BASE_CLASS_DOCKING0x0a
#define PCI_CLASS_DOCKING_GENERIC0x0a00
#define PCI_CLASS_DOCKING_OTHER0x0a80
#define PCI_BASE_CLASS_PROCESSOR0x0b
#define PCI_CLASS_PROCESSOR_3860x0b00
#define PCI_CLASS_PROCESSOR_4860x0b01
#define PCI_CLASS_PROCESSOR_PENTIUM0x0b02
#define PCI_CLASS_PROCESSOR_ALPHA0x0b10
#define PCI_CLASS_PROCESSOR_POWERPC0x0b20
#define PCI_CLASS_PROCESSOR_MIPS0x0b30
#define PCI_CLASS_PROCESSOR_CO0x0b40
#define PCI_BASE_CLASS_SERIAL0x0c
#define PCI_CLASS_SERIAL_FIREWIRE0x0c00
#define PCI_CLASS_SERIAL_ACCESS0x0c01
#define PCI_CLASS_SERIAL_SSA0x0c02
#define PCI_CLASS_SERIAL_USB0x0c03
#define PCI_CLASS_SERIAL_FIBER0x0c04
#define PCI_CLASS_SERIAL_SMBUS0x0c05
#define PCI_CLASS_SERIAL_INFINIBAND0x0c06
#define PCI_BASE_CLASS_WIRELESS0x0d
#define PCI_CLASS_WIRELESS_IRDA0x0d00
#define PCI_CLASS_WIRELESS_CONSUMER_IR0x0d01
#define PCI_CLASS_WIRELESS_RF0x0d10
#define PCI_CLASS_WIRELESS_OTHER0x0d80
#define PCI_BASE_CLASS_INTELLIGENT0x0e
#define PCI_CLASS_INTELLIGENT_I2O0x0e00
#define PCI_BASE_CLASS_SATELLITE0x0f
#define PCI_CLASS_SATELLITE_TV0x0f00
#define PCI_CLASS_SATELLITE_AUDIO0x0f01
#define PCI_CLASS_SATELLITE_VOICE0x0f03
#define PCI_CLASS_SATELLITE_DATA0x0f04
#define PCI_BASE_CLASS_CRYPT0x10
#define PCI_CLASS_CRYPT_NETWORK0x1000
#define PCI_CLASS_CRYPT_ENTERTAINMENT0x1010
#define PCI_CLASS_CRYPT_OTHER0x1080
#define PCI_BASE_CLASS_SIGNAL0x11
#define PCI_CLASS_SIGNAL_DPIO0x1100
#define PCI_CLASS_SIGNAL_PERF_CTR0x1101
#define PCI_CLASS_SIGNAL_SYNCHRONIZER0x1110
#define PCI_CLASS_SIGNAL_OTHER0x1180
#define PCI_CLASS_OTHERS0xff
/* Several ID's we need in the library */
#define PCI_VENDOR_ID_APPLE0x106b
#define PCI_VENDOR_ID_AMD0x1002
#define PCI_VENDOR_ID_ATI0x1002
#define PCI_VENDOR_ID_INTEL0x8086
#define PCI_VENDOR_ID_NVIDIA0x10de
#define PCI_VENDOR_ID_REALTEK0x10ec
#define PCI_VENDOR_ID_TEXAS_INSTRUMENTS0x104c
#define PCI_VENDOR_ID_VIA0x1106
#endif /* !__PCI_OLD_H */
branches/azimutz/Chazi/i386/modules/ATiGraphicsEnabler/ati.h
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/*
* ATI injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas
*
* ATI injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ATI driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with ATI injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
#ifndef __LIBSAIO_ATI_H
#define __LIBSAIO_ATI_H
bool setup_ati_devprop(pci_dt_t *ati_dev);
struct ati_chipsets_t {
unsigned device;
char *name;
};
struct ati_data_key {
uint32_t size;
char *name;
uint8_t data[];
};
#define REG8(reg) ((volatile uint8_t *)regs)[(reg)]
#define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1]
#define REG32R(reg) ((volatile uint32_t *)regs)[(reg) >> 2]
#define REG32W(reg, val) ((volatile uint32_t *)regs)[(reg) >> 2] = (val)
#endif /* !__LIBSAIO_ATI_H */
branches/azimutz/Chazi/i386/modules/ATiGraphicsEnabler/ATiGraphicsEnabler.c
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/*
* ATIGraphicsEnabler Module ---
* Enables many ati "legacy ??" cards to be used out of the box in OS X.
* This was converted from ( < r784) boot2 code to a boot2 module.
*
*/
#include "saio_internal.h"
#include "bootstruct.h"
#include "../modules/ATiGraphicsEnabler/pci_old.h"
#include "ati.h"
#include "modules.h"
#define kGraphicsEnablerKey"GraphicsEnabler" // change?
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4);
void ATiGraphicsEnabler_start()
{
register_hook_callback("PCIDevice", &GraphicsEnabler_hook);
}
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4)
{
pci_dt_t* current = arg1;
if (current->class_id != PCI_CLASS_DISPLAY_VGA) return;
char *devicepath = get_pci_dev_path(current);
bool do_gfx_devprop = true;
getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->bootConfig);
//Azi: check "fail" code...
if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_ATI))
{
verbose("ATI VGA Controller [%04x:%04x] :: %s \n",
current->vendor_id, current->device_id, devicepath);
setup_ati_devprop(current);
}
else
verbose("Not a ATI VGA Controller.\n"); // ---
}
branches/azimutz/Chazi/i386/modules/ATiGraphicsEnabler/Readme.txt
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Module:ATIEnablerLegacy
Description: the GraphicsEnabler ATI code ( < r784) ported to a module.
Based on Meklort's work.
Dependencies: none
Keys: GraphicsEnabler(enabled by default)
UseAtiROM(disabled by default)
TODO:
- naming: ATi or AMD ??
- eliminate the need for pci_old.h
- merge with AMDGraphicsEnabler ??
branches/azimutz/Chazi/i386/modules/ATiGraphicsEnabler/Makefile
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MODULE_NAME = ATiGraphicsEnabler
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = _$(MODULE_NAME)_start
MODULE_DEPENDENCIES =
DIR = Enabler/ATiGraphicsEnabler
MODULE_OBJS = ati.o ATiGraphicsEnabler.o
OPTIM = -Os -Oz
DEBUG = -DNOTHING
#DEBUG = -DDEBUG_HELLO_WORLD=1
CFLAGS= $(RC_CFLAGS) $(OPTIM) $(MORECPP) -arch i386 -g -Wmost \
-D__ARCHITECTURE__=\"i386\" -DSAIO_INTERNAL_USER \
-DRCZ_COMPRESSED_FILE_SUPPORT $(DEBUG) \
-fno-builtin $(OMIT_FRAME_POINTER_CFLAG) \
-mpreferred-stack-boundary=2 -fno-align-functions -fno-stack-protector \
-march=pentium4 -msse2 -mfpmath=sse -msoft-float -fno-common
DEFINES=
CONFIG = hd
INC = -I. -I.. -I$(SYMROOT) -I$(UTILDIR) -I$(LIBSADIR) -I$(LIBSAIODIR) -I$(BOOT2DIR)
LIBS=
VPATH = $(OBJROOT):$(SYMROOT)
SFILES =
CFILES =
HFILES =
EXPORTED_HFILES =
INSTALLED_HFILES =
OTHERFILES = Makefile
ALLSRC = $(SFILES) $(CFILES) \
$(HFILES) $(OTHERFILES)
DIRS_NEEDED = $(OBJROOT) $(SYMROOT)
all embedtheme: dylib
include ../MakeInc.dir
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/*
* ATI injector
*
* Copyright (C) 2009 Jasmin Fazlic, iNDi, netkas
*
* ATI injector is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ATI driver and injector is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with ATI injector. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Alternatively you can choose to comply with APSL
*/
#include "bootstruct.h"
#include "../modules/ATiGraphicsEnabler/pci_old.h"
#include "platform.h"
#include "device_inject.h"
#include "ati.h"
#ifndef DEBUG_ATI
#define DEBUG_ATI 0
#endif
#if DEBUG_ATI
#define DBG(x...)printf(x)
#else
#define DBG(x...)
#endif
#define kUseAtiROMKey"UseAtiROM"
#define MAX_NUM_DCB_ENTRIES 16
#define TYPE_GROUPED 0xff
extern uint32_t devices_number;
const char *ati_compatible_0[]= { "@0,compatible", "ATY,%s" };
const char *ati_compatible_1[]= { "@1,compatible", "ATY,%s" };
const char *ati_device_type_0[]= { "@0,device_type", "display" };
const char *ati_device_type_1[]= { "@1,device_type", "display" };
const char *ati_device_type[]= { "device_type", "ATY,%sParent" };
const char *ati_name_0[]= { "@0,name", "ATY,%s" };
const char *ati_name_1[]= { "@1,name", "ATY,%s" };
const char *ati_name[]= { "name", "ATY,%sParent" };
const char *ati_efidisplay_0[]= { "@0,ATY,EFIDisplay", "TMDSB" };
struct ati_data_key ati_connector_type_0= { 0x04, "@0,connector-type", {0x00, 0x04, 0x00, 0x00} };
struct ati_data_key ati_connector_type_1= { 0x04, "@1,connector-type", {0x04, 0x00, 0x00, 0x00} };
struct ati_data_key ati_display_con_fl_type_0= { 0x04, "@0,display-connect-flags", {0x00, 0x00, 0x04, 0x00} };
const char *ati_display_type_0[]= { "@0,display-type", "LCD" };
const char *ati_display_type_1[]= { "@1,display-type", "NONE" };
struct ati_data_key ati_aux_power_conn= { 0x04, "AAPL,aux-power-connected", {0x01, 0x00, 0x00, 0x00} };
struct ati_data_key ati_backlight_ctrl= { 0x04, "AAPL,backlight-control", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl01_coher= { 0x04, "AAPL01,Coherency", {0x01, 0x00, 0x00, 0x00} };
const char *ati_card_no[]= { "ATY,Card#", "109-B77101-00" };
const char *ati_copyright[]= { "ATY,Copyright", "Copyright AMD Inc. All Rights Reserved. 2005-2009" };
const char *ati_efi_compile_d[]= { "ATY,EFICompileDate", "Jan 26 2009" };
struct ati_data_key ati_efi_disp_conf= { 0x08, "ATY,EFIDispConfig", {0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} };
struct ati_data_key ati_efi_drv_type= { 0x01, "ATY,EFIDriverType", {0x02} };
struct ati_data_key ati_efi_enbl_mode= { 0x01, "ATY,EFIEnabledMode", {0x01} };
struct ati_data_key ati_efi_init_stat= { 0x04, "ATY,EFIHWInitStatus", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_efi_orientation= { 0x02, "ATY,EFIOrientation", {0x02, 0x00} };
const char *ati_efi_version[]= { "ATY,EFIVersion", "01.00.318" };
const char *ati_efi_versionB[]= { "ATY,EFIVersionB", "113-SBSJ1G04-00R-02" };
const char *ati_efi_versionE[]= { "ATY,EFIVersionE", "113-B7710A-318" };
struct ati_data_key ati_mclk= { 0x04, "ATY,MCLK", {0x70, 0x2e, 0x11, 0x00} };
struct ati_data_key ati_mem_rev_id= { 0x02, "ATY,MemRevisionID", {0x03, 0x00} };
struct ati_data_key ati_mem_vend_id= { 0x02, "ATY,MemVendorID", {0x02, 0x00} };
const char *ati_mrt[]= { "ATY,MRT", " " };
const char *ati_romno[]= { "ATY,Rom#", "113-B7710C-176" };
struct ati_data_key ati_sclk= { 0x04, "ATY,SCLK", {0x28, 0xdb, 0x0b, 0x00} };
struct ati_data_key ati_vendor_id= { 0x02, "ATY,VendorID", {0x02, 0x10} };
struct ati_data_key ati_platform_info= { 0x80, "ATY,PlatformInfo", {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_mvad= { 0x40, "MVAD", {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, 0x92, 0x20, 0x00, 0x03} };
struct ati_data_key ati_saved_config= { 0x100, "saved-config", {0x3f, 0x5c, 0x82, 0x02, 0xff, 0x90, 0x00, 0x54, 0x60, 0x00, 0xac, 0x10, 0xa0, 0x17, 0x00, 0x03, 0xb0, 0x68, 0x00, 0x0a, 0xa0, 0x0a, 0x30, 0x00, 0x20, 0x00, 0x40, 0x06, 0x6e, 0x06, 0x03, 0x00, 0x06, 0x00, 0x40, 0x06, 0x00, 0x0a, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x00, 0x10, 0x06, 0x92, 0x20, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xee, 0x02, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
///non 48xx keys
const char *ati_efidisplay_0_n4[]= { "@0,ATY,EFIDisplay", "TMDSA" };
struct ati_data_key ati_connector_type_0_n4= { 0x04, "@0,connector-type", {0x04, 0x00, 0x00, 0x00} };
struct ati_data_key ati_connector_type_1_n4= { 0x04, "@1,connector-type", {0x00, 0x02, 0x00, 0x00} };
struct ati_data_key ati_aapl_emc_disp_list_n4= { 0x40, "AAPL,EMC-Display-List", {0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x1b, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x1c, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x10, 0x00, 0x00, 0x21, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_fb_offset_n4= { 0x08, "ATY,FrameBufferOffset", {0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00} };
struct ati_data_key ati_hwgpio_n4= { 0x04, "ATY,HWGPIO", {0x23, 0xa8, 0x48, 0x00} };
struct ati_data_key ati_iospace_offset_n4= { 0x08, "ATY,IOSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00} };
struct ati_data_key ati_mclk_n4= { 0x04, "ATY,MCLK", {0x00, 0x35, 0x0c, 0x00} };
struct ati_data_key ati_sclk_n4= { 0x04, "ATY,SCLK", {0x60, 0xae, 0x0a, 0x00} };
struct ati_data_key ati_refclk_n4= { 0x04, "ATY,RefCLK", {0x8c, 0x0a, 0x00, 0x00} };
struct ati_data_key ati_regspace_offset_n4= { 0x08, "ATY,RegisterSpaceOffset", {0x00, 0x00, 0x00, 0x00, 0x90, 0xa2, 0x00, 0x00} };
struct ati_data_key ati_vram_memsize_0= { 0x08, "@0,VRAM,memsize", {0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_vram_memsize_1= { 0x08, "@1,VRAM,memsize", {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl_blackscr_prefs_0_n4= { 0x04, "AAPL00,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_aapl_blackscr_prefs_1_n4= { 0x04, "AAPL01,blackscreen-preferences", {0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_swgpio_info_n4= { 0x04, "ATY,SWGPIO Info", {0x00, 0x48, 0xa8, 0x23} };
struct ati_data_key ati_efi_orientation_n4= { 0x01, "ATY,EFIOrientation", {0x08} };
struct ati_data_key ati_mvad_n4= { 0x100, "MVAD", {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct ati_data_key ati_saved_config_n4= { 0x100, "saved-config", {0x3e, 0x5c, 0x82, 0x00, 0xff, 0x90, 0x00, 0xf6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x3c, 0x80, 0x07, 0x20, 0x08, 0x30, 0x00, 0x20, 0x00, 0xb0, 0x04, 0xd3, 0x04, 0x03, 0x00, 0x06, 0x00, 0xb0, 0x04, 0x80, 0x07, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x50, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32, 0x32, 0x32, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} };
struct pcir_s {
uint32_t signature;
uint16_t vid;
uint16_t devid;
};
// Known cards as of 2008/08/26
static struct ati_chipsets_t ATIKnownChipsets[] = {
{ 0x00000000, "Unknown" } ,
//{ 0x10027181, "ATI Radeon 1300 Series"} ,
{ 0x10029589, "ATI Radeon 2600 Series"} ,
{ 0x10029588, "ATI Radeon 2600 Series"} ,
{ 0x100294C3, "ATI Radeon 2400 Series"} ,
{ 0x100294C4, "ATI Radeon 2400 Series"} ,
{ 0x100294C6, "ATI Radeon 2400 Series"} ,
{ 0x10029400, "ATI Radeon 2900 Series"} ,
{ 0x10029405, "ATI Radeon 2900GT Series"} ,
{ 0x10029581, "ATI Radeon 2600 Series"} ,
{ 0x10029583, "ATI Radeon 2600 Series"} ,
{ 0x10029586, "ATI Radeon 2600 Series"} ,
{ 0x10029587, "ATI Radeon 2600 Series"} ,
{ 0x100294C9, "ATI Radeon 2400 Series"} ,
{ 0x10029501, "ATI Radeon 3800 Series"} ,
{ 0x10029505, "ATI Radeon 3800 Series"} ,
{ 0x10029515, "ATI Radeon 3800 Series"} ,
{ 0x10029507, "ATI Radeon 3800 Series"} ,
{ 0x10029500, "ATI Radeon 3800 Series"} ,
{ 0x1002950F, "ATI Radeon 3800X2 Series"} ,
{ 0x100295C5, "ATI Radeon 3400 Series"} ,
{ 0x100295C7, "ATI Radeon 3400 Series"} ,
{ 0x100295C0, "ATI Radeon 3400 Series"} ,
{ 0x10029596, "ATI Radeon 3600 Series"} ,
{ 0x10029590, "ATI Radeon 3600 Series"} ,
{ 0x10029599, "ATI Radeon 3600 Series"} ,
{ 0x10029597, "ATI Radeon 3600 Series"} ,
{ 0x10029598, "ATI Radeon 3600 Series"} ,
{ 0x10029442, "ATI Radeon 4850 Series"} ,
{ 0x10029440, "ATI Radeon 4870 Series"} ,
{ 0x1002944C, "ATI Radeon 4830 Series"} ,
{ 0x10029460, "ATI Radeon 4890 Series"} ,
{ 0x10029462, "ATI Radeon 4890 Series"} ,
{ 0x10029441, "ATI Radeon 4870X2 Series"} ,
{ 0x10029443, "ATI Radeon 4850X2 Series"} ,
{ 0x10029444, "ATI Radeon 4800 Series"} ,
{ 0x10029446, "ATI Radeon 4800 Series"} ,
{ 0x1002944E, "ATI Radeon 4730 Series"} ,
{ 0x10029450, "ATI Radeon 4800 Series"} ,
{ 0x10029452, "ATI Radeon 4800 Series"} ,
{ 0x10029456, "ATI Radeon 4800 Series"} ,
{ 0x1002944A, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002945A, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002945B, "ATI Radeon 4800 Mobility Series"} ,
{ 0x1002944B, "ATI Radeon 4800 Mobility Series"} ,
{ 0x10029490, "ATI Radeon 4670 Series"} ,
{ 0x10029498, "ATI Radeon 4650 Series"} ,
{ 0x10029490, "ATI Radeon 4600 Series"} ,
{ 0x10029498, "ATI Radeon 4600 Series"} ,
{ 0x1002949E, "ATI Radeon 4600 Series"} ,
{ 0x10029480, "ATI Radeon 4600 Series"} ,
{ 0x10029488, "ATI Radeon 4600 Series"} ,
{ 0x10029540, "ATI Radeon 4500 Series"} ,
{ 0x10029541, "ATI Radeon 4500 Series"} ,
{ 0x1002954E, "ATI Radeon 4500 Series"} ,
{ 0x10029552, "ATI Radeon 4300 Mobility Series"} ,
{ 0x10029553, "ATI Radeon 4500 Mobility Series"} ,
{ 0x1002954F, "ATI Radeon 4300 Series"} ,
{ 0x100294B3, "ATI Radeon 4770 Series"} ,
{ 0x100294B5, "ATI Radeon 4770 Series"} ,
{ 0x100268B8, "ATI Radeon 5700 Series"} ,
{ 0x100268BE, "ATI Radeon 5700 Series"} ,
{ 0x10026898, "ATI Radeon 5800 Series"} ,
{ 0x10026899, "ATI Radeon 5800 Series"}
};
static struct ati_chipsets_t ATIKnownFramebuffers[] = {
{ 0x00000000, "Megalodon" },
//{ 0x10027181, "Caretta" },
{ 0x10029589, "Lamna"} ,
{ 0x10029588, "Lamna"} ,
{ 0x100294C3, "Iago"} ,
{ 0x100294C4, "Iago"} ,
{ 0x100294C6, "Iago"} ,
{ 0x10029400, "Franklin"} ,
{ 0x10029405, "Franklin"} ,
{ 0x10029581, "Hypoprion"} ,
{ 0x10029583, "Hypoprion"} ,
{ 0x10029586, "Hypoprion"} ,
{ 0x10029587, "Hypoprion"} ,
{ 0x100294C9, "Iago"} ,
{ 0x10029501, "Megalodon"} ,
{ 0x10029505, "Megalodon"} ,
{ 0x10029515, "Megalodon"} ,
{ 0x10029507, "Megalodon"} ,
{ 0x10029500, "Megalodon"} ,
{ 0x1002950F, "Triakis"} ,
{ 0x100295C5, "Iago"} ,
{ 0x100295C7, "Iago"} ,
{ 0x100295C0, "Iago"} ,
{ 0x10029596, "Megalodon"} ,
{ 0x10029590, "Megalodon"} ,
{ 0x10029599, "Megalodon"} ,
{ 0x10029597, "Megalodon"} ,
{ 0x10029598, "Megalodon"} ,
{ 0x10029442, "Motmot"} ,
{ 0x10029440, "Motmot"} ,
{ 0x1002944C, "Motmot"} ,
{ 0x10029460, "Motmot"} ,
{ 0x10029462, "Motmot"} ,
{ 0x10029441, "Motmot"} ,
{ 0x10029443, "Motmot"} ,
{ 0x10029444, "Motmot"} ,
{ 0x10029446, "Motmot"} ,
{ 0x1002944E, "Motmot"} ,
{ 0x10029450, "Motmot"} ,
{ 0x10029452, "Motmot"} ,
{ 0x10029456, "Motmot"} ,
{ 0x1002944A, "Motmot"} ,
{ 0x1002945A, "Motmot"} ,
{ 0x1002945B, "Motmot"} ,
{ 0x1002944B, "Motmot"} ,
{ 0x10029490, "Peregrine"} ,
{ 0x10029498, "Peregrine"} ,
{ 0x1002949E, "Peregrine"} ,
{ 0x10029480, "Peregrine"} ,
{ 0x10029488, "Peregrine"} ,
{ 0x10029540, "Peregrine"} ,
{ 0x10029541, "Peregrine"} ,
{ 0x1002954E, "Peregrine"} ,
{ 0x10029552, "Peregrine"} ,
{ 0x10029553, "Peregrine"} ,
{ 0x1002954F, "Peregrine"} ,
{ 0x100294B3, "Peregrine"},
{ 0x100294B5, "Peregrine"},
{ 0x100268B8, "Motmot"},
{ 0x100268BE, "Motmot"},
{ 0x10026898, "Motmot"},
{ 0x10026899, "Motmot"}
};
static uint32_t accessROM(pci_dt_t *ati_dev, unsigned int mode)
{
uint32_tbar[7];
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (uint32_t *) (bar[2] & ~0x0f);
if (mode) {
if (mode != 1) {
return 0xe00002c7;
}
REG32W(0x179c, 0x00080000);
REG32W(0x1798, 0x00080721);
REG32W(0x17a0, 0x00080621);
REG32W(0x1600, 0x14030300);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
REG32W(0x17a0, 0x21);
REG32W(0x1798, 0x21);
REG32W(0x1798, 0x21);
} else {
REG32W(0x1600, 0x14030302);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00080000);
REG32W(0x17a0, 0x00080621);
REG32W(0x1798, 0x00080721);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
REG32W(0x1604, 0x0400e9fc);
REG32W(0x161c, 0x00);
REG32W(0x1620, 0x9f);
REG32W(0x1618, 0x00040004);
REG32W(0x161c, 0x00);
REG32W(0x1604, 0xe9fc);
REG32W(0x179c, 0x00080000);
REG32W(0x1798, 0x00080721);
REG32W(0x17a0, 0x00080621);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
}
return 0;
}
static uint8_t *readAtomBIOS(pci_dt_t *ati_dev)
{
uint32_tbar[7];
uint32_t*BIOSBase;
uint32_tcounter;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (volatile uint32_t *) (bar[2] & ~0x0f);
accessROM(ati_dev, 0);
REG32W(0xa8, 0);
REG32R(0xac);
REG32W(0xa8, 0);
REG32R(0xac);
BIOSBase = malloc(0x10000);
REG32W(0xa8, 0);
BIOSBase[0] = REG32R(0xac);
counter = 4;
do {
REG32W(0xa8, counter);
BIOSBase[counter/4] = REG32R(0xac);
counter +=4;
} while (counter != 0x10000);
accessROM((pci_dt_t *)regs, 1);
if (*(uint16_t *)BIOSBase != 0xAA55) {
printf("Wrong BIOS signature: %04x\n", *(uint16_t *)BIOSBase);
return 0;
}
return (uint8_t *)BIOSBase;
}
#define R5XX_CONFIG_MEMSIZE0x00F8 //Azi:---
#define R6XX_CONFIG_MEMSIZE0x5428
uint32_t getvramsizekb(pci_dt_t *ati_dev)
{
uint32_tbar[7];
uint32_tsize;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (uint32_t *) (bar[2] & ~0x0f);
if (ati_dev->device_id < 0x9400) {
size = (REG32R(R5XX_CONFIG_MEMSIZE)) >> 10;
} else {
size = (REG32R(R6XX_CONFIG_MEMSIZE)) >> 10;
}
return size;
}
#define AVIVO_D1CRTC_CONTROL0x6080
#define AVIVO_CRTC_EN(1<<0)
#define AVIVO_D2CRTC_CONTROL0x6880
static bool radeon_card_posted(pci_dt_t *ati_dev)
{
// if devid matches biosimage(from legacy) devid - posted card, fails with X2/crossfire cards.
/*char *biosimage = 0xC0000;
if ((uint8_t)biosimage[0] == 0x55 && (uint8_t)biosimage[1] == 0xaa)
{
struct pci_rom_pci_header_t *rom_pci_header;
rom_pci_header = (struct pci_rom_pci_header_t*)(biosimage + (uint8_t)biosimage[24] + (uint8_t)biosimage[25]*256);
if (rom_pci_header->signature == 0x52494350)
{
if (rom_pci_header->device == ati_dev->device_id)
{
return true;
printf("Card was POSTed\n");
}
}
}
return false;
printf("Card was not POSTed\n");
*/
//fails yet
uint32_tbar[7];
uint32_tval;
volatile uint32_t*regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18);
regs = (uint32_t *) (bar[2] & ~0x0f);
val = REG32R(AVIVO_D1CRTC_CONTROL) | REG32R(AVIVO_D2CRTC_CONTROL);
if (val & AVIVO_CRTC_EN) {
return true;
} else {
return false;
}
}
static uint32_t load_ati_bios_file(const char *filename, uint8_t *buf, int bufsize)
{
intfd;
intsize;
if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {
return 0;
}
size = file_size(fd);
if (size > bufsize) {
printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n", filename, bufsize);
size = bufsize;
}
size = read(fd, (char *)buf, size);
close(fd);
return size > 0 ? size : 0;
}
static char *get_ati_model(uint32_t id)
{
int i;
for (i = 0; i < (sizeof(ATIKnownChipsets) / sizeof(ATIKnownChipsets[0])); i++) {
if (ATIKnownChipsets[i].device == id) {
return ATIKnownChipsets[i].name;
}
}
return ATIKnownChipsets[0].name;
}
static char *get_ati_fb(uint32_t id)
{
inti;
for (i = 0; i < (sizeof(ATIKnownFramebuffers) / sizeof(ATIKnownFramebuffers[0])); i++) {
if (ATIKnownFramebuffers[i].device == id) {
return ATIKnownFramebuffers[i].name;
}
}
return ATIKnownFramebuffers[0].name;
}
static int devprop_add_iopciconfigspace(struct DevPropDevice *device, pci_dt_t *ati_dev)
{
inti;
uint8_t*config_space;
if (!device || !ati_dev) {
return 0;
}
verbose("dumping pci config space, 256 bytes\n");
config_space = malloc(256);
for (i=0; i<=255; i++) {
config_space[i] = pci_config_read8( ati_dev->dev.addr, i);
}
devprop_add_value(device, "ATY,PCIConfigSpace", config_space, 256);
free (config_space);
return 1;
}
static int devprop_add_ati_template_4xxx(struct DevPropDevice *device)
{
if(!device)
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_compatible_0))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_compatible_1))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_1))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_device_type))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name_0))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name_1))
//return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_name))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_display_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_display_type_1))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_slot_name))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_card_no))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_copyright))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_version))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_mrt))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_romno))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_name_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_display_con_fl_type_0))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_disp_conf))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_init_stat))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config))
return 0;
return 1;
}
static int devprop_add_ati_template(struct DevPropDevice *device)
{
if(!device)
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_platform_info))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_0))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_device_type_1))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efidisplay_0_n4))
return 0;
//if(!DP_ADD_TEMP_VAL(device, ati_slot_name_n4))
//return 0;
if(!DP_ADD_TEMP_VAL(device, ati_card_no))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_copyright))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_compile_d))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_version))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionB))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_efi_versionE))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_mrt))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_romno))
return 0;
if(!DP_ADD_TEMP_VAL(device, ati_name_1))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_0_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_connector_type_1_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aux_power_conn))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_backlight_ctrl))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl01_coher))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_drv_type))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_enbl_mode))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_rev_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mem_vend_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_vendor_id))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_emc_disp_list_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_fb_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_hwgpio_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_iospace_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_sclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_refclk_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_regspace_offset_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_0_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_aapl_blackscr_prefs_1_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_swgpio_info_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_efi_orientation_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_mvad_n4))
return 0;
if(!DP_ADD_TEMP_VAL_DATA(device, ati_saved_config_n4))
return 0;
return 1;
}
bool setup_ati_devprop(pci_dt_t *ati_dev)
{
struct DevPropDevice*device;
char*devicepath;
char*model;
char*framebuffer;
chartmp[64];
uint8_t*rom = NULL;
uint32_trom_size = 0;
uint8_t*bios;
uint32_tbios_size;
uint32_tvram_size;
uint32_tboot_display;
uint8_tcmd;
booldoit;
booltoFree;
devicepath = get_pci_dev_path(ati_dev);
cmd = pci_config_read8(ati_dev->dev.addr, 4);
verbose("old pci command - %x\n", cmd);
if (cmd == 0) {
pci_config_write8(ati_dev->dev.addr, 4, 6);
cmd = pci_config_read8(ati_dev->dev.addr, 4);
verbose("new pci command - %x\n", cmd);
}
model = get_ati_model((ati_dev->vendor_id << 16) | ati_dev->device_id);
framebuffer = get_ati_fb((ati_dev->vendor_id << 16) | ati_dev->device_id);
if (!string) {
string = devprop_create_string();
}
device = devprop_add_device(string, devicepath);
if (!device) {
printf("Failed initializing dev-prop string dev-entry, press any key...\n");
getc();
return false;
}
/* FIXME: for primary graphics card only */
if (radeon_card_posted(ati_dev)) {
boot_display = 1;
} else {
boot_display = 0;
}
verbose("boot display - %x\n", boot_display);
devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
if ((framebuffer[0] == 'M' && framebuffer[1] == 'o' && framebuffer[2] == 't') ||
(framebuffer[0] == 'S' && framebuffer[1] == 'h' && framebuffer[2] == 'r') ||
(framebuffer[0] == 'P' && framebuffer[1] == 'e' && framebuffer[2] == 'r')) //faster than strcmp ;)
devprop_add_ati_template_4xxx(device);
else {
devprop_add_ati_template(device);
vram_size = getvramsizekb(ati_dev) * 1024;
if ((vram_size > 0x80000000) || (vram_size == 0)) {
vram_size = 0x10000000;//vram reported wrong, defaulting to 256 mb
}
devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&vram_size, 4);
ati_vram_memsize_0.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway
ati_vram_memsize_0.data[7] = (vram_size >> 24) & 0xFF;
ati_vram_memsize_1.data[6] = (vram_size >> 16) & 0xFF; //4,5 are 0x00 anyway
ati_vram_memsize_1.data[7] = (vram_size >> 24) & 0xFF;
DP_ADD_TEMP_VAL_DATA(device, ati_vram_memsize_0);
DP_ADD_TEMP_VAL_DATA(device, ati_vram_memsize_1);
devprop_add_iopciconfigspace(device, ati_dev);
}
devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1));
devprop_add_value(device, "ATY,DeviceID", (uint8_t*)&ati_dev->device_id, 2);
//fb setup
sprintf(tmp, "Slot-%x",devices_number);
devprop_add_value(device, "AAPL,slot-name", (uint8_t*)tmp, strlen(tmp) + 1);
devices_number++;
sprintf(tmp, ati_compatible_0[1], framebuffer);
devprop_add_value(device, (char *) ati_compatible_0[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_compatible_1[1], framebuffer);
devprop_add_value(device, (char *) ati_compatible_1[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_device_type[1], framebuffer);
devprop_add_value(device, (char *) ati_device_type[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name[1], framebuffer);
devprop_add_value(device, (char *) ati_name[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name_0[1], framebuffer);
devprop_add_value(device, (char *) ati_name_0[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, ati_name_1[1], framebuffer);
devprop_add_value(device, (char *) ati_name_1[0], (uint8_t *)tmp, strlen(tmp) + 1);
sprintf(tmp, "bt(0,0)/Extra/%04x_%04x.rom", (uint16_t)ati_dev->vendor_id, (uint16_t)ati_dev->device_id);
if (getBoolForKey(kUseAtiROMKey, &doit, &bootInfo->bootConfig) && doit) {
verbose("looking for ati video bios file %s\n", tmp);
rom = malloc(0x20000);
rom_size = load_ati_bios_file(tmp, rom, 0x20000);
if (rom_size > 0) {
verbose("Using ATI Video BIOS File %s (%d Bytes)\n", tmp, rom_size);
if (rom_size > 0x10000) {
rom_size = 0x10000; //we dont need rest anyway;
}
} else {
printf("ERROR: unable to open ATI Video BIOS File %s\n", tmp);
}
}
if (rom_size == 0) {
if (boot_display) {// no custom rom
bios = NULL;// try to dump from legacy space, otherwise can result in 100% fan speed
} else {
// readAtomBios result in bug on some cards (100% fan speed and black screen),
// not using it for posted card, reading from legacy space instead
bios = readAtomBIOS(ati_dev);
}
} else {
bios = rom;//going custom rom way
verbose("Using rom %s\n", tmp);
}
if (bios == NULL) {
bios = (uint8_t *)0x000C0000;
toFree = false;
verbose("Not going to use bios image file\n");
} else {
toFree = true;
}
if (bios[0] == 0x55 && bios[1] == 0xaa) {
verbose("Found bios image\n");
bios_size = bios[2] * 512;
struct pci_rom_pci_header_t *rom_pci_header;
rom_pci_header = (struct pci_rom_pci_header_t*)(bios + bios[24] + bios[25]*256);
if (rom_pci_header->signature == 0x52494350) {
if (rom_pci_header->device != ati_dev->device_id) {
verbose("Bios image (%x) doesnt match card (%x), ignoring\n", rom_pci_header->device, ati_dev->device_id);
} else {
if (toFree)
{
//Azi: mmio, Memory-mapped I/O - Kabyl's smbios patcher stuff reminder.
verbose("Adding binimage to card %x from mmio space with size %x\n", ati_dev->device_id, bios_size);
} else {
verbose("Adding binimage to card %x from legacy space with size %x\n", ati_dev->device_id, bios_size);
}
devprop_add_value(device, "ATY,bin_image", bios, bios_size);
}
} else {
verbose("Wrong pci header signature %x\n", rom_pci_header->signature);
}
} else {
verbose("Bios image not found at %x, content %x %x\n", bios, bios[0], bios[1]);
}
if (toFree) {
free(bios);
}
stringdata = malloc(sizeof(uint8_t) * string->length);
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
branches/azimutz/Chazi/i386/modules/AMDGraphicsEnabler/ati_reg.h
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/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Kevin E. Martin <martin@xfree86.org>
* Rickard E. Faith <faith@valinux.com>
* Alan Hourihane <alanh@fairlite.demon.co.uk>
*
* References:
*
* !!!! FIXME !!!!
* RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
* Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
* 1999.
*
* !!!! FIXME !!!!
* RAGE 128 Software Development Manual (Technical Reference Manual P/N
* SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
*
*/
/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h
* AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT
* ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */
#ifndef _ATI_REG_H_
#define _ATI_REG_H_
#define ATI_DATATYPE_VQ0
#define ATI_DATATYPE_CI41
#define ATI_DATATYPE_CI82
#define ATI_DATATYPE_ARGB15553
#define ATI_DATATYPE_RGB5654
#define ATI_DATATYPE_RGB8885
#define ATI_DATATYPE_ARGB88886
#define ATI_DATATYPE_RGB3327
#define ATI_DATATYPE_Y88
#define ATI_DATATYPE_RGB89
#define ATI_DATATYPE_CI1610
#define ATI_DATATYPE_VYUY_42211
#define ATI_DATATYPE_YVYU_42212
#define ATI_DATATYPE_AYUV_44414
#define ATI_DATATYPE_ARGB444415
/* Registers for 2D/Video/Overlay */
#define RADEON_ADAPTER_ID 0x0f2c /* PCI */
#define RADEON_AGP_BASE 0x0170
#define RADEON_AGP_CNTL 0x0174
# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)
# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)
# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)
# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)
# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)
# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
#define RADEON_STATUS_PCI_CONFIG 0x06
# define RADEON_CAP_LIST 0x100000
#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/
# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */
# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */
# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */
# define RADEON_CAP_ID_EXP 0x10 /* PCI Express */
#define RADEON_AGP_COMMAND 0x0f60 /* PCI */
#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/
# define RADEON_AGP_ENABLE (1<<8)
#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */
#define RADEON_AGP_STATUS 0x0f5c /* PCI */
# define RADEON_AGP_1X_MODE 0x01
# define RADEON_AGP_2X_MODE 0x02
# define RADEON_AGP_4X_MODE 0x04
# define RADEON_AGP_FW_MODE 0x10
# define RADEON_AGP_MODE_MASK 0x17
# define RADEON_AGPv3_MODE 0x08
# define RADEON_AGPv3_4X_MODE 0x01
# define RADEON_AGPv3_8X_MODE 0x02
#define RADEON_ATTRDR 0x03c1 /* VGA */
#define RADEON_ATTRDW 0x03c0 /* VGA */
#define RADEON_ATTRX 0x03c0 /* VGA */
#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8
#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc
#define RADEON_BASE_CODE 0x0f0b
#define RADEON_BIOS_0_SCRATCH 0x0010
# define RADEON_FP_PANEL_SCALABLE (1 << 16)
# define RADEON_FP_PANEL_SCALE_EN (1 << 17)
# define RADEON_FP_CHIP_SCALE_EN (1 << 18)
# define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)
# define RADEON_DISPLAY_ROT_MASK (3 << 28)
# define RADEON_DISPLAY_ROT_00 (0 << 28)
# define RADEON_DISPLAY_ROT_90 (1 << 28)
# define RADEON_DISPLAY_ROT_180 (2 << 28)
# define RADEON_DISPLAY_ROT_270 (3 << 28)
#define RADEON_BIOS_1_SCRATCH 0x0014
#define RADEON_BIOS_2_SCRATCH 0x0018
#define RADEON_BIOS_3_SCRATCH 0x001c
#define RADEON_BIOS_4_SCRATCH 0x0020
# define RADEON_CRT1_ATTACHED_MASK (3 << 0)
# define RADEON_CRT1_ATTACHED_MONO (1 << 0)
# define RADEON_CRT1_ATTACHED_COLOR (2 << 0)
# define RADEON_LCD1_ATTACHED (1 << 2)
# define RADEON_DFP1_ATTACHED (1 << 3)
# define RADEON_TV1_ATTACHED_MASK (3 << 4)
# define RADEON_TV1_ATTACHED_COMP (1 << 4)
# define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)
# define RADEON_CRT2_ATTACHED_MASK (3 << 8)
# define RADEON_CRT2_ATTACHED_MONO (1 << 8)
# define RADEON_CRT2_ATTACHED_COLOR (2 << 8)
# define RADEON_DFP2_ATTACHED (1 << 11)
#define RADEON_BIOS_5_SCRATCH 0x0024
# define RADEON_LCD1_ON (1 << 0)
# define RADEON_CRT1_ON (1 << 1)
# define RADEON_TV1_ON (1 << 2)
# define RADEON_DFP1_ON (1 << 3)
# define RADEON_CRT2_ON (1 << 5)
# define RADEON_CV1_ON (1 << 6)
# define RADEON_DFP2_ON (1 << 7)
# define RADEON_LCD1_CRTC_MASK (1 << 8)
# define RADEON_LCD1_CRTC_SHIFT 8
# define RADEON_CRT1_CRTC_MASK (1 << 9)
# define RADEON_CRT1_CRTC_SHIFT 9
# define RADEON_TV1_CRTC_MASK (1 << 10)
# define RADEON_TV1_CRTC_SHIFT 10
# define RADEON_DFP1_CRTC_MASK (1 << 11)
# define RADEON_DFP1_CRTC_SHIFT 11
# define RADEON_CRT2_CRTC_MASK (1 << 12)
# define RADEON_CRT2_CRTC_SHIFT 12
# define RADEON_CV1_CRTC_MASK (1 << 13)
# define RADEON_CV1_CRTC_SHIFT 13
# define RADEON_DFP2_CRTC_MASK (1 << 14)
# define RADEON_DFP2_CRTC_SHIFT 14
#define RADEON_BIOS_6_SCRATCH 0x0028
# define RADEON_ACC_MODE_CHANGE (1 << 2)
# define RADEON_EXT_DESKTOP_MODE (1 << 3)
# define RADEON_LCD_DPMS_ON (1 << 20)
# define RADEON_CRT_DPMS_ON (1 << 21)
# define RADEON_TV_DPMS_ON (1 << 22)
# define RADEON_DFP_DPMS_ON (1 << 23)
# define RADEON_DPMS_MASK (3 << 24)
# define RADEON_DPMS_ON (0 << 24)
# define RADEON_DPMS_STANDBY (1 << 24)
# define RADEON_DPMS_SUSPEND (2 << 24)
# define RADEON_DPMS_OFF (3 << 24)
# define RADEON_SCREEN_BLANKING (1 << 26)
# define RADEON_DRIVER_CRITICAL (1 << 27)
# define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)
#define RADEON_BIOS_7_SCRATCH 0x002c
# define RADEON_SYS_HOTKEY (1 << 10)
# define RADEON_DRV_LOADED (1 << 12)
#define RADEON_BIOS_ROM 0x0f30 /* PCI */
#define RADEON_BIST 0x0f0f /* PCI */
#define RADEON_BRUSH_DATA0 0x1480
#define RADEON_BRUSH_DATA1 0x1484
#define RADEON_BRUSH_DATA10 0x14a8
#define RADEON_BRUSH_DATA11 0x14ac
#define RADEON_BRUSH_DATA12 0x14b0
#define RADEON_BRUSH_DATA13 0x14b4
#define RADEON_BRUSH_DATA14 0x14b8
#define RADEON_BRUSH_DATA15 0x14bc
#define RADEON_BRUSH_DATA16 0x14c0
#define RADEON_BRUSH_DATA17 0x14c4
#define RADEON_BRUSH_DATA18 0x14c8
#define RADEON_BRUSH_DATA19 0x14cc
#define RADEON_BRUSH_DATA2 0x1488
#define RADEON_BRUSH_DATA20 0x14d0
#define RADEON_BRUSH_DATA21 0x14d4
#define RADEON_BRUSH_DATA22 0x14d8
#define RADEON_BRUSH_DATA23 0x14dc
#define RADEON_BRUSH_DATA24 0x14e0
#define RADEON_BRUSH_DATA25 0x14e4
#define RADEON_BRUSH_DATA26 0x14e8
#define RADEON_BRUSH_DATA27 0x14ec
#define RADEON_BRUSH_DATA28 0x14f0
#define RADEON_BRUSH_DATA29 0x14f4
#define RADEON_BRUSH_DATA3 0x148c
#define RADEON_BRUSH_DATA30 0x14f8
#define RADEON_BRUSH_DATA31 0x14fc
#define RADEON_BRUSH_DATA32 0x1500
#define RADEON_BRUSH_DATA33 0x1504
#define RADEON_BRUSH_DATA34 0x1508
#define RADEON_BRUSH_DATA35 0x150c
#define RADEON_BRUSH_DATA36 0x1510
#define RADEON_BRUSH_DATA37 0x1514
#define RADEON_BRUSH_DATA38 0x1518
#define RADEON_BRUSH_DATA39 0x151c
#define RADEON_BRUSH_DATA4 0x1490
#define RADEON_BRUSH_DATA40 0x1520
#define RADEON_BRUSH_DATA41 0x1524
#define RADEON_BRUSH_DATA42 0x1528
#define RADEON_BRUSH_DATA43 0x152c
#define RADEON_BRUSH_DATA44 0x1530
#define RADEON_BRUSH_DATA45 0x1534
#define RADEON_BRUSH_DATA46 0x1538
#define RADEON_BRUSH_DATA47 0x153c
#define RADEON_BRUSH_DATA48 0x1540
#define RADEON_BRUSH_DATA49 0x1544
#define RADEON_BRUSH_DATA5 0x1494
#define RADEON_BRUSH_DATA50 0x1548
#define RADEON_BRUSH_DATA51 0x154c
#define RADEON_BRUSH_DATA52 0x1550
#define RADEON_BRUSH_DATA53 0x1554
#define RADEON_BRUSH_DATA54 0x1558
#define RADEON_BRUSH_DATA55 0x155c
#define RADEON_BRUSH_DATA56 0x1560
#define RADEON_BRUSH_DATA57 0x1564
#define RADEON_BRUSH_DATA58 0x1568
#define RADEON_BRUSH_DATA59 0x156c
#define RADEON_BRUSH_DATA6 0x1498
#define RADEON_BRUSH_DATA60 0x1570
#define RADEON_BRUSH_DATA61 0x1574
#define RADEON_BRUSH_DATA62 0x1578
#define RADEON_BRUSH_DATA63 0x157c
#define RADEON_BRUSH_DATA7 0x149c
#define RADEON_BRUSH_DATA8 0x14a0
#define RADEON_BRUSH_DATA9 0x14a4
#define RADEON_BRUSH_SCALE 0x1470
#define RADEON_BRUSH_Y_X 0x1474
#define RADEON_BUS_CNTL 0x0030
# define RADEON_BUS_MASTER_DIS (1 << 6)
# define RADEON_BUS_BIOS_DIS_ROM (1 << 12)
# define RADEON_BUS_RD_DISCARD_EN (1 << 24)
# define RADEON_BUS_RD_ABORT_EN (1 << 25)
# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)
# define RADEON_BUS_WRT_BURST (1 << 29)
# define RADEON_BUS_READ_BURST (1 << 30)
#define RADEON_BUS_CNTL1 0x0034
# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
#define RADEON_PCIE_INDEX 0x0030
#define RADEON_PCIE_DATA 0x0034
#define R600_PCIE_PORT_INDEX 0x0038
#define R600_PCIE_PORT_DATA 0x003c
/* PCIE_LC_LINK_WIDTH_CNTL is PCIE on r1xx-r5xx, PCIE_PORT on r6xx-r7xx */
#define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */
# define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0
# define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7
# define RADEON_PCIE_LC_LINK_WIDTH_X0 0
# define RADEON_PCIE_LC_LINK_WIDTH_X1 1
# define RADEON_PCIE_LC_LINK_WIDTH_X2 2
# define RADEON_PCIE_LC_LINK_WIDTH_X4 3
# define RADEON_PCIE_LC_LINK_WIDTH_X8 4
# define RADEON_PCIE_LC_LINK_WIDTH_X12 5
# define RADEON_PCIE_LC_LINK_WIDTH_X16 6
# define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4
# define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70
# define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
# define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)
# define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)
# define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)
# define R600_PCIE_LC_RENEGOTIATE_EN (1 << 10)
# define R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11)
#define R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c
#define R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c
#define RADEON_CACHE_CNTL 0x1724
#define RADEON_CACHE_LINE 0x0f0c /* PCI */
#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */
#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */
#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */
# define RADEON_DONT_USE_XTALIN (1 << 4)
# define RADEON_SCLK_DYN_START_CNTL (1 << 15)
#define RADEON_CLOCK_CNTL_DATA 0x000c
#define RADEON_CLOCK_CNTL_INDEX 0x0008
# define RADEON_PLL_WR_EN (1 << 7)
# define RADEON_PLL_DIV_SEL (3 << 8)
# define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8)
#define RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */
# define RADEON_M_SPLL_REF_DIV_MASK 0xff
# define RADEON_M_SPLL_REF_DIV_SHIFT 0
# define RADEON_MPLL_FB_DIV_MASK 0xff
# define RADEON_MPLL_FB_DIV_SHIFT 8
# define RADEON_SPLL_FB_DIV_MASK 0xff
# define RADEON_SPLL_FB_DIV_SHIFT 16
#define RADEON_SPLL_CNTL 0x000c /* PLL */
# define RADEON_SPLL_SLEEP (1 << 0)
# define RADEON_SPLL_RESET (1 << 1)
# define RADEON_SPLL_PCP_MASK 0x7
# define RADEON_SPLL_PCP_SHIFT 8
# define RADEON_SPLL_PVG_MASK 0x7
# define RADEON_SPLL_PVG_SHIFT 11
# define RADEON_SPLL_PDC_MASK 0x3
# define RADEON_SPLL_PDC_SHIFT 14
#define RADEON_CLK_PWRMGT_CNTL 0x0014 /* PLL */
# define RADEON_ENGIN_DYNCLK_MODE (1 << 12)
# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13)
# define RADEON_ACTIVE_HILO_LAT_SHIFT 13
# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)
# define RADEON_MC_BUSY (1 << 16)
# define RADEON_DLL_READY (1 << 19)
# define RADEON_CG_NO1_DEBUG_0 (1 << 24)
# define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24)
# define RADEON_DYN_STOP_MODE_MASK (7 << 21)
# define RADEON_TVPLL_PWRMGT_OFF (1 << 30)
# define RADEON_TVCLK_TURNOFF (1 << 31)
#define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */
# define RADEON_TCL_BYPASS_DISABLE (1 << 20)
#define RADEON_CLR_CMP_CLR_3D 0x1a24
#define RADEON_CLR_CMP_CLR_DST 0x15c8
#define RADEON_CLR_CMP_CLR_SRC 0x15c4
#define RADEON_CLR_CMP_CNTL 0x15c0
# define RADEON_SRC_CMP_EQ_COLOR (4 << 0)
# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0)
# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24)
#define RADEON_CLR_CMP_MASK 0x15cc
# define RADEON_CLR_CMP_MSK 0xffffffff
#define RADEON_CLR_CMP_MASK_3D 0x1A28
#define RADEON_COMMAND 0x0f04 /* PCI */
#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c
#define RADEON_CONFIG_APER_0_BASE 0x0100
#define RADEON_CONFIG_APER_1_BASE 0x0104
#define RADEON_CONFIG_APER_SIZE 0x0108
#define RADEON_CONFIG_BONDS 0x00e8
#define RADEON_CONFIG_CNTL 0x00e0
# define RADEON_CFG_ATI_REV_A11 (0 << 16)
# define RADEON_CFG_ATI_REV_A12 (1 << 16)
# define RADEON_CFG_ATI_REV_A13 (2 << 16)
# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)
#define RADEON_CONFIG_MEMSIZE 0x00f8
#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114
#define RADEON_CONFIG_REG_1_BASE 0x010c
#define RADEON_CONFIG_REG_APER_SIZE 0x0110
#define RADEON_CONFIG_XSTRAP 0x00e4
#define RADEON_CONSTANT_COLOR_C 0x1d34
# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff
# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff
# define RADEON_CONSTANT_COLOR_ZERO 0x00000000
#define RADEON_CRC_CMDFIFO_ADDR 0x0740
#define RADEON_CRC_CMDFIFO_DOUT 0x0744
#define RADEON_GRPH_BUFFER_CNTL 0x02f0
# define RADEON_GRPH_START_REQ_MASK (0x7f)
# define RADEON_GRPH_START_REQ_SHIFT 0
# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)
# define RADEON_GRPH_STOP_REQ_SHIFT 8
# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)
# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16
# define RADEON_GRPH_CRITICAL_CNTL (1<<28)
# define RADEON_GRPH_BUFFER_SIZE (1<<29)
# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)
# define RADEON_GRPH_STOP_CNTL (1<<31)
#define RADEON_GRPH2_BUFFER_CNTL 0x03f0
# define RADEON_GRPH2_START_REQ_MASK (0x7f)
# define RADEON_GRPH2_START_REQ_SHIFT 0
# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)
# define RADEON_GRPH2_STOP_REQ_SHIFT 8
# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)
# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16
# define RADEON_GRPH2_CRITICAL_CNTL (1<<28)
# define RADEON_GRPH2_BUFFER_SIZE (1<<29)
# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)
# define RADEON_GRPH2_STOP_CNTL (1<<31)
#define RADEON_CRTC_CRNT_FRAME 0x0214
#define RADEON_CRTC_EXT_CNTL 0x0054
# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0)
# define RADEON_VGA_ATI_LINEAR (1 << 3)
# define RADEON_XCRT_CNT_EN (1 << 6)
# define RADEON_CRTC_HSYNC_DIS (1 << 8)
# define RADEON_CRTC_VSYNC_DIS (1 << 9)
# define RADEON_CRTC_DISPLAY_DIS (1 << 10)
# define RADEON_CRTC_SYNC_TRISTAT (1 << 11)
# define RADEON_CRTC_CRT_ON (1 << 15)
#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055
# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0)
# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1)
# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2)
#define RADEON_CRTC_GEN_CNTL 0x0050
# define RADEON_CRTC_DBL_SCAN_EN (1 << 0)
# define RADEON_CRTC_INTERLACE_EN (1 << 1)
# define RADEON_CRTC_CSYNC_EN (1 << 4)
# define RADEON_CRTC_ICON_EN (1 << 15)
# define RADEON_CRTC_CUR_EN (1 << 16)
# define RADEON_CRTC_CUR_MODE_MASK (7 << 20)
# define RADEON_CRTC_EXT_DISP_EN (1 << 24)
# define RADEON_CRTC_EN (1 << 25)
# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26)
#define RADEON_CRTC2_GEN_CNTL 0x03f8
# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0)
# define RADEON_CRTC2_INTERLACE_EN (1 << 1)
# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4)
# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)
# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)
# define RADEON_CRTC2_CRT2_ON (1 << 7)
# define RADEON_CRTC2_PIX_WIDTH_SHIFT 8
# define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8)
# define RADEON_CRTC2_ICON_EN (1 << 15)
# define RADEON_CRTC2_CUR_EN (1 << 16)
# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20)
# define RADEON_CRTC2_DISP_DIS (1 << 23)
# define RADEON_CRTC2_EN (1 << 25)
# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26)
# define RADEON_CRTC2_CSYNC_EN (1 << 27)
# define RADEON_CRTC2_HSYNC_DIS (1 << 28)
# define RADEON_CRTC2_VSYNC_DIS (1 << 29)
#define RADEON_CRTC_MORE_CNTL 0x27c
# define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2)
# define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3)
# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218
# define RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT 0
# define RADEON_CRTC_GUI_TRIG_VLINE_INV (1 << 15)
# define RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT 16
# define RADEON_CRTC_GUI_TRIG_VLINE_STALL (1 << 30)
#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204
# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)
# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)
# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3
# define RADEON_CRTC_H_SYNC_WID (0x3f << 16)
# define RADEON_CRTC_H_SYNC_WID_SHIFT 16
# define RADEON_CRTC_H_SYNC_POL (1 << 23)
#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304
# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)
# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)
# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16)
# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16
# define RADEON_CRTC2_H_SYNC_POL (1 << 23)
#define RADEON_CRTC_H_TOTAL_DISP 0x0200
# define RADEON_CRTC_H_TOTAL (0x03ff << 0)
# define RADEON_CRTC_H_TOTAL_SHIFT 0
# define RADEON_CRTC_H_DISP (0x01ff << 16)
# define RADEON_CRTC_H_DISP_SHIFT 16
#define RADEON_CRTC2_H_TOTAL_DISP 0x0300
# define RADEON_CRTC2_H_TOTAL (0x03ff << 0)
# define RADEON_CRTC2_H_TOTAL_SHIFT 0
# define RADEON_CRTC2_H_DISP (0x01ff << 16)
# define RADEON_CRTC2_H_DISP_SHIFT 16
#define RADEON_CRTC_OFFSET_RIGHT 0x0220
#define RADEON_CRTC_OFFSET 0x0224
#define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)
#define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31)
#define RADEON_CRTC2_OFFSET 0x0324
#define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)
#define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31)
#define RADEON_CRTC_OFFSET_CNTL 0x0228
# define RADEON_CRTC_TILE_LINE_SHIFT 0
# define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4
#define R300_CRTC_X_Y_MODE_EN_RIGHT(1 << 6)
#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7)
#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7)
#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)
#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)
#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7)
#define R300_CRTC_X_Y_MODE_EN(1 << 9)
#define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10)
#define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10)
#define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10)
#define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10)
#define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10)
#define R300_CRTC_MICRO_TILE_EN_RIGHT(1 << 12)
#define R300_CRTC_MICRO_TILE_EN(1 << 13)
#define R300_CRTC_MACRO_TILE_EN_RIGHT(1 << 14)
# define R300_CRTC_MACRO_TILE_EN (1 << 15)
# define RADEON_CRTC_TILE_EN_RIGHT (1 << 14)
# define RADEON_CRTC_TILE_EN (1 << 15)
# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
# define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)
#define R300_CRTC_TILE_X0_Y0 0x0350
#define R300_CRTC2_TILE_X0_Y0 0x0358
#define RADEON_CRTC2_OFFSET_CNTL 0x0328
# define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16)
# define RADEON_CRTC2_TILE_EN (1 << 15)
#define RADEON_CRTC_PITCH 0x022c
#define RADEON_CRTC_PITCH__SHIFT 0
#define RADEON_CRTC_PITCH__RIGHT_SHIFT16
#define RADEON_CRTC2_PITCH 0x032c
#define RADEON_CRTC_STATUS 0x005c
# define RADEON_CRTC_VBLANK_SAVE (1 << 1)
# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1)
#define RADEON_CRTC2_STATUS 0x03fc
# define RADEON_CRTC2_VBLANK_SAVE (1 << 1)
# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1)
#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c
# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0)
# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0
# define RADEON_CRTC_V_SYNC_WID (0x1f << 16)
# define RADEON_CRTC_V_SYNC_WID_SHIFT 16
# define RADEON_CRTC_V_SYNC_POL (1 << 23)
#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c
# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0)
# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0
# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16)
# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16
# define RADEON_CRTC2_V_SYNC_POL (1 << 23)
#define RADEON_CRTC_V_TOTAL_DISP 0x0208
# define RADEON_CRTC_V_TOTAL (0x07ff << 0)
# define RADEON_CRTC_V_TOTAL_SHIFT 0
# define RADEON_CRTC_V_DISP (0x07ff << 16)
# define RADEON_CRTC_V_DISP_SHIFT 16
#define RADEON_CRTC2_V_TOTAL_DISP 0x0308
# define RADEON_CRTC2_V_TOTAL (0x07ff << 0)
# define RADEON_CRTC2_V_TOTAL_SHIFT 0
# define RADEON_CRTC2_V_DISP (0x07ff << 16)
# define RADEON_CRTC2_V_DISP_SHIFT 16
#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210
# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16)
#define RADEON_CRTC2_CRNT_FRAME 0x0314
#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318
#define RADEON_CRTC2_STATUS 0x03fc
#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310
#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */
#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */
#define RADEON_CUR_CLR0 0x026c
#define RADEON_CUR_CLR1 0x0270
#define RADEON_CUR_HORZ_VERT_OFF 0x0268
#define RADEON_CUR_HORZ_VERT_POSN 0x0264
#define RADEON_CUR_OFFSET 0x0260
# define RADEON_CUR_LOCK (1 << 31)
#define RADEON_CUR2_CLR0 0x036c
#define RADEON_CUR2_CLR1 0x0370
#define RADEON_CUR2_HORZ_VERT_OFF 0x0368
#define RADEON_CUR2_HORZ_VERT_POSN 0x0364
#define RADEON_CUR2_OFFSET 0x0360
# define RADEON_CUR2_LOCK (1 << 31)
#define RADEON_DAC_CNTL 0x0058
# define RADEON_DAC_RANGE_CNTL (3 << 0)
# define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0)
# define RADEON_DAC_RANGE_CNTL_MASK 0x03
# define RADEON_DAC_BLANKING (1 << 2)
# define RADEON_DAC_CMP_EN (1 << 3)
# define RADEON_DAC_CMP_OUTPUT (1 << 7)
# define RADEON_DAC_8BIT_EN (1 << 8)
# define RADEON_DAC_TVO_EN (1 << 10)
# define RADEON_DAC_VGA_ADR_EN (1 << 13)
# define RADEON_DAC_PDWN (1 << 15)
# define RADEON_DAC_MASK_ALL (0xff << 24)
#define RADEON_DAC_CNTL2 0x007c
# define RADEON_DAC2_TV_CLK_SEL (0 << 1)
# define RADEON_DAC2_DAC_CLK_SEL (1 << 0)
# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1)
# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)
# define RADEON_DAC2_CMP_EN (1 << 7)
# define RADEON_DAC2_CMP_OUT_R (1 << 8)
# define RADEON_DAC2_CMP_OUT_G (1 << 9)
# define RADEON_DAC2_CMP_OUT_B (1 << 10)
# define RADEON_DAC2_CMP_OUTPUT (1 << 11)
#define RADEON_DAC_EXT_CNTL 0x0280
# define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)
# define RADEON_DAC2_FORCE_DATA_EN (1 << 1)
# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)
# define RADEON_DAC_FORCE_DATA_EN (1 << 5)
# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)
# define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6)
# define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6)
# define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6)
# define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6)
# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00
# define RADEON_DAC_FORCE_DATA_SHIFT 8
#define RADEON_DAC_MACRO_CNTL 0x0d04
# define RADEON_DAC_PDWN_R (1 << 16)
# define RADEON_DAC_PDWN_G (1 << 17)
# define RADEON_DAC_PDWN_B (1 << 18)
#define RADEON_TV_DAC_CNTL 0x088c
# define RADEON_TV_DAC_NBLANK (1 << 0)
# define RADEON_TV_DAC_NHOLD (1 << 1)
# define RADEON_TV_DAC_PEDESTAL (1 << 2)
# define RADEON_TV_MONITOR_DETECT_EN (1 << 4)
# define RADEON_TV_DAC_CMPOUT (1 << 5)
# define RADEON_TV_DAC_STD_MASK (3 << 8)
# define RADEON_TV_DAC_STD_PAL (0 << 8)
# define RADEON_TV_DAC_STD_NTSC (1 << 8)
# define RADEON_TV_DAC_STD_PS2 (2 << 8)
# define RADEON_TV_DAC_STD_RS343 (3 << 8)
# define RADEON_TV_DAC_BGSLEEP (1 << 6)
# define RADEON_TV_DAC_BGADJ_MASK (0xf << 16)
# define RADEON_TV_DAC_BGADJ_SHIFT 16
# define RADEON_TV_DAC_DACADJ_MASK (0xf << 20)
# define RADEON_TV_DAC_DACADJ_SHIFT 20
# define RADEON_TV_DAC_RDACPD (1 << 24)
# define RADEON_TV_DAC_GDACPD (1 << 25)
# define RADEON_TV_DAC_BDACPD (1 << 26)
# define RADEON_TV_DAC_RDACDET (1 << 29)
# define RADEON_TV_DAC_GDACDET (1 << 30)
# define RADEON_TV_DAC_BDACDET (1 << 31)
# define R420_TV_DAC_DACADJ_MASK (0x1f << 20)
# define R420_TV_DAC_RDACPD (1 << 25)
# define R420_TV_DAC_GDACPD (1 << 26)
# define R420_TV_DAC_BDACPD (1 << 27)
# define R420_TV_DAC_TVENABLE (1 << 28)
#define RADEON_DISP_HW_DEBUG 0x0d14
# define RADEON_CRT2_DISP1_SEL (1 << 5)
#define RADEON_DISP_OUTPUT_CNTL 0x0d64
# define RADEON_DISP_DAC_SOURCE_MASK 0x03
# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c
# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
# define RADEON_DISP_DAC_SOURCE_RMX 0x02
# define RADEON_DISP_DAC_SOURCE_LTU 0x03
# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04
# define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2)
# define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0
# define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2)
# define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2)
# define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2)
# define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4)
# define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4)
# define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4)
# define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4)
# define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */
# define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */
#define RADEON_DISP_TV_OUT_CNTL 0x0d6c
# define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16)
# define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)
#define RADEON_DAC_CRC_SIG 0x02cc
#define RADEON_DAC_DATA 0x03c9 /* VGA */
#define RADEON_DAC_MASK 0x03c6 /* VGA */
#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */
#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */
#define RADEON_DDA_CONFIG 0x02e0
#define RADEON_DDA_ON_OFF 0x02e4
#define RADEON_DEFAULT_OFFSET 0x16e0
#define RADEON_DEFAULT_PITCH 0x16e4
#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820
#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824
#define RADEON_DEVICE_ID 0x0f02 /* PCI */
#define RADEON_DISP_MISC_CNTL 0x0d00
# define RADEON_SOFT_RESET_GRPH_PP (1 << 0)
#define RADEON_DISP_MERGE_CNTL 0x0d60
# define RADEON_DISP_ALPHA_MODE_MASK 0x03
# define RADEON_DISP_ALPHA_MODE_KEY 0
# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1
# define RADEON_DISP_ALPHA_MODE_GLOBAL 2
# define RADEON_DISP_RGB_OFFSET_EN (1 << 8)
# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)
# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)
#define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)
#define RADEON_DISP2_MERGE_CNTL 0x0d68
# define RADEON_DISP2_RGB_OFFSET_EN (1 << 8)
#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80
#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84
#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88
#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c
#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90
#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98
#define RADEON_DP_BRUSH_BKGD_CLR 0x1478
#define RADEON_DP_BRUSH_FRGD_CLR 0x147c
#define RADEON_DP_CNTL 0x16c0
# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)
# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)
# define RADEON_DP_DST_TILE_LINEAR (0 << 3)
# define RADEON_DP_DST_TILE_MACRO (1 << 3)
# define RADEON_DP_DST_TILE_MICRO (2 << 3)
# define RADEON_DP_DST_TILE_BOTH (3 << 3)
#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
# define RADEON_DST_Y_MAJOR (1 << 2)
# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
#define RADEON_DP_DATATYPE 0x16c4
# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)
#define RADEON_DP_GUI_MASTER_CNTL 0x146c
# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
# define RADEON_GMC_SRC_CLIPPING (1 << 2)
# define RADEON_GMC_DST_CLIPPING (1 << 3)
# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)
# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)
# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)
# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)
# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)
# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)
# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)
# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)
# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)
# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4)
# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4)
# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
# define RADEON_GMC_BRUSH_NONE (15 << 4)
# define RADEON_GMC_DST_8BPP_CI (2 << 8)
# define RADEON_GMC_DST_15BPP (3 << 8)
# define RADEON_GMC_DST_16BPP (4 << 8)
# define RADEON_GMC_DST_24BPP (5 << 8)
# define RADEON_GMC_DST_32BPP (6 << 8)
# define RADEON_GMC_DST_8BPP_RGB (7 << 8)
# define RADEON_GMC_DST_Y8 (8 << 8)
# define RADEON_GMC_DST_RGB8 (9 << 8)
# define RADEON_GMC_DST_VYUY (11 << 8)
# define RADEON_GMC_DST_YVYU (12 << 8)
# define RADEON_GMC_DST_AYUV444 (14 << 8)
# define RADEON_GMC_DST_ARGB4444 (15 << 8)
# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8)
# define RADEON_GMC_DST_DATATYPE_SHIFT 8
# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12)
# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14)
# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14)
# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14)
# define RADEON_GMC_CONVERSION_TEMP (1 << 15)
# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15)
# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15)
# define RADEON_GMC_ROP3_MASK (0xff << 16)
# define RADEON_DP_SRC_SOURCE_MASK (7 << 24)
# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
# define RADEON_GMC_3D_FCN_EN (1 << 27)
# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
# define RADEON_GMC_AUX_CLIP_DIS (1 << 29)
# define RADEON_GMC_WR_MSK_DIS (1 << 30)
# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31)
# define RADEON_ROP3_ZERO 0x00000000
# define RADEON_ROP3_DSa 0x00880000
# define RADEON_ROP3_SDna 0x00440000
# define RADEON_ROP3_S 0x00cc0000
# define RADEON_ROP3_DSna 0x00220000
# define RADEON_ROP3_D 0x00aa0000
# define RADEON_ROP3_DSx 0x00660000
# define RADEON_ROP3_DSo 0x00ee0000
# define RADEON_ROP3_DSon 0x00110000
# define RADEON_ROP3_DSxn 0x00990000
# define RADEON_ROP3_Dn 0x00550000
# define RADEON_ROP3_SDno 0x00dd0000
# define RADEON_ROP3_Sn 0x00330000
# define RADEON_ROP3_DSno 0x00bb0000
# define RADEON_ROP3_DSan 0x00770000
# define RADEON_ROP3_ONE 0x00ff0000
# define RADEON_ROP3_DPa 0x00a00000
# define RADEON_ROP3_PDna 0x00500000
# define RADEON_ROP3_P 0x00f00000
# define RADEON_ROP3_DPna 0x000a0000
# define RADEON_ROP3_D 0x00aa0000
# define RADEON_ROP3_DPx 0x005a0000
# define RADEON_ROP3_DPo 0x00fa0000
# define RADEON_ROP3_DPon 0x00050000
# define RADEON_ROP3_PDxn 0x00a50000
# define RADEON_ROP3_PDno 0x00f50000
# define RADEON_ROP3_Pn 0x000f0000
# define RADEON_ROP3_DPno 0x00af0000
# define RADEON_ROP3_DPan 0x005f0000
#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84
#define RADEON_DP_MIX 0x16c8
#define RADEON_DP_SRC_BKGD_CLR 0x15dc
#define RADEON_DP_SRC_FRGD_CLR 0x15d8
#define RADEON_DP_WRITE_MASK 0x16cc
#define RADEON_DST_BRES_DEC 0x1630
#define RADEON_DST_BRES_ERR 0x1628
#define RADEON_DST_BRES_INC 0x162c
#define RADEON_DST_BRES_LNTH 0x1634
#define RADEON_DST_BRES_LNTH_SUB 0x1638
#define RADEON_DST_HEIGHT 0x1410
#define RADEON_DST_HEIGHT_WIDTH 0x143c
#define RADEON_DST_HEIGHT_WIDTH_8 0x158c
#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4
#define RADEON_DST_HEIGHT_Y 0x15a0
#define RADEON_DST_LINE_START 0x1600
#define RADEON_DST_LINE_END 0x1604
#define RADEON_DST_LINE_PATCOUNT 0x1608
# define RADEON_BRES_CNTL_SHIFT 8
#define RADEON_DST_OFFSET 0x1404
#define RADEON_DST_PITCH 0x1408
#define RADEON_DST_PITCH_OFFSET 0x142c
#define RADEON_DST_PITCH_OFFSET_C 0x1c80
# define RADEON_PITCH_SHIFT 21
# define RADEON_DST_TILE_LINEAR (0 << 30)
# define RADEON_DST_TILE_MACRO (1 << 30)
# define RADEON_DST_TILE_MICRO (2 << 30)
# define RADEON_DST_TILE_BOTH (3 << 30)
#define RADEON_DST_WIDTH 0x140c
#define RADEON_DST_WIDTH_HEIGHT 0x1598
#define RADEON_DST_WIDTH_X 0x1588
#define RADEON_DST_WIDTH_X_INCY 0x159c
#define RADEON_DST_X 0x141c
#define RADEON_DST_X_SUB 0x15a4
#define RADEON_DST_X_Y 0x1594
#define RADEON_DST_Y 0x1420
#define RADEON_DST_Y_SUB 0x15a8
#define RADEON_DST_Y_X 0x1438
#define RADEON_FCP_CNTL 0x0910
# define RADEON_FCP0_SRC_PCICLK 0
# define RADEON_FCP0_SRC_PCLK 1
# define RADEON_FCP0_SRC_PCLKb 2
# define RADEON_FCP0_SRC_HREF 3
# define RADEON_FCP0_SRC_GND 4
# define RADEON_FCP0_SRC_HREFb 5
#define RADEON_FLUSH_1 0x1704
#define RADEON_FLUSH_2 0x1708
#define RADEON_FLUSH_3 0x170c
#define RADEON_FLUSH_4 0x1710
#define RADEON_FLUSH_5 0x1714
#define RADEON_FLUSH_6 0x1718
#define RADEON_FLUSH_7 0x171c
#define RADEON_FOG_3D_TABLE_START 0x1810
#define RADEON_FOG_3D_TABLE_END 0x1814
#define RADEON_FOG_3D_TABLE_DENSITY 0x181c
#define RADEON_FOG_TABLE_INDEX 0x1a14
#define RADEON_FOG_TABLE_DATA 0x1a18
#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250
#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254
# define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff
# define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000
# define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff
# define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000
# define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
# define RADEON_FP_H_SYNC_WID_MASK 0x003f0000
# define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff
# define RADEON_FP_V_SYNC_WID_MASK 0x001f0000
# define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000
# define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010
# define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000
# define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010
# define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
# define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010
# define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000
# define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010
#define RADEON_FP_GEN_CNTL 0x0284
# define RADEON_FP_FPON (1 << 0)
# define RADEON_FP_BLANK_EN (1 << 1)
# define RADEON_FP_TMDS_EN (1 << 2)
# define RADEON_FP_PANEL_FORMAT (1 << 3)
# define RADEON_FP_EN_TMDS (1 << 7)
# define RADEON_FP_DETECT_SENSE (1 << 8)
# define R200_FP_SOURCE_SEL_MASK (3 << 10)
# define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
# define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
# define R200_FP_SOURCE_SEL_RMX (2 << 10)
# define R200_FP_SOURCE_SEL_TRANS (3 << 10)
# define RADEON_FP_SEL_CRTC1 (0 << 13)
# define RADEON_FP_SEL_CRTC2 (1 << 13)
# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
# define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18)
# define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
# define RADEON_FP_DFP_SYNC_SEL (1 << 21)
# define RADEON_FP_CRTC_LOCK_8DOT (1 << 22)
# define RADEON_FP_CRT_SYNC_SEL (1 << 23)
# define RADEON_FP_USE_SHADOW_EN (1 << 24)
# define RADEON_FP_CRT_SYNC_ALT (1 << 26)
#define RADEON_FP2_GEN_CNTL 0x0288
# define RADEON_FP2_BLANK_EN (1 << 1)
# define RADEON_FP2_ON (1 << 2)
# define RADEON_FP2_PANEL_FORMAT (1 << 3)
# define RADEON_FP2_DETECT_SENSE (1 << 8)
# define R200_FP2_SOURCE_SEL_MASK (3 << 10)
# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10)
# define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10)
# define R200_FP2_SOURCE_SEL_RMX (2 << 10)
# define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10)
# define RADEON_FP2_SRC_SEL_MASK (3 << 13)
# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)
# define RADEON_FP2_FP_POL (1 << 16)
# define RADEON_FP2_LP_POL (1 << 17)
# define RADEON_FP2_SCK_POL (1 << 18)
# define RADEON_FP2_LCD_CNTL_MASK (7 << 19)
# define RADEON_FP2_PAD_FLOP_EN (1 << 22)
# define RADEON_FP2_CRC_EN (1 << 23)
# define RADEON_FP2_CRC_READ_EN (1 << 24)
# define RADEON_FP2_DVO_EN (1 << 25)
# define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26)
# define R200_FP2_DVO_RATE_SEL_SDR (1 << 27)
# define R200_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28)
# define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29)
#define RADEON_FP_H_SYNC_STRT_WID 0x02c4
#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4
#define RADEON_FP_HORZ_STRETCH 0x028c
#define RADEON_FP_HORZ2_STRETCH 0x038c
# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff
# define RADEON_HORZ_STRETCH_RATIO_MAX 4096
# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16)
# define RADEON_HORZ_PANEL_SHIFT 16
# define RADEON_HORZ_STRETCH_PIXREP (0 << 25)
# define RADEON_HORZ_STRETCH_BLEND (1 << 26)
# define RADEON_HORZ_STRETCH_ENABLE (1 << 25)
# define RADEON_HORZ_AUTO_RATIO (1 << 27)
# define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28)
# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31)
#define RADEON_FP_HORZ_VERT_ACTIVE 0x0278
#define RADEON_FP_V_SYNC_STRT_WID 0x02c8
#define RADEON_FP_VERT_STRETCH 0x0290
#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8
#define RADEON_FP_VERT2_STRETCH 0x0390
# define RADEON_VERT_PANEL_SIZE (0xfff << 12)
# define RADEON_VERT_PANEL_SHIFT 12
# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff
# define RADEON_VERT_STRETCH_RATIO_SHIFT 0
# define RADEON_VERT_STRETCH_RATIO_MAX 4096
# define RADEON_VERT_STRETCH_ENABLE (1 << 25)
# define RADEON_VERT_STRETCH_LINEREP (0 << 26)
# define RADEON_VERT_STRETCH_BLEND (1 << 26)
# define RADEON_VERT_AUTO_RATIO_EN (1 << 27)
#define RADEON_VERT_AUTO_RATIO_INC (1 << 31)
# define RADEON_VERT_STRETCH_RESERVED 0x71000000
#define RS400_FP_2ND_GEN_CNTL 0x0384
# define RS400_FP_2ND_ON (1 << 0)
# define RS400_FP_2ND_BLANK_EN (1 << 1)
# define RS400_TMDS_2ND_EN (1 << 2)
# define RS400_PANEL_FORMAT_2ND (1 << 3)
# define RS400_FP_2ND_EN_TMDS (1 << 7)
# define RS400_FP_2ND_DETECT_SENSE (1 << 8)
# define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10)
# define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10)
# define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10)
# define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10)
# define RS400_FP_2ND_DETECT_EN (1 << 12)
# define RS400_HPD_2ND_SEL (1 << 13)
#define RS400_FP2_2_GEN_CNTL 0x0388
# define RS400_FP2_2_BLANK_EN (1 << 1)
# define RS400_FP2_2_ON (1 << 2)
# define RS400_FP2_2_PANEL_FORMAT (1 << 3)
# define RS400_FP2_2_DETECT_SENSE (1 << 8)
# define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10)
# define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10)
# define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10)
# define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10)
# define RS400_FP2_2_DVO2_EN (1 << 25)
#define RS400_TMDS2_CNTL 0x0394
#define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4
# define RS400_TMDS2_PLLEN (1 << 0)
# define RS400_TMDS2_PLLRST (1 << 1)
#define RADEON_GEN_INT_CNTL 0x0040
#define RADEON_GEN_INT_STATUS 0x0044
# define RADEON_VSYNC_INT_AK (1 << 2)
# define RADEON_VSYNC_INT (1 << 2)
# define RADEON_VSYNC2_INT_AK (1 << 6)
# define RADEON_VSYNC2_INT (1 << 6)
#define RADEON_GENENB 0x03c3 /* VGA */
#define RADEON_GENFC_RD 0x03ca /* VGA */
#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */
#define RADEON_GENMO_RD 0x03cc /* VGA */
#define RADEON_GENMO_WT 0x03c2 /* VGA */
#define RADEON_GENS0 0x03c2 /* VGA */
#define RADEON_GENS1 0x03da /* VGA, 0x03ba */
#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ /* DDC3 */
#define RADEON_GPIO_MONIDB 0x006c
#define RADEON_GPIO_CRT2_DDC 0x006c
#define RADEON_GPIO_DVI_DDC 0x0064 /* DDC2 */
#define RADEON_GPIO_VGA_DDC 0x0060 /* DDC1 */
# define RADEON_GPIO_A_0 (1 << 0)
# define RADEON_GPIO_A_1 (1 << 1)
# define RADEON_GPIO_Y_0 (1 << 8)
# define RADEON_GPIO_Y_1 (1 << 9)
# define RADEON_GPIO_Y_SHIFT_0 8
# define RADEON_GPIO_Y_SHIFT_1 9
# define RADEON_GPIO_EN_0 (1 << 16)
# define RADEON_GPIO_EN_1 (1 << 17)
# define RADEON_GPIO_MASK_0 (1 << 24) /*??*/
# define RADEON_GPIO_MASK_1 (1 << 25) /*??*/
#define RADEON_GRPH8_DATA 0x03cf /* VGA */
#define RADEON_GRPH8_IDX 0x03ce /* VGA */
#define RADEON_GUI_SCRATCH_REG0 0x15e0
#define RADEON_GUI_SCRATCH_REG1 0x15e4
#define RADEON_GUI_SCRATCH_REG2 0x15e8
#define RADEON_GUI_SCRATCH_REG3 0x15ec
#define RADEON_GUI_SCRATCH_REG4 0x15f0
#define RADEON_GUI_SCRATCH_REG5 0x15f4
#define RADEON_HEADER 0x0f0e /* PCI */
#define RADEON_HOST_DATA0 0x17c0
#define RADEON_HOST_DATA1 0x17c4
#define RADEON_HOST_DATA2 0x17c8
#define RADEON_HOST_DATA3 0x17cc
#define RADEON_HOST_DATA4 0x17d0
#define RADEON_HOST_DATA5 0x17d4
#define RADEON_HOST_DATA6 0x17d8
#define RADEON_HOST_DATA7 0x17dc
#define RADEON_HOST_DATA_LAST 0x17e0
#define RADEON_HOST_PATH_CNTL 0x0130
# define RADEON_HDP_SOFT_RESET (1 << 26)
# define RADEON_HDP_APER_CNTL (1 << 23)
#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */
# define RADEON_HTOT_CNTL_VGA_EN (1 << 28)
#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */
/* Multimedia I2C bus */
#define RADEON_I2C_CNTL_0 0x0090
#define RADEON_I2C_DONE (1 << 0)
#define RADEON_I2C_NACK (1 << 1)
#define RADEON_I2C_HALT (1 << 2)
#define RADEON_I2C_SOFT_RST (1 << 5)
#define RADEON_I2C_DRIVE_EN (1 << 6)
#define RADEON_I2C_DRIVE_SEL (1 << 7)
#define RADEON_I2C_START (1 << 8)
#define RADEON_I2C_STOP (1 << 9)
#define RADEON_I2C_RECEIVE (1 << 10)
#define RADEON_I2C_ABORT (1 << 11)
#define RADEON_I2C_GO (1 << 12)
#define RADEON_I2C_CNTL_1 0x0094
#define RADEON_I2C_SEL (1 << 16)
#define RADEON_I2C_EN (1 << 17)
#define RADEON_I2C_DATA 0x0098
#define RADEON_DVI_I2C_CNTL_0 0x02e0
# define R200_DVI_I2C_PIN_SEL(x) ((x) << 3)
# define R200_SEL_DDC1 0 /* 0x60 - VGA_DDC */
# define R200_SEL_DDC2 1 /* 0x64 - DVI_DDC */
# define R200_SEL_DDC3 2 /* 0x68 - MONID_DDC */
#define RADEON_DVI_I2C_CNTL_1 0x02e4
#define RADEON_DVI_I2C_DATA 0x02e8
#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */
#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */
#define RADEON_IO_BASE 0x0f14 /* PCI */
#define RADEON_LATENCY 0x0f0d /* PCI */
#define RADEON_LEAD_BRES_DEC 0x1608
#define RADEON_LEAD_BRES_LNTH 0x161c
#define RADEON_LEAD_BRES_LNTH_SUB 0x1624
#define RADEON_LVDS_GEN_CNTL 0x02d0
# define RADEON_LVDS_ON (1 << 0)
# define RADEON_LVDS_DISPLAY_DIS (1 << 1)
# define RADEON_LVDS_PANEL_TYPE (1 << 2)
# define RADEON_LVDS_PANEL_FORMAT (1 << 3)
# define RADEON_LVDS_RST_FM (1 << 6)
# define RADEON_LVDS_EN (1 << 7)
# define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8
# define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)
# define RADEON_LVDS_BL_MOD_EN (1 << 16)
# define RADEON_LVDS_DIGON (1 << 18)
# define RADEON_LVDS_BLON (1 << 19)
# define RADEON_LVDS_SEL_CRTC2 (1 << 23)
#define RADEON_LVDS_PLL_CNTL 0x02d4
# define RADEON_HSYNC_DELAY_SHIFT 28
# define RADEON_HSYNC_DELAY_MASK (0xf << 28)
# define RADEON_LVDS_PLL_EN (1 << 16)
# define RADEON_LVDS_PLL_RESET (1 << 17)
# define R300_LVDS_SRC_SEL_MASK (3 << 18)
# define R300_LVDS_SRC_SEL_CRTC1 (0 << 18)
# define R300_LVDS_SRC_SEL_CRTC2 (1 << 18)
# define R300_LVDS_SRC_SEL_RMX (2 << 18)
#define RADEON_MAX_LATENCY 0x0f3f /* PCI */
#define RADEON_MC_AGP_LOCATION 0x014c
#define RADEON_MC_FB_LOCATION 0x0148
#define RADEON_DISPLAY_BASE_ADDR 0x23c
#define RADEON_DISPLAY2_BASE_ADDR 0x33c
#define RADEON_OV0_BASE_ADDR 0x43c
#define RADEON_NB_TOM 0x15c
#define R300_MC_INIT_MISC_LAT_TIMER 0x180
# define R300_MC_DISP0R_INIT_LAT_SHIFT 8
# define R300_MC_DISP0R_INIT_LAT_MASK 0xf
# define R300_MC_DISP1R_INIT_LAT_SHIFT 12
# define R300_MC_DISP1R_INIT_LAT_MASK 0xf
#define RADEON_MCLK_CNTL 0x0012 /* PLL */
# define RADEON_FORCEON_MCLKA (1 << 16)
# define RADEON_FORCEON_MCLKB (1 << 17)
# define RADEON_FORCEON_YCLKA (1 << 18)
# define RADEON_FORCEON_YCLKB (1 << 19)
# define RADEON_FORCEON_MC (1 << 20)
# define RADEON_FORCEON_AIC (1 << 21)
# define R300_DISABLE_MC_MCLKA (1 << 21)
# define R300_DISABLE_MC_MCLKB (1 << 21)
#define RADEON_MCLK_MISC 0x001f /* PLL */
# define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12)
# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13)
# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14)
# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15)
#define RADEON_LCD_GPIO_MASK 0x01a0
#define RADEON_GPIOPAD_EN 0x01a0
#define RADEON_LCD_GPIO_Y_REG 0x01a4
#define RADEON_MDGPIO_A_REG 0x01ac
#define RADEON_MDGPIO_EN_REG 0x01b0
#define RADEON_MDGPIO_MASK 0x0198
#define RADEON_GPIOPAD_MASK 0x0198
#define RADEON_GPIOPAD_A 0x019c
#define RADEON_MDGPIO_Y_REG 0x01b4
#define RADEON_MEM_ADDR_CONFIG 0x0148
#define RADEON_MEM_BASE 0x0f10 /* PCI */
#define RADEON_MEM_CNTL 0x0140
# define RADEON_MEM_NUM_CHANNELS_MASK 0x01
# define RADEON_MEM_USE_B_CH_ONLY (1 << 1)
# define RV100_HALF_MODE (1 << 3)
# define R300_MEM_NUM_CHANNELS_MASK 0x03
# define R300_MEM_USE_CD_CH_ONLY (1 << 2)
#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */
#define RADEON_MEM_INIT_LAT_TIMER 0x0154
#define RADEON_MEM_INTF_CNTL 0x014c
#define RADEON_MEM_SDRAM_MODE_REG 0x0158
# define RADEON_SDRAM_MODE_MASK 0xffff0000
# define RADEON_B3MEM_RESET_MASK 0x6fffffff
# define RADEON_MEM_CFG_TYPE_DDR (1 << 30)
#define RADEON_MEM_STR_CNTL 0x0150
# define RADEON_MEM_PWRUP_COMPL_A (1 << 0)
# define RADEON_MEM_PWRUP_COMPL_B (1 << 1)
# define R300_MEM_PWRUP_COMPL_C (1 << 2)
# define R300_MEM_PWRUP_COMPL_D (1 << 3)
# define RADEON_MEM_PWRUP_COMPLETE 0x03
# define R300_MEM_PWRUP_COMPLETE 0x0f
#define RADEON_MC_STATUS 0x0150
# define RADEON_MC_IDLE (1 << 2)
# define R300_MC_IDLE (1 << 4)
#define RADEON_MEM_VGA_RP_SEL 0x003c
#define RADEON_MEM_VGA_WP_SEL 0x0038
#define RADEON_MIN_GRANT 0x0f3e /* PCI */
#define RADEON_MM_DATA 0x0004
#define RADEON_MM_INDEX 0x0000
#define RADEON_MPLL_CNTL 0x000e /* PLL */
#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */
#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */
#define RADEON_SEPROM_CNTL1 0x01c0
# define RADEON_SCK_PRESCALE_SHIFT 24
# define RADEON_SCK_PRESCALE_MASK (0xff << 24)
#define R300_MC_IND_INDEX 0x01f8
# define R300_MC_IND_ADDR_MASK 0x3f
# define R300_MC_IND_WR_EN (1 << 8)
#define R300_MC_IND_DATA 0x01fc
#define R300_MC_READ_CNTL_AB 0x017c
# define R300_MEM_RBS_POSITION_A_MASK 0x03
#define R300_MC_READ_CNTL_CD_mcind 0x24
# define R300_MEM_RBS_POSITION_C_MASK 0x03
#define RADEON_N_VIF_COUNT 0x0248
#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470
# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007
# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008
# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010
# define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020
# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040
# define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300
# define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000
# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000
# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000
# define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000
#define RADEON_OV0_COLOUR_CNTL 0x04E0
#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474
#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408
# define RADEON_EXCL_HORZ_START_MASK 0x000000ff
# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00
# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000
# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000
#define RADEON_OV0_EXCLUSIVE_VERT 0x040C
# define RADEON_EXCL_VERT_START_MASK 0x000003ff
# define RADEON_EXCL_VERT_END_MASK 0x03ff0000
#define RADEON_OV0_FILTER_CNTL 0x04A0
# define RADEON_FILTER_PROGRAMMABLE_COEF 0x0
# define RADEON_FILTER_HC_COEF_HORZ_Y 0x1
# define RADEON_FILTER_HC_COEF_HORZ_UV 0x2
# define RADEON_FILTER_HC_COEF_VERT_Y 0x4
# define RADEON_FILTER_HC_COEF_VERT_UV 0x8
# define RADEON_FILTER_HARDCODED_COEF 0xf
# define RADEON_FILTER_COEF_MASK 0xf
#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0
#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4
#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8
#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC
#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0
#define RADEON_OV0_FLAG_CNTL 0x04DC
#define RADEON_OV0_GAMMA_000_00F 0x0d40
#define RADEON_OV0_GAMMA_010_01F 0x0d44
#define RADEON_OV0_GAMMA_020_03F 0x0d48
#define RADEON_OV0_GAMMA_040_07F 0x0d4c
#define RADEON_OV0_GAMMA_080_0BF 0x0e00
#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04
#define RADEON_OV0_GAMMA_100_13F 0x0e08
#define RADEON_OV0_GAMMA_140_17F 0x0e0c
#define RADEON_OV0_GAMMA_180_1BF 0x0e10
#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14
#define RADEON_OV0_GAMMA_200_23F 0x0e18
#define RADEON_OV0_GAMMA_240_27F 0x0e1c
#define RADEON_OV0_GAMMA_280_2BF 0x0e20
#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24
#define RADEON_OV0_GAMMA_300_33F 0x0e28
#define RADEON_OV0_GAMMA_340_37F 0x0e2c
#define RADEON_OV0_GAMMA_380_3BF 0x0d50
#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54
#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC
#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0
#define RADEON_OV0_H_INC 0x0480
#define RADEON_OV0_KEY_CNTL 0x04F4
# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L
# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L
# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L
# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L
# define RADEON_VIDEO_KEY_FN_NE 0x00000003L
# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L
# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L
# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L
# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L
# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L
# define RADEON_CMP_MIX_MASK 0x00000100L
# define RADEON_CMP_MIX_OR 0x00000000L
# define RADEON_CMP_MIX_AND 0x00000100L
#define RADEON_OV0_LIN_TRANS_A 0x0d20
#define RADEON_OV0_LIN_TRANS_B 0x0d24
#define RADEON_OV0_LIN_TRANS_C 0x0d28
#define RADEON_OV0_LIN_TRANS_D 0x0d2c
#define RADEON_OV0_LIN_TRANS_E 0x0d30
#define RADEON_OV0_LIN_TRANS_F 0x0d34
#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430
# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL
# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L
#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488
#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428
# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L
# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L
#define RADEON_OV0_P1_X_START_END 0x0494
#define RADEON_OV0_P2_X_START_END 0x0498
#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434
# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL
# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L
#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C
#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C
#define RADEON_OV0_P3_X_START_END 0x049C
#define RADEON_OV0_REG_LOAD_CNTL 0x0410
# define RADEON_REG_LD_CTL_LOCK 0x00000001L
# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L
# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L
# define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L
#define RADEON_OV0_SCALE_CNTL 0x0420
# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L
# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L
# define RADEON_SCALER_SIGNED_UV 0x00000010L
# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L
# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L
# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L
# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L
# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L
# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L
# define RADEON_SCALER_SOURCE_15BPP 0x00000300L
# define RADEON_SCALER_SOURCE_16BPP 0x00000400L
# define RADEON_SCALER_SOURCE_32BPP 0x00000600L
# define RADEON_SCALER_SOURCE_YUV9 0x00000900L
# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L
# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L
# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L
# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L
# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L
# define RADEON_SCALER_CRTC_SEL 0x00004000L
# define RADEON_SCALER_SMART_SWITCH 0x00008000L
# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L
# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L
# define RADEON_SCALER_DIS_LIMIT 0x08000000L
# define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L
# define RADEON_SCALER_INT_EMU 0x20000000L
# define RADEON_SCALER_ENABLE 0x40000000L
# define RADEON_SCALER_SOFT_RESET 0x80000000L
#define RADEON_OV0_STEP_BY 0x0484
#define RADEON_OV0_TEST 0x04F8
#define RADEON_OV0_V_INC 0x0424
#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460
#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464
#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440
# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L
# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L
# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L
# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444
# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L
# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L
# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L
# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448
# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L
# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L
# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L
# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C
#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450
#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454
#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8
#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4
#define RADEON_OV0_Y_X_START 0x0400
#define RADEON_OV0_Y_X_END 0x0404
#define RADEON_OV1_Y_X_START 0x0600
#define RADEON_OV1_Y_X_END 0x0604
#define RADEON_OVR_CLR 0x0230
#define RADEON_OVR_WID_LEFT_RIGHT 0x0234
#define RADEON_OVR_WID_TOP_BOTTOM 0x0238
/* first capture unit */
#define RADEON_CAP0_BUF0_OFFSET 0x0920
#define RADEON_CAP0_BUF1_OFFSET 0x0924
#define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928
#define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C
#define RADEON_CAP0_BUF_PITCH 0x0930
#define RADEON_CAP0_V_WINDOW 0x0934
#define RADEON_CAP0_H_WINDOW 0x0938
#define RADEON_CAP0_VBI0_OFFSET 0x093C
#define RADEON_CAP0_VBI1_OFFSET 0x0940
#define RADEON_CAP0_VBI_V_WINDOW 0x0944
#define RADEON_CAP0_VBI_H_WINDOW 0x0948
#define RADEON_CAP0_PORT_MODE_CNTL 0x094C
#define RADEON_CAP0_TRIG_CNTL 0x0950
#define RADEON_CAP0_DEBUG 0x0954
#define RADEON_CAP0_CONFIG 0x0958
# define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001
# define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002
# define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004
# define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008
# define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010
# define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020
# define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040
# define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080
# define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100
# define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200
# define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400
# define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800
# define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000
# define RADEON_CAP0_CONFIG_VBI_EN 0x00002000
# define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000
# define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000
# define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000
# define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000
# define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000
# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000
# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000
# define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000
# define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000
# define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000
# define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000
# define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000
# define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000
# define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000
# define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000
# define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000
# define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000
# define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000
# define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000
#define RADEON_CAP0_ANC_ODD_OFFSET 0x095C
#define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960
#define RADEON_CAP0_ANC_H_WINDOW 0x0964
#define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968
#define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C
#define RADEON_CAP0_BUF_STATUS 0x0970
/* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */
/* #define RADEON_CAP0_XSHARPNESS 0x097C */
#define RADEON_CAP0_VBI2_OFFSET 0x0980
#define RADEON_CAP0_VBI3_OFFSET 0x0984
#define RADEON_CAP0_ANC2_OFFSET 0x0988
#define RADEON_CAP0_ANC3_OFFSET 0x098C
#define RADEON_VID_BUFFER_CONTROL 0x0900
/* second capture unit */
#define RADEON_CAP1_BUF0_OFFSET 0x0990
#define RADEON_CAP1_BUF1_OFFSET 0x0994
#define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998
#define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C
#define RADEON_CAP1_BUF_PITCH 0x09A0
#define RADEON_CAP1_V_WINDOW 0x09A4
#define RADEON_CAP1_H_WINDOW 0x09A8
#define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC
#define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0
#define RADEON_CAP1_VBI_V_WINDOW 0x09B4
#define RADEON_CAP1_VBI_H_WINDOW 0x09B8
#define RADEON_CAP1_PORT_MODE_CNTL 0x09BC
#define RADEON_CAP1_TRIG_CNTL 0x09C0
#define RADEON_CAP1_DEBUG 0x09C4
#define RADEON_CAP1_CONFIG 0x09C8
#define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC
#define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0
#define RADEON_CAP1_ANC_H_WINDOW 0x09D4
#define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8
#define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC
#define RADEON_CAP1_BUF_STATUS 0x09E0
#define RADEON_CAP1_DWNSC_XRATIO 0x09E8
#define RADEON_CAP1_XSHARPNESS 0x09EC
/* misc multimedia registers */
#define RADEON_IDCT_RUNS 0x1F80
#define RADEON_IDCT_LEVELS 0x1F84
#define RADEON_IDCT_CONTROL 0x1FBC
#define RADEON_IDCT_AUTH_CONTROL 0x1F88
#define RADEON_IDCT_AUTH 0x1F8C
#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */
# define RADEON_P2PLL_RESET (1 << 0)
# define RADEON_P2PLL_SLEEP (1 << 1)
# define RADEON_P2PLL_PVG_MASK (7 << 11)
# define RADEON_P2PLL_PVG_SHIFT 11
# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16)
# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)
#define RADEON_P2PLL_DIV_0 0x002c
# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff
# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000
#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */
# define RADEON_P2PLL_REF_DIV_MASK 0x03ff
# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
# define R300_PPLL_REF_DIV_ACC_SHIFT 18
#define RADEON_PALETTE_DATA 0x00b4
#define RADEON_PALETTE_30_DATA 0x00b8
#define RADEON_PALETTE_INDEX 0x00b0
#define RADEON_PCI_GART_PAGE 0x017c
#define RADEON_PIXCLKS_CNTL 0x002d
# define RADEON_PIX2CLK_SRC_SEL_MASK 0x03
# define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00
# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01
# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02
# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03
# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6)
# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7)
# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8)
# define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)
# define R300_DVOCLK_ALWAYS_ONb (1 << 10)
# define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11)
# define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12)
# define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13)
# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)
# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)
# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)
# define R300_P2G2CLK_ALWAYS_ONb (1 << 18)
# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)
# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
#define RADEON_PLANE_3D_MASK_C 0x1d44
#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */
# define RADEON_PLL_MASK_READ_B (1 << 9)
#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */
#define RADEON_PMI_DATA 0x0f63 /* PCI */
#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */
#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */
#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */
#define RADEON_PMI_REGISTER 0x0f5c /* PCI */
#define RADEON_PPLL_CNTL 0x0002 /* PLL */
# define RADEON_PPLL_RESET (1 << 0)
# define RADEON_PPLL_SLEEP (1 << 1)
# define RADEON_PPLL_PVG_MASK (7 << 11)
# define RADEON_PPLL_PVG_SHIFT 11
# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16)
# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)
#define RADEON_PPLL_DIV_0 0x0004 /* PLL */
#define RADEON_PPLL_DIV_1 0x0005 /* PLL */
#define RADEON_PPLL_DIV_2 0x0006 /* PLL */
#define RADEON_PPLL_DIV_3 0x0007 /* PLL */
# define RADEON_PPLL_FB3_DIV_MASK 0x07ff
# define RADEON_PPLL_POST3_DIV_MASK 0x00070000
#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */
# define RADEON_PPLL_REF_DIV_MASK 0x03ff
# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */
#define RADEON_RBBM_GUICNTL 0x172c
# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
#define RADEON_RBBM_SOFT_RESET 0x00f0
# define RADEON_SOFT_RESET_CP (1 << 0)
# define RADEON_SOFT_RESET_HI (1 << 1)
# define RADEON_SOFT_RESET_SE (1 << 2)
# define RADEON_SOFT_RESET_RE (1 << 3)
# define RADEON_SOFT_RESET_PP (1 << 4)
# define RADEON_SOFT_RESET_E2 (1 << 5)
# define RADEON_SOFT_RESET_RB (1 << 6)
# define RADEON_SOFT_RESET_HDP (1 << 7)
#define RADEON_RBBM_STATUS 0x0e40
# define RADEON_RBBM_FIFOCNT_MASK 0x007f
# define RADEON_RBBM_ACTIVE (1 << 31)
#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
# define RADEON_RB2D_DC_FLUSH (3 << 0)
# define RADEON_RB2D_DC_FREE (3 << 2)
# define RADEON_RB2D_DC_FLUSH_ALL 0xf
# define RADEON_RB2D_DC_BUSY (1 << 31)
#define RADEON_RB2D_DSTCACHE_MODE 0x3428
#define RADEON_DSTCACHE_CTLSTAT 0x1714
#define RADEON_RB3D_ZCACHE_MODE 0x3250
#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
#define RADEON_RB3D_DSTCACHE_MODE 0x3258
# define RADEON_RB3D_DC_CACHE_ENABLE (0)
# define RADEON_RB3D_DC_2D_CACHE_DISABLE (1)
# define RADEON_RB3D_DC_3D_CACHE_DISABLE (2)
# define RADEON_RB3D_DC_CACHE_DISABLE (3)
# define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2)
# define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2)
# define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8)
# define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8)
# define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10)
# define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10)
# define RADEON_RB3D_DC_FORCE_RMW (1 << 16)
# define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24)
# define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25)
#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C
# define RADEON_RB3D_DC_FLUSH (3 << 0)
# define RADEON_RB3D_DC_FREE (3 << 2)
# define RADEON_RB3D_DC_FLUSH_ALL 0xf
# define RADEON_RB3D_DC_BUSY (1 << 31)
#define RADEON_REG_BASE 0x0f18 /* PCI */
#define RADEON_REGPROG_INF 0x0f09 /* PCI */
#define RADEON_REVISION_ID 0x0f08 /* PCI */
#define RADEON_SC_BOTTOM 0x164c
#define RADEON_SC_BOTTOM_RIGHT 0x16f0
#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c
#define RADEON_SC_LEFT 0x1640
#define RADEON_SC_RIGHT 0x1644
#define RADEON_SC_TOP 0x1648
#define RADEON_SC_TOP_LEFT 0x16ec
#define RADEON_SC_TOP_LEFT_C 0x1c88
# define RADEON_SC_SIGN_MASK_LO 0x8000
# define RADEON_SC_SIGN_MASK_HI 0x80000000
#define RADEON_SCLK_CNTL 0x000d /* PLL */
# define RADEON_SCLK_SRC_SEL_MASK 0x0007
# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8
# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008
# define RADEON_SCLK_FORCEON_MASK 0xffff8000
# define RADEON_SCLK_FORCE_DISP2 (1<<15)
# define RADEON_SCLK_FORCE_CP (1<<16)
# define RADEON_SCLK_FORCE_HDP (1<<17)
# define RADEON_SCLK_FORCE_DISP1 (1<<18)
# define RADEON_SCLK_FORCE_TOP (1<<19)
# define RADEON_SCLK_FORCE_E2 (1<<20)
# define RADEON_SCLK_FORCE_SE (1<<21)
# define RADEON_SCLK_FORCE_IDCT (1<<22)
# define RADEON_SCLK_FORCE_VIP (1<<23)
# define RADEON_SCLK_FORCE_RE (1<<24)
# define RADEON_SCLK_FORCE_PB (1<<25)
# define RADEON_SCLK_FORCE_TAM (1<<26)
# define RADEON_SCLK_FORCE_TDM (1<<27)
# define RADEON_SCLK_FORCE_RB (1<<28)
# define RADEON_SCLK_FORCE_TV_SCLK (1<<29)
# define RADEON_SCLK_FORCE_SUBPIC (1<<30)
# define RADEON_SCLK_FORCE_OV0 (1<<31)
# define R300_SCLK_FORCE_VAP (1<<21)
# define R300_SCLK_FORCE_SR (1<<25)
# define R300_SCLK_FORCE_PX (1<<26)
# define R300_SCLK_FORCE_TX (1<<27)
# define R300_SCLK_FORCE_US (1<<28)
# define R300_SCLK_FORCE_SU (1<<30)
#define R300_SCLK_CNTL2 0x1e /* PLL */
# define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10)
# define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11)
# define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12)
# define R300_SCLK_FORCE_TCL (1<<13)
# define R300_SCLK_FORCE_CBA (1<<14)
# define R300_SCLK_FORCE_GA (1<<15)
#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */
# define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007
# define RADEON_SCLK_MORE_FORCEON 0x0700
#define RADEON_SDRAM_MODE_REG 0x0158
#define RADEON_SEQ8_DATA 0x03c5 /* VGA */
#define RADEON_SEQ8_IDX 0x03c4 /* VGA */
#define RADEON_SNAPSHOT_F_COUNT 0x0244
#define RADEON_SNAPSHOT_VH_COUNTS 0x0240
#define RADEON_SNAPSHOT_VIF_COUNT 0x024c
#define RADEON_SRC_OFFSET 0x15ac
#define RADEON_SRC_PITCH 0x15b0
#define RADEON_SRC_PITCH_OFFSET 0x1428
#define RADEON_SRC_SC_BOTTOM 0x165c
#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4
#define RADEON_SRC_SC_RIGHT 0x1654
#define RADEON_SRC_X 0x1414
#define RADEON_SRC_X_Y 0x1590
#define RADEON_SRC_Y 0x1418
#define RADEON_SRC_Y_X 0x1434
#define RADEON_STATUS 0x0f06 /* PCI */
#define RADEON_SUBPIC_CNTL 0x0540 /* ? */
#define RADEON_SUB_CLASS 0x0f0a /* PCI */
#define RADEON_SURFACE_CNTL 0x0b00
# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)
# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)
# define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22)
# define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23)
#define RADEON_SURFACE0_INFO 0x0b0c
# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16)
# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16)
# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16)
# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16)
# define R200_SURF_TILE_NONE (0 << 16)
# define R200_SURF_TILE_COLOR_MACRO (1 << 16)
# define R200_SURF_TILE_COLOR_MICRO (2 << 16)
# define R200_SURF_TILE_COLOR_BOTH (3 << 16)
# define R200_SURF_TILE_DEPTH_32BPP (4 << 16)
# define R200_SURF_TILE_DEPTH_16BPP (5 << 16)
# define R300_SURF_TILE_NONE (0 << 16)
# define R300_SURF_TILE_COLOR_MACRO (1 << 16)
# define R300_SURF_TILE_DEPTH_32BPP (2 << 16)
# define RADEON_SURF_AP0_SWP_16BPP (1 << 20)
# define RADEON_SURF_AP0_SWP_32BPP (1 << 21)
# define RADEON_SURF_AP1_SWP_16BPP (1 << 22)
# define RADEON_SURF_AP1_SWP_32BPP (1 << 23)
#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
#define RADEON_SURFACE1_INFO 0x0b1c
#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
#define RADEON_SURFACE2_INFO 0x0b2c
#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
#define RADEON_SURFACE3_INFO 0x0b3c
#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
#define RADEON_SURFACE4_INFO 0x0b4c
#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
#define RADEON_SURFACE5_INFO 0x0b5c
#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
#define RADEON_SURFACE6_INFO 0x0b6c
#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
#define RADEON_SURFACE7_INFO 0x0b7c
#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
#define RADEON_SW_SEMAPHORE 0x013c
#define RADEON_TEST_DEBUG_CNTL 0x0120
#define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001
#define RADEON_TEST_DEBUG_MUX 0x0124
#define RADEON_TEST_DEBUG_OUT 0x012c
#define RADEON_TMDS_PLL_CNTL 0x02a8
#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4
# define RADEON_TMDS_TRANSMITTER_PLLEN 1
# define RADEON_TMDS_TRANSMITTER_PLLRST 2
#define RADEON_TRAIL_BRES_DEC 0x1614
#define RADEON_TRAIL_BRES_ERR 0x160c
#define RADEON_TRAIL_BRES_INC 0x1610
#define RADEON_TRAIL_X 0x1618
#define RADEON_TRAIL_X_SUB 0x1620
#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */
# define RADEON_VCLK_SRC_SEL_MASK 0x03
# define RADEON_VCLK_SRC_SEL_CPUCLK 0x00
# define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01
# define RADEON_VCLK_SRC_SEL_BYTECLK 0x02
# define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03
# define RADEON_PIXCLK_ALWAYS_ONb (1<<6)
# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)
# define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
#define RADEON_VENDOR_ID 0x0f00 /* PCI */
#define RADEON_VGA_DDA_CONFIG 0x02e8
#define RADEON_VGA_DDA_ON_OFF 0x02ec
#define RADEON_VID_BUFFER_CONTROL 0x0900
#define RADEON_VIDEOMUX_CNTL 0x0190
/* VIP bus */
#define RADEON_VIPH_CH0_DATA 0x0c00
#define RADEON_VIPH_CH1_DATA 0x0c04
#define RADEON_VIPH_CH2_DATA 0x0c08
#define RADEON_VIPH_CH3_DATA 0x0c0c
#define RADEON_VIPH_CH0_ADDR 0x0c10
#define RADEON_VIPH_CH1_ADDR 0x0c14
#define RADEON_VIPH_CH2_ADDR 0x0c18
#define RADEON_VIPH_CH3_ADDR 0x0c1c
#define RADEON_VIPH_CH0_SBCNT 0x0c20
#define RADEON_VIPH_CH1_SBCNT 0x0c24
#define RADEON_VIPH_CH2_SBCNT 0x0c28
#define RADEON_VIPH_CH3_SBCNT 0x0c2c
#define RADEON_VIPH_CH0_ABCNT 0x0c30
#define RADEON_VIPH_CH1_ABCNT 0x0c34
#define RADEON_VIPH_CH2_ABCNT 0x0c38
#define RADEON_VIPH_CH3_ABCNT 0x0c3c
#define RADEON_VIPH_CONTROL 0x0c40
# define RADEON_VIP_BUSY 0
# define RADEON_VIP_IDLE 1
# define RADEON_VIP_RESET 2
# define RADEON_VIPH_EN (1 << 21)
#define RADEON_VIPH_DV_LAT 0x0c44
#define RADEON_VIPH_BM_CHUNK 0x0c48
#define RADEON_VIPH_DV_INT 0x0c4c
#define RADEON_VIPH_TIMEOUT_STAT 0x0c50
#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010
#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010
#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000
#define RADEON_VIPH_REG_DATA 0x0084
#define RADEON_VIPH_REG_ADDR 0x0080
#define RADEON_WAIT_UNTIL 0x1720
# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
# define RADEON_WAIT_RE_CRTC_VLINE (1 << 1)
# define RADEON_WAIT_FE_CRTC_VLINE (1 << 2)
# define RADEON_WAIT_CRTC_VLINE (1 << 3)
# define RADEON_WAIT_DMA_VID_IDLE (1 << 8)
# define RADEON_WAIT_DMA_GUI_IDLE (1 << 9)
# define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */
# define RADEON_WAIT_OV0_FLIP (1 << 11)
# define RADEON_WAIT_AGP_FLUSH (1 << 13)
# define RADEON_WAIT_2D_IDLE (1 << 14)
# define RADEON_WAIT_3D_IDLE (1 << 15)
# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
# define RADEON_CMDFIFO_ENTRIES_SHIFT 10
# define RADEON_CMDFIFO_ENTRIES_MASK 0x7f
# define RADEON_WAIT_VAP_IDLE (1 << 28)
# define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30)
# define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31)
# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31)
#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */
#define RADEON_XCLK_CNTL 0x000d /* PLL */
#define RADEON_XDLL_CNTL 0x000c /* PLL */
#define RADEON_XPLL_CNTL 0x000b /* PLL */
/* Registers for 3D/TCL */
#define RADEON_PP_BORDER_COLOR_0 0x1d40
#define RADEON_PP_BORDER_COLOR_1 0x1d44
#define RADEON_PP_BORDER_COLOR_2 0x1d48
#define RADEON_PP_CNTL 0x1c38
# define RADEON_STIPPLE_ENABLE (1 << 0)
# define RADEON_SCISSOR_ENABLE (1 << 1)
# define RADEON_PATTERN_ENABLE (1 << 2)
# define RADEON_SHADOW_ENABLE (1 << 3)
# define RADEON_TEX_ENABLE_MASK (0xf << 4)
# define RADEON_TEX_0_ENABLE (1 << 4)
# define RADEON_TEX_1_ENABLE (1 << 5)
# define RADEON_TEX_2_ENABLE (1 << 6)
# define RADEON_TEX_3_ENABLE (1 << 7)
# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)
# define RADEON_TEX_BLEND_0_ENABLE (1 << 12)
# define RADEON_TEX_BLEND_1_ENABLE (1 << 13)
# define RADEON_TEX_BLEND_2_ENABLE (1 << 14)
# define RADEON_TEX_BLEND_3_ENABLE (1 << 15)
# define RADEON_PLANAR_YUV_ENABLE (1 << 20)
# define RADEON_SPECULAR_ENABLE (1 << 21)
# define RADEON_FOG_ENABLE (1 << 22)
# define RADEON_ALPHA_TEST_ENABLE (1 << 23)
# define RADEON_ANTI_ALIAS_NONE (0 << 24)
# define RADEON_ANTI_ALIAS_LINE (1 << 24)
# define RADEON_ANTI_ALIAS_POLY (2 << 24)
# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24)
# define RADEON_BUMP_MAP_ENABLE (1 << 26)
# define RADEON_BUMPED_MAP_T0 (0 << 27)
# define RADEON_BUMPED_MAP_T1 (1 << 27)
# define RADEON_BUMPED_MAP_T2 (2 << 27)
# define RADEON_TEX_3D_ENABLE_0 (1 << 29)
# define RADEON_TEX_3D_ENABLE_1 (1 << 30)
# define RADEON_MC_ENABLE (1 << 31)
#define RADEON_PP_FOG_COLOR 0x1c18
# define RADEON_FOG_COLOR_MASK 0x00ffffff
# define RADEON_FOG_VERTEX (0 << 24)
# define RADEON_FOG_TABLE (1 << 24)
# define RADEON_FOG_USE_DEPTH (0 << 25)
# define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25)
# define RADEON_FOG_USE_SPEC_ALPHA (3 << 25)
#define RADEON_PP_LUM_MATRIX 0x1d00
#define RADEON_PP_MISC 0x1c14
# define RADEON_REF_ALPHA_MASK 0x000000ff
# define RADEON_ALPHA_TEST_FAIL (0 << 8)
# define RADEON_ALPHA_TEST_LESS (1 << 8)
# define RADEON_ALPHA_TEST_LEQUAL (2 << 8)
# define RADEON_ALPHA_TEST_EQUAL (3 << 8)
# define RADEON_ALPHA_TEST_GEQUAL (4 << 8)
# define RADEON_ALPHA_TEST_GREATER (5 << 8)
# define RADEON_ALPHA_TEST_NEQUAL (6 << 8)
# define RADEON_ALPHA_TEST_PASS (7 << 8)
# define RADEON_ALPHA_TEST_OP_MASK (7 << 8)
# define RADEON_CHROMA_FUNC_FAIL (0 << 16)
# define RADEON_CHROMA_FUNC_PASS (1 << 16)
# define RADEON_CHROMA_FUNC_NEQUAL (2 << 16)
# define RADEON_CHROMA_FUNC_EQUAL (3 << 16)
# define RADEON_CHROMA_KEY_NEAREST (0 << 18)
# define RADEON_CHROMA_KEY_ZERO (1 << 18)
# define RADEON_SHADOW_ID_AUTO_INC (1 << 20)
# define RADEON_SHADOW_FUNC_EQUAL (0 << 21)
# define RADEON_SHADOW_FUNC_NEQUAL (1 << 21)
# define RADEON_SHADOW_PASS_1 (0 << 22)
# define RADEON_SHADOW_PASS_2 (1 << 22)
# define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24)
# define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24)
#define RADEON_PP_ROT_MATRIX_0 0x1d58
#define RADEON_PP_ROT_MATRIX_1 0x1d5c
#define RADEON_PP_TXFILTER_0 0x1c54
#define RADEON_PP_TXFILTER_1 0x1c6c
#define RADEON_PP_TXFILTER_2 0x1c84
# define RADEON_MAG_FILTER_NEAREST (0 << 0)
# define RADEON_MAG_FILTER_LINEAR (1 << 0)
# define RADEON_MAG_FILTER_MASK (1 << 0)
# define RADEON_MIN_FILTER_NEAREST (0 << 1)
# define RADEON_MIN_FILTER_LINEAR (1 << 1)
# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)
# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)
# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)
# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)
# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1)
# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1)
# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)
# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)
# define RADEON_MIN_FILTER_MASK (15 << 1)
# define RADEON_MAX_ANISO_1_TO_1 (0 << 5)
# define RADEON_MAX_ANISO_2_TO_1 (1 << 5)
# define RADEON_MAX_ANISO_4_TO_1 (2 << 5)
# define RADEON_MAX_ANISO_8_TO_1 (3 << 5)
# define RADEON_MAX_ANISO_16_TO_1 (4 << 5)
# define RADEON_MAX_ANISO_MASK (7 << 5)
# define RADEON_LOD_BIAS_MASK (0xff << 8)
# define RADEON_LOD_BIAS_SHIFT 8
# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16)
# define RADEON_MAX_MIP_LEVEL_SHIFT 16
# define RADEON_YUV_TO_RGB (1 << 20)
# define RADEON_YUV_TEMPERATURE_COOL (0 << 21)
# define RADEON_YUV_TEMPERATURE_HOT (1 << 21)
# define RADEON_YUV_TEMPERATURE_MASK (1 << 21)
# define RADEON_WRAPEN_S (1 << 22)
# define RADEON_CLAMP_S_WRAP (0 << 23)
# define RADEON_CLAMP_S_MIRROR (1 << 23)
# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23)
# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)
# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23)
# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)
# define RADEON_CLAMP_S_CLAMP_GL (6 << 23)
# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)
# define RADEON_CLAMP_S_MASK (7 << 23)
# define RADEON_WRAPEN_T (1 << 26)
# define RADEON_CLAMP_T_WRAP (0 << 27)
# define RADEON_CLAMP_T_MIRROR (1 << 27)
# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27)
# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)
# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27)
# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)
# define RADEON_CLAMP_T_CLAMP_GL (6 << 27)
# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)
# define RADEON_CLAMP_T_MASK (7 << 27)
# define RADEON_BORDER_MODE_OGL (0 << 31)
# define RADEON_BORDER_MODE_D3D (1 << 31)
#define RADEON_PP_TXFORMAT_0 0x1c58
#define RADEON_PP_TXFORMAT_1 0x1c70
#define RADEON_PP_TXFORMAT_2 0x1c88
# define RADEON_TXFORMAT_I8 (0 << 0)
# define RADEON_TXFORMAT_AI88 (1 << 0)
# define RADEON_TXFORMAT_RGB332 (2 << 0)
# define RADEON_TXFORMAT_ARGB1555 (3 << 0)
# define RADEON_TXFORMAT_RGB565 (4 << 0)
# define RADEON_TXFORMAT_ARGB4444 (5 << 0)
# define RADEON_TXFORMAT_ARGB8888 (6 << 0)
# define RADEON_TXFORMAT_RGBA8888 (7 << 0)
# define RADEON_TXFORMAT_Y8 (8 << 0)
# define RADEON_TXFORMAT_VYUY422 (10 << 0)
# define RADEON_TXFORMAT_YVYU422 (11 << 0)
# define RADEON_TXFORMAT_DXT1 (12 << 0)
# define RADEON_TXFORMAT_DXT23 (14 << 0)
# define RADEON_TXFORMAT_DXT45 (15 << 0)
# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)
# define RADEON_TXFORMAT_FORMAT_SHIFT 0
# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)
# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6)
# define RADEON_TXFORMAT_NON_POWER2 (1 << 7)
# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8)
# define RADEON_TXFORMAT_WIDTH_SHIFT 8
# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12)
# define RADEON_TXFORMAT_HEIGHT_SHIFT 12
# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16)
# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16
# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20)
# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20
# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)
# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)
# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)
# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)
# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26)
# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26)
# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26)
# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26)
# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)
# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)
# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)
# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31)
#define RADEON_PP_CUBIC_FACES_0 0x1d24
#define RADEON_PP_CUBIC_FACES_1 0x1d28
#define RADEON_PP_CUBIC_FACES_2 0x1d2c
# define RADEON_FACE_WIDTH_1_SHIFT 0
# define RADEON_FACE_HEIGHT_1_SHIFT 4
# define RADEON_FACE_WIDTH_1_MASK (0xf << 0)
# define RADEON_FACE_HEIGHT_1_MASK (0xf << 4)
# define RADEON_FACE_WIDTH_2_SHIFT 8
# define RADEON_FACE_HEIGHT_2_SHIFT 12
# define RADEON_FACE_WIDTH_2_MASK (0xf << 8)
# define RADEON_FACE_HEIGHT_2_MASK (0xf << 12)
# define RADEON_FACE_WIDTH_3_SHIFT 16
# define RADEON_FACE_HEIGHT_3_SHIFT 20
# define RADEON_FACE_WIDTH_3_MASK (0xf << 16)
# define RADEON_FACE_HEIGHT_3_MASK (0xf << 20)
# define RADEON_FACE_WIDTH_4_SHIFT 24
# define RADEON_FACE_HEIGHT_4_SHIFT 28
# define RADEON_FACE_WIDTH_4_MASK (0xf << 24)
# define RADEON_FACE_HEIGHT_4_MASK (0xf << 28)
#define RADEON_PP_TXOFFSET_0 0x1c5c
#define RADEON_PP_TXOFFSET_1 0x1c74
#define RADEON_PP_TXOFFSET_2 0x1c8c
# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0)
# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0)
# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0)
# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
# define RADEON_TXO_MACRO_LINEAR (0 << 2)
# define RADEON_TXO_MACRO_TILE (1 << 2)
# define RADEON_TXO_MICRO_LINEAR (0 << 3)
# define RADEON_TXO_MICRO_TILE_X2 (1 << 3)
# define RADEON_TXO_MICRO_TILE_OPT (2 << 3)
# define RADEON_TXO_OFFSET_MASK 0xffffffe0
# define RADEON_TXO_OFFSET_SHIFT 5
#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4
#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8
#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc
#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0
#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04
#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08
#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c
#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10
#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18
#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c
#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20
#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24
#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
#define RADEON_PP_TEX_SIZE_1 0x1d0c
#define RADEON_PP_TEX_SIZE_2 0x1d14
# define RADEON_TEX_USIZE_MASK (0x7ff << 0)
# define RADEON_TEX_USIZE_SHIFT 0
# define RADEON_TEX_VSIZE_MASK (0x7ff << 16)
# define RADEON_TEX_VSIZE_SHIFT 16
# define RADEON_SIGNED_RGB_MASK (1 << 30)
# define RADEON_SIGNED_RGB_SHIFT 30
# define RADEON_SIGNED_ALPHA_MASK (1 << 31)
# define RADEON_SIGNED_ALPHA_SHIFT 31
#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */
#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */
#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */
/* note: bits 13-5: 32 byte aligned stride of texture map */
#define RADEON_PP_TXCBLEND_0 0x1c60
#define RADEON_PP_TXCBLEND_1 0x1c78
#define RADEON_PP_TXCBLEND_2 0x1c90
# define RADEON_COLOR_ARG_A_SHIFT 0
# define RADEON_COLOR_ARG_A_MASK (0x1f << 0)
# define RADEON_COLOR_ARG_A_ZERO (0 << 0)
# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0)
# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0)
# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0)
# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0)
# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0)
# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0)
# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0)
# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0)
# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0)
# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0)
# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0)
# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0)
# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0)
# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0)
# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0)
# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0)
# define RADEON_COLOR_ARG_B_SHIFT 5
# define RADEON_COLOR_ARG_B_MASK (0x1f << 5)
# define RADEON_COLOR_ARG_B_ZERO (0 << 5)
# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5)
# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5)
# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5)
# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5)
# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5)
# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5)
# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5)
# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5)
# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5)
# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5)
# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5)
# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5)
# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5)
# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5)
# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5)
# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5)
# define RADEON_COLOR_ARG_C_SHIFT 10
# define RADEON_COLOR_ARG_C_MASK (0x1f << 10)
# define RADEON_COLOR_ARG_C_ZERO (0 << 10)
# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10)
# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10)
# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10)
# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10)
# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10)
# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10)
# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10)
# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10)
# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10)
# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10)
# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10)
# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10)
# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10)
# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10)
# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10)
# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10)
# define RADEON_COMP_ARG_A (1 << 15)
# define RADEON_COMP_ARG_A_SHIFT 15
# define RADEON_COMP_ARG_B (1 << 16)
# define RADEON_COMP_ARG_B_SHIFT 16
# define RADEON_COMP_ARG_C (1 << 17)
# define RADEON_COMP_ARG_C_SHIFT 17
# define RADEON_BLEND_CTL_MASK (7 << 18)
# define RADEON_BLEND_CTL_ADD (0 << 18)
# define RADEON_BLEND_CTL_SUBTRACT (1 << 18)
# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18)
# define RADEON_BLEND_CTL_BLEND (3 << 18)
# define RADEON_BLEND_CTL_DOT3 (4 << 18)
# define RADEON_SCALE_SHIFT 21
# define RADEON_SCALE_MASK (3 << 21)
# define RADEON_SCALE_1X (0 << 21)
# define RADEON_SCALE_2X (1 << 21)
# define RADEON_SCALE_4X (2 << 21)
# define RADEON_CLAMP_TX (1 << 23)
# define RADEON_T0_EQ_TCUR (1 << 24)
# define RADEON_T1_EQ_TCUR (1 << 25)
# define RADEON_T2_EQ_TCUR (1 << 26)
# define RADEON_T3_EQ_TCUR (1 << 27)
# define RADEON_COLOR_ARG_MASK 0x1f
# define RADEON_COMP_ARG_SHIFT 15
#define RADEON_PP_TXABLEND_0 0x1c64
#define RADEON_PP_TXABLEND_1 0x1c7c
#define RADEON_PP_TXABLEND_2 0x1c94
# define RADEON_ALPHA_ARG_A_SHIFT 0
# define RADEON_ALPHA_ARG_A_MASK (0xf << 0)
# define RADEON_ALPHA_ARG_A_ZERO (0 << 0)
# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0)
# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0)
# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0)
# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0)
# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0)
# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0)
# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0)
# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0)
# define RADEON_ALPHA_ARG_B_SHIFT 4
# define RADEON_ALPHA_ARG_B_MASK (0xf << 4)
# define RADEON_ALPHA_ARG_B_ZERO (0 << 4)
# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4)
# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4)
# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4)
# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4)
# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4)
# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4)
# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4)
# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4)
# define RADEON_ALPHA_ARG_C_SHIFT 8
# define RADEON_ALPHA_ARG_C_MASK (0xf << 8)
# define RADEON_ALPHA_ARG_C_ZERO (0 << 8)
# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8)
# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8)
# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8)
# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8)
# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8)
# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8)
# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8)
# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8)
# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9)
# define RADEON_ALPHA_ARG_MASK 0xf
#define RADEON_PP_TFACTOR_0 0x1c68
#define RADEON_PP_TFACTOR_1 0x1c80
#define RADEON_PP_TFACTOR_2 0x1c98
#define RADEON_RB3D_BLENDCNTL 0x1c20
# define RADEON_COMB_FCN_MASK (3 << 12)
# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12)
# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12)
# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12)
# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12)
# define RADEON_SRC_BLEND_GL_ZERO (32 << 16)
# define RADEON_SRC_BLEND_GL_ONE (33 << 16)
# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16)
# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)
# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16)
# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)
# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16)
# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)
# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16)
# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)
# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)
# define RADEON_SRC_BLEND_MASK (63 << 16)
# define RADEON_DST_BLEND_GL_ZERO (32 << 24)
# define RADEON_DST_BLEND_GL_ONE (33 << 24)
# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24)
# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)
# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24)
# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)
# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24)
# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)
# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24)
# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)
# define RADEON_DST_BLEND_MASK (63 << 24)
#define RADEON_RB3D_CNTL 0x1c3c
# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
# define RADEON_PLANE_MASK_ENABLE (1 << 1)
# define RADEON_DITHER_ENABLE (1 << 2)
# define RADEON_ROUND_ENABLE (1 << 3)
# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
# define RADEON_DITHER_INIT (1 << 5)
# define RADEON_ROP_ENABLE (1 << 6)
# define RADEON_STENCIL_ENABLE (1 << 7)
# define RADEON_Z_ENABLE (1 << 8)
# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9)
# define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10)
# define RADEON_COLOR_FORMAT_RGB565 (4 << 10)
# define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10)
# define RADEON_COLOR_FORMAT_RGB332 (7 << 10)
# define RADEON_COLOR_FORMAT_Y8 (8 << 10)
# define RADEON_COLOR_FORMAT_RGB8 (9 << 10)
# define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10)
# define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10)
# define RADEON_COLOR_FORMAT_aYUV444 (14 << 10)
# define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10)
# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14)
#define RADEON_RB3D_COLOROFFSET 0x1c40
# define RADEON_COLOROFFSET_MASK 0xfffffff0
#define RADEON_RB3D_COLORPITCH 0x1c48
# define RADEON_COLORPITCH_MASK 0x000001ff8
# define RADEON_COLOR_TILE_ENABLE (1 << 16)
# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17)
# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18)
# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18)
# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18)
#define RADEON_RB3D_DEPTHOFFSET 0x1c24
#define RADEON_RB3D_DEPTHPITCH 0x1c28
# define RADEON_DEPTHPITCH_MASK 0x00001ff8
# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18)
# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18)
# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18)
#define RADEON_RB3D_PLANEMASK 0x1d84
#define RADEON_RB3D_ROPCNTL 0x1d80
# define RADEON_ROP_MASK (15 << 8)
# define RADEON_ROP_CLEAR (0 << 8)
# define RADEON_ROP_NOR (1 << 8)
# define RADEON_ROP_AND_INVERTED (2 << 8)
# define RADEON_ROP_COPY_INVERTED (3 << 8)
# define RADEON_ROP_AND_REVERSE (4 << 8)
# define RADEON_ROP_INVERT (5 << 8)
# define RADEON_ROP_XOR (6 << 8)
# define RADEON_ROP_NAND (7 << 8)
# define RADEON_ROP_AND (8 << 8)
# define RADEON_ROP_EQUIV (9 << 8)
# define RADEON_ROP_NOOP (10 << 8)
# define RADEON_ROP_OR_INVERTED (11 << 8)
# define RADEON_ROP_COPY (12 << 8)
# define RADEON_ROP_OR_REVERSE (13 << 8)
# define RADEON_ROP_OR (14 << 8)
# define RADEON_ROP_SET (15 << 8)
#define RADEON_RB3D_STENCILREFMASK 0x1d7c
# define RADEON_STENCIL_REF_SHIFT 0
# define RADEON_STENCIL_REF_MASK (0xff << 0)
# define RADEON_STENCIL_MASK_SHIFT 16
# define RADEON_STENCIL_VALUE_MASK (0xff << 16)
# define RADEON_STENCIL_WRITEMASK_SHIFT 24
# define RADEON_STENCIL_WRITE_MASK (0xff << 24)
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_DEPTH_FORMAT_MASK (0xf << 0)
# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0)
# define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0)
# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0)
# define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0)
# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0)
# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0)
# define RADEON_Z_TEST_NEVER (0 << 4)
# define RADEON_Z_TEST_LESS (1 << 4)
# define RADEON_Z_TEST_LEQUAL (2 << 4)
# define RADEON_Z_TEST_EQUAL (3 << 4)
# define RADEON_Z_TEST_GEQUAL (4 << 4)
# define RADEON_Z_TEST_GREATER (5 << 4)
# define RADEON_Z_TEST_NEQUAL (6 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4)
# define RADEON_Z_TEST_MASK (7 << 4)
# define RADEON_STENCIL_TEST_NEVER (0 << 12)
# define RADEON_STENCIL_TEST_LESS (1 << 12)
# define RADEON_STENCIL_TEST_LEQUAL (2 << 12)
# define RADEON_STENCIL_TEST_EQUAL (3 << 12)
# define RADEON_STENCIL_TEST_GEQUAL (4 << 12)
# define RADEON_STENCIL_TEST_GREATER (5 << 12)
# define RADEON_STENCIL_TEST_NEQUAL (6 << 12)
# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
# define RADEON_STENCIL_TEST_MASK (0x7 << 12)
# define RADEON_STENCIL_FAIL_KEEP (0 << 16)
# define RADEON_STENCIL_FAIL_ZERO (1 << 16)
# define RADEON_STENCIL_FAIL_REPLACE (2 << 16)
# define RADEON_STENCIL_FAIL_INC (3 << 16)
# define RADEON_STENCIL_FAIL_DEC (4 << 16)
# define RADEON_STENCIL_FAIL_INVERT (5 << 16)
# define RADEON_STENCIL_FAIL_MASK (0x7 << 16)
# define RADEON_STENCIL_ZPASS_KEEP (0 << 20)
# define RADEON_STENCIL_ZPASS_ZERO (1 << 20)
# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
# define RADEON_STENCIL_ZPASS_INC (3 << 20)
# define RADEON_STENCIL_ZPASS_DEC (4 << 20)
# define RADEON_STENCIL_ZPASS_INVERT (5 << 20)
# define RADEON_STENCIL_ZPASS_MASK (0x7 << 20)
# define RADEON_STENCIL_ZFAIL_KEEP (0 << 24)
# define RADEON_STENCIL_ZFAIL_ZERO (1 << 24)
# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
# define RADEON_STENCIL_ZFAIL_INC (3 << 24)
# define RADEON_STENCIL_ZFAIL_DEC (4 << 24)
# define RADEON_STENCIL_ZFAIL_INVERT (5 << 24)
# define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24)
# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
# define RADEON_FORCE_Z_DIRTY (1 << 29)
# define RADEON_Z_WRITE_ENABLE (1 << 30)
#define RADEON_RE_LINE_PATTERN 0x1cd0
# define RADEON_LINE_PATTERN_MASK 0x0000ffff
# define RADEON_LINE_REPEAT_COUNT_SHIFT 16
# define RADEON_LINE_PATTERN_START_SHIFT 24
# define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28)
# define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28)
# define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29)
#define RADEON_RE_LINE_STATE 0x1cd4
# define RADEON_LINE_CURRENT_PTR_SHIFT 0
# define RADEON_LINE_CURRENT_COUNT_SHIFT 8
#define RADEON_RE_MISC 0x26c4
# define RADEON_STIPPLE_COORD_MASK 0x1f
# define RADEON_STIPPLE_X_OFFSET_SHIFT 0
# define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0)
# define RADEON_STIPPLE_Y_OFFSET_SHIFT 8
# define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8)
# define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16)
# define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16)
#define RADEON_RE_SOLID_COLOR 0x1c1c
#define RADEON_RE_TOP_LEFT 0x26c0
# define RADEON_RE_LEFT_SHIFT 0
# define RADEON_RE_TOP_SHIFT 16
#define RADEON_RE_WIDTH_HEIGHT 0x1c44
# define RADEON_RE_WIDTH_SHIFT 0
# define RADEON_RE_HEIGHT_SHIFT 16
#define RADEON_SE_CNTL 0x1c4c
# define RADEON_FFACE_CULL_CW (0 << 0)
# define RADEON_FFACE_CULL_CCW (1 << 0)
# define RADEON_FFACE_CULL_DIR_MASK (1 << 0)
# define RADEON_BFACE_CULL (0 << 1)
# define RADEON_BFACE_SOLID (3 << 1)
# define RADEON_FFACE_CULL (0 << 3)
# define RADEON_FFACE_SOLID (3 << 3)
# define RADEON_FFACE_CULL_MASK (3 << 3)
# define RADEON_BADVTX_CULL_DISABLE (1 << 5)
# define RADEON_FLAT_SHADE_VTX_0 (0 << 6)
# define RADEON_FLAT_SHADE_VTX_1 (1 << 6)
# define RADEON_FLAT_SHADE_VTX_2 (2 << 6)
# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8)
# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
# define RADEON_DIFFUSE_SHADE_MASK (3 << 8)
# define RADEON_ALPHA_SHADE_SOLID (0 << 10)
# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
# define RADEON_ALPHA_SHADE_MASK (3 << 10)
# define RADEON_SPECULAR_SHADE_SOLID (0 << 12)
# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
# define RADEON_SPECULAR_SHADE_MASK (3 << 12)
# define RADEON_FOG_SHADE_SOLID (0 << 14)
# define RADEON_FOG_SHADE_FLAT (1 << 14)
# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
# define RADEON_FOG_SHADE_MASK (3 << 14)
# define RADEON_ZBIAS_ENABLE_POINT (1 << 16)
# define RADEON_ZBIAS_ENABLE_LINE (1 << 17)
# define RADEON_ZBIAS_ENABLE_TRI (1 << 18)
# define RADEON_WIDELINE_ENABLE (1 << 20)
# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
# define RADEON_VTX_PIX_CENTER_D3D (0 << 27)
# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
# define RADEON_ROUND_MODE_TRUNC (0 << 28)
# define RADEON_ROUND_MODE_ROUND (1 << 28)
# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28)
# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28)
# define RADEON_ROUND_PREC_16TH_PIX (0 << 30)
# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
# define RADEON_ROUND_PREC_4TH_PIX (2 << 30)
# define RADEON_ROUND_PREC_HALF_PIX (3 << 30)
#define R200_RE_CNTL0x1c50
# define R200_STIPPLE_ENABLE0x1
# define R200_SCISSOR_ENABLE0x2
# define R200_PATTERN_ENABLE0x4
# define R200_PERSPECTIVE_ENABLE0x8
# define R200_POINT_SMOOTH0x20
# define R200_VTX_STQ0_D3D0x00010000
# define R200_VTX_STQ1_D3D0x00040000
# define R200_VTX_STQ2_D3D0x00100000
# define R200_VTX_STQ3_D3D0x00400000
# define R200_VTX_STQ4_D3D0x01000000
# define R200_VTX_STQ5_D3D0x04000000
#define R200_RE_SCISSOR_TL_00x1cd8
#define R200_RE_SCISSOR_BR_00x1cdc
#define R200_RE_SCISSOR_TL_10x1ce0
#define R200_RE_SCISSOR_BR_10x1ce4
#define R200_RE_SCISSOR_TL_20x1ce8
#define R200_RE_SCISSOR_BR_20x1cec
# define R200_SCISSOR_X_SHIFT0
# define R200_SCISSOR_Y_SHIFT16
#define RADEON_SE_CNTL_STATUS 0x2140
# define RADEON_VC_NO_SWAP (0 << 0)
# define RADEON_VC_16BIT_SWAP (1 << 0)
# define RADEON_VC_32BIT_SWAP (2 << 0)
# define RADEON_VC_HALF_DWORD_SWAP (3 << 0)
# define RADEON_TCL_BYPASS (1 << 8)
#define RADEON_SE_COORD_FMT 0x1c50
# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0)
# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1)
# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8)
# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9)
# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10)
# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11)
# define RADEON_VTX_W0_NORMALIZE (1 << 12)
# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16)
# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17)
# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19)
# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21)
# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23)
# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26)
# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26)
#define RADEON_SE_LINE_WIDTH 0x1db8
#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c
# define RADEON_LIGHTING_ENABLE (1 << 0)
# define RADEON_LIGHT_IN_MODELSPACE (1 << 1)
# define RADEON_LOCAL_VIEWER (1 << 2)
# define RADEON_NORMALIZE_NORMALS (1 << 3)
# define RADEON_RESCALE_NORMALS (1 << 4)
# define RADEON_SPECULAR_LIGHTS (1 << 5)
# define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6)
# define RADEON_LIGHT_ALPHA (1 << 7)
# define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8)
# define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9)
# define RADEON_LM_SOURCE_STATE_PREMULT 0
# define RADEON_LM_SOURCE_STATE_MULT 1
# define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2
# define RADEON_LM_SOURCE_VERTEX_SPECULAR 3
# define RADEON_EMISSIVE_SOURCE_SHIFT 16
# define RADEON_AMBIENT_SOURCE_SHIFT 18
# define RADEON_DIFFUSE_SOURCE_SHIFT 20
# define RADEON_SPECULAR_SOURCE_SHIFT 22
#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220
#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224
#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228
#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c
#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230
#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234
#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238
#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c
#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214
#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218
#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c
#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240
#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244
#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248
#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c
#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c
# define RADEON_MODELVIEW_0_SHIFT 0
# define RADEON_MODELVIEW_1_SHIFT 4
# define RADEON_MODELVIEW_2_SHIFT 8
# define RADEON_MODELVIEW_3_SHIFT 12
# define RADEON_IT_MODELVIEW_0_SHIFT 16
# define RADEON_IT_MODELVIEW_1_SHIFT 20
# define RADEON_IT_MODELVIEW_2_SHIFT 24
# define RADEON_IT_MODELVIEW_3_SHIFT 28
#define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260
# define RADEON_MODELPROJECT_0_SHIFT 0
# define RADEON_MODELPROJECT_1_SHIFT 4
# define RADEON_MODELPROJECT_2_SHIFT 8
# define RADEON_MODELPROJECT_3_SHIFT 12
# define RADEON_TEXMAT_0_SHIFT 16
# define RADEON_TEXMAT_1_SHIFT 20
# define RADEON_TEXMAT_2_SHIFT 24
# define RADEON_TEXMAT_3_SHIFT 28
#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
# define RADEON_TCL_VTX_W0 (1 << 0)
# define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1)
# define RADEON_TCL_VTX_FP_ALPHA (1 << 2)
# define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3)
# define RADEON_TCL_VTX_FP_SPEC (1 << 4)
# define RADEON_TCL_VTX_FP_FOG (1 << 5)
# define RADEON_TCL_VTX_PK_SPEC (1 << 6)
# define RADEON_TCL_VTX_ST0 (1 << 7)
# define RADEON_TCL_VTX_ST1 (1 << 8)
# define RADEON_TCL_VTX_Q1 (1 << 9)
# define RADEON_TCL_VTX_ST2 (1 << 10)
# define RADEON_TCL_VTX_Q2 (1 << 11)
# define RADEON_TCL_VTX_ST3 (1 << 12)
# define RADEON_TCL_VTX_Q3 (1 << 13)
# define RADEON_TCL_VTX_Q0 (1 << 14)
# define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15
# define RADEON_TCL_VTX_NORM0 (1 << 18)
# define RADEON_TCL_VTX_XY1 (1 << 27)
# define RADEON_TCL_VTX_Z1 (1 << 28)
# define RADEON_TCL_VTX_W1 (1 << 29)
# define RADEON_TCL_VTX_NORM1 (1 << 30)
# define RADEON_TCL_VTX_Z0 (1 << 31)
#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258
# define RADEON_TCL_COMPUTE_XYZW (1 << 0)
# define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1)
# define RADEON_TCL_COMPUTE_SPECULAR (1 << 2)
# define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3)
# define RADEON_TCL_FORCE_INORDER_PROC (1 << 4)
# define RADEON_TCL_TEX_INPUT_TEX_0 0
# define RADEON_TCL_TEX_INPUT_TEX_1 1
# define RADEON_TCL_TEX_INPUT_TEX_2 2
# define RADEON_TCL_TEX_INPUT_TEX_3 3
# define RADEON_TCL_TEX_COMPUTED_TEX_0 8
# define RADEON_TCL_TEX_COMPUTED_TEX_1 9
# define RADEON_TCL_TEX_COMPUTED_TEX_2 10
# define RADEON_TCL_TEX_COMPUTED_TEX_3 11
# define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16
# define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20
# define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24
# define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28
#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270
# define RADEON_LIGHT_0_ENABLE (1 << 0)
# define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1)
# define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2)
# define RADEON_LIGHT_0_IS_LOCAL (1 << 3)
# define RADEON_LIGHT_0_IS_SPOT (1 << 4)
# define RADEON_LIGHT_0_DUAL_CONE (1 << 5)
# define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6)
# define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7)
# define RADEON_LIGHT_0_SHIFT 0
# define RADEON_LIGHT_1_ENABLE (1 << 16)
# define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17)
# define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18)
# define RADEON_LIGHT_1_IS_LOCAL (1 << 19)
# define RADEON_LIGHT_1_IS_SPOT (1 << 20)
# define RADEON_LIGHT_1_DUAL_CONE (1 << 21)
# define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22)
# define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23)
# define RADEON_LIGHT_1_SHIFT 16
#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274
# define RADEON_LIGHT_2_SHIFT 0
# define RADEON_LIGHT_3_SHIFT 16
#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278
# define RADEON_LIGHT_4_SHIFT 0
# define RADEON_LIGHT_5_SHIFT 16
#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c
# define RADEON_LIGHT_6_SHIFT 0
# define RADEON_LIGHT_7_SHIFT 16
#define RADEON_SE_TCL_SHININESS 0x2250
#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268
# define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0)
# define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1)
# define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2)
# define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3)
# define RADEON_TEXMAT_0_ENABLE (1 << 4)
# define RADEON_TEXMAT_1_ENABLE (1 << 5)
# define RADEON_TEXMAT_2_ENABLE (1 << 6)
# define RADEON_TEXMAT_3_ENABLE (1 << 7)
# define RADEON_TEXGEN_INPUT_MASK 0xf
# define RADEON_TEXGEN_INPUT_TEXCOORD_0 0
# define RADEON_TEXGEN_INPUT_TEXCOORD_1 1
# define RADEON_TEXGEN_INPUT_TEXCOORD_2 2
# define RADEON_TEXGEN_INPUT_TEXCOORD_3 3
# define RADEON_TEXGEN_INPUT_OBJ 4
# define RADEON_TEXGEN_INPUT_EYE 5
# define RADEON_TEXGEN_INPUT_EYE_NORMAL 6
# define RADEON_TEXGEN_INPUT_EYE_REFLECT 7
# define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8
# define RADEON_TEXGEN_0_INPUT_SHIFT 16
# define RADEON_TEXGEN_1_INPUT_SHIFT 20
# define RADEON_TEXGEN_2_INPUT_SHIFT 24
# define RADEON_TEXGEN_3_INPUT_SHIFT 28
#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264
# define RADEON_UCP_IN_CLIP_SPACE (1 << 0)
# define RADEON_UCP_IN_MODEL_SPACE (1 << 1)
# define RADEON_UCP_ENABLE_0 (1 << 2)
# define RADEON_UCP_ENABLE_1 (1 << 3)
# define RADEON_UCP_ENABLE_2 (1 << 4)
# define RADEON_UCP_ENABLE_3 (1 << 5)
# define RADEON_UCP_ENABLE_4 (1 << 6)
# define RADEON_UCP_ENABLE_5 (1 << 7)
# define RADEON_TCL_FOG_MASK (3 << 8)
# define RADEON_TCL_FOG_DISABLE (0 << 8)
# define RADEON_TCL_FOG_EXP (1 << 8)
# define RADEON_TCL_FOG_EXP2 (2 << 8)
# define RADEON_TCL_FOG_LINEAR (3 << 8)
# define RADEON_RNG_BASED_FOG (1 << 10)
# define RADEON_LIGHT_TWOSIDE (1 << 11)
# define RADEON_BLEND_OP_COUNT_MASK (7 << 12)
# define RADEON_BLEND_OP_COUNT_SHIFT 12
# define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16)
# define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17)
# define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18)
# define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18)
# define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19)
# define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19)
# define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20)
# define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20)
# define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21)
# define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21)
# define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22)
# define RADEON_CULL_FRONT_IS_CW (0 << 28)
# define RADEON_CULL_FRONT_IS_CCW (1 << 28)
# define RADEON_CULL_FRONT (1 << 29)
# define RADEON_CULL_BACK (1 << 30)
# define RADEON_FORCE_W_TO_ONE (1 << 31)
#define RADEON_SE_VPORT_XSCALE 0x1d98
#define RADEON_SE_VPORT_XOFFSET 0x1d9c
#define RADEON_SE_VPORT_YSCALE 0x1da0
#define RADEON_SE_VPORT_YOFFSET 0x1da4
#define RADEON_SE_VPORT_ZSCALE 0x1da8
#define RADEON_SE_VPORT_ZOFFSET 0x1dac
#define RADEON_SE_ZBIAS_FACTOR 0x1db0
#define RADEON_SE_ZBIAS_CONSTANT 0x1db4
#define RADEON_SE_VTX_FMT 0x2080
# define RADEON_SE_VTX_FMT_XY 0x00000000
# define RADEON_SE_VTX_FMT_W0 0x00000001
# define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002
# define RADEON_SE_VTX_FMT_FPALPHA 0x00000004
# define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008
# define RADEON_SE_VTX_FMT_FPSPEC 0x00000010
# define RADEON_SE_VTX_FMT_FPFOG 0x00000020
# define RADEON_SE_VTX_FMT_PKSPEC 0x00000040
# define RADEON_SE_VTX_FMT_ST0 0x00000080
# define RADEON_SE_VTX_FMT_ST1 0x00000100
# define RADEON_SE_VTX_FMT_Q1 0x00000200
# define RADEON_SE_VTX_FMT_ST2 0x00000400
# define RADEON_SE_VTX_FMT_Q2 0x00000800
# define RADEON_SE_VTX_FMT_ST3 0x00001000
# define RADEON_SE_VTX_FMT_Q3 0x00002000
# define RADEON_SE_VTX_FMT_Q0 0x00004000
# define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000
# define RADEON_SE_VTX_FMT_N0 0x00040000
# define RADEON_SE_VTX_FMT_XY1 0x08000000
# define RADEON_SE_VTX_FMT_Z1 0x10000000
# define RADEON_SE_VTX_FMT_W1 0x20000000
# define RADEON_SE_VTX_FMT_N1 0x40000000
# define RADEON_SE_VTX_FMT_Z 0x80000000
#define RADEON_SE_VF_CNTL 0x2084
# define RADEON_VF_PRIM_TYPE_POINT_LIST 1
# define RADEON_VF_PRIM_TYPE_LINE_LIST 2
# define RADEON_VF_PRIM_TYPE_LINE_STRIP 3
# define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4
# define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5
# define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6
# define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7
# define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8
# define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9
# define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10
# define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11
# define RADEON_VF_PRIM_TYPE_LINE_LOOP 12
# define RADEON_VF_PRIM_TYPE_QUAD_LIST 13
# define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14
# define RADEON_VF_PRIM_TYPE_POLYGON 15
# define RADEON_VF_PRIM_WALK_STATE (0<<4)
# define RADEON_VF_PRIM_WALK_INDEX (1<<4)
# define RADEON_VF_PRIM_WALK_LIST (2<<4)
# define RADEON_VF_PRIM_WALK_DATA (3<<4)
# define RADEON_VF_COLOR_ORDER_RGBA (1<<6)
# define RADEON_VF_RADEON_MODE (1<<8)
# define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9)
# define RADEON_VF_PROG_STREAM_ENA (1<<10)
# define RADEON_VF_INDEX_SIZE_SHIFT 11
# define RADEON_VF_NUM_VERTICES_SHIFT 16
#define RADEON_SE_PORT_DATA00x2000
#define R200_SE_VAP_CNTL0x2080
# define R200_VAP_TCL_ENABLE0x00000001
# define R200_VAP_SINGLE_BUF_STATE_ENABLE0x00000010
# define R200_VAP_FORCE_W_TO_ONE0x00010000
# define R200_VAP_D3D_TEX_DEFAULT0x00020000
# define R200_VAP_VF_MAX_VTX_NUM__SHIFT18
# define R200_VAP_VF_MAX_VTX_NUM(9 << 18)
# define R200_VAP_DX_CLIP_SPACE_DEF0x00400000
#define R200_VF_MAX_VTX_INDX0x210c
#define R200_VF_MIN_VTX_INDX0x2110
#define R200_SE_VTE_CNTL0x20b0
# define R200_VPORT_X_SCALE_ENA0x00000001
# define R200_VPORT_X_OFFSET_ENA0x00000002
# define R200_VPORT_Y_SCALE_ENA0x00000004
# define R200_VPORT_Y_OFFSET_ENA0x00000008
# define R200_VPORT_Z_SCALE_ENA0x00000010
# define R200_VPORT_Z_OFFSET_ENA0x00000020
# define R200_VTX_XY_FMT0x00000100
# define R200_VTX_Z_FMT0x00000200
# define R200_VTX_W0_FMT0x00000400
# define R200_VTX_W0_NORMALIZE0x00000800
# define R200_VTX_ST_DENORMALIZED0x00001000
#define R200_SE_VAP_CNTL_STATUS0x2140
# define R200_VC_NO_SWAP(0 << 0)
# define R200_VC_16BIT_SWAP(1 << 0)
# define R200_VC_32BIT_SWAP(2 << 0)
#define R200_RE_AUX_SCISSOR_CNTL0x26f0
# define R200_EXCLUSIVE_SCISSOR_00x01000000
# define R200_EXCLUSIVE_SCISSOR_10x02000000
# define R200_EXCLUSIVE_SCISSOR_20x04000000
# define R200_SCISSOR_ENABLE_00x10000000
# define R200_SCISSOR_ENABLE_10x20000000
# define R200_SCISSOR_ENABLE_20x40000000
#define R200_PP_TXFILTER_00x2c00
#define R200_PP_TXFILTER_10x2c20
#define R200_PP_TXFILTER_20x2c40
#define R200_PP_TXFILTER_30x2c60
#define R200_PP_TXFILTER_40x2c80
#define R200_PP_TXFILTER_50x2ca0
# define R200_MAG_FILTER_NEAREST(0 << 0)
# define R200_MAG_FILTER_LINEAR(1 << 0)
# define R200_MAG_FILTER_MASK(1 << 0)
# define R200_MIN_FILTER_NEAREST(0 << 1)
# define R200_MIN_FILTER_LINEAR(1 << 1)
# define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)
# define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)
# define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)
# define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)
# define R200_MIN_FILTER_ANISO_NEAREST(8 << 1)
# define R200_MIN_FILTER_ANISO_LINEAR(9 << 1)
# define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)
# define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)
# define R200_MIN_FILTER_MASK(15 << 1)
# define R200_MAX_ANISO_1_TO_1(0 << 5)
# define R200_MAX_ANISO_2_TO_1(1 << 5)
# define R200_MAX_ANISO_4_TO_1(2 << 5)
# define R200_MAX_ANISO_8_TO_1(3 << 5)
# define R200_MAX_ANISO_16_TO_1(4 << 5)
# define R200_MAX_ANISO_MASK(7 << 5)
# define R200_MAX_MIP_LEVEL_MASK(0x0f << 16)
# define R200_MAX_MIP_LEVEL_SHIFT16
# define R200_YUV_TO_RGB(1 << 20)
# define R200_YUV_TEMPERATURE_COOL(0 << 21)
# define R200_YUV_TEMPERATURE_HOT(1 << 21)
# define R200_YUV_TEMPERATURE_MASK(1 << 21)
# define R200_WRAPEN_S(1 << 22)
# define R200_CLAMP_S_WRAP(0 << 23)
# define R200_CLAMP_S_MIRROR(1 << 23)
# define R200_CLAMP_S_CLAMP_LAST(2 << 23)
# define R200_CLAMP_S_MIRROR_CLAMP_LAST(3 << 23)
# define R200_CLAMP_S_CLAMP_BORDER(4 << 23)
# define R200_CLAMP_S_MIRROR_CLAMP_BORDER(5 << 23)
# define R200_CLAMP_S_CLAMP_GL(6 << 23)
# define R200_CLAMP_S_MIRROR_CLAMP_GL(7 << 23)
# define R200_CLAMP_S_MASK(7 << 23)
# define R200_WRAPEN_T(1 << 26)
# define R200_CLAMP_T_WRAP(0 << 27)
# define R200_CLAMP_T_MIRROR(1 << 27)
# define R200_CLAMP_T_CLAMP_LAST(2 << 27)
# define R200_CLAMP_T_MIRROR_CLAMP_LAST(3 << 27)
# define R200_CLAMP_T_CLAMP_BORDER(4 << 27)
# define R200_CLAMP_T_MIRROR_CLAMP_BORDER(5 << 27)
# define R200_CLAMP_T_CLAMP_GL(6 << 27)
# define R200_CLAMP_T_MIRROR_CLAMP_GL(7 << 27)
# define R200_CLAMP_T_MASK(7 << 27)
# define R200_KILL_LT_ZERO(1 << 30)
# define R200_BORDER_MODE_OGL(0 << 31)
# define R200_BORDER_MODE_D3D(1 << 31)
#define R200_PP_TXFORMAT_00x2c04
#define R200_PP_TXFORMAT_10x2c24
#define R200_PP_TXFORMAT_20x2c44
#define R200_PP_TXFORMAT_30x2c64
#define R200_PP_TXFORMAT_40x2c84
#define R200_PP_TXFORMAT_50x2ca4
# define R200_TXFORMAT_I8(0 << 0)
# define R200_TXFORMAT_AI88(1 << 0)
# define R200_TXFORMAT_RGB332(2 << 0)
# define R200_TXFORMAT_ARGB1555(3 << 0)
# define R200_TXFORMAT_RGB565(4 << 0)
# define R200_TXFORMAT_ARGB4444(5 << 0)
# define R200_TXFORMAT_ARGB8888(6 << 0)
# define R200_TXFORMAT_RGBA8888(7 << 0)
# define R200_TXFORMAT_Y8(8 << 0)
# define R200_TXFORMAT_AVYU4444(9 << 0)
# define R200_TXFORMAT_VYUY422(10 << 0)
# define R200_TXFORMAT_YVYU422(11 << 0)
# define R200_TXFORMAT_DXT1(12 << 0)
# define R200_TXFORMAT_DXT23(14 << 0)
# define R200_TXFORMAT_DXT45(15 << 0)
# define R200_TXFORMAT_ABGR8888(22 << 0)
# define R200_TXFORMAT_FORMAT_MASK(31 <<0)
# define R200_TXFORMAT_FORMAT_SHIFT0
# define R200_TXFORMAT_ALPHA_IN_MAP(1 << 6)
# define R200_TXFORMAT_NON_POWER2(1 << 7)
# define R200_TXFORMAT_WIDTH_MASK(15 <<8)
# define R200_TXFORMAT_WIDTH_SHIFT8
# define R200_TXFORMAT_HEIGHT_MASK(15 << 12)
# define R200_TXFORMAT_HEIGHT_SHIFT12
# define R200_TXFORMAT_F5_WIDTH_MASK(15 << 16)/* cube face 5 */
# define R200_TXFORMAT_F5_WIDTH_SHIFT16
# define R200_TXFORMAT_F5_HEIGHT_MASK(15 << 20)
# define R200_TXFORMAT_F5_HEIGHT_SHIFT20
# define R200_TXFORMAT_ST_ROUTE_STQ0(0 << 24)
# define R200_TXFORMAT_ST_ROUTE_STQ1(1 << 24)
# define R200_TXFORMAT_ST_ROUTE_STQ2(2 << 24)
# define R200_TXFORMAT_ST_ROUTE_STQ3(3 << 24)
# define R200_TXFORMAT_ST_ROUTE_STQ4(4 << 24)
# define R200_TXFORMAT_ST_ROUTE_STQ5(5 << 24)
# define R200_TXFORMAT_ST_ROUTE_MASK(7 << 24)
# define R200_TXFORMAT_ST_ROUTE_SHIFT24
# define R200_TXFORMAT_ALPHA_MASK_ENABLE(1 << 28)
# define R200_TXFORMAT_CHROMA_KEY_ENABLE(1 << 29)
# define R200_TXFORMAT_CUBIC_MAP_ENABLE(1 << 30)
#define R200_PP_TXFORMAT_X_0 0x2c08
#define R200_PP_TXFORMAT_X_1 0x2c28
#define R200_PP_TXFORMAT_X_2 0x2c48
#define R200_PP_TXFORMAT_X_3 0x2c68
#define R200_PP_TXFORMAT_X_4 0x2c88
#define R200_PP_TXFORMAT_X_5 0x2ca8
#define R200_PP_TXSIZE_00x2c0c /* NPOT only */
#define R200_PP_TXSIZE_10x2c2c /* NPOT only */
#define R200_PP_TXSIZE_20x2c4c /* NPOT only */
#define R200_PP_TXSIZE_30x2c6c /* NPOT only */
#define R200_PP_TXSIZE_40x2c8c /* NPOT only */
#define R200_PP_TXSIZE_50x2cac /* NPOT only */
#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */
#define R200_PP_TXPITCH_10x2c30 /* NPOT only */
#define R200_PP_TXPITCH_20x2c50 /* NPOT only */
#define R200_PP_TXPITCH_30x2c70 /* NPOT only */
#define R200_PP_TXPITCH_40x2c90 /* NPOT only */
#define R200_PP_TXPITCH_50x2cb0 /* NPOT only */
#define R200_PP_TXOFFSET_00x2d00
# define R200_TXO_ENDIAN_NO_SWAP(0 << 0)
# define R200_TXO_ENDIAN_BYTE_SWAP(1 << 0)
# define R200_TXO_ENDIAN_WORD_SWAP(2 << 0)
# define R200_TXO_ENDIAN_HALFDW_SWAP(3 << 0)
# define R200_TXO_MACRO_LINEAR(0 << 2)
# define R200_TXO_MACRO_TILE(1 << 2)
# define R200_TXO_MICRO_LINEAR(0 << 3)
# define R200_TXO_MICRO_TILE(1 << 3)
# define R200_TXO_OFFSET_MASK0xffffffe0
# define R200_TXO_OFFSET_SHIFT5
#define R200_PP_TXOFFSET_10x2d18
#define R200_PP_TXOFFSET_20x2d30
#define R200_PP_TXOFFSET_30x2d48
#define R200_PP_TXOFFSET_40x2d60
#define R200_PP_TXOFFSET_50x2d78
#define R200_PP_TFACTOR_00x2ee0
#define R200_PP_TFACTOR_10x2ee4
#define R200_PP_TFACTOR_20x2ee8
#define R200_PP_TFACTOR_30x2eec
#define R200_PP_TFACTOR_40x2ef0
#define R200_PP_TFACTOR_50x2ef4
#define R200_PP_TXCBLEND_00x2f00
# define R200_TXC_ARG_A_ZERO(0)
# define R200_TXC_ARG_A_CURRENT_COLOR(2)
# define R200_TXC_ARG_A_CURRENT_ALPHA(3)
# define R200_TXC_ARG_A_DIFFUSE_COLOR(4)
# define R200_TXC_ARG_A_DIFFUSE_ALPHA(5)
# define R200_TXC_ARG_A_SPECULAR_COLOR(6)
# define R200_TXC_ARG_A_SPECULAR_ALPHA(7)
# define R200_TXC_ARG_A_TFACTOR_COLOR(8)
# define R200_TXC_ARG_A_TFACTOR_ALPHA(9)
# define R200_TXC_ARG_A_R0_COLOR(10)
# define R200_TXC_ARG_A_R0_ALPHA(11)
# define R200_TXC_ARG_A_R1_COLOR(12)
# define R200_TXC_ARG_A_R1_ALPHA(13)
# define R200_TXC_ARG_A_R2_COLOR(14)
# define R200_TXC_ARG_A_R2_ALPHA(15)
# define R200_TXC_ARG_A_R3_COLOR(16)
# define R200_TXC_ARG_A_R3_ALPHA(17)
# define R200_TXC_ARG_A_R4_COLOR(18)
# define R200_TXC_ARG_A_R4_ALPHA(19)
# define R200_TXC_ARG_A_R5_COLOR(20)
# define R200_TXC_ARG_A_R5_ALPHA(21)
# define R200_TXC_ARG_A_TFACTOR1_COLOR(26)
# define R200_TXC_ARG_A_TFACTOR1_ALPHA(27)
# define R200_TXC_ARG_A_MASK(31 << 0)
# define R200_TXC_ARG_A_SHIFT0
# define R200_TXC_ARG_B_ZERO(0 << 5)
# define R200_TXC_ARG_B_CURRENT_COLOR(2 << 5)
# define R200_TXC_ARG_B_CURRENT_ALPHA(3 << 5)
# define R200_TXC_ARG_B_DIFFUSE_COLOR(4 << 5)
# define R200_TXC_ARG_B_DIFFUSE_ALPHA(5 << 5)
# define R200_TXC_ARG_B_SPECULAR_COLOR(6 << 5)
# define R200_TXC_ARG_B_SPECULAR_ALPHA(7 << 5)
# define R200_TXC_ARG_B_TFACTOR_COLOR(8 << 5)
# define R200_TXC_ARG_B_TFACTOR_ALPHA(9 << 5)
# define R200_TXC_ARG_B_R0_COLOR(10 << 5)
# define R200_TXC_ARG_B_R0_ALPHA(11 << 5)
# define R200_TXC_ARG_B_R1_COLOR(12 << 5)
# define R200_TXC_ARG_B_R1_ALPHA(13 << 5)
# define R200_TXC_ARG_B_R2_COLOR(14 << 5)
# define R200_TXC_ARG_B_R2_ALPHA(15 << 5)
# define R200_TXC_ARG_B_R3_COLOR(16 << 5)
# define R200_TXC_ARG_B_R3_ALPHA(17 << 5)
# define R200_TXC_ARG_B_R4_COLOR(18 << 5)
# define R200_TXC_ARG_B_R4_ALPHA(19 << 5)
# define R200_TXC_ARG_B_R5_COLOR(20 << 5)
# define R200_TXC_ARG_B_R5_ALPHA(21 << 5)
# define R200_TXC_ARG_B_TFACTOR1_COLOR(26 << 5)
# define R200_TXC_ARG_B_TFACTOR1_ALPHA(27 << 5)
# define R200_TXC_ARG_B_MASK(31 << 5)
# define R200_TXC_ARG_B_SHIFT5
# define R200_TXC_ARG_C_ZERO(0 << 10)
# define R200_TXC_ARG_C_CURRENT_COLOR(2 << 10)
# define R200_TXC_ARG_C_CURRENT_ALPHA(3 << 10)
# define R200_TXC_ARG_C_DIFFUSE_COLOR(4 << 10)
# define R200_TXC_ARG_C_DIFFUSE_ALPHA(5 << 10)
# define R200_TXC_ARG_C_SPECULAR_COLOR(6 << 10)
# define R200_TXC_ARG_C_SPECULAR_ALPHA(7 << 10)
# define R200_TXC_ARG_C_TFACTOR_COLOR(8 << 10)
# define R200_TXC_ARG_C_TFACTOR_ALPHA(9 << 10)
# define R200_TXC_ARG_C_R0_COLOR(10 << 10)
# define R200_TXC_ARG_C_R0_ALPHA(11 << 10)
# define R200_TXC_ARG_C_R1_COLOR(12 << 10)
# define R200_TXC_ARG_C_R1_ALPHA(13 << 10)
# define R200_TXC_ARG_C_R2_COLOR(14 << 10)
# define R200_TXC_ARG_C_R2_ALPHA(15 << 10)
# define R200_TXC_ARG_C_R3_COLOR(16 << 10)
# define R200_TXC_ARG_C_R3_ALPHA(17 << 10)
# define R200_TXC_ARG_C_R4_COLOR(18 << 10)
# define R200_TXC_ARG_C_R4_ALPHA(19 << 10)
# define R200_TXC_ARG_C_R5_COLOR(20 << 10)
# define R200_TXC_ARG_C_R5_ALPHA(21 << 10)
# define R200_TXC_ARG_C_TFACTOR1_COLOR(26 << 10)
# define R200_TXC_ARG_C_TFACTOR1_ALPHA(27 << 10)
# define R200_TXC_ARG_C_MASK(31 << 10)
# define R200_TXC_ARG_C_SHIFT10
# define R200_TXC_COMP_ARG_A(1 << 16)
# define R200_TXC_COMP_ARG_A_SHIFT(16)
# define R200_TXC_BIAS_ARG_A(1 << 17)
# define R200_TXC_SCALE_ARG_A(1 << 18)
# define R200_TXC_NEG_ARG_A(1 << 19)
# define R200_TXC_COMP_ARG_B(1 << 20)
# define R200_TXC_COMP_ARG_B_SHIFT(20)
# define R200_TXC_BIAS_ARG_B(1 << 21)
# define R200_TXC_SCALE_ARG_B(1 << 22)
# define R200_TXC_NEG_ARG_B(1 << 23)
# define R200_TXC_COMP_ARG_C(1 << 24)
# define R200_TXC_COMP_ARG_C_SHIFT(24)
# define R200_TXC_BIAS_ARG_C(1 << 25)
# define R200_TXC_SCALE_ARG_C(1 << 26)
# define R200_TXC_NEG_ARG_C(1 << 27)
# define R200_TXC_OP_MADD(0 << 28)
# define R200_TXC_OP_CND0(2 << 28)
# define R200_TXC_OP_LERP(3 << 28)
# define R200_TXC_OP_DOT3(4 << 28)
# define R200_TXC_OP_DOT4(5 << 28)
# define R200_TXC_OP_CONDITIONAL(6 << 28)
# define R200_TXC_OP_DOT2_ADD(7 << 28)
# define R200_TXC_OP_MASK(7 << 28)
#define R200_PP_TXCBLEND2_00x2f04
# define R200_TXC_TFACTOR_SEL_SHIFT0
# define R200_TXC_TFACTOR_SEL_MASK0x7
# define R200_TXC_TFACTOR1_SEL_SHIFT4
# define R200_TXC_TFACTOR1_SEL_MASK(0x7 << 4)
# define R200_TXC_SCALE_SHIFT8
# define R200_TXC_SCALE_MASK(7 << 8)
# define R200_TXC_SCALE_1X(0 << 8)
# define R200_TXC_SCALE_2X(1 << 8)
# define R200_TXC_SCALE_4X(2 << 8)
# define R200_TXC_SCALE_8X(3 << 8)
# define R200_TXC_SCALE_INV2(5 << 8)
# define R200_TXC_SCALE_INV4(6 << 8)
# define R200_TXC_SCALE_INV8(7 << 8)
# define R200_TXC_CLAMP_SHIFT12
# define R200_TXC_CLAMP_MASK(3 << 12)
# define R200_TXC_CLAMP_WRAP(0 << 12)
# define R200_TXC_CLAMP_0_1(1 << 12)
# define R200_TXC_CLAMP_8_8(2 << 12)
# define R200_TXC_OUTPUT_REG_MASK(7 << 16)
# define R200_TXC_OUTPUT_REG_NONE(0 << 16)
# define R200_TXC_OUTPUT_REG_R0(1 << 16)
# define R200_TXC_OUTPUT_REG_R1(2 << 16)
# define R200_TXC_OUTPUT_REG_R2(3 << 16)
# define R200_TXC_OUTPUT_REG_R3(4 << 16)
# define R200_TXC_OUTPUT_REG_R4(5 << 16)
# define R200_TXC_OUTPUT_REG_R5(6 << 16)
# define R200_TXC_OUTPUT_MASK_MASK(7 << 20)
# define R200_TXC_OUTPUT_MASK_RGB(0 << 20)
# define R200_TXC_OUTPUT_MASK_RG(1 << 20)
# define R200_TXC_OUTPUT_MASK_RB(2 << 20)
# define R200_TXC_OUTPUT_MASK_R(3 << 20)
# define R200_TXC_OUTPUT_MASK_GB(4 << 20)
# define R200_TXC_OUTPUT_MASK_G(5 << 20)
# define R200_TXC_OUTPUT_MASK_B(6 << 20)
# define R200_TXC_OUTPUT_MASK_NONE(7 << 20)
# define R200_TXC_REPL_NORMAL0
# define R200_TXC_REPL_RED1
# define R200_TXC_REPL_GREEN2
# define R200_TXC_REPL_BLUE3
# define R200_TXC_REPL_ARG_A_SHIFT26
# define R200_TXC_REPL_ARG_A_MASK(3 << 26)
# define R200_TXC_REPL_ARG_B_SHIFT28
# define R200_TXC_REPL_ARG_B_MASK(3 << 28)
# define R200_TXC_REPL_ARG_C_SHIFT30
# define R200_TXC_REPL_ARG_C_MASK(3 << 30)
#define R200_PP_TXABLEND_00x2f08
# define R200_TXA_ARG_A_ZERO(0)
# define R200_TXA_ARG_A_CURRENT_ALPHA(2) /* guess */
# define R200_TXA_ARG_A_CURRENT_BLUE(3) /* guess */
# define R200_TXA_ARG_A_DIFFUSE_ALPHA(4)
# define R200_TXA_ARG_A_DIFFUSE_BLUE(5)
# define R200_TXA_ARG_A_SPECULAR_ALPHA(6)
# define R200_TXA_ARG_A_SPECULAR_BLUE(7)
# define R200_TXA_ARG_A_TFACTOR_ALPHA(8)
# define R200_TXA_ARG_A_TFACTOR_BLUE(9)
# define R200_TXA_ARG_A_R0_ALPHA(10)
# define R200_TXA_ARG_A_R0_BLUE(11)
# define R200_TXA_ARG_A_R1_ALPHA(12)
# define R200_TXA_ARG_A_R1_BLUE(13)
# define R200_TXA_ARG_A_R2_ALPHA(14)
# define R200_TXA_ARG_A_R2_BLUE(15)
# define R200_TXA_ARG_A_R3_ALPHA(16)
# define R200_TXA_ARG_A_R3_BLUE(17)
# define R200_TXA_ARG_A_R4_ALPHA(18)
# define R200_TXA_ARG_A_R4_BLUE(19)
# define R200_TXA_ARG_A_R5_ALPHA(20)
# define R200_TXA_ARG_A_R5_BLUE(21)
# define R200_TXA_ARG_A_TFACTOR1_ALPHA(26)
# define R200_TXA_ARG_A_TFACTOR1_BLUE(27)
# define R200_TXA_ARG_A_MASK(31 << 0)
# define R200_TXA_ARG_A_SHIFT0
# define R200_TXA_ARG_B_ZERO(0 << 5)
# define R200_TXA_ARG_B_CURRENT_ALPHA(2 << 5) /* guess */
# define R200_TXA_ARG_B_CURRENT_BLUE(3 << 5) /* guess */
# define R200_TXA_ARG_B_DIFFUSE_ALPHA(4 << 5)
# define R200_TXA_ARG_B_DIFFUSE_BLUE(5 << 5)
# define R200_TXA_ARG_B_SPECULAR_ALPHA(6 << 5)
# define R200_TXA_ARG_B_SPECULAR_BLUE(7 << 5)
# define R200_TXA_ARG_B_TFACTOR_ALPHA(8 << 5)
# define R200_TXA_ARG_B_TFACTOR_BLUE(9 << 5)
# define R200_TXA_ARG_B_R0_ALPHA(10 << 5)
# define R200_TXA_ARG_B_R0_BLUE(11 << 5)
# define R200_TXA_ARG_B_R1_ALPHA(12 << 5)
# define R200_TXA_ARG_B_R1_BLUE(13 << 5)
# define R200_TXA_ARG_B_R2_ALPHA(14 << 5)
# define R200_TXA_ARG_B_R2_BLUE(15 << 5)
# define R200_TXA_ARG_B_R3_ALPHA(16 << 5)
# define R200_TXA_ARG_B_R3_BLUE(17 << 5)
# define R200_TXA_ARG_B_R4_ALPHA(18 << 5)
# define R200_TXA_ARG_B_R4_BLUE(19 << 5)
# define R200_TXA_ARG_B_R5_ALPHA(20 << 5)
# define R200_TXA_ARG_B_R5_BLUE(21 << 5)
# define R200_TXA_ARG_B_TFACTOR1_ALPHA(26 << 5)
# define R200_TXA_ARG_B_TFACTOR1_BLUE(27 << 5)
# define R200_TXA_ARG_B_MASK(31 << 5)
# define R200_TXA_ARG_B_SHIFT5
# define R200_TXA_ARG_C_ZERO(0 << 10)
# define R200_TXA_ARG_C_CURRENT_ALPHA(2 << 10) /* guess */
# define R200_TXA_ARG_C_CURRENT_BLUE(3 << 10) /* guess */
# define R200_TXA_ARG_C_DIFFUSE_ALPHA(4 << 10)
# define R200_TXA_ARG_C_DIFFUSE_BLUE(5 << 10)
# define R200_TXA_ARG_C_SPECULAR_ALPHA(6 << 10)
# define R200_TXA_ARG_C_SPECULAR_BLUE(7 << 10)
# define R200_TXA_ARG_C_TFACTOR_ALPHA(8 << 10)
# define R200_TXA_ARG_C_TFACTOR_BLUE(9 << 10)
# define R200_TXA_ARG_C_R0_ALPHA(10 << 10)
# define R200_TXA_ARG_C_R0_BLUE(11 << 10)
# define R200_TXA_ARG_C_R1_ALPHA(12 << 10)
# define R200_TXA_ARG_C_R1_BLUE(13 << 10)
# define R200_TXA_ARG_C_R2_ALPHA(14 << 10)
# define R200_TXA_ARG_C_R2_BLUE(15 << 10)
# define R200_TXA_ARG_C_R3_ALPHA(16 << 10)
# define R200_TXA_ARG_C_R3_BLUE(17 << 10)
# define R200_TXA_ARG_C_R4_ALPHA(18 << 10)
# define R200_TXA_ARG_C_R4_BLUE(19 << 10)
# define R200_TXA_ARG_C_R5_ALPHA(20 << 10)
# define R200_TXA_ARG_C_R5_BLUE(21 << 10)
# define R200_TXA_ARG_C_TFACTOR1_ALPHA(26 << 10)
# define R200_TXA_ARG_C_TFACTOR1_BLUE(27 << 10)
# define R200_TXA_ARG_C_MASK(31 << 10)
# define R200_TXA_ARG_C_SHIFT10
# define R200_TXA_COMP_ARG_A(1 << 16)
# define R200_TXA_COMP_ARG_A_SHIFT(16)
# define R200_TXA_BIAS_ARG_A(1 << 17)
# define R200_TXA_SCALE_ARG_A(1 << 18)
# define R200_TXA_NEG_ARG_A(1 << 19)
# define R200_TXA_COMP_ARG_B(1 << 20)
# define R200_TXA_COMP_ARG_B_SHIFT(20)
# define R200_TXA_BIAS_ARG_B(1 << 21)
# define R200_TXA_SCALE_ARG_B(1 << 22)
# define R200_TXA_NEG_ARG_B(1 << 23)
# define R200_TXA_COMP_ARG_C(1 << 24)
# define R200_TXA_COMP_ARG_C_SHIFT(24)
# define R200_TXA_BIAS_ARG_C(1 << 25)
# define R200_TXA_SCALE_ARG_C(1 << 26)
# define R200_TXA_NEG_ARG_C(1 << 27)
# define R200_TXA_OP_MADD(0 << 28)
# define R200_TXA_OP_CND0(2 << 28)
# define R200_TXA_OP_LERP(3 << 28)
# define R200_TXA_OP_CONDITIONAL(6 << 28)
# define R200_TXA_OP_MASK(7 << 28)
#define R200_PP_TXABLEND2_00x2f0c
# define R200_TXA_TFACTOR_SEL_SHIFT0
# define R200_TXA_TFACTOR_SEL_MASK0x7
# define R200_TXA_TFACTOR1_SEL_SHIFT4
# define R200_TXA_TFACTOR1_SEL_MASK(0x7 << 4)
# define R200_TXA_SCALE_SHIFT8
# define R200_TXA_SCALE_MASK(7 << 8)
# define R200_TXA_SCALE_1X(0 << 8)
# define R200_TXA_SCALE_2X(1 << 8)
# define R200_TXA_SCALE_4X(2 << 8)
# define R200_TXA_SCALE_8X(3 << 8)
# define R200_TXA_SCALE_INV2(5 << 8)
# define R200_TXA_SCALE_INV4(6 << 8)
# define R200_TXA_SCALE_INV8(7 << 8)
# define R200_TXA_CLAMP_SHIFT12
# define R200_TXA_CLAMP_MASK(3 << 12)
# define R200_TXA_CLAMP_WRAP(0 << 12)
# define R200_TXA_CLAMP_0_1(1 << 12)
# define R200_TXA_CLAMP_8_8(2 << 12)
# define R200_TXA_OUTPUT_REG_MASK(7 << 16)
# define R200_TXA_OUTPUT_REG_NONE(0 << 16)
# define R200_TXA_OUTPUT_REG_R0(1 << 16)
# define R200_TXA_OUTPUT_REG_R1(2 << 16)
# define R200_TXA_OUTPUT_REG_R2(3 << 16)
# define R200_TXA_OUTPUT_REG_R3(4 << 16)
# define R200_TXA_OUTPUT_REG_R4(5 << 16)
# define R200_TXA_OUTPUT_REG_R5(6 << 16)
# define R200_TXA_DOT_ALPHA(1 << 20)
# define R200_TXA_REPL_NORMAL0
# define R200_TXA_REPL_RED1
# define R200_TXA_REPL_GREEN2
# define R200_TXA_REPL_ARG_A_SHIFT26
# define R200_TXA_REPL_ARG_A_MASK(3 << 26)
# define R200_TXA_REPL_ARG_B_SHIFT28
# define R200_TXA_REPL_ARG_B_MASK(3 << 28)
# define R200_TXA_REPL_ARG_C_SHIFT30
# define R200_TXA_REPL_ARG_C_MASK(3 << 30)
#define R200_PP_TXCBLEND_10x2f10
#define R200_PP_TXCBLEND2_10x2f14
#define R200_PP_TXABLEND_10x2f18
#define R200_PP_TXABLEND2_10x2f1c
#define R200_PP_TXCBLEND_20x2f20
#define R200_PP_TXCBLEND2_20x2f24
#define R200_PP_TXABLEND_20x2f28
#define R200_PP_TXABLEND2_20x2f2c
#define R200_PP_TXCBLEND_30x2f30
#define R200_PP_TXCBLEND2_30x2f34
#define R200_PP_TXABLEND_30x2f38
#define R200_PP_TXABLEND2_30x2f3c
#define R200_SE_VTX_FMT_00x2088
# define R200_VTX_XY0 /* always have xy */
# define R200_VTX_Z0(1<<0)
# define R200_VTX_W0(1<<1)
# define R200_VTX_WEIGHT_COUNT_SHIFT(2)
# define R200_VTX_PV_MATRIX_SEL(1<<5)
# define R200_VTX_N0(1<<6)
# define R200_VTX_POINT_SIZE(1<<7)
# define R200_VTX_DISCRETE_FOG(1<<8)
# define R200_VTX_SHININESS_0(1<<9)
# define R200_VTX_SHININESS_1(1<<10)
# define R200_VTX_COLOR_NOT_PRESENT0
# define R200_VTX_PK_RGBA1
# define R200_VTX_FP_RGB2
# define R200_VTX_FP_RGBA3
# define R200_VTX_COLOR_MASK3
# define R200_VTX_COLOR_0_SHIFT11
# define R200_VTX_COLOR_1_SHIFT13
# define R200_VTX_COLOR_2_SHIFT15
# define R200_VTX_COLOR_3_SHIFT17
# define R200_VTX_COLOR_4_SHIFT19
# define R200_VTX_COLOR_5_SHIFT21
# define R200_VTX_COLOR_6_SHIFT23
# define R200_VTX_COLOR_7_SHIFT25
# define R200_VTX_XY1(1<<28)
# define R200_VTX_Z1(1<<29)
# define R200_VTX_W1(1<<30)
# define R200_VTX_N1(1<<31)
#define R200_SE_VTX_FMT_10x208c
# define R200_VTX_TEX0_COMP_CNT_SHIFT0
# define R200_VTX_TEX1_COMP_CNT_SHIFT3
# define R200_VTX_TEX2_COMP_CNT_SHIFT6
# define R200_VTX_TEX3_COMP_CNT_SHIFT9
# define R200_VTX_TEX4_COMP_CNT_SHIFT12
# define R200_VTX_TEX5_COMP_CNT_SHIFT15
#define R200_SE_TCL_OUTPUT_VTX_FMT_00x2090
#define R200_SE_TCL_OUTPUT_VTX_FMT_10x2094
#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL0x2250
# define R200_OUTPUT_XYZW(1<<0)
# define R200_OUTPUT_COLOR_0(1<<8)
# define R200_OUTPUT_COLOR_1(1<<9)
# define R200_OUTPUT_TEX_0(1<<16)
# define R200_OUTPUT_TEX_1(1<<17)
# define R200_OUTPUT_TEX_2(1<<18)
# define R200_OUTPUT_TEX_3(1<<19)
# define R200_OUTPUT_TEX_4(1<<20)
# define R200_OUTPUT_TEX_5(1<<21)
# define R200_OUTPUT_TEX_MASK(0x3f<<16)
# define R200_OUTPUT_DISCRETE_FOG(1<<24)
# define R200_OUTPUT_PT_SIZE(1<<25)
# define R200_FORCE_INORDER_PROC(1<<31)
#define R200_PP_CNTL_X0x2cc4
#define R200_PP_TXMULTI_CTL_00x2c1c
#define R200_SE_VTX_STATE_CNTL0x2180
# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16)
/* Registers for CP and Microcode Engine */
#define RADEON_CP_ME_RAM_ADDR 0x07d4
#define RADEON_CP_ME_RAM_RADDR 0x07d8
#define RADEON_CP_ME_RAM_DATAH 0x07dc
#define RADEON_CP_ME_RAM_DATAL 0x07e0
#define RADEON_CP_RB_BASE 0x0700
#define RADEON_CP_RB_CNTL 0x0704
#define RADEON_CP_RB_RPTR_ADDR 0x070c
#define RADEON_CP_RB_RPTR 0x0710
#define RADEON_CP_RB_WPTR 0x0714
#define RADEON_CP_IB_BASE 0x0738
#define RADEON_CP_IB_BUFSZ 0x073c
#define RADEON_CP_CSQ_CNTL 0x0740
# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
#define RADEON_CP_CSQ_STAT 0x07f8
# define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0)
# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8)
# define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16)
# define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24)
#define RADEON_CP_CSQ_ADDR 0x07f0
#define RADEON_CP_CSQ_DATA 0x07f4
#define RADEON_CP_CSQ_APER_PRIMARY 0x1000
#define RADEON_CP_CSQ_APER_INDIRECT 0x1300
#define RADEON_CP_RB_WPTR_DELAY 0x0718
# define RADEON_PRE_WRITE_TIMER_SHIFT 0
# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
#define RADEON_AIC_CNTL 0x01d0
# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
#define RADEON_AIC_LO_ADDR 0x01dc
/* Constants */
#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0
#define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2
/* CP packet types */
#define RADEON_CP_PACKET0 0x00000000
#define RADEON_CP_PACKET1 0x40000000
#define RADEON_CP_PACKET2 0x80000000
#define RADEON_CP_PACKET3 0xC0000000
# define RADEON_CP_PACKET_MASK 0xC0000000
# define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
# define RADEON_CP_PACKET_MAX_DWORDS (1 << 12)
# define RADEON_CP_PACKET0_REG_MASK 0x000007ff
# define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
# define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
#define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000
#define RADEON_CP_PACKET3_NOP 0xC0001000
#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900
#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00
#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00
#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300
#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400
#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600
#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800
#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900
#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00
#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00
#define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500
#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00
#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100
#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200
#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300
#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400
#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500
#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800
#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00
#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00
#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00
#define RADEON_CP_VC_FRMT_XY 0x00000000
#define RADEON_CP_VC_FRMT_W0 0x00000001
#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002
#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004
#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008
#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010
#define RADEON_CP_VC_FRMT_FPFOG 0x00000020
#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040
#define RADEON_CP_VC_FRMT_ST0 0x00000080
#define RADEON_CP_VC_FRMT_ST1 0x00000100
#define RADEON_CP_VC_FRMT_Q1 0x00000200
#define RADEON_CP_VC_FRMT_ST2 0x00000400
#define RADEON_CP_VC_FRMT_Q2 0x00000800
#define RADEON_CP_VC_FRMT_ST3 0x00001000
#define RADEON_CP_VC_FRMT_Q3 0x00002000
#define RADEON_CP_VC_FRMT_Q0 0x00004000
#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000
#define RADEON_CP_VC_FRMT_N0 0x00040000
#define RADEON_CP_VC_FRMT_XY1 0x08000000
#define RADEON_CP_VC_FRMT_Z1 0x10000000
#define RADEON_CP_VC_FRMT_W1 0x20000000
#define RADEON_CP_VC_FRMT_N1 0x40000000
#define RADEON_CP_VC_FRMT_Z 0x80000000
#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000
#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001
#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002
#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003
#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007
#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008
#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009
#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a
#define RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST 0x0000000d
#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010
#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020
#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030
#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000
#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040
#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080
#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000
#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100
#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000
#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200
#define RADEON_CP_VC_CNTL_NUM_SHIFT 16
#define RADEON_VS_MATRIX_0_ADDR 0
#define RADEON_VS_MATRIX_1_ADDR 4
#define RADEON_VS_MATRIX_2_ADDR 8
#define RADEON_VS_MATRIX_3_ADDR 12
#define RADEON_VS_MATRIX_4_ADDR 16
#define RADEON_VS_MATRIX_5_ADDR 20
#define RADEON_VS_MATRIX_6_ADDR 24
#define RADEON_VS_MATRIX_7_ADDR 28
#define RADEON_VS_MATRIX_8_ADDR 32
#define RADEON_VS_MATRIX_9_ADDR 36
#define RADEON_VS_MATRIX_10_ADDR 40
#define RADEON_VS_MATRIX_11_ADDR 44
#define RADEON_VS_MATRIX_12_ADDR 48
#define RADEON_VS_MATRIX_13_ADDR 52
#define RADEON_VS_MATRIX_14_ADDR 56
#define RADEON_VS_MATRIX_15_ADDR 60
#define RADEON_VS_LIGHT_AMBIENT_ADDR 64
#define RADEON_VS_LIGHT_DIFFUSE_ADDR 72
#define RADEON_VS_LIGHT_SPECULAR_ADDR 80
#define RADEON_VS_LIGHT_DIRPOS_ADDR 88
#define RADEON_VS_LIGHT_HWVSPOT_ADDR 96
#define RADEON_VS_LIGHT_ATTENUATION_ADDR 104
#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112
#define RADEON_VS_UCP_ADDR 116
#define RADEON_VS_GLOBAL_AMBIENT_ADDR 122
#define RADEON_VS_FOG_PARAM_ADDR 123
#define RADEON_VS_EYE_VECTOR_ADDR 124
#define RADEON_SS_LIGHT_DCD_ADDR 0
#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8
#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16
#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24
#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32
#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48
#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49
#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50
#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51
#define RADEON_SS_SHININESS 60
#define RADEON_TV_MASTER_CNTL 0x0800
# define RADEON_TV_ASYNC_RST (1 << 0)
# define RADEON_CRT_ASYNC_RST (1 << 1)
# define RADEON_RESTART_PHASE_FIX (1 << 3)
#define RADEON_TV_FIFO_ASYNC_RST (1 << 4)
#define RADEON_VIN_ASYNC_RST (1 << 5)
#define RADEON_AUD_ASYNC_RST (1 << 6)
#define RADEON_DVS_ASYNC_RST (1 << 7)
# define RADEON_CRT_FIFO_CE_EN (1 << 9)
# define RADEON_TV_FIFO_CE_EN (1 << 10)
# define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14)
# define RADEON_TVCLK_ALWAYS_ONb (1 << 30)
#define RADEON_TV_ON (1 << 31)
#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888
# define RADEON_Y_RED_EN (1 << 0)
# define RADEON_C_GRN_EN (1 << 1)
# define RADEON_CMP_BLU_EN (1 << 2)
# define RADEON_DAC_DITHER_EN (1 << 3)
# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4)
# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8)
# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12)
# define RADEON_TV_FORCE_DAC_DATA_SHIFT 16
#define RADEON_TV_RGB_CNTL 0x0804
# define RADEON_SWITCH_TO_BLUE (1 << 4)
# define RADEON_RGB_DITHER_EN (1 << 5)
# define RADEON_RGB_SRC_SEL_MASK (3 << 8)
# define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8)
# define RADEON_RGB_SRC_SEL_RMX (1 << 8)
# define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8)
# define RADEON_RGB_CONVERT_BY_PASS (1 << 10)
# define RADEON_UVRAM_READ_MARGIN_SHIFT 16
# define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20
#define RADEON_RGB_ATTEN_SEL(x) ((x) << 24)
#define RADEON_TVOUT_SCALE_EN (1 << 26)
#define RADEON_RGB_ATTEN_VAL(x) ((x) << 28)
#define RADEON_TV_SYNC_CNTL 0x0808
# define RADEON_SYNC_OE (1 << 0)
# define RADEON_SYNC_OUT (1 << 1)
# define RADEON_SYNC_IN (1 << 2)
# define RADEON_SYNC_PUB (1 << 3)
# define RADEON_SYNC_PD (1 << 4)
# define RADEON_TV_SYNC_IO_DRIVE (1 << 5)
#define RADEON_TV_HTOTAL 0x080c
#define RADEON_TV_HDISP 0x0810
#define RADEON_TV_HSTART 0x0818
#define RADEON_TV_HCOUNT 0x081C
#define RADEON_TV_VTOTAL 0x0820
#define RADEON_TV_VDISP 0x0824
#define RADEON_TV_VCOUNT 0x0828
#define RADEON_TV_FTOTAL 0x082c
#define RADEON_TV_FCOUNT 0x0830
#define RADEON_TV_FRESTART 0x0834
#define RADEON_TV_HRESTART 0x0838
#define RADEON_TV_VRESTART 0x083c
#define RADEON_TV_HOST_READ_DATA 0x0840
#define RADEON_TV_HOST_WRITE_DATA 0x0844
#define RADEON_TV_HOST_RD_WT_CNTL 0x0848
#define RADEON_HOST_FIFO_RD (1 << 12)
#define RADEON_HOST_FIFO_RD_ACK (1 << 13)
#define RADEON_HOST_FIFO_WT (1 << 14)
#define RADEON_HOST_FIFO_WT_ACK (1 << 15)
#define RADEON_TV_VSCALER_CNTL1 0x084c
# define RADEON_UV_INC_MASK 0xffff
# define RADEON_UV_INC_SHIFT 0
# define RADEON_Y_W_EN (1 << 24)
# define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */
# define RADEON_Y_DEL_W_SIG_SHIFT 26
#define RADEON_TV_TIMING_CNTL 0x0850
# define RADEON_H_INC_MASK 0xfff
# define RADEON_H_INC_SHIFT 0
# define RADEON_REQ_Y_FIRST (1 << 19)
# define RADEON_FORCE_BURST_ALWAYS (1 << 21)
# define RADEON_UV_POST_SCALE_BYPASS (1 << 23)
# define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24
#define RADEON_TV_VSCALER_CNTL2 0x0854
# define RADEON_DITHER_MODE (1 << 0)
# define RADEON_Y_OUTPUT_DITHER_EN (1 << 1)
# define RADEON_UV_OUTPUT_DITHER_EN (1 << 2)
# define RADEON_UV_TO_BUF_DITHER_EN (1 << 3)
#define RADEON_TV_Y_FALL_CNTL 0x0858
# define RADEON_Y_FALL_PING_PONG (1 << 16)
# define RADEON_Y_COEF_EN (1 << 17)
#define RADEON_TV_Y_RISE_CNTL 0x085c
# define RADEON_Y_RISE_PING_PONG (1 << 16)
#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860
#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864
#define RADEON_YUPSAMP_EN (1 << 0)
#define RADEON_UVUPSAMP_EN (1 << 2)
#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868
# define RADEON_Y_GAIN_LIMIT_SHIFT 0
# define RADEON_UV_GAIN_LIMIT_SHIFT 16
#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c
# define RADEON_Y_GAIN_SHIFT 0
# define RADEON_UV_GAIN_SHIFT 16
#define RADEON_TV_MODULATOR_CNTL1 0x0870
#define RADEON_YFLT_EN (1 << 2)
#define RADEON_UVFLT_EN (1 << 3)
# define RADEON_ALT_PHASE_EN (1 << 6)
# define RADEON_SYNC_TIP_LEVEL (1 << 7)
# define RADEON_BLANK_LEVEL_SHIFT 8
# define RADEON_SET_UP_LEVEL_SHIFT 16
#define RADEON_SLEW_RATE_LIMIT (1 << 23)
# define RADEON_CY_FILT_BLEND_SHIFT 28
#define RADEON_TV_MODULATOR_CNTL2 0x0874
# define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff
# define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff
# define RADEON_TV_V_BURST_LEVEL_SHIFT 16
#define RADEON_TV_CRC_CNTL 0x0890
#define RADEON_TV_UV_ADR 0x08ac
#define RADEON_MAX_UV_ADR_MASK 0x000000ff
#define RADEON_MAX_UV_ADR_SHIFT 0
#define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00
#define RADEON_TABLE1_BOT_ADR_SHIFT 8
#define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000
#define RADEON_TABLE3_TOP_ADR_SHIFT 16
#define RADEON_HCODE_TABLE_SEL_MASK 0x06000000
#define RADEON_HCODE_TABLE_SEL_SHIFT 25
#define RADEON_VCODE_TABLE_SEL_MASK 0x18000000
#define RADEON_VCODE_TABLE_SEL_SHIFT 27
#define RADEON_TV_MAX_FIFO_ADDR 0x1a7
#define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff
#define RADEON_TV_PLL_FINE_CNTL 0x0020/* PLL */
#define RADEON_TV_PLL_CNTL 0x0021/* PLL */
# define RADEON_TV_M0LO_MASK 0xff
# define RADEON_TV_M0HI_MASK 0x7
# define RADEON_TV_M0HI_SHIFT 18
# define RADEON_TV_N0LO_MASK 0x1ff
# define RADEON_TV_N0LO_SHIFT 8
# define RADEON_TV_N0HI_MASK 0x3
# define RADEON_TV_N0HI_SHIFT 21
# define RADEON_TV_P_MASK 0xf
# define RADEON_TV_P_SHIFT 24
# define RADEON_TV_SLIP_EN (1 << 23)
# define RADEON_TV_DTO_EN (1 << 28)
#define RADEON_TV_PLL_CNTL1 0x0022/* PLL */
# define RADEON_TVPLL_RESET (1 << 1)
# define RADEON_TVPLL_SLEEP (1 << 3)
# define RADEON_TVPLL_REFCLK_SEL (1 << 4)
# define RADEON_TVPCP_SHIFT 8
# define RADEON_TVPCP_MASK (7 << 8)
# define RADEON_TVPVG_SHIFT 11
# define RADEON_TVPVG_MASK (7 << 11)
# define RADEON_TVPDC_SHIFT 14
# define RADEON_TVPDC_MASK (3 << 14)
# define RADEON_TVPLL_TEST_DIS (1 << 31)
# define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30)
#define RS400_DISP2_REQ_CNTL10xe30
# define RS400_DISP2_START_REQ_LEVEL_SHIFT 0
# define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff
# define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12
# define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff
# define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22
# define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff
#define RS400_DISP2_REQ_CNTL20xe34
# define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12
# define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff
# define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22
# define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff
#define RS400_DMIF_MEM_CNTL10xe38
# define RS400_DISP2_START_ADR_SHIFT 0
# define RS400_DISP2_START_ADR_MASK 0x3ff
# define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12
# define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff
# define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22
# define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff
#define RS400_DISP1_REQ_CNTL10xe3c
# define RS400_DISP1_START_REQ_LEVEL_SHIFT 0
# define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff
# define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12
# define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff
# define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22
# define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff
#define RS690_MC_INDEX0x78
#define RS690_MC_INDEX_MASK0x1ff
#define RS690_MC_INDEX_WR_EN(1 << 9)
#define RS690_MC_INDEX_WR_ACK0x7f
#define RS690_MC_DATA0x7c
#define RS690_MC_FB_LOCATION0x100
#define RS690_MC_AGP_LOCATION0x101
#define RS690_MC_AGP_BASE0x102
#define RS690_MC_AGP_BASE_2 0x103
#define RS690_MC_INIT_MISC_LAT_TIMER 0x104
#define RS690_MC_STATUS 0x90
#define RS690_MC_STATUS_IDLE (1 << 0)
#define RS600_MC_INDEX 0x70
#define RS600_MC_ADDR_MASK0xffff
# define RS600_MC_IND_SEQ_RBS_0 (1 << 16)
# define RS600_MC_IND_SEQ_RBS_1 (1 << 17)
# define RS600_MC_IND_SEQ_RBS_2 (1 << 18)
# define RS600_MC_IND_SEQ_RBS_3 (1 << 19)
# define RS600_MC_IND_AIC_RBS (1 << 20)
# define RS600_MC_IND_CITF_ARB0 (1 << 21)
# define RS600_MC_IND_CITF_ARB1 (1 << 22)
# define RS600_MC_IND_WR_EN (1 << 23)
#define RS600_MC_DATA 0x74
#define RS600_MC_STATUS 0x0
#define RS600_MC_IDLE (1 << 1)
#define RS600_MC_FB_LOCATION 0x4
#define RS600_MC_AGP_LOCATION 0x5
#define RS600_AGP_BASE 0x6
#define RS600_AGP_BASE2 0x7
#define AVIVO_MC_INDEX0x0070
#define R520_MC_STATUS 0x00
# define R520_MC_STATUS_IDLE (1 << 1)
#define RV515_MC_STATUS 0x08
# define RV515_MC_STATUS_IDLE (1 << 4)
#define RV515_MC_INIT_MISC_LAT_TIMER 0x09
#define AVIVO_MC_DATA0x0074
#define RV515_MC_FB_LOCATION 0x1
#define RV515_MC_AGP_LOCATION 0x2
#define RV515_MC_AGP_BASE 0x3
#define RV515_MC_AGP_BASE_2 0x4
#define RV515_MC_CNTL 0x5
#define RV515_MEM_NUM_CHANNELS_MASK 0x3
#define R520_MC_FB_LOCATION 0x4
#define R520_MC_AGP_LOCATION 0x5
#define R520_MC_AGP_BASE 0x6
#define R520_MC_AGP_BASE_2 0x7
#define R520_MC_CNTL0 0x8
#define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24)
#define R520_MEM_NUM_CHANNELS_SHIFT 24
#define R520_MC_CHANNEL_SIZE (1 << 23)
#define RS780_MC_INDEX0x28f8
#define RS780_MC_INDEX_MASK0x1ff
#define RS780_MC_INDEX_WR_EN(1 << 9)
#define RS780_MC_DATA0x28fc
#define R600_RAMCFG 0x2408
# define R600_CHANSIZE (1 << 7)
# define R600_CHANSIZE_OVERRIDE (1 << 10)
#define R600_SRBM_STATUS 0x0e50
#define AVIVO_CP_DYN_CNTL 0x000f /* PLL */
# define AVIVO_CP_FORCEON (1 << 0)
#define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */
# define AVIVO_E2_FORCEON (1 << 0)
#define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */
# define AVIVO_IDCT_FORCEON (1 << 0)
#define AVIVO_HDP_FB_LOCATION 0x134
#define AVIVO_VGA_RENDER_CONTROL0x0300
# define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16)
#define AVIVO_D1VGA_CONTROL0x0330
# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0)
# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8)
# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9)
# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10)
# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16)
# define AVIVO_DVGA_CONTROL_ROTATE (1<<24)
#define AVIVO_D2VGA_CONTROL0x0338
#define AVIVO_VGA25_PPLL_REF_DIV_SRC0x0360
#define AVIVO_VGA25_PPLL_REF_DIV0x0364
#define AVIVO_VGA28_PPLL_REF_DIV_SRC0x0368
#define AVIVO_VGA28_PPLL_REF_DIV0x036c
#define AVIVO_VGA41_PPLL_REF_DIV_SRC0x0370
#define AVIVO_VGA41_PPLL_REF_DIV0x0374
#define AVIVO_VGA25_PPLL_FB_DIV0x0378
#define AVIVO_VGA28_PPLL_FB_DIV0x037c
#define AVIVO_VGA41_PPLL_FB_DIV0x0380
#define AVIVO_VGA25_PPLL_POST_DIV_SRC0x0384
#define AVIVO_VGA25_PPLL_POST_DIV0x0388
#define AVIVO_VGA28_PPLL_POST_DIV_SRC0x038c
#define AVIVO_VGA28_PPLL_POST_DIV0x0390
#define AVIVO_VGA41_PPLL_POST_DIV_SRC0x0394
#define AVIVO_VGA41_PPLL_POST_DIV0x0398
#define AVIVO_VGA25_PPLL_CNTL0x039c
#define AVIVO_VGA28_PPLL_CNTL0x03a0
#define AVIVO_VGA41_PPLL_CNTL0x03a4
#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400
#define AVIVO_EXT1_PPLL_REF_DIV 0x404
#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408
#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c
#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410
#define AVIVO_EXT2_PPLL_REF_DIV 0x414
#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418
#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c
#define AVIVO_EXT1_PPLL_FB_DIV 0x430
#define AVIVO_EXT2_PPLL_FB_DIV 0x434
#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438
#define AVIVO_EXT1_PPLL_POST_DIV 0x43c
#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440
#define AVIVO_EXT2_PPLL_POST_DIV 0x444
#define AVIVO_EXT1_PPLL_CNTL 0x448
#define AVIVO_EXT2_PPLL_CNTL 0x44c
#define AVIVO_P1PLL_CNTL 0x450
#define AVIVO_P2PLL_CNTL 0x454
#define AVIVO_P1PLL_INT_SS_CNTL 0x458
#define AVIVO_P2PLL_INT_SS_CNTL 0x45c
#define AVIVO_P1PLL_TMDSA_CNTL 0x460
#define AVIVO_P2PLL_LVTMA_CNTL 0x464
#define AVIVO_PCLK_CRTC1_CNTL 0x480
#define AVIVO_PCLK_CRTC2_CNTL 0x484
#define AVIVO_D1CRTC_H_TOTAL0x6000
#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004
#define AVIVO_D1CRTC_H_SYNC_A 0x6008
#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c
#define AVIVO_D1CRTC_H_SYNC_B 0x6010
#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014
#define AVIVO_D1CRTC_V_TOTAL0x6020
#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024
#define AVIVO_D1CRTC_V_SYNC_A 0x6028
#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c
#define AVIVO_D1CRTC_V_SYNC_B 0x6030
#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034
#define AVIVO_D1CRTC_CONTROL 0x6080
# define AVIVO_CRTC_EN (1<<0)
#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084
#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088
#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c
#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
/* master controls */
#define AVIVO_DC_CRTC_MASTER_EN 0x60f8
#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc
#define AVIVO_D1GRPH_ENABLE 0x6100
#define AVIVO_D1GRPH_CONTROL 0x6104
# define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0)
# define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0)
# define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0)
# define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0)
# define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8)
# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8)
# define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8)
# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8)
# define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8)
# define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8)
# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8)
# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8)
# define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8)
# define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8)
# define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8)
# define AVIVO_D1GRPH_SWAP_RB (1<<16)
# define AVIVO_D1GRPH_TILED (1<<20)
# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21)
#define AVIVO_D1GRPH_LUT_SEL 0x6108
#define R600_D1GRPH_SWAP_CONTROL 0x610C
# define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)
# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
/* the *_HIGH surface regs are backwards; the D1 regs are in the D2
* block and vice versa. This applies to GRPH, CUR, etc.
*/
#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914
#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114
#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c
#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c
#define AVIVO_D1GRPH_PITCH 0x6120
#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124
#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128
#define AVIVO_D1GRPH_X_START 0x612c
#define AVIVO_D1GRPH_Y_START 0x6130
#define AVIVO_D1GRPH_X_END 0x6134
#define AVIVO_D1GRPH_Y_END 0x6138
#define AVIVO_D1GRPH_UPDATE 0x6144
# define AVIVO_D1GRPH_UPDATE_LOCK (1<<16)
#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148
#define AVIVO_D1GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL 0x6380
#define AVIVO_D1CUR_CONTROL 0x6400
# define AVIVO_D1CURSOR_EN (1<<0)
# define AVIVO_D1CURSOR_MODE_SHIFT 8
# define AVIVO_D1CURSOR_MODE_MASK (0x3<<8)
# define AVIVO_D1CURSOR_MODE_24BPP (0x2)
#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408
#define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c
#define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c
#define AVIVO_D1CUR_SIZE 0x6410
#define AVIVO_D1CUR_POSITION 0x6414
#define AVIVO_D1CUR_HOT_SPOT 0x6418
#define AVIVO_D1CUR_UPDATE 0x6424
# define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16)
#define AVIVO_DC_LUT_RW_SELECT 0x6480
#define AVIVO_DC_LUT_RW_MODE 0x6484
#define AVIVO_DC_LUT_RW_INDEX 0x6488
#define AVIVO_DC_LUT_SEQ_COLOR 0x648c
#define AVIVO_DC_LUT_PWL_DATA 0x6490
#define AVIVO_DC_LUT_30_COLOR 0x6494
#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498
#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c
#define AVIVO_DC_LUT_AUTOFILL 0x64a0
#define AVIVO_DC_LUTA_CONTROL 0x64c0
#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4
#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8
#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc
#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0
#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
#define AVIVO_DC_LB_MEMORY_SPLIT 0x6520
# define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3
# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0
# define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0
# define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1
# define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2
# define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3
# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2)
# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4
# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff
#define AVIVO_D1MODE_PRIORITY_A_CNT 0x6548
# define AVIVO_DxMODE_PRIORITY_MARK_MASK 0x7fff
# define AVIVO_DxMODE_PRIORITY_OFF (1 << 16)
# define AVIVO_DxMODE_PRIORITY_ALWAYS_ON (1 << 20)
# define AVIVO_DxMODE_PRIORITY_FORCE_MASK (1 << 24)
#define AVIVO_D1MODE_PRIORITY_B_CNT 0x654c
#define AVIVO_D2MODE_PRIORITY_A_CNT 0x6d48
#define AVIVO_D2MODE_PRIORITY_B_CNT 0x6d4c
#define AVIVO_LB_MAX_REQ_OUTSTANDING 0x6d58
# define AVIVO_LB_D1_MAX_REQ_OUTSTANDING_MASK 0xf
# define AVIVO_LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0
# define AVIVO_LB_D2_MAX_REQ_OUTSTANDING_MASK 0xf
# define AVIVO_LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16
#define AVIVO_D1MODE_DATA_FORMAT 0x6528
# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0)
#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c
#define AVIVO_D1MODE_VLINE_START_END 0x6538
# define AVIVO_D1MODE_VLINE_START_SHIFT 0
# define AVIVO_D1MODE_VLINE_END_SHIFT 16
# define AVIVO_D1MODE_VLINE_INV (1 << 31)
#define AVIVO_D1MODE_VLINE_STATUS 0x653c
# define AVIVO_D1MODE_VLINE_STAT (1 << 12)
#define AVIVO_D1MODE_VIEWPORT_START 0x6580
#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c
#define AVIVO_D1SCL_SCALER_ENABLE 0x6590
#define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594
#define AVIVO_D1SCL_UPDATE 0x65cc
# define AVIVO_D1SCL_UPDATE_LOCK (1<<16)
/* second crtc */
#define AVIVO_D2CRTC_H_TOTAL0x6800
#define AVIVO_D2CRTC_H_BLANK_START_END 0x6804
#define AVIVO_D2CRTC_H_SYNC_A 0x6808
#define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c
#define AVIVO_D2CRTC_H_SYNC_B 0x6810
#define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814
#define AVIVO_D2CRTC_V_TOTAL0x6820
#define AVIVO_D2CRTC_V_BLANK_START_END 0x6824
#define AVIVO_D2CRTC_V_SYNC_A 0x6828
#define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c
#define AVIVO_D2CRTC_V_SYNC_B 0x6830
#define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834
#define AVIVO_D2CRTC_CONTROL 0x6880
#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884
#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888
#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c
#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4
#define AVIVO_D2GRPH_ENABLE 0x6900
#define AVIVO_D2GRPH_CONTROL 0x6904
#define AVIVO_D2GRPH_LUT_SEL 0x6908
#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918
#define AVIVO_D2GRPH_PITCH 0x6920
#define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924
#define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928
#define AVIVO_D2GRPH_X_START 0x692c
#define AVIVO_D2GRPH_Y_START 0x6930
#define AVIVO_D2GRPH_X_END 0x6934
#define AVIVO_D2GRPH_Y_END 0x6938
#define AVIVO_D2GRPH_UPDATE 0x6944
#define AVIVO_D2GRPH_FLIP_CONTROL 0x6948
#define AVIVO_D2CUR_CONTROL 0x6c00
#define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08
#define AVIVO_D2CUR_SIZE 0x6c10
#define AVIVO_D2CUR_POSITION 0x6c14
#define RS690_DCP_CONTROL 0x6c9c
#define AVIVO_D2MODE_DATA_FORMAT 0x6d28
#define AVIVO_D2MODE_DESKTOP_HEIGHT 0x6d2c
#define AVIVO_D2MODE_VIEWPORT_START 0x6d80
#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84
#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88
#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c
#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90
#define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94
#define AVIVO_D2SCL_UPDATE 0x6dcc
#define AVIVO_DDIA_BIT_DEPTH_CONTROL0x7214
#define AVIVO_DACA_ENABLE0x7800
#define AVIVO_DAC_ENABLE(1 << 0)
#define AVIVO_DACA_SOURCE_SELECT0x7804
# define AVIVO_DAC_SOURCE_CRTC1 (0 << 0)
# define AVIVO_DAC_SOURCE_CRTC2 (1 << 0)
# define AVIVO_DAC_SOURCE_TV (2 << 0)
#define AVIVO_DACA_FORCE_OUTPUT_CNTL0x783c
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
#define AVIVO_DACA_POWERDOWN0x7850
# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0)
# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8)
# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16)
# define AVIVO_DACA_POWERDOWN_RED (1 << 24)
#define AVIVO_DACB_ENABLE0x7a00
#define AVIVO_DACB_SOURCE_SELECT0x7a04
#define AVIVO_DACB_FORCE_OUTPUT_CNTL0x7a3c
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
#define AVIVO_DACB_POWERDOWN0x7a50
# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0)
# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8)
# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16)
# define AVIVO_DACB_POWERDOWN_RED
#define AVIVO_TMDSA_CNTL 0x7880
# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0)
# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4)
# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8)
# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12)
# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16)
# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24)
# define AVIVO_TMDSA_CNTL_SWAP (1 << 28)
#define AVIVO_TMDSA_SOURCE_SELECT0x7884
/* 78a8 appears to be some kind of (reasonably tolerant) clock?
* 78d0 definitely hits the transmitter, definitely clock. */
/* MYSTERY1 This appears to control dithering? */
#define AVIVO_TMDSA_BIT_DEPTH_CONTROL0x7894
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0
# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0)
# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24)
#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8
# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900
#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL0x7910
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE(1 << 0)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT(2)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN(1 << 6)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS(1 << 13)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS(1 << 15)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL(1 << 28)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL(1 << 31)
#define AVIVO_LVTMA_CNTL0x7a80
# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4)
# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8)
# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12)
# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16)
# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24)
# define AVIVO_LVTMA_CNTL_SWAP (1 << 28)
#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84
#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88
#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0
# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0)
# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24)
#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8
# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
#define R500_LVTMA_CLOCK_ENABLE0x7b00
#define R600_LVTMA_CLOCK_ENABLE0x7b04
#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04
#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
#define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10
#define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
#define R500_LVTMA_PWRSEQ_CNTL0x7af0
#define R600_LVTMA_PWRSEQ_CNTL0x7af4
#define AVIVO_LVTMA_PWRSEQ_EN (1 << 0)
#define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2)
#define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3)
#define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4)
#define AVIVO_LVTMA_SYNCEN (1 << 8)
#define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9)
#define AVIVO_LVTMA_SYNCEN_POL (1 << 10)
#define AVIVO_LVTMA_DIGON (1 << 16)
#define AVIVO_LVTMA_DIGON_OVRD (1 << 17)
#define AVIVO_LVTMA_DIGON_POL (1 << 18)
#define AVIVO_LVTMA_BLON (1 << 24)
#define AVIVO_LVTMA_BLON_OVRD (1 << 25)
#define AVIVO_LVTMA_BLON_POL (1 << 26)
#define R500_LVTMA_PWRSEQ_STATE 0x7af4
#define R600_LVTMA_PWRSEQ_STATE 0x7af8
# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0)
# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1)
# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2)
# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3)
# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4)
# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8)
#define AVIVO_LVDS_BACKLIGHT_CNTL0x7af8
#define AVIVO_LVDS_BACKLIGHT_CNTL_EN(1 << 0)
#define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK0x0000ff00
#define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT8
#define AVIVO_DVOA_BIT_DEPTH_CONTROL0x7988
#define AVIVO_GPIO_0 0x7e30
#define AVIVO_GPIO_1 0x7e40
#define AVIVO_GPIO_2 0x7e50
#define AVIVO_GPIO_3 0x7e60
#define AVIVO_DC_GPIO_HPD_MASK 0x7e90
#define AVIVO_DC_GPIO_HPD_A 0x7e94
#define AVIVO_DC_GPIO_HPD_EN 0x7e98
#define AVIVO_DC_GPIO_HPD_Y 0x7e9c
#define AVIVO_I2C_STATUS0x7d30
#define AVIVO_I2C_STATUS_DONE(1 << 0)
#define AVIVO_I2C_STATUS_NACK(1 << 1)
#define AVIVO_I2C_STATUS_HALT(1 << 2)
#define AVIVO_I2C_STATUS_GO(1 << 3)
#define AVIVO_I2C_STATUS_MASK0x7
/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe
* DONE? */
#define AVIVO_I2C_STATUS_CMD_RESET0x7
#define AVIVO_I2C_STATUS_CMD_WAIT(1 << 3)
#define AVIVO_I2C_STOP0x7d34
#define AVIVO_I2C_START_CNTL0x7d38
#define AVIVO_I2C_START(1 << 8)
#define AVIVO_I2C_CONNECTOR0(0 << 16)
#define AVIVO_I2C_CONNECTOR1(1 << 16)
#define R520_I2C_START (1<<0)
#define R520_I2C_STOP (1<<1)
#define R520_I2C_RX (1<<2)
#define R520_I2C_EN (1<<8)
#define R520_I2C_DDC1 (0<<16)
#define R520_I2C_DDC2 (1<<16)
#define R520_I2C_DDC3 (2<<16)
#define R520_I2C_DDC_MASK (3<<16)
#define AVIVO_I2C_CONTROL20x7d3c
#define AVIVO_I2C_7D3C_SIZE_SHIFT8
#define AVIVO_I2C_7D3C_SIZE_MASK(0xf << 8)
#define AVIVO_I2C_CONTROL30x7d40
/* Reading is done 4 bytes at a time: read the bottom 8 bits from
* 7d44, four times in a row.
* Writing is a little more complex. First write DATA with
* 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic
* magic number, zz is, I think, the slave address, and yy is the byte
* you want to write. */
#define AVIVO_I2C_DATA0x7d44
#define R520_I2C_ADDR_COUNT_MASK (0x7)
#define R520_I2C_DATA_COUNT_SHIFT (8)
#define R520_I2C_DATA_COUNT_MASK (0xF00)
#define AVIVO_I2C_CNTL0x7d50
#define AVIVO_I2C_EN(1 << 0)
#define AVIVO_I2C_RESET(1 << 8)
#define R600_GENERAL_PWRMGT 0x618
#define R600_OPEN_DRAIN_PADS (1 << 11)
#define R600_LOWER_GPIO_ENABLE 0x710
#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718
#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c
#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720
#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724
#define R600_MC_VM_FB_LOCATION 0x2180
#define R600_MC_VM_AGP_TOP 0x2184
#define R600_MC_VM_AGP_BOT 0x2188
#define R600_MC_VM_AGP_BASE 0x218c
#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
#define R700_MC_VM_FB_LOCATION 0x2024
#define R700_MC_VM_AGP_TOP 0x2028
#define R700_MC_VM_AGP_BOT 0x202c
#define R700_MC_VM_AGP_BASE 0x2030
#define R600_HDP_NONSURFACE_BASE 0x2c04
#define R600_BUS_CNTL 0x5420
#define R600_CONFIG_CNTL 0x5424
#define R600_CONFIG_MEMSIZE 0x5428
#define R600_CONFIG_F0_BASE 0x542C
#define R600_CONFIG_APER_SIZE 0x5430
#define R600_ROM_CNTL 0x1600
# define R600_SCK_OVERWRITE (1 << 1)
# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)
#define R600_CG_SPLL_FUNC_CNTL 0x600
# define R600_SPLL_BYPASS_EN (1 << 3)
#define R600_CG_SPLL_STATUS 0x60c
# define R600_SPLL_CHG_STATUS (1 << 1)
#define R600_BIOS_0_SCRATCH 0x1724
#define R600_BIOS_1_SCRATCH 0x1728
#define R600_BIOS_2_SCRATCH 0x172c
#define R600_BIOS_3_SCRATCH 0x1730
#define R600_BIOS_4_SCRATCH 0x1734
#define R600_BIOS_5_SCRATCH 0x1738
#define R600_BIOS_6_SCRATCH 0x173c
#define R600_BIOS_7_SCRATCH 0x1740
/* evergreen */
#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310
#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324
#define EVERGREEN_D3VGA_CONTROL 0x3e0
#define EVERGREEN_D4VGA_CONTROL 0x3e4
#define EVERGREEN_D5VGA_CONTROL 0x3e8
#define EVERGREEN_D6VGA_CONTROL 0x3ec
#define EVERGREEN_P1PLL_SS_CNTL 0x414
#define EVERGREEN_P2PLL_SS_CNTL 0x454
# define EVERGREEN_PxPLL_SS_EN (1 << 12)
/* GRPH blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */
#define EVERGREEN_GRPH_ENABLE 0x6800
#define EVERGREEN_GRPH_CONTROL 0x6804
# define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0)
# define EVERGREEN_GRPH_DEPTH_8BPP 0
# define EVERGREEN_GRPH_DEPTH_16BPP 1
# define EVERGREEN_GRPH_DEPTH_32BPP 2
# define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8)
/* 8 BPP */
# define EVERGREEN_GRPH_FORMAT_INDEXED 0
/* 16 BPP */
# define EVERGREEN_GRPH_FORMAT_ARGB1555 0
# define EVERGREEN_GRPH_FORMAT_ARGB565 1
# define EVERGREEN_GRPH_FORMAT_ARGB4444 2
# define EVERGREEN_GRPH_FORMAT_AI88 3
# define EVERGREEN_GRPH_FORMAT_MONO16 4
# define EVERGREEN_GRPH_FORMAT_BGRA5551 5
/* 32 BPP */
# define EVERGREEN_GRPH_FORMAT_ARGB8888 0
# define EVERGREEN_GRPH_FORMAT_ARGB2101010 1
# define EVERGREEN_GRPH_FORMAT_32BPP_DIG 2
# define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 3
# define EVERGREEN_GRPH_FORMAT_BGRA1010102 4
# define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5
# define EVERGREEN_GRPH_FORMAT_RGB111110 6
# define EVERGREEN_GRPH_FORMAT_BGR101111 7
#define EVERGREEN_GRPH_SWAP_CONTROL 0x680c
# define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)
# define EVERGREEN_GRPH_ENDIAN_NONE 0
# define EVERGREEN_GRPH_ENDIAN_8IN16 1
# define EVERGREEN_GRPH_ENDIAN_8IN32 2
# define EVERGREEN_GRPH_ENDIAN_8IN64 3
# define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)
# define EVERGREEN_GRPH_RED_SEL_R 0
# define EVERGREEN_GRPH_RED_SEL_G 1
# define EVERGREEN_GRPH_RED_SEL_B 2
# define EVERGREEN_GRPH_RED_SEL_A 3
# define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)
# define EVERGREEN_GRPH_GREEN_SEL_G 0
# define EVERGREEN_GRPH_GREEN_SEL_B 1
# define EVERGREEN_GRPH_GREEN_SEL_A 2
# define EVERGREEN_GRPH_GREEN_SEL_R 3
# define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)
# define EVERGREEN_GRPH_BLUE_SEL_B 0
# define EVERGREEN_GRPH_BLUE_SEL_A 1
# define EVERGREEN_GRPH_BLUE_SEL_R 2
# define EVERGREEN_GRPH_BLUE_SEL_G 3
# define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10)
# define EVERGREEN_GRPH_ALPHA_SEL_A 0
# define EVERGREEN_GRPH_ALPHA_SEL_R 1
# define EVERGREEN_GRPH_ALPHA_SEL_G 2
# define EVERGREEN_GRPH_ALPHA_SEL_B 3
#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x6810
#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x6814
# define EVERGREEN_GRPH_DFQ_ENABLE (1 << 0)
# define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff00
#define EVERGREEN_GRPH_PITCH 0x6818
#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x681c
#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x6820
#define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x6824
#define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x6828
#define EVERGREEN_GRPH_X_START 0x682c
#define EVERGREEN_GRPH_Y_START 0x6830
#define EVERGREEN_GRPH_X_END 0x6834
#define EVERGREEN_GRPH_Y_END 0x6838
/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */
#define EVERGREEN_CUR_CONTROL 0x6998
# define EVERGREEN_CURSOR_EN (1 << 0)
# define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8)
# define EVERGREEN_CURSOR_MONO 0
# define EVERGREEN_CURSOR_24_1 1
# define EVERGREEN_CURSOR_24_8_PRE_MULT 2
# define EVERGREEN_CURSOR_24_8_UNPRE_MULT 3
# define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16)
# define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20)
# define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)
# define EVERGREEN_CURSOR_URGENT_ALWAYS 0
# define EVERGREEN_CURSOR_URGENT_1_8 1
# define EVERGREEN_CURSOR_URGENT_1_4 2
# define EVERGREEN_CURSOR_URGENT_3_8 3
# define EVERGREEN_CURSOR_URGENT_1_2 4
#define EVERGREEN_CUR_SURFACE_ADDRESS 0x699c
# define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff000
#define EVERGREEN_CUR_SIZE 0x69a0
#define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x69a4
#define EVERGREEN_CUR_POSITION 0x69a8
#define EVERGREEN_CUR_HOT_SPOT 0x69ac
#define EVERGREEN_CUR_COLOR1 0x69b0
#define EVERGREEN_CUR_COLOR2 0x69b4
#define EVERGREEN_CUR_UPDATE 0x69b8
# define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0)
# define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1)
# define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16)
# define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
/* LUT blocks at 0x69e0, 0x75e0, 0x101e0, 0x10de0, 0x119e0, 0x125e0 */
#define EVERGREEN_DC_LUT_RW_MODE 0x69e0
#define EVERGREEN_DC_LUT_RW_INDEX 0x69e4
#define EVERGREEN_DC_LUT_SEQ_COLOR 0x69e8
#define EVERGREEN_DC_LUT_PWL_DATA 0x69ec
#define EVERGREEN_DC_LUT_30_COLOR 0x69f0
#define EVERGREEN_DC_LUT_VGA_ACCESS_ENABLE 0x69f4
#define EVERGREEN_DC_LUT_WRITE_EN_MASK 0x69f8
#define EVERGREEN_DC_LUT_AUTOFILL 0x69fc
#define EVERGREEN_DC_LUT_CONTROL 0x6a00
#define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE 0x6a04
#define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN 0x6a08
#define EVERGREEN_DC_LUT_BLACK_OFFSET_RED 0x6a0c
#define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE 0x6a10
#define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN 0x6a14
#define EVERGREEN_DC_LUT_WHITE_OFFSET_RED 0x6a18
#define EVERGREEN_DATA_FORMAT 0x6b00
# define EVERGREEN_INTERLEAVE_EN (1 << 0)
#define EVERGREEN_DESKTOP_HEIGHT 0x6b04
#define EVERGREEN_VIEWPORT_START 0x6d70
#define EVERGREEN_VIEWPORT_SIZE 0x6d74
/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */
#define EVERGREEN_CRTC0_REGISTER_OFFSET (0x6df0 - 0x6df0)
#define EVERGREEN_CRTC1_REGISTER_OFFSET (0x79f0 - 0x6df0)
#define EVERGREEN_CRTC2_REGISTER_OFFSET (0x105f0 - 0x6df0)
#define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0)
#define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0)
#define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0)
/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */
#define EVERGREEN_CRTC_CONTROL 0x6e70
# define EVERGREEN_CRTC_MASTER_EN (1 << 0)
#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4
#define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0
#define EVERGREEN_DC_GPIO_HPD_A 0x64b4
#define EVERGREEN_DC_GPIO_HPD_EN 0x64b8
#define EVERGREEN_DC_GPIO_HPD_Y 0x64bc
#define R300_GB_TILE_CONFIG0x4018
# define R300_ENABLE_TILING (1 << 0)
# define R300_PIPE_COUNT_RV350 (0 << 1)
# define R300_PIPE_COUNT_R300 (3 << 1)
# define R300_PIPE_COUNT_R420_3P (6 << 1)
# define R300_PIPE_COUNT_R420 (7 << 1)
# define R300_TILE_SIZE_8 (0 << 4)
# define R300_TILE_SIZE_16 (1 << 4)
# define R300_TILE_SIZE_32 (2 << 4)
# define R300_SUBPIXEL_1_12 (0 << 16)
# define R300_SUBPIXEL_1_16 (1 << 16)
#define R300_GB_SELECT 0x401c
#define R300_GB_ENABLE 0x4008
#define R300_GB_AA_CONFIG0x4020
#define R400_GB_PIPE_SELECT 0x402c
#define R300_GB_MSPOS0 0x4010
# define R300_MS_X0_SHIFT 0
# define R300_MS_Y0_SHIFT 4
# define R300_MS_X1_SHIFT 8
# define R300_MS_Y1_SHIFT 12
# define R300_MS_X2_SHIFT 16
# define R300_MS_Y2_SHIFT 20
# define R300_MSBD0_Y_SHIFT 24
# define R300_MSBD0_X_SHIFT 28
#define R300_GB_MSPOS1 0x4014
# define R300_MS_X3_SHIFT 0
# define R300_MS_Y3_SHIFT 4
# define R300_MS_X4_SHIFT 8
# define R300_MS_Y4_SHIFT 12
# define R300_MS_X5_SHIFT 16
# define R300_MS_Y5_SHIFT 20
# define R300_MSBD1_SHIFT 24
#define R300_GA_ENHANCE 0x4274
# define R300_GA_DEADLOCK_CNTL (1 << 0)
# define R300_GA_FASTSYNC_CNTL (1 << 1)
#define R300_GA_POLY_MODE0x4288
# define R300_FRONT_PTYPE_POINT (0 << 4)
# define R300_FRONT_PTYPE_LINE (1 << 4)
# define R300_FRONT_PTYPE_TRIANGE (2 << 4)
# define R300_BACK_PTYPE_POINT (0 << 7)
# define R300_BACK_PTYPE_LINE (1 << 7)
# define R300_BACK_PTYPE_TRIANGE (2 << 7)
#define R300_GA_ROUND_MODE0x428c
# define R300_GEOMETRY_ROUND_TRUNC (0 << 0)
# define R300_GEOMETRY_ROUND_NEAREST (1 << 0)
# define R300_COLOR_ROUND_TRUNC (0 << 2)
# define R300_COLOR_ROUND_NEAREST (1 << 2)
#define R300_GA_COLOR_CONTROL 0x4278
# define R300_RGB0_SHADING_SOLID (0 << 0)
# define R300_RGB0_SHADING_FLAT (1 << 0)
# define R300_RGB0_SHADING_GOURAUD (2 << 0)
# define R300_ALPHA0_SHADING_SOLID (0 << 2)
# define R300_ALPHA0_SHADING_FLAT (1 << 2)
# define R300_ALPHA0_SHADING_GOURAUD (2 << 2)
# define R300_RGB1_SHADING_SOLID (0 << 4)
# define R300_RGB1_SHADING_FLAT (1 << 4)
# define R300_RGB1_SHADING_GOURAUD (2 << 4)
# define R300_ALPHA1_SHADING_SOLID (0 << 6)
# define R300_ALPHA1_SHADING_FLAT (1 << 6)
# define R300_ALPHA1_SHADING_GOURAUD (2 << 6)
# define R300_RGB2_SHADING_SOLID (0 << 8)
# define R300_RGB2_SHADING_FLAT (1 << 8)
# define R300_RGB2_SHADING_GOURAUD (2 << 8)
# define R300_ALPHA2_SHADING_SOLID (0 << 10)
# define R300_ALPHA2_SHADING_FLAT (1 << 10)
# define R300_ALPHA2_SHADING_GOURAUD (2 << 10)
# define R300_RGB3_SHADING_SOLID (0 << 12)
# define R300_RGB3_SHADING_FLAT (1 << 12)
# define R300_RGB3_SHADING_GOURAUD (2 << 12)
# define R300_ALPHA3_SHADING_SOLID (0 << 14)
# define R300_ALPHA3_SHADING_FLAT (1 << 14)
# define R300_ALPHA3_SHADING_GOURAUD (2 << 14)
#define R300_GA_OFFSET 0x4290
#define R500_SU_REG_DEST 0x42c8
#define R300_VAP_CNTL_STATUS0x2140
# define R300_PVS_BYPASS (1 << 8)
#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284
#define R300_VAP_CNTL 0x2080
# define R300_PVS_NUM_SLOTS_SHIFT 0
# define R300_PVS_NUM_CNTLRS_SHIFT 4
# define R300_PVS_NUM_FPUS_SHIFT 8
# define R300_VF_MAX_VTX_NUM_SHIFT 18
# define R300_GL_CLIP_SPACE_DEF (0 << 22)
# define R300_DX_CLIP_SPACE_DEF (1 << 22)
# define R500_TCL_STATE_OPTIMIZATION (1 << 23)
#define R300_VAP_VTE_CNTL0x20B0
# define R300_VPORT_X_SCALE_ENA (1 << 0)
# define R300_VPORT_X_OFFSET_ENA (1 << 1)
# define R300_VPORT_Y_SCALE_ENA (1 << 2)
# define R300_VPORT_Y_OFFSET_ENA (1 << 3)
# define R300_VPORT_Z_SCALE_ENA (1 << 4)
# define R300_VPORT_Z_OFFSET_ENA (1 << 5)
# define R300_VTX_XY_FMT (1 << 8)
# define R300_VTX_Z_FMT (1 << 9)
# define R300_VTX_W0_FMT (1 << 10)
#define R300_VAP_VTX_STATE_CNTL 0x2180
#define R300_VAP_PSC_SGN_NORM_CNTL 0x21DC
#define R300_VAP_PROG_STREAM_CNTL_0 0x2150
# define R300_DATA_TYPE_0_SHIFT 0
# define R300_DATA_TYPE_FLOAT_1 0
# define R300_DATA_TYPE_FLOAT_2 1
# define R300_DATA_TYPE_FLOAT_3 2
# define R300_DATA_TYPE_FLOAT_4 3
# define R300_DATA_TYPE_BYTE 4
# define R300_DATA_TYPE_D3DCOLOR 5
# define R300_DATA_TYPE_SHORT_2 6
# define R300_DATA_TYPE_SHORT_4 7
# define R300_DATA_TYPE_VECTOR_3_TTT 8
# define R300_DATA_TYPE_VECTOR_3_EET 9
# define R300_SKIP_DWORDS_0_SHIFT 4
# define R300_DST_VEC_LOC_0_SHIFT 8
# define R300_LAST_VEC_0 (1 << 13)
# define R300_SIGNED_0 (1 << 14)
# define R300_NORMALIZE_0 (1 << 15)
# define R300_DATA_TYPE_1_SHIFT 16
# define R300_SKIP_DWORDS_1_SHIFT 20
# define R300_DST_VEC_LOC_1_SHIFT 24
# define R300_LAST_VEC_1 (1 << 29)
# define R300_SIGNED_1 (1 << 30)
# define R300_NORMALIZE_1 (1 << 31)
#define R300_VAP_PROG_STREAM_CNTL_1 0x2154
# define R300_DATA_TYPE_2_SHIFT 0
# define R300_SKIP_DWORDS_2_SHIFT 4
# define R300_DST_VEC_LOC_2_SHIFT 8
# define R300_LAST_VEC_2 (1 << 13)
# define R300_SIGNED_2 (1 << 14)
# define R300_NORMALIZE_2 (1 << 15)
# define R300_DATA_TYPE_3_SHIFT 16
# define R300_SKIP_DWORDS_3_SHIFT 20
# define R300_DST_VEC_LOC_3_SHIFT 24
# define R300_LAST_VEC_3 (1 << 29)
# define R300_SIGNED_3 (1 << 30)
# define R300_NORMALIZE_3 (1 << 31)
#define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0
# define R300_SWIZZLE_SELECT_X_0_SHIFT 0
# define R300_SWIZZLE_SELECT_Y_0_SHIFT 3
# define R300_SWIZZLE_SELECT_Z_0_SHIFT 6
# define R300_SWIZZLE_SELECT_W_0_SHIFT 9
# define R300_SWIZZLE_SELECT_X 0
# define R300_SWIZZLE_SELECT_Y 1
# define R300_SWIZZLE_SELECT_Z 2
# define R300_SWIZZLE_SELECT_W 3
# define R300_SWIZZLE_SELECT_FP_ZERO 4
# define R300_SWIZZLE_SELECT_FP_ONE 5
# define R300_WRITE_ENA_0_SHIFT 12
# define R300_WRITE_ENA_X 1
# define R300_WRITE_ENA_Y 2
# define R300_WRITE_ENA_Z 4
# define R300_WRITE_ENA_W 8
# define R300_SWIZZLE_SELECT_X_1_SHIFT 16
# define R300_SWIZZLE_SELECT_Y_1_SHIFT 19
# define R300_SWIZZLE_SELECT_Z_1_SHIFT 22
# define R300_SWIZZLE_SELECT_W_1_SHIFT 25
# define R300_WRITE_ENA_1_SHIFT 28
#define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4
# define R300_SWIZZLE_SELECT_X_2_SHIFT 0
# define R300_SWIZZLE_SELECT_Y_2_SHIFT 3
# define R300_SWIZZLE_SELECT_Z_2_SHIFT 6
# define R300_SWIZZLE_SELECT_W_2_SHIFT 9
# define R300_WRITE_ENA_2_SHIFT 12
# define R300_SWIZZLE_SELECT_X_3_SHIFT 16
# define R300_SWIZZLE_SELECT_Y_3_SHIFT 19
# define R300_SWIZZLE_SELECT_Z_3_SHIFT 22
# define R300_SWIZZLE_SELECT_W_3_SHIFT 25
# define R300_WRITE_ENA_3_SHIFT 28
#define R300_VAP_PVS_CODE_CNTL_00x22D0
# define R300_PVS_FIRST_INST_SHIFT 0
# define R300_PVS_XYZW_VALID_INST_SHIFT 10
# define R300_PVS_LAST_INST_SHIFT 20
#define R300_VAP_PVS_CODE_CNTL_10x22D8
# define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0
#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200
# define R300_PVS_CODE_START 0
# define R300_PVS_CONST_START 512
# define R500_PVS_CONST_START 1024
# define R300_PVS_VECTOR_INST_INDEX(x) ((x) + R300_PVS_CODE_START)
# define R300_PVS_VECTOR_CONST_INDEX(x) ((x) + R300_PVS_CONST_START)
# define R500_PVS_VECTOR_CONST_INDEX(x) ((x) + R500_PVS_CONST_START)
#define R300_VAP_PVS_VECTOR_DATA_REG 0x2204
/* PVS instructions */
/* Opcode and dst instruction */
#define R300_PVS_DST_OPCODE(x) ((x) << 0)
/* Vector ops */
# define R300_VECTOR_NO_OP 0
# define R300_VE_DOT_PRODUCT 1
# define R300_VE_MULTIPLY 2
# define R300_VE_ADD 3
# define R300_VE_MULTIPLY_ADD 4
# define R300_VE_DISTANCE_VECTOR 5
# define R300_VE_FRACTION 6
# define R300_VE_MAXIMUM 7
# define R300_VE_MINIMUM 8
# define R300_VE_SET_GREATER_THAN_EQUAL 9
# define R300_VE_SET_LESS_THAN 10
# define R300_VE_MULTIPLYX2_ADD 11
# define R300_VE_MULTIPLY_CLAMP 12
# define R300_VE_FLT2FIX_DX 13
# define R300_VE_FLT2FIX_DX_RND 14
/* R500 additions */
# define R500_VE_PRED_SET_EQ_PUSH 15
# define R500_VE_PRED_SET_GT_PUSH 16
# define R500_VE_PRED_SET_GTE_PUSH 17
# define R500_VE_PRED_SET_NEQ_PUSH 18
# define R500_VE_COND_WRITE_EQ 19
# define R500_VE_COND_WRITE_GT 20
# define R500_VE_COND_WRITE_GTE 21
# define R500_VE_COND_WRITE_NEQ 22
# define R500_VE_COND_MUX_EQ 23
# define R500_VE_COND_MUX_GT 24
# define R500_VE_COND_MUX_GTE 25
# define R500_VE_SET_GREATER_THAN 26
# define R500_VE_SET_EQUAL 27
# define R500_VE_SET_NOT_EQUAL 28
/* Math ops */
# define R300_MATH_NO_OP 0
# define R300_ME_EXP_BASE2_DX 1
# define R300_ME_LOG_BASE2_DX 2
# define R300_ME_EXP_BASEE_FF 3
# define R300_ME_LIGHT_COEFF_DX 4
# define R300_ME_POWER_FUNC_FF 5
# define R300_ME_RECIP_DX 6
# define R300_ME_RECIP_FF 7
# define R300_ME_RECIP_SQRT_DX 8
# define R300_ME_RECIP_SQRT_FF 9
# define R300_ME_MULTIPLY 10
# define R300_ME_EXP_BASE2_FULL_DX 11
# define R300_ME_LOG_BASE2_FULL_DX 12
# define R300_ME_POWER_FUNC_FF_CLAMP_B 13
# define R300_ME_POWER_FUNC_FF_CLAMP_B1 14
# define R300_ME_POWER_FUNC_FF_CLAMP_01 15
# define R300_ME_SIN 16
# define R300_ME_COS 17
/* R500 additions */
# define R500_ME_LOG_BASE2_IEEE 18
# define R500_ME_RECIP_IEEE 19
# define R500_ME_RECIP_SQRT_IEEE 20
# define R500_ME_PRED_SET_EQ 21
# define R500_ME_PRED_SET_GT 22
# define R500_ME_PRED_SET_GTE 23
# define R500_ME_PRED_SET_NEQ 24
# define R500_ME_PRED_SET_CLR 25
# define R500_ME_PRED_SET_INV 26
# define R500_ME_PRED_SET_POP 27
# define R500_ME_PRED_SET_RESTORE 28
/* macro */
# define R300_PVS_MACRO_OP_2CLK_MADD 0
# define R300_PVS_MACRO_OP_2CLK_M2X_ADD 1
#define R300_PVS_DST_MATH_INST (1 << 6)
#define R300_PVS_DST_MACRO_INST (1 << 7)
#define R300_PVS_DST_REG_TYPE(x) ((x) << 8)
# define R300_PVS_DST_REG_TEMPORARY 0
# define R300_PVS_DST_REG_A0 1
# define R300_PVS_DST_REG_OUT 2
# define R500_PVS_DST_REG_OUT_REPL_X 3
# define R300_PVS_DST_REG_ALT_TEMPORARY 4
# define R300_PVS_DST_REG_INPUT 5
#define R300_PVS_DST_ADDR_MODE_1 (1 << 12)
#define R300_PVS_DST_OFFSET(x) ((x) << 13)
#define R300_PVS_DST_WE_X (1 << 20)
#define R300_PVS_DST_WE_Y (1 << 21)
#define R300_PVS_DST_WE_Z (1 << 22)
#define R300_PVS_DST_WE_W (1 << 23)
#define R300_PVS_DST_VE_SAT (1 << 24)
#define R300_PVS_DST_ME_SAT (1 << 25)
#define R300_PVS_DST_PRED_ENABLE (1 << 26)
#define R300_PVS_DST_PRED_SENSE (1 << 27)
#define R300_PVS_DST_DUAL_MATH_OP (1 << 28)
#define R300_PVS_DST_ADDR_SEL(x) ((x) << 29)
#define R300_PVS_DST_ADDR_MODE_0 (1 << 31)
/* src operand instruction */
#define R300_PVS_SRC_REG_TYPE(x) ((x) << 0)
# define R300_PVS_SRC_REG_TEMPORARY 0
# define R300_PVS_SRC_REG_INPUT 1
# define R300_PVS_SRC_REG_CONSTANT 2
# define R300_PVS_SRC_REG_ALT_TEMPORARY 3
#define R300_SPARE_0 (1 << 2)
#define R300_PVS_SRC_ABS_XYZW (1 << 3)
#define R300_PVS_SRC_ADDR_MODE_0 (1 << 4)
#define R300_PVS_SRC_OFFSET(x) ((x) << 5)
#define R300_PVS_SRC_SWIZZLE_X(x) ((x) << 13)
#define R300_PVS_SRC_SWIZZLE_Y(x) ((x) << 16)
#define R300_PVS_SRC_SWIZZLE_Z(x) ((x) << 19)
#define R300_PVS_SRC_SWIZZLE_W(x) ((x) << 22)
# define R300_PVS_SRC_SELECT_X 0
# define R300_PVS_SRC_SELECT_Y 1
# define R300_PVS_SRC_SELECT_Z 2
# define R300_PVS_SRC_SELECT_W 3
# define R300_PVS_SRC_SELECT_FORCE_0 4
# define R300_PVS_SRC_SELECT_FORCE_1 5
#define R300_PVS_SRC_NEG_X (1 << 25)
#define R300_PVS_SRC_NEG_Y (1 << 26)
#define R300_PVS_SRC_NEG_Z (1 << 27)
#define R300_PVS_SRC_NEG_W (1 << 28)
#define R300_PVS_SRC_ADDR_SEL(x) ((x) << 29)
#define R300_PVS_SRC_ADDR_MODE_1 (1 << 31)
#define R300_VAP_PVS_CONST_CNTL 0x22d4
# define R300_PVS_CONST_BASE_OFFSET(x) ((x) << 0)
# define R300_PVS_MAX_CONST_ADDR(x) ((x) << 16)
#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22dc
#define R300_VAP_OUT_VTX_FMT_0 0x2090
# define R300_VTX_POS_PRESENT (1 << 0)
# define R300_VTX_COLOR_0_PRESENT (1 << 1)
# define R300_VTX_COLOR_1_PRESENT (1 << 2)
# define R300_VTX_COLOR_2_PRESENT (1 << 3)
# define R300_VTX_COLOR_3_PRESENT (1 << 4)
# define R300_VTX_PT_SIZE_PRESENT (1 << 16)
#define R300_VAP_OUT_VTX_FMT_1 0x2094
# define R300_TEX_0_COMP_CNT_SHIFT 0
# define R300_TEX_1_COMP_CNT_SHIFT 3
# define R300_TEX_2_COMP_CNT_SHIFT 6
# define R300_TEX_3_COMP_CNT_SHIFT 9
# define R300_TEX_4_COMP_CNT_SHIFT 12
# define R300_TEX_5_COMP_CNT_SHIFT 15
# define R300_TEX_6_COMP_CNT_SHIFT 18
# define R300_TEX_7_COMP_CNT_SHIFT 21
#define R300_VAP_VTX_SIZE0x20b4
#define R300_VAP_GB_VERT_CLIP_ADJ 0x2220
#define R300_VAP_GB_VERT_DISC_ADJ 0x2224
#define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228
#define R300_VAP_GB_HORZ_DISC_ADJ 0x222c
#define R300_VAP_CLIP_CNTL0x221c
# define R300_UCP_ENA_0 (1 << 0)
# define R300_UCP_ENA_1 (1 << 1)
# define R300_UCP_ENA_2 (1 << 2)
# define R300_UCP_ENA_3 (1 << 3)
# define R300_UCP_ENA_4 (1 << 4)
# define R300_UCP_ENA_5 (1 << 5)
# define R300_PS_UCP_MODE_SHIFT 14
# define R300_CLIP_DISABLE (1 << 16)
# define R300_UCP_CULL_ONLY_ENA (1 << 17)
# define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18)
#define R300_VAP_PVS_STATE_FLUSH_REG0x2284
#define R500_VAP_INDEX_OFFSET 0x208c
#define R300_SU_TEX_WRAP0x42a0
#define R300_SU_POLY_OFFSET_ENABLE 0x42b4
#define R300_SU_CULL_MODE0x42b8
# define R300_CULL_FRONT (1 << 0)
# define R300_CULL_BACK (1 << 1)
# define R300_FACE_POS (0 << 2)
# define R300_FACE_NEG (1 << 2)
#define R300_SU_DEPTH_SCALE0x42c0
#define R300_SU_DEPTH_OFFSET 0x42c4
#define R300_RS_COUNT 0x4300
#define R300_RS_COUNT_IT_COUNT_SHIFT0
#define R300_RS_COUNT_IC_COUNT_SHIFT7
#define R300_RS_COUNT_HIRES_EN(1 << 18)
#define R300_RS_IP_0 0x4310
#define R300_RS_IP_1 0x4314
#define R300_RS_TEX_PTR(x) ((x) << 0)
#define R300_RS_COL_PTR(x) ((x) << 6)
#define R300_RS_COL_FMT(x) ((x) << 9)
#define R300_RS_COL_FMT_RGBA 0
#define R300_RS_COL_FMT_RGB0 2
#define R300_RS_COL_FMT_RGB1 3
#define R300_RS_COL_FMT_000A 4
#define R300_RS_COL_FMT_0000 5
#define R300_RS_COL_FMT_0001 6
#define R300_RS_COL_FMT_111A 8
#define R300_RS_COL_FMT_1110 9
#define R300_RS_COL_FMT_1111 10
#define R300_RS_SEL_S(x) ((x) << 13)
#define R300_RS_SEL_T(x) ((x) << 16)
#define R300_RS_SEL_R(x) ((x) << 19)
#define R300_RS_SEL_Q(x) ((x) << 22)
#define R300_RS_SEL_C0 0
#define R300_RS_SEL_C1 1
#define R300_RS_SEL_C2 2
#define R300_RS_SEL_C3 3
#define R300_RS_SEL_K0 4
#define R300_RS_SEL_K1 5
#define R300_RS_INST_COUNT0x4304
#define R300_INST_COUNT_RS(x) ((x) << 0)
#define R300_RS_W_EN (1 << 4)
#define R300_TX_OFFSET_RS(x) ((x) << 5)
#define R300_RS_INST_0 0x4330
#define R300_RS_INST_1 0x4334
#define R300_INST_TEX_ID(x) ((x) << 0)
# define R300_RS_INST_TEX_CN_WRITE(1 << 3)
#define R300_INST_TEX_ADDR(x) ((x) << 6)
#define R300_TX_INVALTAGS0x4100
#define R300_TX_FILTER0_00x4400
#define R300_TX_FILTER0_10x4404
#define R300_TX_FILTER0_20x4408
# define R300_TX_CLAMP_S(x) ((x) << 0)
# define R300_TX_CLAMP_T(x) ((x) << 3)
# define R300_TX_CLAMP_R(x) ((x) << 6)
# define R300_TX_CLAMP_WRAP 0
# define R300_TX_CLAMP_MIRROR 1
# define R300_TX_CLAMP_CLAMP_LAST 2
# define R300_TX_CLAMP_MIRROR_CLAMP_LAST 3
# define R300_TX_CLAMP_CLAMP_BORDER 4
# define R300_TX_CLAMP_MIRROR_CLAMP_BORDER 5
# define R300_TX_CLAMP_CLAMP_GL 6
# define R300_TX_CLAMP_MIRROR_CLAMP_GL 7
# define R300_TX_MAG_FILTER_NEAREST (1 << 9)
# define R300_TX_MIN_FILTER_NEAREST (1 << 11)
# define R300_TX_MAG_FILTER_LINEAR (2 << 9)
# define R300_TX_MIN_FILTER_LINEAR (2 << 11)
# define R300_TX_ID_SHIFT 28
#define R300_TX_FILTER1_00x4440
#define R300_TX_FILTER1_10x4444
#define R300_TX_FILTER1_20x4448
#define R300_TX_FORMAT0_00x4480
#define R300_TX_FORMAT0_10x4484
#define R300_TX_FORMAT0_20x4488
# define R300_TXWIDTH_SHIFT 0
# define R300_TXHEIGHT_SHIFT 11
# define R300_NUM_LEVELS_SHIFT 26
# define R300_NUM_LEVELS_MASK 0x
# define R300_TXPROJECTED (1 << 30)
# define R300_TXPITCH_EN (1 << 31)
#define R300_TX_FORMAT1_00x44c0
#define R300_TX_FORMAT1_10x44c4
#define R300_TX_FORMAT1_20x44c8
#define R300_TX_FORMAT_X8 0x0
#define R300_TX_FORMAT_X16 0x1
#define R300_TX_FORMAT_Y4X4 0x2
#define R300_TX_FORMAT_Y8X8 0x3
#define R300_TX_FORMAT_Y16X16 0x4
#define R300_TX_FORMAT_Z3Y3X2 0x5
#define R300_TX_FORMAT_Z5Y6X5 0x6
#define R300_TX_FORMAT_Z6Y5X5 0x7
#define R300_TX_FORMAT_Z11Y11X10 0x8
#define R300_TX_FORMAT_Z10Y11X11 0x9
#define R300_TX_FORMAT_W4Z4Y4X4 0xA
#define R300_TX_FORMAT_W1Z5Y5X5 0xB
#define R300_TX_FORMAT_W8Z8Y8X8 0xC
#define R300_TX_FORMAT_W2Z10Y10X10 0xD
#define R300_TX_FORMAT_W16Z16Y16X16 0xE
#define R300_TX_FORMAT_DXT1 0xF
#define R300_TX_FORMAT_DXT3 0x10
#define R300_TX_FORMAT_DXT5 0x11
#define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */
#define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
#define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
#define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
#define R300_TX_FORMAT_VYUY422 0x14 /* no swizzle */
#define R300_TX_FORMAT_YVYU422 0x15 /* no swizzle */
#define R300_TX_FORMAT_X24_Y8 0x1e
#define R300_TX_FORMAT_X32 0x1e
/* Floating point formats */
/* Note - hardware supports both 16 and 32 bit floating point */
#define R300_TX_FORMAT_FL_I16 0x18
#define R300_TX_FORMAT_FL_I16A16 0x19
#define R300_TX_FORMAT_FL_R16G16B16A16 0x1A
#define R300_TX_FORMAT_FL_I32 0x1B
#define R300_TX_FORMAT_FL_I32A32 0x1C
#define R300_TX_FORMAT_FL_R32G32B32A32 0x1D
/* alpha modes, convenience mostly */
/* if you have alpha, pick constant appropriate to the
number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
# define R300_TX_FORMAT_ALPHA_1CH 0x000
# define R300_TX_FORMAT_ALPHA_2CH 0x200
# define R300_TX_FORMAT_ALPHA_4CH 0x600
# define R300_TX_FORMAT_ALPHA_NONE 0xA00
/* Swizzling */
/* constants */
#define R300_TX_FORMAT_X0
#define R300_TX_FORMAT_Y1
#define R300_TX_FORMAT_Z2
#define R300_TX_FORMAT_W3
#define R300_TX_FORMAT_ZERO4
#define R300_TX_FORMAT_ONE5
/* 2.0*Z, everything above 1.0 is set to 0.0 */
#define R300_TX_FORMAT_CUT_Z6
/* 2.0*W, everything above 1.0 is set to 0.0 */
#define R300_TX_FORMAT_CUT_W7
#define R300_TX_FORMAT_B_SHIFT18
#define R300_TX_FORMAT_G_SHIFT15
#define R300_TX_FORMAT_R_SHIFT12
#define R300_TX_FORMAT_A_SHIFT9
/* Convenience macro to take care of layout and swizzling */
#define R300_EASY_TX_FORMAT(B, G, R, A, FMT)(\
((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT)\
| ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT)\
| ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT)\
| ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT)\
| (R300_TX_FORMAT_##FMT)\
)
# define R300_TX_FORMAT_YUV_TO_RGB_CLAMP (1 << 22)
# define R300_TX_FORMAT_YUV_TO_RGB_NO_CLAMP (2 << 22)
# define R300_TX_FORMAT_SWAP_YUV (1 << 24)
# define R300_TX_FORMAT_CACHE_WHOLE (0 << 27)
# define R300_TX_FORMAT_CACHE_HALF_REGION_0 (2 << 27)
# define R300_TX_FORMAT_CACHE_HALF_REGION_1 (3 << 27)
# define R300_TX_FORMAT_CACHE_FOURTH_REGION_0 (4 << 27)
# define R300_TX_FORMAT_CACHE_FOURTH_REGION_1 (5 << 27)
# define R300_TX_FORMAT_CACHE_FOURTH_REGION_2 (6 << 27)
# define R300_TX_FORMAT_CACHE_FOURTH_REGION_3 (7 << 27)
#define R300_TX_FORMAT2_00x4500
#define R300_TX_FORMAT2_10x4504
#define R300_TX_FORMAT2_20x4508
# define R500_TXWIDTH_11 (1 << 15)
# define R500_TXHEIGHT_11 (1 << 16)
#define R300_TX_OFFSET_00x4540
#define R300_TX_OFFSET_10x4544
#define R300_TX_OFFSET_20x4548
# define R300_ENDIAN_SWAP_16_BIT (1 << 0)
# define R300_ENDIAN_SWAP_32_BIT (2 << 0)
# define R300_ENDIAN_SWAP_HALF_DWORD (3 << 0)
# define R300_MACRO_TILE (1 << 2)
#define R300_TX_BORDER_COLOR_0 0x45c0
#define R300_TX_ENABLE 0x4104
# define R300_TEX_0_ENABLE (1 << 0)
# define R300_TEX_1_ENABLE (1 << 1)
# define R300_TEX_2_ENABLE (1 << 2)
#define R300_US_W_FMT 0x46b4
#define R300_US_OUT_FMT_10x46a8
#define R300_US_OUT_FMT_20x46ac
#define R300_US_OUT_FMT_30x46b0
#define R300_US_OUT_FMT_00x46a4
# define R300_OUT_FMT_C4_8 (0 << 0)
# define R300_OUT_FMT_C4_10 (1 << 0)
# define R300_OUT_FMT_C4_10_GAMMA (2 << 0)
# define R300_OUT_FMT_C_16 (3 << 0)
# define R300_OUT_FMT_C2_16 (4 << 0)
# define R300_OUT_FMT_C4_16 (5 << 0)
# define R300_OUT_FMT_C_16_MPEG (6 << 0)
# define R300_OUT_FMT_C2_16_MPEG (7 << 0)
# define R300_OUT_FMT_C2_4 (8 << 0)
# define R300_OUT_FMT_C_3_3_2 (9 << 0)
# define R300_OUT_FMT_C_5_6_5 (10 << 0)
# define R300_OUT_FMT_C_11_11_10 (11 << 0)
# define R300_OUT_FMT_C_10_11_11 (12 << 0)
# define R300_OUT_FMT_C_2_10_10_10 (13 << 0)
# define R300_OUT_FMT_UNUSED (15 << 0)
# define R300_OUT_FMT_C_16_FP (16 << 0)
# define R300_OUT_FMT_C2_16_FP (17 << 0)
# define R300_OUT_FMT_C4_16_FP (18 << 0)
# define R300_OUT_FMT_C_32_FP (19 << 0)
# define R300_OUT_FMT_C2_32_FP (20 << 0)
# define R300_OUT_FMT_C4_32_FP (21 << 0)
# define R300_OUT_FMT_C0_SEL_ALPHA (0 << 8)
# define R300_OUT_FMT_C0_SEL_RED (1 << 8)
# define R300_OUT_FMT_C0_SEL_GREEN (2 << 8)
# define R300_OUT_FMT_C0_SEL_BLUE (3 << 8)
# define R300_OUT_FMT_C1_SEL_ALPHA (0 << 10)
# define R300_OUT_FMT_C1_SEL_RED (1 << 10)
# define R300_OUT_FMT_C1_SEL_GREEN (2 << 10)
# define R300_OUT_FMT_C1_SEL_BLUE (3 << 10)
# define R300_OUT_FMT_C2_SEL_ALPHA (0 << 12)
# define R300_OUT_FMT_C2_SEL_RED (1 << 12)
# define R300_OUT_FMT_C2_SEL_GREEN (2 << 12)
# define R300_OUT_FMT_C2_SEL_BLUE (3 << 12)
# define R300_OUT_FMT_C3_SEL_ALPHA (0 << 14)
# define R300_OUT_FMT_C3_SEL_RED (1 << 14)
# define R300_OUT_FMT_C3_SEL_GREEN (2 << 14)
# define R300_OUT_FMT_C3_SEL_BLUE (3 << 14)
#define R300_US_CONFIG 0x4600
# define R300_NLEVEL_SHIFT 0
# define R300_FIRST_TEX (1 << 3)
# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1)
#define R300_US_PIXSIZE 0x4604
#define R300_US_CODE_OFFSET0x4608
# define R300_ALU_CODE_OFFSET(x) ((x) << 0)
# define R300_ALU_CODE_SIZE(x) ((x) << 6)
# define R300_TEX_CODE_OFFSET(x) ((x) << 13)
# define R300_TEX_CODE_SIZE(x) ((x) << 18)
#define R300_US_CODE_ADDR_00x4610
# define R300_ALU_START(x) ((x) << 0)
# define R300_ALU_SIZE(x) ((x) << 6)
# define R300_TEX_START(x) ((x) << 12)
# define R300_TEX_SIZE(x) ((x) << 17)
# define R300_RGBA_OUT (1 << 22)
# define R300_W_OUT (1 << 23)
#define R300_US_CODE_ADDR_10x4614
#define R300_US_CODE_ADDR_20x4618
#define R300_US_CODE_ADDR_30x461c
#define R300_US_TEX_INST_00x4620
#define R300_US_TEX_INST_10x4624
#define R300_US_TEX_INST_20x4628
#define R300_US_TEX_INST(x) (R300_US_TEX_INST_0 + (x)*4)
# define R300_TEX_SRC_ADDR(x) ((x) << 0)
# define R300_TEX_DST_ADDR(x) ((x) << 6)
# define R300_TEX_ID(x) ((x) << 11)
# define R300_TEX_INST(x) ((x) << 15)
# define R300_TEX_INST_NOP 0
# define R300_TEX_INST_LD 1
# define R300_TEX_INST_TEXKILL 2
# define R300_TEX_INST_PROJ 3
# define R300_TEX_INST_LODBIAS 4
#define R300_US_ALU_RGB_ADDR_0 0x46c0
#define R300_US_ALU_RGB_ADDR_1 0x46c4
#define R300_US_ALU_RGB_ADDR_2 0x46c8
#define R300_US_ALU_RGB_ADDR(x) (R300_US_ALU_RGB_ADDR_0 + (x)*4)
/* for ADDR0-2, values 0-31 specify a location in the pixel stack,
values 32-63 specify a constant */
# define R300_ALU_RGB_ADDR0(x) ((x) << 0)
# define R300_ALU_RGB_ADDR1(x) ((x) << 6)
# define R300_ALU_RGB_ADDR2(x) ((x) << 12)
# define R300_ALU_RGB_CONST(x) ((x) | (1 << 5))
/* ADDRD - where on the pixel stack the result of this instruction
will be written */
# define R300_ALU_RGB_ADDRD(x) ((x) << 18)
# define R300_ALU_RGB_WMASK(x) ((x) << 23)
# define R300_ALU_RGB_OMASK(x) ((x) << 26)
# define R300_ALU_RGB_MASK_NONE 0
# define R300_ALU_RGB_MASK_R 1
# define R300_ALU_RGB_MASK_G 2
# define R300_ALU_RGB_MASK_B 4
# define R300_ALU_RGB_MASK_RGB 7
# define R300_ALU_RGB_TARGET_A (0 << 29)
# define R300_ALU_RGB_TARGET_B (1 << 29)
# define R300_ALU_RGB_TARGET_C (2 << 29)
# define R300_ALU_RGB_TARGET_D (3 << 29)
#define R300_US_ALU_RGB_INST_0 0x48c0
#define R300_US_ALU_RGB_INST_1 0x48c4
#define R300_US_ALU_RGB_INST_2 0x48c8
#define R300_US_ALU_RGB_INST(x) (R300_US_ALU_RGB_INST_0 + (x)*4)
# define R300_ALU_RGB_SEL_A(x) ((x) << 0)
# define R300_ALU_RGB_SRC0_RGB 0
# define R300_ALU_RGB_SRC0_RRR 1
# define R300_ALU_RGB_SRC0_GGG 2
# define R300_ALU_RGB_SRC0_BBB 3
# define R300_ALU_RGB_SRC1_RGB 4
# define R300_ALU_RGB_SRC1_RRR 5
# define R300_ALU_RGB_SRC1_GGG 6
# define R300_ALU_RGB_SRC1_BBB 7
# define R300_ALU_RGB_SRC2_RGB 8
# define R300_ALU_RGB_SRC2_RRR 9
# define R300_ALU_RGB_SRC2_GGG 10
# define R300_ALU_RGB_SRC2_BBB 11
# define R300_ALU_RGB_SRC0_AAA 12
# define R300_ALU_RGB_SRC1_AAA 13
# define R300_ALU_RGB_SRC2_AAA 14
# define R300_ALU_RGB_SRCP_RGB 15
# define R300_ALU_RGB_SRCP_RRR 16
# define R300_ALU_RGB_SRCP_GGG 17
# define R300_ALU_RGB_SRCP_BBB 18
# define R300_ALU_RGB_SRCP_AAA 19
# define R300_ALU_RGB_0_0 20
# define R300_ALU_RGB_1_0 21
# define R300_ALU_RGB_0_5 22
# define R300_ALU_RGB_SRC0_GBR 23
# define R300_ALU_RGB_SRC1_GBR 24
# define R300_ALU_RGB_SRC2_GBR 25
# define R300_ALU_RGB_SRC0_BRG 26
# define R300_ALU_RGB_SRC1_BRG 27
# define R300_ALU_RGB_SRC2_BRG 28
# define R300_ALU_RGB_SRC0_ABG 29
# define R300_ALU_RGB_SRC1_ABG 30
# define R300_ALU_RGB_SRC2_ABG 31
# define R300_ALU_RGB_MOD_A(x) ((x) << 5)
# define R300_ALU_RGB_MOD_NOP 0
# define R300_ALU_RGB_MOD_NEG 1
# define R300_ALU_RGB_MOD_ABS 2
# define R300_ALU_RGB_MOD_NAB 3
# define R300_ALU_RGB_SEL_B(x) ((x) << 7)
# define R300_ALU_RGB_MOD_B(x) ((x) << 12)
# define R300_ALU_RGB_SEL_C(x) ((x) << 14)
# define R300_ALU_RGB_MOD_C(x) ((x) << 19)
# define R300_ALU_RGB_SRCP_OP(x) ((x) << 21)
# define R300_ALU_RGB_SRCP_OP_1_MINUS_2RGB00
# define R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB01
# define R300_ALU_RGB_SRCP_OP_RGB1_PLUS_RGB02
# define R300_ALU_RGB_SRCP_OP_1_MINUS_RGB03
# define R300_ALU_RGB_OP(x) ((x) << 23)
# define R300_ALU_RGB_OP_MAD 0
# define R300_ALU_RGB_OP_DP3 1
# define R300_ALU_RGB_OP_DP4 2
# define R300_ALU_RGB_OP_D2A 3
# define R300_ALU_RGB_OP_MIN 4
# define R300_ALU_RGB_OP_MAX 5
# define R300_ALU_RGB_OP_CND 7
# define R300_ALU_RGB_OP_CMP 8
# define R300_ALU_RGB_OP_FRC 9
# define R300_ALU_RGB_OP_SOP 10
# define R300_ALU_RGB_OMOD(x) ((x) << 27)
# define R300_ALU_RGB_OMOD_NONE 0
# define R300_ALU_RGB_OMOD_MUL_2 1
# define R300_ALU_RGB_OMOD_MUL_4 2
# define R300_ALU_RGB_OMOD_MUL_8 3
# define R300_ALU_RGB_OMOD_DIV_2 4
# define R300_ALU_RGB_OMOD_DIV_4 5
# define R300_ALU_RGB_OMOD_DIV_8 6
# define R300_ALU_RGB_CLAMP (1 << 30)
# define R300_ALU_RGB_INSERT_NOP (1 << 31)
#define R300_US_ALU_ALPHA_ADDR_0 0x47c0
#define R300_US_ALU_ALPHA_ADDR_1 0x47c4
#define R300_US_ALU_ALPHA_ADDR_2 0x47c8
#define R300_US_ALU_ALPHA_ADDR(x) (R300_US_ALU_ALPHA_ADDR_0 + (x)*4)
/* for ADDR0-2, values 0-31 specify a location in the pixel stack,
values 32-63 specify a constant */
# define R300_ALU_ALPHA_ADDR0(x) ((x) << 0)
# define R300_ALU_ALPHA_ADDR1(x) ((x) << 6)
# define R300_ALU_ALPHA_ADDR2(x) ((x) << 12)
# define R300_ALU_ALPHA_CONST(x) ((x) | (1 << 5))
/* ADDRD - where on the pixel stack the result of this instruction
will be written */
# define R300_ALU_ALPHA_ADDRD(x) ((x) << 18)
# define R300_ALU_ALPHA_WMASK(x) ((x) << 23)
# define R300_ALU_ALPHA_OMASK(x) ((x) << 24)
# define R300_ALU_ALPHA_OMASK_W(x) ((x) << 27)
# define R300_ALU_ALPHA_MASK_NONE 0
# define R300_ALU_ALPHA_MASK_A 1
# define R300_ALU_ALPHA_TARGET_A (0 << 25)
# define R300_ALU_ALPHA_TARGET_B (1 << 25)
# define R300_ALU_ALPHA_TARGET_C (2 << 25)
# define R300_ALU_ALPHA_TARGET_D (3 << 25)
#define R300_US_ALU_ALPHA_INST_0 0x49c0
#define R300_US_ALU_ALPHA_INST_1 0x49c4
#define R300_US_ALU_ALPHA_INST_2 0x49c8
#define R300_US_ALU_ALPHA_INST(x) (R300_US_ALU_ALPHA_INST_0 + (x)*4)
# define R300_ALU_ALPHA_SEL_A(x) ((x) << 0)
# define R300_ALU_ALPHA_SRC0_R 0
# define R300_ALU_ALPHA_SRC0_G 1
# define R300_ALU_ALPHA_SRC0_B 2
# define R300_ALU_ALPHA_SRC1_R 3
# define R300_ALU_ALPHA_SRC1_G 4
# define R300_ALU_ALPHA_SRC1_B 5
# define R300_ALU_ALPHA_SRC2_R 6
# define R300_ALU_ALPHA_SRC2_G 7
# define R300_ALU_ALPHA_SRC2_B 8
# define R300_ALU_ALPHA_SRC0_A 9
# define R300_ALU_ALPHA_SRC1_A 10
# define R300_ALU_ALPHA_SRC2_A 11
# define R300_ALU_ALPHA_SRCP_R 12
# define R300_ALU_ALPHA_SRCP_G 13
# define R300_ALU_ALPHA_SRCP_B 14
# define R300_ALU_ALPHA_SRCP_A 15
# define R300_ALU_ALPHA_0_0 16
# define R300_ALU_ALPHA_1_0 17
# define R300_ALU_ALPHA_0_5 18
# define R300_ALU_ALPHA_MOD_A(x) ((x) << 5)
# define R300_ALU_ALPHA_MOD_NOP 0
# define R300_ALU_ALPHA_MOD_NEG 1
# define R300_ALU_ALPHA_MOD_ABS 2
# define R300_ALU_ALPHA_MOD_NAB 3
# define R300_ALU_ALPHA_SEL_B(x) ((x) << 7)
# define R300_ALU_ALPHA_MOD_B(x) ((x) << 12)
# define R300_ALU_ALPHA_SEL_C(x) ((x) << 14)
# define R300_ALU_ALPHA_MOD_C(x) ((x) << 19)
# define R300_ALU_ALPHA_SRCP_OP(x) ((x) << 21)
# define R300_ALU_ALPHA_SRCP_OP_1_MINUS_2RGB00
# define R300_ALU_ALPHA_SRCP_OP_RGB1_MINUS_RGB01
# define R300_ALU_ALPHA_SRCP_OP_RGB1_PLUS_RGB02
# define R300_ALU_ALPHA_SRCP_OP_1_MINUS_RGB03
# define R300_ALU_ALPHA_OP(x) ((x) << 23)
# define R300_ALU_ALPHA_OP_MAD 0
# define R300_ALU_ALPHA_OP_DP 1
# define R300_ALU_ALPHA_OP_MIN 2
# define R300_ALU_ALPHA_OP_MAX 3
# define R300_ALU_ALPHA_OP_CND 5
# define R300_ALU_ALPHA_OP_CMP 6
# define R300_ALU_ALPHA_OP_FRC 7
# define R300_ALU_ALPHA_OP_EX2 8
# define R300_ALU_ALPHA_OP_LN2 9
# define R300_ALU_ALPHA_OP_RCP 10
# define R300_ALU_ALPHA_OP_RSQ 11
# define R300_ALU_ALPHA_OMOD(x) ((x) << 27)
# define R300_ALU_ALPHA_OMOD_NONE 0
# define R300_ALU_ALPHA_OMOD_MUL_2 1
# define R300_ALU_ALPHA_OMOD_MUL_4 2
# define R300_ALU_ALPHA_OMOD_MUL_8 3
# define R300_ALU_ALPHA_OMOD_DIV_2 4
# define R300_ALU_ALPHA_OMOD_DIV_4 5
# define R300_ALU_ALPHA_OMOD_DIV_8 6
# define R300_ALU_ALPHA_CLAMP (1 << 30)
#define R300_US_ALU_CONST_R_0 0x4c00
#define R300_US_ALU_CONST_R(x) (R300_US_ALU_CONST_R_0 + (x)*16)
#define R300_US_ALU_CONST_G_0 0x4c04
#define R300_US_ALU_CONST_G(x) (R300_US_ALU_CONST_G_0 + (x)*16)
#define R300_US_ALU_CONST_B_0 0x4c08
#define R300_US_ALU_CONST_B(x) (R300_US_ALU_CONST_B_0 + (x)*16)
#define R300_US_ALU_CONST_A_0 0x4c0c
#define R300_US_ALU_CONST_A(x) (R300_US_ALU_CONST_A_0 + (x)*16)
#define R300_FG_DEPTH_SRC0x4bd8
#define R300_FG_FOG_BLEND0x4bc0
#define R300_FG_ALPHA_FUNC0x4bd4
#define R300_DST_PIPE_CONFIG 0x170c
# define R300_PIPE_AUTO_CONFIG (1 << 31)
#define R300_RB2D_DSTCACHE_MODE 0x3428
#define R300_RB2D_DSTCACHE_MODE 0x3428
# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use DSTCACHE_CTLSTAT instead */
#define R300_DSTCACHE_CTLSTAT 0x1714
# define R300_DC_FLUSH_2D (1 << 0)
# define R300_DC_FREE_2D (1 << 2)
# define R300_RB2D_DC_FLUSH_ALL (R300_DC_FLUSH_2D | R300_DC_FREE_2D)
# define R300_RB2D_DC_BUSY (1 << 31)
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
# define R300_DC_FLUSH_3D (2 << 0)
# define R300_DC_FREE_3D (2 << 2)
# define R300_RB3D_DC_FLUSH_ALL (R300_DC_FLUSH_3D | R300_DC_FREE_3D)
# define R300_DC_FINISH_3D (1 << 4)
#define R300_RB3D_ZCACHE_CTLSTAT0x4f18
# define R300_ZC_FLUSH (1 << 0)
# define R300_ZC_FREE (1 << 1)
# define R300_ZC_FLUSH_ALL 0x3
#define R300_RB3D_ZSTENCILCNTL 0x4f04
#define R300_RB3D_ZCACHE_CTLSTAT 0x4f18
#define R300_RB3D_BW_CNTL0x4f1c
#define R300_RB3D_ZCNTL 0x4f00
#define R300_RB3D_ZTOP 0x4f14
#define R300_RB3D_ROPCNTL0x4e18
#define R300_RB3D_BLENDCNTL0x4e04
# define R300_ALPHA_BLEND_ENABLE (1 << 0)
# define R300_SEPARATE_ALPHA_ENABLE (1 << 1)
# define R300_READ_ENABLE (1 << 2)
#define R300_RB3D_ABLENDCNTL 0x4e08
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
#define R300_RB3D_COLOROFFSET0 0x4e28
#define R300_RB3D_COLORPITCH0 0x4e38
# define R300_COLORTILE (1 << 16)
# define R300_COLORENDIAN_WORD (1 << 19)
# define R300_COLORENDIAN_DWORD (2 << 19)
# define R300_COLORENDIAN_HALF_DWORD (3 << 19)
# define R300_COLORFORMAT_ARGB1555 (3 << 21)
# define R300_COLORFORMAT_RGB565 (4 << 21)
# define R300_COLORFORMAT_ARGB8888 (6 << 21)
# define R300_COLORFORMAT_ARGB32323232 (7 << 21)
# define R300_COLORFORMAT_I8 (9 << 21)
# define R300_COLORFORMAT_ARGB16161616 (10 << 21)
# define R300_COLORFORMAT_VYUY (11 << 21)
# define R300_COLORFORMAT_YVYU (12 << 21)
# define R300_COLORFORMAT_UV88 (13 << 21)
# define R300_COLORFORMAT_ARGB4444 (15 << 21)
#define R300_RB3D_AARESOLVE_CTL 0x4e88
#define R300_RB3D_COLOR_CHANNEL_MASK 0x4e0c
# define R300_BLUE_MASK_EN (1 << 0)
# define R300_GREEN_MASK_EN (1 << 1)
# define R300_RED_MASK_EN (1 << 2)
# define R300_ALPHA_MASK_EN (1 << 3)
#define R300_RB3D_COLOR_CLEAR_VALUE 0x4e14
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
#define R300_RB3D_CCTL 0x4e00
#define R300_RB3D_DITHER_CTL 0x4e50
#define R300_SC_EDGERULE0x43a8
#define R300_SC_SCISSOR00x43e0
#define R300_SC_SCISSOR10x43e4
# define R300_SCISSOR_X_SHIFT 0
# define R300_SCISSOR_Y_SHIFT 13
#define R300_SC_CLIP_0_A0x43b0
#define R300_SC_CLIP_0_B0x43b4
# define R300_CLIP_X_SHIFT 0
# define R300_CLIP_Y_SHIFT 13
#define R300_SC_CLIP_RULE0x43d0
#define R300_SC_SCREENDOOR0x43e8
/* R500 US has to be loaded through an index/data pair */
#define R500_GA_US_VECTOR_INDEX0x4250
# define R500_US_VECTOR_TYPE_INST(0 << 16)
# define R500_US_VECTOR_TYPE_CONST(1 << 16)
# define R500_US_VECTOR_CLAMP(1 << 17)
# define R500_US_VECTOR_INST_INDEX(x)((x) | R500_US_VECTOR_TYPE_INST)
# define R500_US_VECTOR_CONST_INDEX(x)((x) | R500_US_VECTOR_TYPE_CONST)
#define R500_GA_US_VECTOR_DATA0x4254
/*
* The R500 unified shader (US) registers come in banks of 512 each, one
* for each instruction slot in the shader. You can't touch them directly.
* R500_US_VECTOR_INDEX() sets the base instruction to modify; successive
* writes to R500_GA_US_VECTOR_DATA autoincrement the index after the
* instruction is fully specified.
*/
#define R500_US_ALU_ALPHA_INST_00xa800
# define R500_ALPHA_OP_MAD0
# define R500_ALPHA_OP_DP1
# define R500_ALPHA_OP_MIN2
# define R500_ALPHA_OP_MAX3
/* #define R500_ALPHA_OP_RESERVED4 */
# define R500_ALPHA_OP_CND5
# define R500_ALPHA_OP_CMP6
# define R500_ALPHA_OP_FRC7
# define R500_ALPHA_OP_EX28
# define R500_ALPHA_OP_LN29
# define R500_ALPHA_OP_RCP10
# define R500_ALPHA_OP_RSQ11
# define R500_ALPHA_OP_SIN12
# define R500_ALPHA_OP_COS13
# define R500_ALPHA_OP_MDH14
# define R500_ALPHA_OP_MDV15
# define R500_ALPHA_ADDRD(x)((x) << 4)
# define R500_ALPHA_ADDRD_REL(1 << 11)
# define R500_ALPHA_SEL_A_SRC0(0 << 12)
# define R500_ALPHA_SEL_A_SRC1(1 << 12)
# define R500_ALPHA_SEL_A_SRC2(2 << 12)
# define R500_ALPHA_SEL_A_SRCP(3 << 12)
# define R500_ALPHA_SWIZ_A_R(0 << 14)
# define R500_ALPHA_SWIZ_A_G(1 << 14)
# define R500_ALPHA_SWIZ_A_B(2 << 14)
# define R500_ALPHA_SWIZ_A_A(3 << 14)
# define R500_ALPHA_SWIZ_A_0(4 << 14)
# define R500_ALPHA_SWIZ_A_HALF(5 << 14)
# define R500_ALPHA_SWIZ_A_1(6 << 14)
/* #define R500_ALPHA_SWIZ_A_UNUSED(7 << 14) */
# define R500_ALPHA_MOD_A_NOP(0 << 17)
# define R500_ALPHA_MOD_A_NEG(1 << 17)
# define R500_ALPHA_MOD_A_ABS(2 << 17)
# define R500_ALPHA_MOD_A_NAB(3 << 17)
# define R500_ALPHA_SEL_B_SRC0(0 << 19)
# define R500_ALPHA_SEL_B_SRC1(1 << 19)
# define R500_ALPHA_SEL_B_SRC2(2 << 19)
# define R500_ALPHA_SEL_B_SRCP(3 << 19)
# define R500_ALPHA_SWIZ_B_R(0 << 21)
# define R500_ALPHA_SWIZ_B_G(1 << 21)
# define R500_ALPHA_SWIZ_B_B(2 << 21)
# define R500_ALPHA_SWIZ_B_A(3 << 21)
# define R500_ALPHA_SWIZ_B_0(4 << 21)
# define R500_ALPHA_SWIZ_B_HALF(5 << 21)
# define R500_ALPHA_SWIZ_B_1(6 << 21)
/* #define R500_ALPHA_SWIZ_B_UNUSED(7 << 21) */
# define R500_ALPHA_MOD_B_NOP(0 << 24)
# define R500_ALPHA_MOD_B_NEG(1 << 24)
# define R500_ALPHA_MOD_B_ABS(2 << 24)
# define R500_ALPHA_MOD_B_NAB(3 << 24)
# define R500_ALPHA_OMOD_IDENTITY(0 << 26)
# define R500_ALPHA_OMOD_MUL_2(1 << 26)
# define R500_ALPHA_OMOD_MUL_4(2 << 26)
# define R500_ALPHA_OMOD_MUL_8(3 << 26)
# define R500_ALPHA_OMOD_DIV_2(4 << 26)
# define R500_ALPHA_OMOD_DIV_4(5 << 26)
# define R500_ALPHA_OMOD_DIV_8(6 << 26)
# define R500_ALPHA_OMOD_DISABLE(7 << 26)
# define R500_ALPHA_TARGET(x)((x) << 29)
# define R500_ALPHA_W_OMASK(1 << 31)
#define R500_US_ALU_ALPHA_ADDR_00x9800
# define R500_ALPHA_ADDR0(x)((x) << 0)
# define R500_ALPHA_ADDR0_CONST(1 << 8)
# define R500_ALPHA_ADDR0_REL(1 << 9)
# define R500_ALPHA_ADDR1(x)((x) << 10)
# define R500_ALPHA_ADDR1_CONST(1 << 18)
# define R500_ALPHA_ADDR1_REL(1 << 19)
# define R500_ALPHA_ADDR2(x)((x) << 20)
# define R500_ALPHA_ADDR2_CONST(1 << 28)
# define R500_ALPHA_ADDR2_REL(1 << 29)
# define R500_ALPHA_SRCP_OP_1_MINUS_2A0(0 << 30)
# define R500_ALPHA_SRCP_OP_A1_MINUS_A0(1 << 30)
# define R500_ALPHA_SRCP_OP_A1_PLUS_A0(2 << 30)
# define R500_ALPHA_SRCP_OP_1_MINUS_A0(3 << 30)
#define R500_US_ALU_RGBA_INST_00xb000
# define R500_ALU_RGBA_OP_MAD(0 << 0)
# define R500_ALU_RGBA_OP_DP3(1 << 0)
# define R500_ALU_RGBA_OP_DP4(2 << 0)
# define R500_ALU_RGBA_OP_D2A(3 << 0)
# define R500_ALU_RGBA_OP_MIN(4 << 0)
# define R500_ALU_RGBA_OP_MAX(5 << 0)
/* #define R500_ALU_RGBA_OP_RESERVED(6 << 0) */
# define R500_ALU_RGBA_OP_CND(7 << 0)
# define R500_ALU_RGBA_OP_CMP(8 << 0)
# define R500_ALU_RGBA_OP_FRC(9 << 0)
# define R500_ALU_RGBA_OP_SOP(10 << 0)
# define R500_ALU_RGBA_OP_MDH(11 << 0)
# define R500_ALU_RGBA_OP_MDV(12 << 0)
# define R500_ALU_RGBA_ADDRD(x)((x) << 4)
# define R500_ALU_RGBA_ADDRD_REL(1 << 11)
# define R500_ALU_RGBA_SEL_C_SRC0(0 << 12)
# define R500_ALU_RGBA_SEL_C_SRC1(1 << 12)
# define R500_ALU_RGBA_SEL_C_SRC2(2 << 12)
# define R500_ALU_RGBA_SEL_C_SRCP(3 << 12)
# define R500_ALU_RGBA_R_SWIZ_R(0 << 14)
# define R500_ALU_RGBA_R_SWIZ_G(1 << 14)
# define R500_ALU_RGBA_R_SWIZ_B(2 << 14)
# define R500_ALU_RGBA_R_SWIZ_A(3 << 14)
# define R500_ALU_RGBA_R_SWIZ_0(4 << 14)
# define R500_ALU_RGBA_R_SWIZ_HALF(5 << 14)
# define R500_ALU_RGBA_R_SWIZ_1(6 << 14)
/* #define R500_ALU_RGBA_R_SWIZ_UNUSED(7 << 14) */
# define R500_ALU_RGBA_G_SWIZ_R(0 << 17)
# define R500_ALU_RGBA_G_SWIZ_G(1 << 17)
# define R500_ALU_RGBA_G_SWIZ_B(2 << 17)
# define R500_ALU_RGBA_G_SWIZ_A(3 << 17)
# define R500_ALU_RGBA_G_SWIZ_0(4 << 17)
# define R500_ALU_RGBA_G_SWIZ_HALF(5 << 17)
# define R500_ALU_RGBA_G_SWIZ_1(6 << 17)
/* #define R500_ALU_RGBA_G_SWIZ_UNUSED(7 << 17) */
# define R500_ALU_RGBA_B_SWIZ_R(0 << 20)
# define R500_ALU_RGBA_B_SWIZ_G(1 << 20)
# define R500_ALU_RGBA_B_SWIZ_B(2 << 20)
# define R500_ALU_RGBA_B_SWIZ_A(3 << 20)
# define R500_ALU_RGBA_B_SWIZ_0(4 << 20)
# define R500_ALU_RGBA_B_SWIZ_HALF(5 << 20)
# define R500_ALU_RGBA_B_SWIZ_1(6 << 20)
/* #define R500_ALU_RGBA_B_SWIZ_UNUSED(7 << 20) */
# define R500_ALU_RGBA_MOD_C_NOP(0 << 23)
# define R500_ALU_RGBA_MOD_C_NEG(1 << 23)
# define R500_ALU_RGBA_MOD_C_ABS(2 << 23)
# define R500_ALU_RGBA_MOD_C_NAB(3 << 23)
# define R500_ALU_RGBA_ALPHA_SEL_C_SRC0(0 << 25)
# define R500_ALU_RGBA_ALPHA_SEL_C_SRC1(1 << 25)
# define R500_ALU_RGBA_ALPHA_SEL_C_SRC2(2 << 25)
# define R500_ALU_RGBA_ALPHA_SEL_C_SRCP(3 << 25)
# define R500_ALU_RGBA_A_SWIZ_R(0 << 27)
# define R500_ALU_RGBA_A_SWIZ_G(1 << 27)
# define R500_ALU_RGBA_A_SWIZ_B(2 << 27)
# define R500_ALU_RGBA_A_SWIZ_A(3 << 27)
# define R500_ALU_RGBA_A_SWIZ_0(4 << 27)
# define R500_ALU_RGBA_A_SWIZ_HALF(5 << 27)
# define R500_ALU_RGBA_A_SWIZ_1(6 << 27)
/* #define R500_ALU_RGBA_A_SWIZ_UNUSED(7 << 27) */
# define R500_ALU_RGBA_ALPHA_MOD_C_NOP(0 << 30)
# define R500_ALU_RGBA_ALPHA_MOD_C_NEG(1 << 30)
# define R500_ALU_RGBA_ALPHA_MOD_C_ABS(2 << 30)
# define R500_ALU_RGBA_ALPHA_MOD_C_NAB(3 << 30)
#define R500_US_ALU_RGB_INST_00xa000
# define R500_ALU_RGB_SEL_A_SRC0(0 << 0)
# define R500_ALU_RGB_SEL_A_SRC1(1 << 0)
# define R500_ALU_RGB_SEL_A_SRC2(2 << 0)
# define R500_ALU_RGB_SEL_A_SRCP(3 << 0)
# define R500_ALU_RGB_R_SWIZ_A_R(0 << 2)
# define R500_ALU_RGB_R_SWIZ_A_G(1 << 2)
# define R500_ALU_RGB_R_SWIZ_A_B(2 << 2)
# define R500_ALU_RGB_R_SWIZ_A_A(3 << 2)
# define R500_ALU_RGB_R_SWIZ_A_0(4 << 2)
# define R500_ALU_RGB_R_SWIZ_A_HALF(5 << 2)
# define R500_ALU_RGB_R_SWIZ_A_1(6 << 2)
/* #define R500_ALU_RGB_R_SWIZ_A_UNUSED(7 << 2) */
# define R500_ALU_RGB_G_SWIZ_A_R(0 << 5)
# define R500_ALU_RGB_G_SWIZ_A_G(1 << 5)
# define R500_ALU_RGB_G_SWIZ_A_B(2 << 5)
# define R500_ALU_RGB_G_SWIZ_A_A(3 << 5)
# define R500_ALU_RGB_G_SWIZ_A_0(4 << 5)
# define R500_ALU_RGB_G_SWIZ_A_HALF(5 << 5)
# define R500_ALU_RGB_G_SWIZ_A_1(6 << 5)
/* #define R500_ALU_RGB_G_SWIZ_A_UNUSED(7 << 5) */
# define R500_ALU_RGB_B_SWIZ_A_R(0 << 8)
# define R500_ALU_RGB_B_SWIZ_A_G(1 << 8)
# define R500_ALU_RGB_B_SWIZ_A_B(2 << 8)
# define R500_ALU_RGB_B_SWIZ_A_A(3 << 8)
# define R500_ALU_RGB_B_SWIZ_A_0(4 << 8)
# define R500_ALU_RGB_B_SWIZ_A_HALF(5 << 8)
# define R500_ALU_RGB_B_SWIZ_A_1(6 << 8)
/* #define R500_ALU_RGB_B_SWIZ_A_UNUSED(7 << 8) */
# define R500_ALU_RGB_MOD_A_NOP(0 << 11)
# define R500_ALU_RGB_MOD_A_NEG(1 << 11)
# define R500_ALU_RGB_MOD_A_ABS(2 << 11)
# define R500_ALU_RGB_MOD_A_NAB(3 << 11)
# define R500_ALU_RGB_SEL_B_SRC0(0 << 13)
# define R500_ALU_RGB_SEL_B_SRC1(1 << 13)
# define R500_ALU_RGB_SEL_B_SRC2(2 << 13)
# define R500_ALU_RGB_SEL_B_SRCP(3 << 13)
# define R500_ALU_RGB_R_SWIZ_B_R(0 << 15)
# define R500_ALU_RGB_R_SWIZ_B_G(1 << 15)
# define R500_ALU_RGB_R_SWIZ_B_B(2 << 15)
# define R500_ALU_RGB_R_SWIZ_B_A(3 << 15)
# define R500_ALU_RGB_R_SWIZ_B_0(4 << 15)
# define R500_ALU_RGB_R_SWIZ_B_HALF(5 << 15)
# define R500_ALU_RGB_R_SWIZ_B_1(6 << 15)
/* #define R500_ALU_RGB_R_SWIZ_B_UNUSED(7 << 15) */
# define R500_ALU_RGB_G_SWIZ_B_R(0 << 18)
# define R500_ALU_RGB_G_SWIZ_B_G(1 << 18)
# define R500_ALU_RGB_G_SWIZ_B_B(2 << 18)
# define R500_ALU_RGB_G_SWIZ_B_A(3 << 18)
# define R500_ALU_RGB_G_SWIZ_B_0(4 << 18)
# define R500_ALU_RGB_G_SWIZ_B_HALF(5 << 18)
# define R500_ALU_RGB_G_SWIZ_B_1(6 << 18)
/* #define R500_ALU_RGB_G_SWIZ_B_UNUSED(7 << 18) */
# define R500_ALU_RGB_B_SWIZ_B_R(0 << 21)
# define R500_ALU_RGB_B_SWIZ_B_G(1 << 21)
# define R500_ALU_RGB_B_SWIZ_B_B(2 << 21)
# define R500_ALU_RGB_B_SWIZ_B_A(3 << 21)
# define R500_ALU_RGB_B_SWIZ_B_0(4 << 21)
# define R500_ALU_RGB_B_SWIZ_B_HALF(5 << 21)
# define R500_ALU_RGB_B_SWIZ_B_1(6 << 21)
/* #define R500_ALU_RGB_B_SWIZ_B_UNUSED(7 << 21) */
# define R500_ALU_RGB_MOD_B_NOP(0 << 24)
# define R500_ALU_RGB_MOD_B_NEG(1 << 24)
# define R500_ALU_RGB_MOD_B_ABS(2 << 24)
# define R500_ALU_RGB_MOD_B_NAB(3 << 24)
# define R500_ALU_RGB_OMOD_IDENTITY(0 << 26)
# define R500_ALU_RGB_OMOD_MUL_2(1 << 26)
# define R500_ALU_RGB_OMOD_MUL_4(2 << 26)
# define R500_ALU_RGB_OMOD_MUL_8(3 << 26)
# define R500_ALU_RGB_OMOD_DIV_2(4 << 26)
# define R500_ALU_RGB_OMOD_DIV_4(5 << 26)
# define R500_ALU_RGB_OMOD_DIV_8(6 << 26)
# define R500_ALU_RGB_OMOD_DISABLE(7 << 26)
# define R500_ALU_RGB_TARGET(x)((x) << 29)
# define R500_ALU_RGB_WMASK(1 << 31)
#define R500_US_ALU_RGB_ADDR_00x9000
# define R500_RGB_ADDR0(x)((x) << 0)
# define R500_RGB_ADDR0_CONST(1 << 8)
# define R500_RGB_ADDR0_REL(1 << 9)
# define R500_RGB_ADDR1(x)((x) << 10)
# define R500_RGB_ADDR1_CONST(1 << 18)
# define R500_RGB_ADDR1_REL(1 << 19)
# define R500_RGB_ADDR2(x)((x) << 20)
# define R500_RGB_ADDR2_CONST(1 << 28)
# define R500_RGB_ADDR2_REL(1 << 29)
# define R500_RGB_SRCP_OP_1_MINUS_2RGB0(0 << 30)
# define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0(1 << 30)
# define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0(2 << 30)
# define R500_RGB_SRCP_OP_1_MINUS_RGB0(3 << 30)
#define R500_US_CMN_INST_00xb800
# define R500_INST_TYPE_ALU(0 << 0)
# define R500_INST_TYPE_OUT(1 << 0)
# define R500_INST_TYPE_FC(2 << 0)
# define R500_INST_TYPE_TEX(3 << 0)
# define R500_INST_TEX_SEM_WAIT(1 << 2)
# define R500_INST_RGB_PRED_SEL_NONE(0 << 3)
# define R500_INST_RGB_PRED_SEL_RGBA(1 << 3)
# define R500_INST_RGB_PRED_SEL_RRRR(2 << 3)
# define R500_INST_RGB_PRED_SEL_GGGG(3 << 3)
# define R500_INST_RGB_PRED_SEL_BBBB(4 << 3)
# define R500_INST_RGB_PRED_SEL_AAAA(5 << 3)
# define R500_INST_RGB_PRED_INV(1 << 6)
# define R500_INST_WRITE_INACTIVE(1 << 7)
# define R500_INST_LAST(1 << 8)
# define R500_INST_NOP(1 << 9)
# define R500_INST_ALU_WAIT(1 << 10)
# define R500_INST_RGB_WMASK_R(1 << 11)
# define R500_INST_RGB_WMASK_G(1 << 12)
# define R500_INST_RGB_WMASK_B(1 << 13)
# define R500_INST_ALPHA_WMASK(1 << 14)
# define R500_INST_RGB_OMASK_R(1 << 15)
# define R500_INST_RGB_OMASK_G(1 << 16)
# define R500_INST_RGB_OMASK_B(1 << 17)
# define R500_INST_ALPHA_OMASK(1 << 18)
# define R500_INST_RGB_CLAMP(1 << 19)
# define R500_INST_ALPHA_CLAMP(1 << 20)
# define R500_INST_ALU_RESULT_SEL(1 << 21)
# define R500_INST_ALPHA_PRED_INV(1 << 22)
# define R500_INST_ALU_RESULT_OP_EQ(0 << 23)
# define R500_INST_ALU_RESULT_OP_LT(1 << 23)
# define R500_INST_ALU_RESULT_OP_GE(2 << 23)
# define R500_INST_ALU_RESULT_OP_NE(3 << 23)
# define R500_INST_ALPHA_PRED_SEL_NONE(0 << 25)
# define R500_INST_ALPHA_PRED_SEL_RGBA(1 << 25)
# define R500_INST_ALPHA_PRED_SEL_RRRR(2 << 25)
# define R500_INST_ALPHA_PRED_SEL_GGGG(3 << 25)
# define R500_INST_ALPHA_PRED_SEL_BBBB(4 << 25)
# define R500_INST_ALPHA_PRED_SEL_AAAA(5 << 25)
/* XXX next four are kind of guessed */
# define R500_INST_STAT_WE_R(1 << 28)
# define R500_INST_STAT_WE_G(1 << 29)
# define R500_INST_STAT_WE_B(1 << 30)
# define R500_INST_STAT_WE_A(1 << 31)
/* note that these are 8 bit lengths, despite the offsets, at least for R500 */
#define R500_US_CODE_ADDR0x4630
# define R500_US_CODE_START_ADDR(x)((x) << 0)
# define R500_US_CODE_END_ADDR(x)((x) << 16)
#define R500_US_CODE_OFFSET0x4638
# define R500_US_CODE_OFFSET_ADDR(x)((x) << 0)
#define R500_US_CODE_RANGE0x4634
# define R500_US_CODE_RANGE_ADDR(x)((x) << 0)
# define R500_US_CODE_RANGE_SIZE(x)((x) << 16)
#define R500_US_CONFIG0x4600
# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO(1 << 1)
#define R500_US_FC_ADDR_00xa000
# define R500_FC_BOOL_ADDR(x)((x) << 0)
# define R500_FC_INT_ADDR(x)((x) << 8)
# define R500_FC_JUMP_ADDR(x)((x) << 16)
# define R500_FC_JUMP_GLOBAL(1 << 31)
#define R500_US_FC_BOOL_CONST0x4620
# define R500_FC_KBOOL(x)(x)
#define R500_US_FC_CTRL0x4624
# define R500_FC_TEST_EN(1 << 30)
# define R500_FC_FULL_FC_EN(1 << 31)
#define R500_US_FC_INST_00x9800
# define R500_FC_OP_JUMP(0 << 0)
# define R500_FC_OP_LOOP(1 << 0)
# define R500_FC_OP_ENDLOOP(2 << 0)
# define R500_FC_OP_REP(3 << 0)
# define R500_FC_OP_ENDREP(4 << 0)
# define R500_FC_OP_BREAKLOOP(5 << 0)
# define R500_FC_OP_BREAKREP(6 << 0)
# define R500_FC_OP_CONTINUE(7 << 0)
# define R500_FC_B_ELSE(1 << 4)
# define R500_FC_JUMP_ANY(1 << 5)
# define R500_FC_A_OP_NONE(0 << 6)
# define R500_FC_A_OP_POP(1 << 6)
# define R500_FC_A_OP_PUSH(2 << 6)
# define R500_FC_JUMP_FUNC(x)((x) << 8)
# define R500_FC_B_POP_CNT(x)((x) << 16)
# define R500_FC_B_OP0_NONE(0 << 24)
# define R500_FC_B_OP0_DECR(1 << 24)
# define R500_FC_B_OP0_INCR(2 << 24)
# define R500_FC_B_OP1_DECR(0 << 26)
# define R500_FC_B_OP1_NONE(1 << 26)
# define R500_FC_B_OP1_INCR(2 << 26)
# define R500_FC_IGNORE_UNCOVERED(1 << 28)
#define R500_US_FC_INT_CONST_00x4c00
# define R500_FC_INT_CONST_KR(x)((x) << 0)
# define R500_FC_INT_CONST_KG(x)((x) << 8)
# define R500_FC_INT_CONST_KB(x)((x) << 16)
/* _0 through _15 */
#define R500_US_FORMAT0_00x4640
# define R500_FORMAT_TXWIDTH(x)((x) << 0)
# define R500_FORMAT_TXHEIGHT(x)((x) << 11)
# define R500_FORMAT_TXDEPTH(x)((x) << 22)
/* _0 through _3 */
#define R500_US_OUT_FMT_00x46a4
# define R500_OUT_FMT_C4_8(0 << 0)
# define R500_OUT_FMT_C4_10(1 << 0)
# define R500_OUT_FMT_C4_10_GAMMA(2 << 0)
# define R500_OUT_FMT_C_16(3 << 0)
# define R500_OUT_FMT_C2_16(4 << 0)
# define R500_OUT_FMT_C4_16(5 << 0)
# define R500_OUT_FMT_C_16_MPEG(6 << 0)
# define R500_OUT_FMT_C2_16_MPEG(7 << 0)
# define R500_OUT_FMT_C2_4(8 << 0)
# define R500_OUT_FMT_C_3_3_2(9 << 0)
# define R500_OUT_FMT_C_6_5_6(10 << 0)
# define R500_OUT_FMT_C_11_11_10(11 << 0)
# define R500_OUT_FMT_C_10_11_11(12 << 0)
# define R500_OUT_FMT_C_2_10_10_10(13 << 0)
/* #define R500_OUT_FMT_RESERVED(14 << 0) */
# define R500_OUT_FMT_UNUSED(15 << 0)
# define R500_OUT_FMT_C_16_FP(16 << 0)
# define R500_OUT_FMT_C2_16_FP(17 << 0)
# define R500_OUT_FMT_C4_16_FP(18 << 0)
# define R500_OUT_FMT_C_32_FP(19 << 0)
# define R500_OUT_FMT_C2_32_FP(20 << 0)
# define R500_OUT_FMT_C4_32_FP(21 << 0)
# define R500_C0_SEL_A(0 << 8)
# define R500_C0_SEL_R(1 << 8)
# define R500_C0_SEL_G(2 << 8)
# define R500_C0_SEL_B(3 << 8)
# define R500_C1_SEL_A(0 << 10)
# define R500_C1_SEL_R(1 << 10)
# define R500_C1_SEL_G(2 << 10)
# define R500_C1_SEL_B(3 << 10)
# define R500_C2_SEL_A(0 << 12)
# define R500_C2_SEL_R(1 << 12)
# define R500_C2_SEL_G(2 << 12)
# define R500_C2_SEL_B(3 << 12)
# define R500_C3_SEL_A(0 << 14)
# define R500_C3_SEL_R(1 << 14)
# define R500_C3_SEL_G(2 << 14)
# define R500_C3_SEL_B(3 << 14)
# define R500_OUT_SIGN(x)((x) << 16)
# define R500_ROUND_ADJ(1 << 20)
#define R500_US_PIXSIZE0x4604
# define R500_PIX_SIZE(x)(x)
#define R500_US_TEX_ADDR_00x9800
# define R500_TEX_SRC_ADDR(x)((x) << 0)
# define R500_TEX_SRC_ADDR_REL(1 << 7)
# define R500_TEX_SRC_S_SWIZ_R(0 << 8)
# define R500_TEX_SRC_S_SWIZ_G(1 << 8)
# define R500_TEX_SRC_S_SWIZ_B(2 << 8)
# define R500_TEX_SRC_S_SWIZ_A(3 << 8)
# define R500_TEX_SRC_T_SWIZ_R(0 << 10)
# define R500_TEX_SRC_T_SWIZ_G(1 << 10)
# define R500_TEX_SRC_T_SWIZ_B(2 << 10)
# define R500_TEX_SRC_T_SWIZ_A(3 << 10)
# define R500_TEX_SRC_R_SWIZ_R(0 << 12)
# define R500_TEX_SRC_R_SWIZ_G(1 << 12)
# define R500_TEX_SRC_R_SWIZ_B(2 << 12)
# define R500_TEX_SRC_R_SWIZ_A(3 << 12)
# define R500_TEX_SRC_Q_SWIZ_R(0 << 14)
# define R500_TEX_SRC_Q_SWIZ_G(1 << 14)
# define R500_TEX_SRC_Q_SWIZ_B(2 << 14)
# define R500_TEX_SRC_Q_SWIZ_A(3 << 14)
# define R500_TEX_DST_ADDR(x)((x) << 16)
# define R500_TEX_DST_ADDR_REL(1 << 23)
# define R500_TEX_DST_R_SWIZ_R(0 << 24)
# define R500_TEX_DST_R_SWIZ_G(1 << 24)
# define R500_TEX_DST_R_SWIZ_B(2 << 24)
# define R500_TEX_DST_R_SWIZ_A(3 << 24)
# define R500_TEX_DST_G_SWIZ_R(0 << 26)
# define R500_TEX_DST_G_SWIZ_G(1 << 26)
# define R500_TEX_DST_G_SWIZ_B(2 << 26)
# define R500_TEX_DST_G_SWIZ_A(3 << 26)
# define R500_TEX_DST_B_SWIZ_R(0 << 28)
# define R500_TEX_DST_B_SWIZ_G(1 << 28)
# define R500_TEX_DST_B_SWIZ_B(2 << 28)
# define R500_TEX_DST_B_SWIZ_A(3 << 28)
# define R500_TEX_DST_A_SWIZ_R(0 << 30)
# define R500_TEX_DST_A_SWIZ_G(1 << 30)
# define R500_TEX_DST_A_SWIZ_B(2 << 30)
# define R500_TEX_DST_A_SWIZ_A(3 << 30)
#define R500_US_TEX_ADDR_DXDY_00xa000
# define R500_DX_ADDR(x)((x) << 0)
# define R500_DX_ADDR_REL(1 << 7)
# define R500_DX_S_SWIZ_R(0 << 8)
# define R500_DX_S_SWIZ_G(1 << 8)
# define R500_DX_S_SWIZ_B(2 << 8)
# define R500_DX_S_SWIZ_A(3 << 8)
# define R500_DX_T_SWIZ_R(0 << 10)
# define R500_DX_T_SWIZ_G(1 << 10)
# define R500_DX_T_SWIZ_B(2 << 10)
# define R500_DX_T_SWIZ_A(3 << 10)
# define R500_DX_R_SWIZ_R(0 << 12)
# define R500_DX_R_SWIZ_G(1 << 12)
# define R500_DX_R_SWIZ_B(2 << 12)
# define R500_DX_R_SWIZ_A(3 << 12)
# define R500_DX_Q_SWIZ_R(0 << 14)
# define R500_DX_Q_SWIZ_G(1 << 14)
# define R500_DX_Q_SWIZ_B(2 << 14)
# define R500_DX_Q_SWIZ_A(3 << 14)
# define R500_DY_ADDR(x)((x) << 16)
# define R500_DY_ADDR_REL(1 << 17)
# define R500_DY_S_SWIZ_R(0 << 24)
# define R500_DY_S_SWIZ_G(1 << 24)
# define R500_DY_S_SWIZ_B(2 << 24)
# define R500_DY_S_SWIZ_A(3 << 24)
# define R500_DY_T_SWIZ_R(0 << 26)
# define R500_DY_T_SWIZ_G(1 << 26)
# define R500_DY_T_SWIZ_B(2 << 26)
# define R500_DY_T_SWIZ_A(3 << 26)
# define R500_DY_R_SWIZ_R(0 << 28)
# define R500_DY_R_SWIZ_G(1 << 28)
# define R500_DY_R_SWIZ_B(2 << 28)
# define R500_DY_R_SWIZ_A(3 << 28)
# define R500_DY_Q_SWIZ_R(0 << 30)
# define R500_DY_Q_SWIZ_G(1 << 30)
# define R500_DY_Q_SWIZ_B(2 << 30)
# define R500_DY_Q_SWIZ_A(3 << 30)
#define R500_US_TEX_INST_00x9000
# define R500_TEX_ID(x)((x) << 16)
# define R500_TEX_INST_NOP(0 << 22)
# define R500_TEX_INST_LD(1 << 22)
# define R500_TEX_INST_TEXKILL(2 << 22)
# define R500_TEX_INST_PROJ(3 << 22)
# define R500_TEX_INST_LODBIAS(4 << 22)
# define R500_TEX_INST_LOD(5 << 22)
# define R500_TEX_INST_DXDY(6 << 22)
# define R500_TEX_SEM_ACQUIRE(1 << 25)
# define R500_TEX_IGNORE_UNCOVERED(1 << 26)
# define R500_TEX_UNSCALED(1 << 27)
#define R500_US_W_FMT0x46b4
# define R500_W_FMT_W0(0 << 0)
# define R500_W_FMT_W24(1 << 0)
# define R500_W_FMT_W24FP(2 << 0)
# define R500_W_SRC_US(0 << 2)
# define R500_W_SRC_RAS(1 << 2)
#define R500_RS_INST_00x4320
#define R500_RS_INST_10x4324
# define R500_RS_INST_TEX_ID_SHIFT0
# define R500_RS_INST_TEX_CN_WRITE(1 << 4)
# define R500_RS_INST_TEX_ADDR_SHIFT5
# define R500_RS_INST_COL_ID_SHIFT12
# define R500_RS_INST_COL_CN_NO_WRITE(0 << 16)
# define R500_RS_INST_COL_CN_WRITE(1 << 16)
# define R500_RS_INST_COL_CN_WRITE_FBUFFER(2 << 16)
# define R500_RS_INST_COL_CN_WRITE_BACKFACE(3 << 16)
# define R500_RS_INST_COL_COL_ADDR_SHIFT18
# define R500_RS_INST_TEX_ADJ(1 << 25)
# define R500_RS_INST_W_CN(1 << 26)
#define R500_US_FC_CTRL0x4624
#define R500_US_CODE_ADDR0x4630
#define R500_US_CODE_RANGE 0x4634
#define R500_US_CODE_OFFSET 0x4638
#define R500_RS_IP_00x4074
#define R500_RS_IP_10x4078
# define R500_RS_IP_PTR_K062
# define R500_RS_IP_PTR_K1 63
# define R500_RS_IP_TEX_PTR_S_SHIFT 0
# define R500_RS_IP_TEX_PTR_T_SHIFT 6
# define R500_RS_IP_TEX_PTR_R_SHIFT 12
# define R500_RS_IP_TEX_PTR_Q_SHIFT 18
# define R500_RS_IP_COL_PTR_SHIFT 24
# define R500_RS_IP_COL_FMT_SHIFT 27
# define R500_RS_IP_COL_FMT_RGBA(0 << 27)
# define R500_RS_IP_OFFSET_EN (1 << 31)
#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
/* r6xx/r7xx stuff */
#define R600_GRBM_STATUS 0x8010
# define R600_CMDFIFO_AVAIL_MASK 0x1f
# define R700_CMDFIFO_AVAIL_MASK 0xf
# define R600_GUI_ACTIVE (1 << 31)
#define R600_GRBM_SOFT_RESET 0x8020
# define R600_SOFT_RESET_CP (1 << 0)
#define R600_WAIT_UNTIL 0x8040
#define R600_CP_ME_CNTL 0x86d8
# define R600_CP_ME_HALT (1 << 28)
#define R600_CP_RB_BASE 0xc100
#define R600_CP_RB_CNTL 0xc104
# define R600_RB_NO_UPDATE (1 << 27)
# define R600_RB_RPTR_WR_ENA (1 << 31)
#define R600_CP_RB_RPTR_WR 0xc108
#define R600_CP_RB_RPTR_ADDR 0xc10c
#define R600_CP_RB_RPTR_ADDR_HI 0xc110
#define R600_CP_RB_WPTR 0xc114
#define R600_CP_RB_WPTR_ADDR 0xc118
#define R600_CP_RB_WPTR_ADDR_HI 0xc11c
#define R600_CP_RB_RPTR 0x8700
#define R600_CP_RB_WPTR_DELAY 0x8704
#endif
branches/azimutz/Chazi/i386/modules/AMDGraphicsEnabler/Readme.txt
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Module:ATiGraphicsEnabler
Description: the GraphicsEnabler ATI code ( > r784) ported to a module.
This code has no support for "legacy" ATI cards.
Based on Meklort's work.
Dependencies: none
Keys: GraphicsEnabler(enabled by default)
UseAtiROM(disabled by default)
AtiConfig...
ATYbinimage
TODO: ---
branches/azimutz/Chazi/i386/modules/AMDGraphicsEnabler/AMDGraphicsEnabler.c
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/*
* ATIGraphicsEnabler Module ---
* Enables many ati "HD ??" cards to be used out of the box in OS X.
* This was converted from ( > r784) boot2 code to a boot2 module.
*
*/
#include "saio_internal.h"
#include "bootstruct.h"
#include "pci.h"
#include "modules.h"
#define kGraphicsEnablerKey"GraphicsEnabler"
extern bool setup_ati_devprop(pci_dt_t *ati_dev);
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4);
void AMDGraphicsEnabler_start()
{
register_hook_callback("PCIDevice", &GraphicsEnabler_hook);
}
void GraphicsEnabler_hook(void* arg1, void* arg2, void* arg3, void* arg4)
{
pci_dt_t* current = arg1;
if (current->class_id != PCI_CLASS_DISPLAY_VGA) return;
char *devicepath = get_pci_dev_path(current);
bool do_gfx_devprop = true;
getBoolForKey(kGraphicsEnablerKey, &do_gfx_devprop, &bootInfo->bootConfig);
//Azi: check "fail" code...
if (do_gfx_devprop && (current->vendor_id == PCI_VENDOR_ID_ATI))
{
verbose("ATI VGA Controller [%04x:%04x] :: %s \n",
current->vendor_id, current->device_id, devicepath);
setup_ati_devprop(current);
}
else
verbose("Not a ATI VGA Controller.\n"); // ---
}
branches/azimutz/Chazi/i386/modules/AMDGraphicsEnabler/Makefile
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MODULE_NAME = AMDGraphicsEnabler
MODULE_VERSION = "1.0.0"
MODULE_COMPAT_VERSION = "1.0.0"
MODULE_START = _$(MODULE_NAME)_start
MODULE_DEPENDENCIES =
DIR = AMDGraphicsEnabler
MODULE_OBJS = ati.o AMDGraphicsEnabler.o
OPTIM = -Os -Oz
DEBUG = -DNOTHING
#DEBUG = -DDEBUG_HELLO_WORLD=1
CFLAGS= $(RC_CFLAGS) $(OPTIM) $(MORECPP) -arch i386 -g -Wmost \
-D__ARCHITECTURE__=\"i386\" -DSAIO_INTERNAL_USER \
-DRCZ_COMPRESSED_FILE_SUPPORT $(DEBUG) \
-fno-builtin $(OMIT_FRAME_POINTER_CFLAG) \
-mpreferred-stack-boundary=2 -fno-align-functions -fno-stack-protector \
-march=pentium4 -msse2 -mfpmath=sse -msoft-float -fno-common
DEFINES=
CONFIG = hd
INC = -I. -I.. -I$(SYMROOT) -I$(UTILDIR) -I$(LIBSADIR) -I$(LIBSAIODIR) -I$(BOOT2DIR)
LIBS=
VPATH = $(OBJROOT):$(SYMROOT)
SFILES =
CFILES =
HFILES =
EXPORTED_HFILES =
INSTALLED_HFILES =
OTHERFILES = Makefile
ALLSRC = $(SFILES) $(CFILES) \
$(HFILES) $(OTHERFILES)
DIRS_NEEDED = $(OBJROOT) $(SYMROOT)
all embedtheme optionrom: dylib
include ../MakeInc.dir
branches/azimutz/Chazi/i386/modules/AMDGraphicsEnabler/ati.c
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/*
* ATI Graphics Card Enabler, part of the Chameleon Boot Loader Project
*
* Copyright 2010 by Islam M. Ahmed Zaid. All rights reserved.
*
*/
#include "bootstruct.h"
#include "pci.h"
#include "platform.h"
#include "device_inject.h"
#include "ati_reg.h"
#define kUseAtiROM"UseAtiROM"
#define kAtiConfig"AtiConfig"
#define kATYbinimage"ATYbinimage"
#defineOFFSET_TO_GET_ATOMBIOS_STRINGS_START0x6e
#define Reg32(reg)(*(volatile uint32_t *)(card->mmio + reg))
#define RegRead32(reg)(Reg32(reg))
#define RegWrite32(reg, value)(Reg32(reg) = value)
typedef enum {
kNul,
kStr,
kPtr,
kCst
} type_t;
typedef enum {
CHIP_FAMILY_UNKNOW,
CHIP_FAMILY_RS600,
CHIP_FAMILY_RS690,
CHIP_FAMILY_RS740,
/* R600 */
CHIP_FAMILY_R600,
CHIP_FAMILY_RV610,
CHIP_FAMILY_RV630,
CHIP_FAMILY_RV670,
CHIP_FAMILY_RV620,
CHIP_FAMILY_RV635,
CHIP_FAMILY_RS780,
CHIP_FAMILY_RS880,
/* R700 */
CHIP_FAMILY_RV770,
CHIP_FAMILY_RV730,
CHIP_FAMILY_RV710,
CHIP_FAMILY_RV740,
/* Evergreen */
CHIP_FAMILY_CEDAR,
CHIP_FAMILY_REDWOOD,
CHIP_FAMILY_JUNIPER,
CHIP_FAMILY_CYPRESS,
CHIP_FAMILY_HEMLOCK,
/* Northern Islands */
CHIP_FAMILY_BARTS,
CHIP_FAMILY_CAICOS,
CHIP_FAMILY_CAYMAN,
CHIP_FAMILY_TURKS,
CHIP_FAMILY_LAST
} chip_family_t;
static const char *chip_family_name[] = {
"UNKNOW",
"RS600",
"RS690",
"RS740",
/* R600 */
"R600",
"RV610",
"RV630",
"RV670",
"RV620",
"RV635",
"RS780",
"RS880",
/* R700 */
"RV770",
"RV730",
"RV710",
"RV740",
/* Evergreen */
"Cedar",// RV810
"Redwood",// RV830
"Juniper",// RV840
"Cypress",// RV870
"Hemlock",
/* Northern Islands */
"Barts",
"Caicos",
"Cayman",
"Turks",
""
};
typedef struct {
const char*name;
uint8_tports;
} card_config_t;
static card_config_t card_configs[] = {
{NULL,0},
{"Alopias",2},
{"Alouatta",4},
{"Baboon",3},
{"Cardinal",2},
{"Caretta",1},
{"Colobus",2},
{"Douc",2},
{"Eulemur",3},
{"Flicker",3},
{"Galago",2},
{"Gliff",3},
{"Hoolock",3},
{"Hypoprion",2},
{"Iago",2},
{"Kakapo",3},
{"Kipunji",4},
{"Lamna",2},
{"Langur",3},
{"Megalodon",3},
{"Motmot",2},
{"Nomascus",5},
{"Orangutan",2},
{"Peregrine",2},
{"Quail",3},
{"Raven",3},
{"Shrike",3},
{"Sphyrna",1},
{"Triakis",2},
{"Uakari",4},
{"Vervet",4},
{"Zonalis",6},
{"Pithecia",3},
{"Bulrushes",6},
{"Cattail",4},
{"Hydrilla",5},
{"Duckweed",4},
{"Fanwort",4},
{"Elodea",5},
{"Kudzu",2},
{"Gibba",5},
{"Lotus",3},
{"Ipomoea",3},
{"Mangabey",2},
{"Muskgrass",4},
{"Juncus",4}
};
typedef enum {
kNull,
kAlopias,
kAlouatta,
kBaboon,
kCardinal,
kCaretta,
kColobus,
kDouc,
kEulemur,
kFlicker,
kGalago,
kGliff,
kHoolock,
kHypoprion,
kIago,
kKakapo,
kKipunji,
kLamna,
kLangur,
kMegalodon,
kMotmot,
kNomascus,
kOrangutan,
kPeregrine,
kQuail,
kRaven,
kShrike,
kSphyrna,
kTriakis,
kUakari,
kVervet,
kZonalis,
kPithecia,
kBulrushes,
kCattail,
kHydrilla,
kDuckweed,
kFanwort,
kElodea,
kKudzu,
kGibba,
kLotus,
kIpomoea,
kMangabey,
kMuskgrass,
kJuncus,
kCfgEnd
} config_name_t;
typedef struct {
uint16_tdevice_id;
uint32_tsubsys_id;
chip_family_tchip_family;
const char*model_name;
config_name_tcfg_name;
} radeon_card_info_t;
static radeon_card_info_t radeon_cards[] = {
/* Earlier cards are not supported */
{ 0x9400,0x30001002,CHIP_FAMILY_R600,"ATI Radeon HD 2900 PRO",kNull},
{ 0x9400,0x25521002,CHIP_FAMILY_R600,"ATI Radeon HD 2900 XT",kNull},
{ 0x9440,0x24401682,CHIP_FAMILY_RV770,"ATI Radeon HD 4870",kMotmot},
{ 0x9440,0x24411682,CHIP_FAMILY_RV770,"ATI Radeon HD 4870",kMotmot},
{ 0x9440,0x24441682,CHIP_FAMILY_RV770,"ATI Radeon HD 4870",kMotmot},
{ 0x9440,0x24451682,CHIP_FAMILY_RV770,"ATI Radeon HD 4870",kMotmot},
{ 0x9441,0x24401682,CHIP_FAMILY_RV770,"ATI Radeon HD 4870 X2",kMotmot},
{ 0x9442,0x24701682,CHIP_FAMILY_RV770,"ATI Radeon HD 4850",kMotmot},
{ 0x9442,0x24711682,CHIP_FAMILY_RV770,"ATI Radeon HD 4850",kMotmot},
{ 0x9442,0x080110B0,CHIP_FAMILY_RV770,"ATI Radeon HD 4850",kMotmot},
{ 0x9442,0xE104174B,CHIP_FAMILY_RV770,"ATI Radeon HD 4850",kMotmot},
{ 0x944A,0x30001682,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x30001043,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x30001458,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x30001462,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x30001545,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x30001787,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x3000174B,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944A,0x300017AF,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944C,0x24801682,CHIP_FAMILY_RV770,"ATI Radeon HD 4830",kMotmot},
{ 0x944C,0x24811682,CHIP_FAMILY_RV770,"ATI Radeon HD 4830",kMotmot},
{ 0x944E,0x3260174B,CHIP_FAMILY_RV770,"ATI Radeon HD 4810 Series",kMotmot},
{ 0x944E,0x3261174B,CHIP_FAMILY_RV770,"ATI Radeon HD 4810 series",kMotmot},
{ 0x944E,0x30001787,CHIP_FAMILY_RV770,"ATI Radeon HD 4730 Series",kMotmot},
{ 0x944E,0x30101787,CHIP_FAMILY_RV770,"ATI Radeon HD 4810 Series",kMotmot},
{ 0x944E,0x31001787,CHIP_FAMILY_RV770,"ATI Radeon HD 4820",kMotmot},
{ 0x9490,0x30501787,CHIP_FAMILY_RV730,"ATI Radeon HD 4710",kNull},
{ 0x9490,0x4710174B,CHIP_FAMILY_RV730,"ATI Radeon HD 4710",kNull},
{ 0x9490,0x300017AF,CHIP_FAMILY_RV730,"ATI Radeon HD 4710",kNull},
{ 0x9498,0x30501787,CHIP_FAMILY_RV730,"ATI Radeon HD 4700",kNull},
{ 0x9498,0x31001787,CHIP_FAMILY_RV730,"ATI Radeon HD 4720",kNull},
{ 0x9498,0x24511682,CHIP_FAMILY_RV730,"ATI Radeon HD 4650",kNull},
{ 0x9498,0x24521682,CHIP_FAMILY_RV730,"ATI Radeon HD 4650",kNull},
{ 0x9498,0x24541682,CHIP_FAMILY_RV730,"ATI Radeon HD 4650",kNull},
{ 0x9498,0x29331682,CHIP_FAMILY_RV730,"ATI Radeon HD 4670",kNull},
{ 0x9498,0x29341682,CHIP_FAMILY_RV730,"ATI Radeon HD 4670",kNull},
{ 0x9498,0x21CF1458,CHIP_FAMILY_RV730,"ATI Radeon HD 4600 Series",kNull},
{ 0x94B3,0x29001682,CHIP_FAMILY_RV740,"ATI Radeon HD 4770",kFlicker},
{ 0x94B3,0x1170174B,CHIP_FAMILY_RV740,"ATI Radeon HD 4770",kFlicker},
{ 0x94B3,0x10020D00,CHIP_FAMILY_RV740,"ATI Radeon HD 4770",kFlicker},
{ 0x94C1,0x10021002,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 Pro",kNull},
{ 0x94C1,0x0D021002,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x0D021028,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 Pro",kNull},
{ 0x94C1,0x0D021028,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x21741458,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x10401462,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x10331462,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x10331462,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C1,0x11101462,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 XT",kNull},
{ 0x94C3,0x37161642,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x30001642,CHIP_FAMILY_RV610,"ATI Radeon HD 3410",kNull},
{ 0x94C3,0x03421002,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x30001025,CHIP_FAMILY_RV610,"ATI Radeon HD 2350 Series",kNull},
{ 0x94C3,0x04021028,CHIP_FAMILY_RV610,"ATI Radeon HD 2400",kNull},
{ 0x94C3,0x03021028,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x04021028,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x216A1458,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x21721458,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x30001458,CHIP_FAMILY_RV610,"ATI Radeon HD 3410",kNull},
{ 0x94C3,0x11041462,CHIP_FAMILY_RV610,"ATI Radeon HD 2400",kNull},
{ 0x94C3,0x10411462,CHIP_FAMILY_RV610,"ATI Radeon HD 2400",kNull},
{ 0x94C3,0x11051462,CHIP_FAMILY_RV610,"ATI Radeon HD 2400",kNull},
{ 0x94C3,0x10321462,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x30001462,CHIP_FAMILY_RV610,"ATI Radeon HD 3410",kNull},
{ 0x94C3,0x3000148C,CHIP_FAMILY_RV610,"ATI Radeon HD 2350 Series",kNull},
{ 0x94C3,0x2247148C,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 LE",kNull},
{ 0x94C3,0x3000174B,CHIP_FAMILY_RV610,"ATI Radeon HD 2350 Series",kNull},
{ 0x94C3,0xE400174B,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0xE370174B,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0xE400174B,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0xE370174B,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0xE400174B,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 PRO",kNull},
{ 0x94C3,0x203817AF,CHIP_FAMILY_RV610,"ATI Radeon HD 2400",kNull},
{ 0x94C3,0x30001787,CHIP_FAMILY_RV610,"ATI Radeon HD 2350 Series",kNull},
{ 0x94C3,0x22471787,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 LE",kNull},
{ 0x94C3,0x01011A93,CHIP_FAMILY_RV610,"Qimonda Radeon HD 2400 PRO",kNull},
{ 0x9501,0x30001002,CHIP_FAMILY_RV670,"ATI Radeon HD 3690",kNull},
{ 0x9501,0x25421002,CHIP_FAMILY_RV670,"ATI Radeon HD 3870",kNull},
{ 0x9501,0x4750174B,CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9501,0x3000174B,CHIP_FAMILY_RV670,"Sapphire Radeon HD 3690",kNull},
{ 0x9501,0x30001787,CHIP_FAMILY_RV670,"ATI Radeon HD 3690",kNull},
{ 0x9505,0x30001002,CHIP_FAMILY_RV670,"ATI Radeon HD 3690",kNull},
{ 0x9505,0x25421002,CHIP_FAMILY_RV670,"ATI Radeon HD 3850",kNull},
{ 0x9505,0x30011043,CHIP_FAMILY_RV670,"ATI Radeon HD 4730",kNull},
{ 0x9505,0x3000148C,CHIP_FAMILY_RV670,"ATI Radeon HD 3850",kNull},
{ 0x9505,0x3002148C,CHIP_FAMILY_RV670,"ATI Radeon HD 4730",kNull},
{ 0x9505,0x3001148C,CHIP_FAMILY_RV670,"ATI Radeon HD 4730",kNull},
{ 0x9505,0x3003148C,CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9505,0x3004148C,CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9505,0x4730174B,CHIP_FAMILY_RV670,"ATI Radeon HD 4730",kNull},
{ 0x9505,0x3010174B,CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9505,0x3001174B,CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9505,0x3000174B,CHIP_FAMILY_RV670,"Sapphire Radeon HD 3690",kNull},
{ 0x9505,0x30001787,CHIP_FAMILY_RV670,"ATI Radeon HD 3690",kNull},
{ 0x9505,0x301017AF,CHIP_FAMILY_RV670,"ATI Radeon HD 4750",kNull},
{ 0x9540,0x4590174B,CHIP_FAMILY_RV710,"ATI Radeon HD 4590",kNull},
{ 0x9540,0x30501787,CHIP_FAMILY_RV710,"ATI Radeon HD 4590",kNull},
{ 0x954F,0x29201682,CHIP_FAMILY_RV710,"ATI Radeon HD 4550",kNull},
{ 0x954F,0x29211682,CHIP_FAMILY_RV710,"ATI Radeon HD 4550",kNull},
{ 0x954F,0x30901682,CHIP_FAMILY_RV710,"XFX Radeon HD 4570",kNull},
{ 0x954F,0x4450174B,CHIP_FAMILY_RV710,"ATI Radeon HD 4450",kNull},
{ 0x954F,0x3000174B,CHIP_FAMILY_RV710,"ATI Radeon HD 4520",kNull},
{ 0x954F,0x30501787,CHIP_FAMILY_RV710,"ATI Radeon HD 4450",kNull},
{ 0x954F,0x31001787,CHIP_FAMILY_RV710,"ATI Radeon HD 4520",kNull},
{ 0x954F,0x4570174B,CHIP_FAMILY_RV710,"Sapphire Radeon HD4570",kNull},
{ 0x954F,0x301017AF,CHIP_FAMILY_RV710,"ATI Radeon HD 4450",kNull},
{ 0x9552,0x3000148C,CHIP_FAMILY_RV710,"ATI Radeon HD 4300/4500 Series",kNull},
{ 0x9552,0x3000174B,CHIP_FAMILY_RV710,"ATI Radeon HD 4300/4500 Series",kNull},
{ 0x9552,0x30001787,CHIP_FAMILY_RV710,"ATI Radeon HD 4300/4500 Series",kNull},
{ 0x9552,0x300017AF,CHIP_FAMILY_RV710,"ATI Radeon HD 4300/4500 Series",kNull},
{ 0x9581,0x95811002,CHIP_FAMILY_RV630,"ATI Radeon HD 3600 Series",kNull},
{ 0x9581,0x3000148C,CHIP_FAMILY_RV630,"ATI Radeon HD 3600 Series",kNull},
{ 0x9583,0x3000148C,CHIP_FAMILY_RV630,"ATI Radeon HD 3600 Series",kNull},
{ 0x9588,0x01021A93,CHIP_FAMILY_RV630,"Qimonda Radeon HD 2600 XT",kNull},
{ 0x9589,0x30001462,CHIP_FAMILY_RV630,"ATI Radeon HD 3610",kNull},
{ 0x9589,0x30001642,CHIP_FAMILY_RV630,"ATI Radeon HD 3610",kNull},
{ 0x9589,0x0E41174B,CHIP_FAMILY_RV630,"ATI Radeon HD 3600 Series",kNull},
{ 0x9589,0x30001787,CHIP_FAMILY_RV630,"ATI Radeon HD 3600 Series",kNull},
{ 0x9589,0x01001A93,CHIP_FAMILY_RV630,"Qimonda Radeon HD 2600 PRO",kNull},
{ 0x9591,0x2303148C,CHIP_FAMILY_RV635,"ATI Radeon HD 3600 Series",kNull},
{ 0x9598,0xB3831002,CHIP_FAMILY_RV635,"ATI All-in-Wonder HD",kNull},
{ 0x9598,0x30011043,CHIP_FAMILY_RV635,"ATI Radeon HD 4570",kNull},
{ 0x9598,0x30001043,CHIP_FAMILY_RV635,"HD3730",kNull},
{ 0x9598,0x3000148C,CHIP_FAMILY_RV635,"ATI Radeon HD 3730",kNull},
{ 0x9598,0x3031148C,CHIP_FAMILY_RV635,"ATI Radeon HD 4570",kNull},
{ 0x9598,0x3001148C,CHIP_FAMILY_RV635,"ATI Radeon HD 4580",kNull},
{ 0x9598,0x30011545,CHIP_FAMILY_RV635,"VisionTek Radeon HD 2600 Pro",kNull},
{ 0x9598,0x30001545,CHIP_FAMILY_RV635,"VisionTek Radeon HD 2600 XT",kNull},
{ 0x9598,0x4570174B,CHIP_FAMILY_RV635,"ATI Radeon HD 4570",kNull},
{ 0x9598,0x4580174B,CHIP_FAMILY_RV635,"ATI Radeon HD 4580",kNull},
{ 0x9598,0x4610174B,CHIP_FAMILY_RV635,"ATI Radeon HD 4610",kNull},
{ 0x9598,0x3000174B,CHIP_FAMILY_RV635,"Sapphire Radeon HD 3730",kNull},
{ 0x9598,0x3001174B,CHIP_FAMILY_RV635,"Sapphire Radeon HD 3750",kNull},
{ 0x9598,0x301017AF,CHIP_FAMILY_RV635,"ATI Radeon HD 4570",kNull},
{ 0x9598,0x301117AF,CHIP_FAMILY_RV635,"ATI Radeon HD 4580",kNull},
{ 0x9598,0x300117AF,CHIP_FAMILY_RV635,"ATI Radeon HD3750",kNull},
{ 0x9598,0x30501787,CHIP_FAMILY_RV635,"ATI Radeon HD 4610",kNull},
{ 0x95C0,0x3000148C,CHIP_FAMILY_RV620,"ATI Radeon HD 3550",kNull},
{ 0x95C0,0xE3901745,CHIP_FAMILY_RV620,"ATI Radeon HD 3550",kNull},
{ 0x95C0,0x3002174B,CHIP_FAMILY_RV620,"ATI Radeon HD 3570",kNull},
{ 0x95C0,0x3020174B,CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C0,0x3000174B,CHIP_FAMILY_RV620,"Sapphire Radeon HD 3550",kNull},
{ 0x95C5,0x3000148C,CHIP_FAMILY_RV620,"ATI Radeon HD 3450",kNull},
{ 0x95C5,0x3001148C,CHIP_FAMILY_RV620,"ATI Radeon HD 3550",kNull},
{ 0x95C5,0x3002148C,CHIP_FAMILY_RV620,"ATI Radeon HD 4230",kNull},
{ 0x95C5,0x3033148C,CHIP_FAMILY_RV620,"ATI Radeon HD 4230",kNull},
{ 0x95C5,0x3003148C,CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C5,0x3032148C,CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C5,0x3010174B,CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C5,0x4250174B,CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C5,0x30501787,CHIP_FAMILY_RV620,"ATI Radeon HD 4250",kNull},
{ 0x95C5,0x301017AF,CHIP_FAMILY_RV620,"ATI Radeon HD 4230",kNull},
{ 0x95C5,0x01051A93,CHIP_FAMILY_RV620,"Qimonda Radeon HD 3450",kNull},
{ 0x95C5,0x01041A93,CHIP_FAMILY_RV620,"Qimonda Radeon HD 3450",kNull},
/* Evergreen */
{ 0x6898,0x032E1043,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kUakari},
{ 0x6898,0xE140174B,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kUakari},
{ 0x6898,0x29611682,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kUakari},
{ 0x6898,0x0B001002,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kZonalis},
{ 0x6898,0x00D0106B,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5870",kLangur},
{ 0x6899,0x21E41458,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5850",kUakari},
{ 0x6899,0x200A1787,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5850",kUakari},
{ 0x6899,0x22901787,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5850",kUakari},
{ 0x6899,0xE140174B,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5850",kUakari},
{ 0x689C,0x03521043,CHIP_FAMILY_HEMLOCK,"ASUS ARES",kUakari},
{ 0x689C,0x039E1043,CHIP_FAMILY_HEMLOCK,"ASUS EAH5870 Series",kUakari},
{ 0x689C,0x30201682,CHIP_FAMILY_HEMLOCK,"ATI Radeon HD 5970",kUakari},
{ 0x68B8,0xE147174B,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x21D71458,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x1482174B,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x29901682,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x29911682,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x200B1787,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x22881787,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kVervet},
{ 0x68B8,0x00CF106B,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5770",kHoolock},
{ 0x68D8,0x301117AF,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5690",kNull},
{ 0x68D8,0x301017AF,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5730",kNull},
{ 0x68D8,0x30001787,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5730",kNull},
{ 0x68D8,0x5690174B,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5690",kNull},
{ 0x68D8,0x5730174B,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5730",kNull},
{ 0x68D8,0x21D91458,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5670",kBaboon},
{ 0x68D8,0x03561043,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5670",kBaboon},
{ 0x68D8,0xE151174B,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5670",kBaboon},
{ 0x68D9,0x301017AF,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5630",kNull},
{ 0x68DA,0x301017AF,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5630",kNull},
{ 0x68DA,0x30001787,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5630",kNull},
{ 0x68DA,0x5630174B,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5630",kNull},
{ 0x68E0,0x04561028,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5470M",kEulemur},
{ 0x68E1,0x1426103C,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5430M",kEulemur},
{ 0x68F9,0x301317AF,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5470",kNull},
{ 0x68F9,0x301117AF,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5470",kNull},
{ 0x68F9,0x301217AF,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5490",kNull},
{ 0x68F9,0x30001787,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5470",kNull},
{ 0x68F9,0x30021787,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5490",kNull},
{ 0x68F9,0x30011787,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5530",kNull},
{ 0x68F9,0x5470174B,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5470",kNull},
{ 0x68F9,0x5490174B,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5490",kNull},
{ 0x68F9,0x5530174B,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5530",kNull},
/* Northen Islands */
{ 0x6718,0x0B001002,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970",kNull},
{ 0x6718,0x31301682,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970",kNull},
{ 0x6718,0x67181002,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6970",kNull},
{ 0x6738,0x67381002,CHIP_FAMILY_BARTS,"AMD Radeon HD 6870",kDuckweed},
{ 0x6739,0x67391002,CHIP_FAMILY_BARTS,"AMD Radeon HD 6850",kDuckweed},
{ 0x6759,0xE193174B,CHIP_FAMILY_TURKS,"AMD Radeon HD 6570",kNull},
/* standard/default models */
{ 0x9400,0x00000000,CHIP_FAMILY_R600,"ATI Radeon HD 2900 XT",kNull},
{ 0x9405,0x00000000,CHIP_FAMILY_R600,"ATI Radeon HD 2900 GT",kNull},
{ 0x9440,0x00000000,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x9441,0x00000000,CHIP_FAMILY_RV770,"ATI Radeon HD 4870 X2",kMotmot},
{ 0x9442,0x00000000,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x9443,0x00000000,CHIP_FAMILY_RV770,"ATI Radeon HD 4850 X2",kMotmot},
{ 0x944C,0x00000000,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x944E,0x00000000,CHIP_FAMILY_RV770,"ATI Radeon HD 4700 Series",kMotmot},
{ 0x944E,0x00000000,CHIP_FAMILY_RV770,"ATI Radeon HD 4700 Series",kMotmot},
{ 0x9450,0x00000000,CHIP_FAMILY_RV770,"AMD FireStream 9270",kMotmot},
{ 0x9452,0x00000000,CHIP_FAMILY_RV770,"AMD FireStream 9250",kMotmot},
{ 0x9460,0x00000000,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x9462,0x00000000,CHIP_FAMILY_RV770,"ATI Radeon HD 4800 Series",kMotmot},
{ 0x9490,0x00000000,CHIP_FAMILY_RV730,"ATI Radeon HD 4600 Series",kFlicker},
{ 0x9498,0x00000000,CHIP_FAMILY_RV730,"ATI Radeon HD 4600 Series",kFlicker},
{ 0x94B3,0x00000000,CHIP_FAMILY_RV740,"ATI Radeon HD 4770",kFlicker},
{ 0x94B4,0x00000000,CHIP_FAMILY_RV740,"ATI Radeon HD 4700 Series",kFlicker},
{ 0x94B5,0x00000000,CHIP_FAMILY_RV740,"ATI Radeon HD 4770",kFlicker},
{ 0x94C1,0x00000000,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 Series",kIago},
{ 0x94C3,0x00000000,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 Series",kIago},
{ 0x94C7,0x00000000,CHIP_FAMILY_RV610,"ATI Radeon HD 2350",kIago},
{ 0x94CC,0x00000000,CHIP_FAMILY_RV610,"ATI Radeon HD 2400 Series",kIago},
{ 0x9501,0x00000000,CHIP_FAMILY_RV670,"ATI Radeon HD 3800 Series",kMegalodon},
{ 0x9505,0x00000000,CHIP_FAMILY_RV670,"ATI Radeon HD 3800 Series",kMegalodon},
{ 0x9507,0x00000000,CHIP_FAMILY_RV670,"ATI Radeon HD 3830",kMegalodon},
{ 0x950F,0x00000000,CHIP_FAMILY_RV670,"ATI Radeon HD 3870 X2",kMegalodon},
{ 0x9513,0x00000000,CHIP_FAMILY_RV670,"ATI Radeon HD 3850 X2",kMegalodon},
{ 0x9519,0x00000000,CHIP_FAMILY_RV670,"AMD FireStream 9170",kMegalodon},
{ 0x9540,0x00000000,CHIP_FAMILY_RV710,"ATI Radeon HD 4550",kNull},
{ 0x954F,0x00000000,CHIP_FAMILY_RV710,"ATI Radeon HD 4300/4500 Series",kNull},
{ 0x9588,0x00000000,CHIP_FAMILY_RV630,"ATI Radeon HD 2600 XT",kLamna},
{ 0x9589,0x00000000,CHIP_FAMILY_RV630,"ATI Radeon HD 2600 PRO",kLamna},
{ 0x958A,0x00000000,CHIP_FAMILY_RV630,"ATI Radeon HD 2600 X2 Series",kLamna},
{ 0x9598,0x00000000,CHIP_FAMILY_RV635,"ATI Radeon HD 3600 Series",kMegalodon},
{ 0x95C0,0x00000000,CHIP_FAMILY_RV620,"ATI Radeon HD 3400 Series",kIago},
{ 0x95C5,0x00000000,CHIP_FAMILY_RV620,"ATI Radeon HD 3400 Series",kIago},
{ 0x9610,0x00000000,CHIP_FAMILY_RS780,"ATI Radeon HD 3200 Graphics",kNull},
{ 0x9611,0x00000000,CHIP_FAMILY_RS780,"ATI Radeon 3100 Graphics",kNull},
{ 0x9614,0x00000000,CHIP_FAMILY_RS780,"ATI Radeon HD 3300 Graphics",kNull},
{ 0x9616,0x00000000,CHIP_FAMILY_RS780,"AMD 760G",kNull},
{ 0x9710,0x00000000,CHIP_FAMILY_RS880,"ATI Radeon HD 4200",kNull},
{ 0x9715,0x00000000,CHIP_FAMILY_RS880,"ATI Radeon HD 4250",kNull},
{ 0x9714,0x00000000,CHIP_FAMILY_RS880,"ATI Radeon HD 4290",kNull},
/* Evergreen */
{ 0x688D,0x00000000,CHIP_FAMILY_CYPRESS,"AMD FireStream 9350",kUakari},
{ 0x6898,0x00000000,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5800 Series",kUakari},
{ 0x6899,0x00000000,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5800 Series",kUakari},
{ 0x689E,0x00000000,CHIP_FAMILY_CYPRESS,"ATI Radeon HD 5800 Series",kUakari},
{ 0x689C,0x00000000,CHIP_FAMILY_HEMLOCK,"ATI Radeon HD 5900 Series",kUakari},
{ 0x68B9,0x00000000,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5600 Series",kVervet},
{ 0x68B8,0x00000000,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5700 Series",kVervet},
{ 0x68BE,0x00000000,CHIP_FAMILY_JUNIPER,"ATI Radeon HD 5700 Series",kVervet},
{ 0x68D8,0x00000000,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5600 Series",kBaboon},
{ 0x68D9,0x00000000,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5500 Series",kBaboon},
{ 0x68DA,0x00000000,CHIP_FAMILY_REDWOOD,"ATI Radeon HD 5500 Series",kBaboon},
{ 0x68F9,0x00000000,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5400 Series",kNull},
{ 0x6718,0x00000000,CHIP_FAMILY_CAYMAN,"AMD Radeon HD 6900 Series",kNull},
/* Northen Islands */
{ 0x6758,0x00000000,CHIP_FAMILY_TURKS,"AMD Radeon HD 6670",kNull},
{ 0x6759,0x00000000,CHIP_FAMILY_TURKS,"AMD Radeon HD 6500 Series",kNull},
{ 0x6770,0x00000000,CHIP_FAMILY_CAICOS,"AMD Radeon HD 6400 Series",kNull},
{ 0x6779,0x00000000,CHIP_FAMILY_CAICOS,"AMD Radeon HD 6450 Series",kNull},
{ 0x68F9,0x00000000,CHIP_FAMILY_CEDAR,"ATI Radeon HD 5400 Series",kNull},
{ 0x0000,0x00000000,CHIP_FAMILY_UNKNOW,NULL,kNull}
};
typedef struct {
struct DevPropDevice*device;
radeon_card_info_t*info;
pci_dt_t *pci_dev;
uint8_t*fb;
uint8_t*mmio;
uint8_t*io;
uint8_t*rom;
uint32_trom_size;
uint32_tvram_size;
uint8_tports;
uint32_tflags;
boolposted;
} card_t;
card_t *card;
/* Flags */
#define MKFLAG(n)(1 << n)
#define FLAGTRUEMKFLAG(0)
#define EVERGREENMKFLAG(1)
static uint8_t atN = 0;
typedef struct {
type_ttype;
uint32_tsize;
uint8_t*data;
} value_t;
static value_t aty_name;
static value_t aty_nameparent;
//static value_t aty_model;
#define DATVAL(x){kPtr, sizeof(x), (uint8_t *)x}
#define STRVAL(x){kStr, sizeof(x), (uint8_t *)x}
#define BYTVAL(x){kCst, 1, (uint8_t *)x}
#define WRDVAL(x){kCst, 2, (uint8_t *)x}
#define DWRVAL(x){kCst, 4, (uint8_t *)x}
#define QWRVAL(x){kCst, 8, (uint8_t *)x}
#define NULVAL{kNul, 0, (uint8_t *)NULL}
bool get_bootdisplay_val(value_t *val);
bool get_vrammemory_val(value_t *val);
bool get_name_val(value_t *val);
bool get_nameparent_val(value_t *val);
bool get_model_val(value_t *val);
bool get_conntype_val(value_t *val);
bool get_vrammemsize_val(value_t *val);
bool get_binimage_val(value_t *val);
bool get_romrevision_val(value_t *val);
bool get_deviceid_val(value_t *val);
bool get_mclk_val(value_t *val);
bool get_sclk_val(value_t *val);
bool get_refclk_val(value_t *val);
bool get_platforminfo_val(value_t *val);
bool get_vramtotalsize_val(value_t *val);
typedef struct {
uint32_tflags;
boolall_ports;
char*name;
bool(*get_value)(value_t *val);
value_tdefault_val;
} dev_prop_t;
dev_prop_t ati_devprop_list[] = {
{FLAGTRUE,false,"@0,AAPL,boot-display",get_bootdisplay_val,NULVAL},
//{FLAGTRUE,false,"@0,ATY,EFIDisplay",NULL,STRVAL("TMDSA")},
//{FLAGTRUE,true,"@0,AAPL,vram-memory",get_vrammemory_val,NULVAL},
//{FLAGTRUE,true,"@0,compatible",get_name_val,NULVAL},
//{FLAGTRUE,true,"@0,connector-type",get_conntype_val,NULVAL},
//{FLAGTRUE,true,"@0,device_type",NULL,STRVAL("display")},
//{FLAGTRUE,false,"@0,display-connect-flags",NULL,DWRVAL((uint32_t)0)},
//{FLAGTRUE,true,"@0,display-type",NULL,STRVAL("NONE")},
{FLAGTRUE,true,"@0,name",get_name_val,NULVAL},
//{FLAGTRUE,true,"@0,VRAM,memsize",get_vrammemsize_val,NULVAL},
//{FLAGTRUE,false,"AAPL,aux-power-connected",NULL,DWRVAL((uint32_t)1)},
//{FLAGTRUE,false,"AAPL,backlight-control",NULL,DWRVAL((uint32_t)0)},
{FLAGTRUE,false,"ATY,bin_image",get_binimage_val,NULVAL},
{FLAGTRUE,false,"ATY,Copyright",NULL,STRVAL("Copyright AMD Inc. All Rights Reserved. 2005-2010")},
{FLAGTRUE,false,"ATY,Card#",get_romrevision_val,NULVAL},
{FLAGTRUE,false,"ATY,VendorID",NULL,WRDVAL((uint16_t)0x1002)},
{FLAGTRUE,false,"ATY,DeviceID",get_deviceid_val,NULVAL},
//{FLAGTRUE,false,"ATY,MCLK",get_mclk_val,NULVAL},
//{FLAGTRUE,false,"ATY,SCLK",get_sclk_val,NULVAL},
//{FLAGTRUE,false,"ATY,RefCLK",get_refclk_val,DWRVAL((uint32_t)0x0a8c)},
//{FLAGTRUE,false,"ATY,PlatformInfo",get_platforminfo_val,NULVAL},
{FLAGTRUE,false,"name",get_nameparent_val,NULVAL},
{FLAGTRUE,false,"device_type",get_nameparent_val,NULVAL},
{FLAGTRUE,false,"model",get_model_val,STRVAL("ATI Radeon")},
//{FLAGTRUE,false,"VRAM,totalsize",get_vramtotalsize_val,NULVAL},
{FLAGTRUE,false,NULL,NULL,NULVAL}
};
bool get_bootdisplay_val(value_t *val)
{
static uint32_t v = 0;
if (v)
return false;
if (!card->posted)
return false;
v = 1;
val->type = kCst;
val->size = 4;
val->data = (uint8_t *)&v;
return true;
}
bool get_vrammemory_val(value_t *val)
{
return false;
}
bool get_name_val(value_t *val)
{
val->type = aty_name.type;
val->size = aty_name.size;
val->data = aty_name.data;
return true;
}
bool get_nameparent_val(value_t *val)
{
val->type = aty_nameparent.type;
val->size = aty_nameparent.size;
val->data = aty_nameparent.data;
return true;
}
bool get_model_val(value_t *val)
{
if (!card->info->model_name)
return false;
val->type = kStr;
val->size = strlen(card->info->model_name) + 1;
val->data = (uint8_t *)card->info->model_name;
return true;
}
bool get_conntype_val(value_t *val)
{
/*
Connector types:
0x4 : DisplayPort
0x400: DL DVI-I
0x800: HDMI
*/
return false;
}
bool get_vrammemsize_val(value_t *val)
{
static int idx = -1;
static uint64_t memsize;
idx++;
memsize = ((uint64_t)card->vram_size << 32);
if (idx == 0)
memsize = memsize | (uint64_t)card->vram_size;
val->type = kCst;
val->size = 8;
val->data = (uint8_t *)&memsize;
return true;
}
bool get_binimage_val(value_t *val)
{
if (!card->rom)
return false;
val->type = kPtr;
val->size = card->rom_size;
val->data = card->rom;
return true;
}
bool get_romrevision_val(value_t *val)
{
uint8_t *rev;
if (!card->rom)
return false;
rev = card->rom + *(uint8_t *)(card->rom + OFFSET_TO_GET_ATOMBIOS_STRINGS_START);
val->type = kPtr;
val->size = strlen((char *)rev);
val->data = malloc(val->size);
if (!val->data)
return false;
memcpy(val->data, rev, val->size);
return true;
}
bool get_deviceid_val(value_t *val)
{
val->type = kCst;
val->size = 2;
val->data = (uint8_t *)&card->pci_dev->device_id;
return true;
}
bool get_mclk_val(value_t *val)
{
return false;
}
bool get_sclk_val(value_t *val)
{
return false;
}
bool get_refclk_val(value_t *val)
{
return false;
}
bool get_platforminfo_val(value_t *val)
{
val->data = malloc(0x80);
if (!val->data)
return false;
bzero(val->data, 0x80);
val->type= kPtr;
val->size= 0x80;
val->data[0]= 1;
return true;
}
bool get_vramtotalsize_val(value_t *val)
{
val->type = kCst;
val->size = 4;
val->data = (uint8_t *)&card->vram_size;
return true;
}
void free_val(value_t *val)
{
if (val->type == kPtr)
free(val->data);
bzero(val, sizeof(value_t));
}
void devprop_add_list(dev_prop_t devprop_list[])
{
value_t *val = malloc(sizeof(value_t));
int i, pnum;
for (i = 0; devprop_list[i].name != NULL; i++)
if ((devprop_list[i].flags == FLAGTRUE) || (devprop_list[i].flags | card->flags))
if (devprop_list[i].get_value && devprop_list[i].get_value(val))
{
devprop_add_value(card->device, devprop_list[i].name, val->data, val->size);
free_val(val);
if (devprop_list[i].all_ports)
{
for (pnum = 1; pnum < card->ports; pnum++)
{
if (devprop_list[i].get_value(val))
{
devprop_list[i].name[1] = 0x30 + pnum; // convert to ascii
devprop_add_value(card->device, devprop_list[i].name, val->data, val->size);
free_val(val);
}
}
devprop_list[i].name[1] = 0x30; // write back our "@0," for a next possible card
}
}
else
{
if (devprop_list[i].default_val.type != kNul)
devprop_add_value(card->device, devprop_list[i].name,
devprop_list[i].default_val.type == kCst ?
(uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data,
devprop_list[i].default_val.size);
if (devprop_list[i].all_ports)
{
for (pnum = 1; pnum < card->ports; pnum++)
{
if (devprop_list[i].default_val.type != kNul)
{
devprop_list[i].name[1] = 0x30 + pnum; // convert to ascii
devprop_add_value(card->device, devprop_list[i].name,
devprop_list[i].default_val.type == kCst ?
(uint8_t *)&(devprop_list[i].default_val.data) : devprop_list[i].default_val.data,
devprop_list[i].default_val.size);
}
}
devprop_list[i].name[1] = 0x30; // write back our "@0," for a next possible card
}
}
free(val);
}
bool validate_rom(option_rom_header_t *rom_header, pci_dt_t *pci_dev)
{
option_rom_pci_header_t *rom_pci_header;
if (rom_header->signature != 0xaa55)
return false;
rom_pci_header = (option_rom_pci_header_t *)((uint8_t *)rom_header + rom_header->pci_header_offset);
if (rom_pci_header->signature != 0x52494350)
return false;
if (rom_pci_header->vendor_id != pci_dev->vendor_id || rom_pci_header->device_id != pci_dev->device_id)
return false;
return true;
}
bool load_vbios_file(const char *key, uint16_t vendor_id, uint16_t device_id, uint32_t subsys_id)
{
intfd;
char file_name[24];
bool do_load = false;
getBoolForKey(key, &do_load, &bootInfo->bootConfig);
if (!do_load)
return false;
sprintf(file_name, "/Extra/%04x_%04x_%08x.rom", vendor_id, device_id, subsys_id);
if ((fd = open_bvdev("bt(0,0)", file_name, 0)) < 0)
return false;
card->rom_size = file_size(fd);
card->rom = malloc(card->rom_size);
if (!card->rom)
return false;
read(fd, (char *)card->rom, card->rom_size);
if (!validate_rom((option_rom_header_t *)card->rom, card->pci_dev))
{
card->rom_size = 0;
card->rom = 0;
return false;
}
card->rom_size = ((option_rom_header_t *)card->rom)->rom_size * 512;
close(fd);
return true;
}
void get_vram_size(void)
{
chip_family_t chip_family = card->info->chip_family;
card->vram_size = 0;
if (chip_family >= CHIP_FAMILY_CEDAR)
/* size in MB on evergreen */
/* XXX watch for overflow!!! */
card->vram_size = RegRead32(R600_CONFIG_MEMSIZE) * 1024 * 1024;
else
if (chip_family >= CHIP_FAMILY_R600)
card->vram_size = RegRead32(R600_CONFIG_MEMSIZE);
}
bool read_vbios(bool from_pci)
{
option_rom_header_t *rom_addr;
if (from_pci)
{
rom_addr = (option_rom_header_t *)(pci_config_read32(card->pci_dev->dev.addr, PCI_ROM_ADDRESS) & ~0x7ff);
verbose(" @0x%x", rom_addr);
}
else
rom_addr = (option_rom_header_t *)0xc0000;
if (!validate_rom(rom_addr, card->pci_dev))
return false;
card->rom_size = rom_addr->rom_size * 512;
if (!card->rom_size)
return false;
card->rom = malloc(card->rom_size);
if (!card->rom)
return false;
memcpy(card->rom, (void *)rom_addr, card->rom_size);
return true;
}
bool read_disabled_vbios(void)
{
bool ret = false;
chip_family_t chip_family = card->info->chip_family;
if (chip_family >= CHIP_FAMILY_RV770)
{
uint32_t viph_control= RegRead32(RADEON_VIPH_CONTROL);
uint32_t bus_cntl= RegRead32(RADEON_BUS_CNTL);
uint32_t d1vga_control= RegRead32(AVIVO_D1VGA_CONTROL);
uint32_t d2vga_control= RegRead32(AVIVO_D2VGA_CONTROL);
uint32_t vga_render_control= RegRead32(AVIVO_VGA_RENDER_CONTROL);
uint32_t rom_cntl= RegRead32(R600_ROM_CNTL);
uint32_t cg_spll_func_cntl= 0;
uint32_t cg_spll_status;
/* disable VIP */
RegWrite32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
/* enable the rom */
RegWrite32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
/* Disable VGA mode */
RegWrite32(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT)));
RegWrite32(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT)));
RegWrite32(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
if (chip_family == CHIP_FAMILY_RV730)
{
cg_spll_func_cntl = RegRead32(R600_CG_SPLL_FUNC_CNTL);
/* enable bypass mode */
RegWrite32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | R600_SPLL_BYPASS_EN));
/* wait for SPLL_CHG_STATUS to change to 1 */
cg_spll_status = 0;
while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
cg_spll_status = RegRead32(R600_CG_SPLL_STATUS);
RegWrite32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
}
else
RegWrite32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
ret = read_vbios(true);
/* restore regs */
if (chip_family == CHIP_FAMILY_RV730)
{
RegWrite32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
/* wait for SPLL_CHG_STATUS to change to 1 */
cg_spll_status = 0;
while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
cg_spll_status = RegRead32(R600_CG_SPLL_STATUS);
}
RegWrite32(RADEON_VIPH_CONTROL, viph_control);
RegWrite32(RADEON_BUS_CNTL, bus_cntl);
RegWrite32(AVIVO_D1VGA_CONTROL, d1vga_control);
RegWrite32(AVIVO_D2VGA_CONTROL, d2vga_control);
RegWrite32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
RegWrite32(R600_ROM_CNTL, rom_cntl);
}
else
if (chip_family >= CHIP_FAMILY_R600)
{
uint32_t viph_control= RegRead32(RADEON_VIPH_CONTROL);
uint32_t bus_cntl= RegRead32(RADEON_BUS_CNTL);
uint32_t d1vga_control= RegRead32(AVIVO_D1VGA_CONTROL);
uint32_t d2vga_control = RegRead32(AVIVO_D2VGA_CONTROL);
uint32_t vga_render_control= RegRead32(AVIVO_VGA_RENDER_CONTROL);
uint32_t rom_cntl= RegRead32(R600_ROM_CNTL);
uint32_t general_pwrmgt= RegRead32(R600_GENERAL_PWRMGT);
uint32_t low_vid_lower_gpio_cntl= RegRead32(R600_LOW_VID_LOWER_GPIO_CNTL);
uint32_t medium_vid_lower_gpio_cntl= RegRead32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
uint32_t high_vid_lower_gpio_cntl= RegRead32(R600_HIGH_VID_LOWER_GPIO_CNTL);
uint32_t ctxsw_vid_lower_gpio_cntl= RegRead32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
uint32_t lower_gpio_enable= RegRead32(R600_LOWER_GPIO_ENABLE);
/* disable VIP */
RegWrite32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
/* enable the rom */
RegWrite32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
/* Disable VGA mode */
RegWrite32(AVIVO_D1VGA_CONTROL, (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT)));
RegWrite32(AVIVO_D2VGA_CONTROL, (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | AVIVO_DVGA_CONTROL_TIMING_SELECT)));
RegWrite32(AVIVO_VGA_RENDER_CONTROL, (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
RegWrite32(R600_ROM_CNTL, ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | R600_SCK_OVERWRITE));
RegWrite32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
RegWrite32(R600_LOW_VID_LOWER_GPIO_CNTL, (low_vid_lower_gpio_cntl & ~0x400));
RegWrite32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, (medium_vid_lower_gpio_cntl & ~0x400));
RegWrite32(R600_HIGH_VID_LOWER_GPIO_CNTL, (high_vid_lower_gpio_cntl & ~0x400));
RegWrite32(R600_CTXSW_VID_LOWER_GPIO_CNTL, (ctxsw_vid_lower_gpio_cntl & ~0x400));
RegWrite32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
ret = read_vbios(true);
/* restore regs */
RegWrite32(RADEON_VIPH_CONTROL, viph_control);
RegWrite32(RADEON_BUS_CNTL, bus_cntl);
RegWrite32(AVIVO_D1VGA_CONTROL, d1vga_control);
RegWrite32(AVIVO_D2VGA_CONTROL, d2vga_control);
RegWrite32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
RegWrite32(R600_ROM_CNTL, rom_cntl);
RegWrite32(R600_GENERAL_PWRMGT, general_pwrmgt);
RegWrite32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
RegWrite32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
RegWrite32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
RegWrite32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
RegWrite32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
}
return ret;
}
bool radeon_card_posted(void)
{
uint32_t reg;
/* first check CRTCs */
reg = RegRead32(RADEON_CRTC_GEN_CNTL) | RegRead32(RADEON_CRTC2_GEN_CNTL);
if (reg & RADEON_CRTC_EN)
return true;
/* then check MEM_SIZE, in case something turned the crtcs off */
reg = RegRead32(R600_CONFIG_MEMSIZE);
if (reg)
return true;
return false;
}
#if 0
bool devprop_add_pci_config_space(void)
{
int offset;
uint8_t *config_space = malloc(0x100);
if (!config_space)
return false;
for (offset = 0; offset < 0x100; offset += 4)
config_space[offset / 4] = pci_config_read32(card->pci_dev->dev.addr, offset);
devprop_add_value(card->device, "ATY,PCIConfigSpace", config_space, 0x100);
free(config_space);
return true;
}
#endif
static bool init_card(pci_dt_t *pci_dev)
{
const char *fb_name;
char name[24];
char name_parent[24];
int i;
bool add_vbios = true;
card = malloc(sizeof(card_t));
if (!card)
return false;
bzero(card, sizeof(card_t));
card->pci_dev = pci_dev;
for (i = 0; radeon_cards[i].device_id ; i++)
if (radeon_cards[i].device_id == pci_dev->device_id)
{
card->info = &radeon_cards[i];
if ((radeon_cards[i].subsys_id == 0x00000000) ||
(radeon_cards[i].subsys_id == pci_dev->subsys_id.subsys_id))
break;
}
if (!card->info->device_id || !card->info->cfg_name)
{
printf("Unsupported card!\n");
return false;
}
card->fb= (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_0) & ~0x0f);
card->mmio= (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_2) & ~0x0f);
card->io= (uint8_t *)(pci_config_read32(pci_dev->dev.addr, PCI_BASE_ADDRESS_4) & ~0x03);
verbose("Framebuffer @0x%08X MMIO @0x%08X I/O Port @0x%08X ROM Addr @0x%08X\n",
card->fb, card->mmio, card->io, pci_config_read32(pci_dev->dev.addr, PCI_ROM_ADDRESS));
card->posted= radeon_card_posted();
verbose("ATI card %s, ", card->posted ? "POSTed" : "non-POSTed");
get_vram_size();
getBoolForKey(kATYbinimage, &add_vbios, &bootInfo->bootConfig);
if (add_vbios)
if (!load_vbios_file(kUseAtiROM, pci_dev->vendor_id, pci_dev->device_id, pci_dev->subsys_id.subsys_id))
{
verbose("reading VBIOS from %s", card->posted ? "legacy space" : "PCI ROM");
if (card->posted)
read_vbios(false);
else
read_disabled_vbios();
verbose("\n");
}
card->ports = 2; // default
if (card->info->chip_family >= CHIP_FAMILY_CEDAR)
{
card->flags |= EVERGREEN;
card->ports = 3;
}
atN = 0;
fb_name = getStringForKey(kAtiConfig, &bootInfo->bootConfig);
if (!fb_name)
{
fb_name = card_configs[card->info->cfg_name].name;
card->ports = card_configs[card->info->cfg_name].ports;
}
else
{
for (i = 0; i < kCfgEnd; i++)
if (strcmp(fb_name, card_configs[i].name) == 0)
card->ports = card_configs[i].ports;
}
sprintf(name, "ATY,%s", fb_name);
aty_name.type = kStr;
aty_name.size = strlen(name) + 1;
aty_name.data = (uint8_t *)name;
sprintf(name_parent, "ATY,%sParent", fb_name);
aty_nameparent.type = kStr;
aty_nameparent.size = strlen(name_parent) + 1;
aty_nameparent.data = (uint8_t *)name_parent;
return true;
}
bool setup_ati_devprop(pci_dt_t *ati_dev)
{
char *devicepath;
if (!init_card(ati_dev))
return false;
/* ------------------------------------------------- */
/* Find a better way to do this (in device_inject.c) */
if (!string)
string = devprop_create_string();
devicepath = get_pci_dev_path(ati_dev);
card->device = devprop_add_device(string, devicepath);
if (!card->device)
return false;
/* ------------------------------------------------- */
#if 0
uint64_t fb= (uint32_t)card->fb;
uint64_t mmio= (uint32_t)card->mmio;
uint64_t io= (uint32_t)card->io;
devprop_add_value(card->device, "ATY,FrameBufferOffset", &fb, 8);
devprop_add_value(card->device, "ATY,RegisterSpaceOffset", &mmio, 8);
devprop_add_value(card->device, "ATY,IOSpaceOffset", &io, 8);
#endif
devprop_add_list(ati_devprop_list);
/* ------------------------------------------------- */
/* Find a better way to do this (in device_inject.c) */
//Azi: tried to fix a malloc error in vain; this is caused by XCode 4 compilation!
stringdata = malloc(sizeof(uint8_t) * string->length);
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
/* ------------------------------------------------- */
verbose("ATI %s %s %dMB (%s) [%04x:%04x] (subsys [%04x:%04x]):: %s\n",
chip_family_name[card->info->chip_family], card->info->model_name,
(uint32_t)(card->vram_size / (1024 * 1024)), card_configs[card->info->cfg_name].name,
ati_dev->vendor_id, ati_dev->device_id,
ati_dev->subsys_id.subsys.vendor_id, ati_dev->subsys_id.subsys.device_id,
devicepath);
free(card);
return true;
}
branches/azimutz/Chazi/i386/modules/Makefile
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#Makefile for i386 modules
# The order of building is important.
SUBDIRS = klibc uClibc++ GraphicsEnablerLegacy KernelPatcher Memory HPET
SUBDIRS = klibc uClibc++ KernelPatcher Memory HPET \
ATiGraphicsEnabler AMDGraphicsEnabler NVIDIAGraphicsEnabler IntelGraphicsEnabler
#SUBDIRS = HelloWorld
#-- Resolution (only tested on Meklort's branch, never did any good for my resolution;
#conflicts with AutoResolution)
#conflicts with AutoResolution - fix! )
#-- GraphicsEnabler (no support for ATI legacy cards, e.g. 1000 series)
#-- AMDGraphicsEnabler (no support for ATI legacy cards, e.g. 1000 series)
#testing = http://www.insanelymac.com/forum/index.php?s=&showtopic=231075&view=findpost&p=1683785
#-- Memory ("Attempting to execute hook ScanMemory"
branches/azimutz/Cleancut/i386/modules/ATiGraphicsEnabler/Readme.txt
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TODO:
- naming: ATi or AMD ??
- eliminate the need for pci_old.h
- merge with
- merge with AMDGraphicsEnabler ??

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Revision: 872